Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
0 |
8 |
100.00 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
0 |
8 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_watermark_lvl
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
2498 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T7 |
5 |
all_levels[1] |
443 |
1 |
|
|
T12 |
1 |
|
T113 |
2 |
|
T129 |
3 |
all_levels[2] |
384 |
1 |
|
|
T18 |
1 |
|
T16 |
3 |
|
T28 |
2 |
all_levels[3] |
402 |
1 |
|
|
T112 |
1 |
|
T197 |
1 |
|
T165 |
1 |
all_levels[4] |
532 |
1 |
|
|
T11 |
1 |
|
T28 |
1 |
|
T112 |
1 |
all_levels[5] |
343 |
1 |
|
|
T210 |
1 |
|
T79 |
1 |
|
T132 |
2 |
all_levels[6] |
537 |
1 |
|
|
T16 |
2 |
|
T15 |
5 |
|
T25 |
2 |
all_levels[7] |
186 |
1 |
|
|
T131 |
1 |
|
T263 |
4 |
|
T402 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |