Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2498 1 T3 1 T4 4 T7 5
all_levels[1] 443 1 T12 1 T113 2 T129 3
all_levels[2] 384 1 T18 1 T16 3 T28 2
all_levels[3] 402 1 T112 1 T197 1 T165 1
all_levels[4] 532 1 T11 1 T28 1 T112 1
all_levels[5] 343 1 T210 1 T79 1 T132 2
all_levels[6] 537 1 T16 2 T15 5 T25 2
all_levels[7] 186 1 T131 1 T263 4 T402 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%