Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	124954	1			T3	5		T4	8		T5	1
all_pins[1]	124954	1			T3	5		T4	8		T5	1
all_pins[2]	124954	1			T3	5		T4	8		T5	1
all_pins[3]	124954	1			T3	5		T4	8		T5	1
all_pins[4]	124954	1			T3	5		T4	8		T5	1
all_pins[5]	124954	1			T3	5		T4	8		T5	1
all_pins[6]	124954	1			T3	5		T4	8		T5	1
all_pins[7]	124954	1			T3	5		T4	8		T5	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	990144	1			T3	35		T4	47		T5	8
values[0x1]	9488	1			T3	5		T4	17		T7	9
transitions[0x0=>0x1]	8604	1			T3	5		T4	10		T7	7
transitions[0x1=>0x0]	8620	1			T3	5		T4	10		T7	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	122544	1			T3	5		T4	4		T5	1
all_pins[0]	values[0x1]	2410	1			T4	4		T7	2		T36	1
all_pins[0]	transitions[0x0=>0x1]	2161	1			T4	1		T7	2		T36	1
all_pins[0]	transitions[0x1=>0x0]	2291	1			T4	1		T7	2		T36	2
all_pins[1]	values[0x0]	122414	1			T3	5		T4	4		T5	1
all_pins[1]	values[0x1]	2540	1			T4	4		T7	2		T36	2
all_pins[1]	transitions[0x0=>0x1]	2255	1			T4	4		T7	2		T36	2
all_pins[1]	transitions[0x1=>0x0]	2087	1			T3	3		T4	1		T7	2
all_pins[2]	values[0x0]	122582	1			T3	2		T4	7		T5	1
all_pins[2]	values[0x1]	2372	1			T3	3		T4	1		T7	2
all_pins[2]	transitions[0x0=>0x1]	2328	1			T3	3		T4	1		T7	1
all_pins[2]	transitions[0x1=>0x0]	186	1			T4	1		T36	2		T389	1
all_pins[3]	values[0x0]	124724	1			T3	5		T4	7		T5	1
all_pins[3]	values[0x1]	230	1			T4	1		T7	1		T36	2
all_pins[3]	transitions[0x0=>0x1]	180	1			T7	1		T36	2		T389	2
all_pins[3]	transitions[0x1=>0x0]	411	1			T4	2		T51	2		T110	5
all_pins[4]	values[0x0]	124493	1			T3	5		T4	5		T5	1
all_pins[4]	values[0x1]	461	1			T4	3		T51	2		T110	5
all_pins[4]	transitions[0x0=>0x1]	385	1			T4	3		T51	1		T110	5
all_pins[4]	transitions[0x1=>0x0]	171	1			T3	2		T4	1		T36	2
all_pins[5]	values[0x0]	124707	1			T3	3		T4	7		T5	1
all_pins[5]	values[0x1]	247	1			T3	2		T4	1		T36	2
all_pins[5]	transitions[0x0=>0x1]	191	1			T3	2		T51	1		T389	1
all_pins[5]	transitions[0x1=>0x0]	811	1			T4	1		T7	1		T51	3
all_pins[6]	values[0x0]	124087	1			T3	5		T4	6		T5	1
all_pins[6]	values[0x1]	867	1			T4	2		T7	1		T36	2
all_pins[6]	transitions[0x0=>0x1]	808	1			T4	1		T7	1		T51	3
all_pins[6]	transitions[0x1=>0x0]	302	1			T7	1		T51	1		T390	1
all_pins[7]	values[0x0]	124593	1			T3	5		T4	7		T5	1
all_pins[7]	values[0x1]	361	1			T4	1		T7	1		T36	2
all_pins[7]	transitions[0x0=>0x1]	296	1			T36	2		T51	1		T389	1
all_pins[7]	transitions[0x1=>0x0]	2361	1			T4	3		T7	1		T36	1