Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	812	1			T3	4		T4	7		T7	7
all_values[1]	812	1			T3	4		T4	7		T7	7
all_values[2]	812	1			T3	4		T4	7		T7	7
all_values[3]	812	1			T3	4		T4	7		T7	7
all_values[4]	812	1			T3	4		T4	7		T7	7
all_values[5]	812	1			T3	4		T4	7		T7	7
all_values[6]	812	1			T3	4		T4	7		T7	7
all_values[7]	812	1			T3	4		T4	7		T7	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3477

1

T3

19

T4

28

T7

29

auto[1]

3019

1

T3

13

T4

28

T7

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2538

1

T3

19

T4

16

T7

21

auto[1]

3958

1

T3

13

T4

40

T7

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3834

1

T3

24

T4

30

T7

30

auto[1]

2662

1

T3

8

T4

26

T7

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	172	1			T3	3		T4	1		T36	2
all_values[0]	auto[0]	auto[0]	auto[1]	95	1			T4	1		T51	1		T391	3
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T3	1		T7	2		T392	2
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T4	1		T7	2		T36	1
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T4	3		T7	2		T36	1
all_values[0]	auto[1]	auto[1]	auto[1]	139	1			T4	1		T7	1		T51	2
all_values[1]	auto[0]	auto[0]	auto[0]	163	1			T3	1		T4	1		T51	2
all_values[1]	auto[0]	auto[0]	auto[1]	93	1			T3	1		T51	1		T392	1
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T3	1		T7	1		T36	1
all_values[1]	auto[0]	auto[1]	auto[1]	86	1			T4	2		T7	1		T36	1
all_values[1]	auto[1]	auto[0]	auto[1]	177	1			T3	1		T4	1		T7	4
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T4	3		T7	1		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T4	1		T7	3		T36	3
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T4	1		T51	1		T110	1
all_values[2]	auto[0]	auto[1]	auto[0]	142	1			T4	1		T36	1		T110	1
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T3	2		T4	1		T7	2
all_values[2]	auto[1]	auto[0]	auto[1]	174	1			T3	1		T4	1		T7	2
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T3	1		T4	2		T51	2
all_values[3]	auto[0]	auto[0]	auto[0]	175	1			T3	2		T4	2		T7	1
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T4	1		T7	1		T51	2
all_values[3]	auto[0]	auto[1]	auto[0]	144	1			T3	2		T7	1		T110	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T4	1		T7	1		T36	1
all_values[3]	auto[1]	auto[0]	auto[1]	174	1			T4	3		T7	1		T51	5
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T7	2		T36	2		T110	2
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T3	1		T7	1		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T4	1		T36	2		T110	2
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T3	2		T4	1		T7	1
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T4	2		T110	3		T389	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T4	2		T7	2		T392	1
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T3	1		T4	1		T7	3
all_values[5]	auto[0]	auto[0]	auto[0]	162	1			T3	1		T7	2		T51	1
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T51	1		T392	1		T110	2
all_values[5]	auto[0]	auto[1]	auto[0]	160	1			T4	5		T7	3		T392	2
all_values[5]	auto[0]	auto[1]	auto[1]	77	1			T3	1		T36	1		T51	1
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T3	1		T4	1		T7	2
all_values[5]	auto[1]	auto[1]	auto[1]	141	1			T3	1		T4	1		T36	1
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T3	2		T7	2		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T4	1		T392	1		T110	1
all_values[6]	auto[0]	auto[1]	auto[0]	161	1			T3	1		T7	1		T110	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T36	1		T51	2		T110	2
all_values[6]	auto[1]	auto[0]	auto[1]	184	1			T3	1		T4	4		T7	3
all_values[6]	auto[1]	auto[1]	auto[1]	148	1			T4	2		T7	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T3	2		T4	1		T7	1
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T3	1		T4	2		T7	1
all_values[7]	auto[0]	auto[1]	auto[0]	157	1			T4	3		T7	2		T51	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T7	1		T36	1		T389	1
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T3	1		T7	1		T51	2
all_values[7]	auto[1]	auto[1]	auto[1]	146	1			T4	1		T7	1		T36	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal