Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.79 98.45 100.00 99.76 100.00 97.61


Total test records in report: 1299
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T1253 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1753977653 Feb 07 12:38:30 PM PST 24 Feb 07 12:38:34 PM PST 24 167591624 ps
T1254 /workspace/coverage/cover_reg_top/4.uart_intr_test.1571899121 Feb 07 12:38:43 PM PST 24 Feb 07 12:38:45 PM PST 24 28617739 ps
T91 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1231554702 Feb 07 12:39:05 PM PST 24 Feb 07 12:39:07 PM PST 24 61608174 ps
T1255 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2727643506 Feb 07 12:39:16 PM PST 24 Feb 07 12:39:18 PM PST 24 52510276 ps
T388 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2009402429 Feb 07 12:38:31 PM PST 24 Feb 07 12:38:36 PM PST 24 383726795 ps
T1256 /workspace/coverage/cover_reg_top/48.uart_intr_test.2046069692 Feb 07 12:39:30 PM PST 24 Feb 07 12:39:32 PM PST 24 15458174 ps
T1257 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3698326013 Feb 07 12:38:45 PM PST 24 Feb 07 12:38:51 PM PST 24 19121292 ps
T1258 /workspace/coverage/cover_reg_top/10.uart_intr_test.3825281797 Feb 07 12:38:53 PM PST 24 Feb 07 12:38:54 PM PST 24 39999520 ps
T1259 /workspace/coverage/cover_reg_top/6.uart_intr_test.2067433415 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:46 PM PST 24 26205760 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4007215215 Feb 07 12:38:30 PM PST 24 Feb 07 12:38:34 PM PST 24 58768225 ps
T1261 /workspace/coverage/cover_reg_top/9.uart_csr_rw.4066458053 Feb 07 12:38:54 PM PST 24 Feb 07 12:38:55 PM PST 24 24094477 ps
T1262 /workspace/coverage/cover_reg_top/43.uart_intr_test.1615868291 Feb 07 12:39:32 PM PST 24 Feb 07 12:39:34 PM PST 24 45432326 ps
T1263 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2734172691 Feb 07 12:38:55 PM PST 24 Feb 07 12:38:57 PM PST 24 95477765 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2972857089 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:47 PM PST 24 22821464 ps
T1265 /workspace/coverage/cover_reg_top/14.uart_intr_test.1231877504 Feb 07 12:39:04 PM PST 24 Feb 07 12:39:05 PM PST 24 11382162 ps
T1266 /workspace/coverage/cover_reg_top/5.uart_intr_test.3928885120 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:46 PM PST 24 12251093 ps
T1267 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.59492984 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:47 PM PST 24 47944709 ps
T1268 /workspace/coverage/cover_reg_top/34.uart_intr_test.2475605957 Feb 07 12:39:32 PM PST 24 Feb 07 12:39:34 PM PST 24 14913123 ps
T1269 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1277355075 Feb 07 12:39:06 PM PST 24 Feb 07 12:39:07 PM PST 24 15288429 ps
T1270 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2028593450 Feb 07 12:38:54 PM PST 24 Feb 07 12:38:57 PM PST 24 204645783 ps
T1271 /workspace/coverage/cover_reg_top/45.uart_intr_test.889149699 Feb 07 12:39:30 PM PST 24 Feb 07 12:39:32 PM PST 24 20353206 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_intr_test.3166572502 Feb 07 12:38:36 PM PST 24 Feb 07 12:38:40 PM PST 24 49754634 ps
T1273 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1598837131 Feb 07 12:39:06 PM PST 24 Feb 07 12:39:08 PM PST 24 21138937 ps
T1274 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3836793778 Feb 07 12:38:32 PM PST 24 Feb 07 12:38:39 PM PST 24 63194027 ps
T1275 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.581280481 Feb 07 12:38:32 PM PST 24 Feb 07 12:38:39 PM PST 24 19550425 ps
T1276 /workspace/coverage/cover_reg_top/44.uart_intr_test.3294185283 Feb 07 12:39:27 PM PST 24 Feb 07 12:39:29 PM PST 24 18983910 ps
T1277 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.80679511 Feb 07 12:38:46 PM PST 24 Feb 07 12:38:51 PM PST 24 15786447 ps
T1278 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3481740113 Feb 07 12:38:53 PM PST 24 Feb 07 12:38:56 PM PST 24 66687833 ps
T1279 /workspace/coverage/cover_reg_top/25.uart_intr_test.2331801042 Feb 07 12:39:14 PM PST 24 Feb 07 12:39:15 PM PST 24 30119636 ps
T1280 /workspace/coverage/cover_reg_top/19.uart_intr_test.1943822878 Feb 07 12:39:15 PM PST 24 Feb 07 12:39:16 PM PST 24 48449476 ps
T1281 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.167618095 Feb 07 12:38:52 PM PST 24 Feb 07 12:38:54 PM PST 24 18144565 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.319564036 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:46 PM PST 24 31640027 ps
T1283 /workspace/coverage/cover_reg_top/16.uart_intr_test.2798721931 Feb 07 12:39:07 PM PST 24 Feb 07 12:39:08 PM PST 24 57896225 ps
T1284 /workspace/coverage/cover_reg_top/26.uart_intr_test.1974351094 Feb 07 12:39:16 PM PST 24 Feb 07 12:39:18 PM PST 24 16195057 ps
T1285 /workspace/coverage/cover_reg_top/29.uart_intr_test.2923979334 Feb 07 12:39:31 PM PST 24 Feb 07 12:39:33 PM PST 24 31898117 ps
T1286 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.402223479 Feb 07 12:39:07 PM PST 24 Feb 07 12:39:09 PM PST 24 24826841 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1122464768 Feb 07 12:38:49 PM PST 24 Feb 07 12:38:53 PM PST 24 181725001 ps
T1288 /workspace/coverage/cover_reg_top/20.uart_intr_test.2339152390 Feb 07 12:39:17 PM PST 24 Feb 07 12:39:18 PM PST 24 13012866 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3885434478 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:47 PM PST 24 95878577 ps
T1290 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3786529012 Feb 07 12:38:42 PM PST 24 Feb 07 12:38:45 PM PST 24 89506655 ps
T1291 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.155953444 Feb 07 12:38:51 PM PST 24 Feb 07 12:38:53 PM PST 24 89127320 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1515837119 Feb 07 12:38:44 PM PST 24 Feb 07 12:38:46 PM PST 24 34742819 ps
T1293 /workspace/coverage/cover_reg_top/13.uart_csr_rw.454399941 Feb 07 12:39:02 PM PST 24 Feb 07 12:39:04 PM PST 24 23553605 ps
T1294 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3891658145 Feb 07 12:38:43 PM PST 24 Feb 07 12:38:45 PM PST 24 18185562 ps
T1295 /workspace/coverage/cover_reg_top/1.uart_tl_errors.652140929 Feb 07 12:38:33 PM PST 24 Feb 07 12:38:40 PM PST 24 36266983 ps
T1296 /workspace/coverage/cover_reg_top/8.uart_intr_test.1601322980 Feb 07 12:38:55 PM PST 24 Feb 07 12:38:57 PM PST 24 40421162 ps
T1297 /workspace/coverage/cover_reg_top/36.uart_intr_test.2257658119 Feb 07 12:39:37 PM PST 24 Feb 07 12:39:38 PM PST 24 16460293 ps
T1298 /workspace/coverage/cover_reg_top/40.uart_intr_test.1128652403 Feb 07 12:39:33 PM PST 24 Feb 07 12:39:35 PM PST 24 13004233 ps
T1299 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1993614464 Feb 07 12:39:03 PM PST 24 Feb 07 12:39:05 PM PST 24 83201103 ps

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1073935908
Short name T9
Test name
Test status
Simulation time 78221125 ps
CPU time 0.74 seconds
Started Feb 07 12:38:56 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 198736 kb
Host smart-60e69658-864b-4bde-85dd-57444018746c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073935908 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1073935908
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2338381597
Short name T13
Test name
Test status
Simulation time 48193039375 ps
CPU time 227.08 seconds
Started Feb 07 01:38:12 PM PST 24
Finished Feb 07 01:42:00 PM PST 24
Peak memory 216708 kb
Host smart-f33f234b-34cd-4d52-a4b2-2e2441ba3acb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338381597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2338381597
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2621962264
Short name T79
Test name
Test status
Simulation time 388551426845 ps
CPU time 789.24 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:50:05 PM PST 24
Peak memory 224920 kb
Host smart-5e7f914d-b236-4fe3-b881-92e5db78c146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621962264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2621962264
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.621836464
Short name T7
Test name
Test status
Simulation time 11464181 ps
CPU time 0.58 seconds
Started Feb 07 12:39:19 PM PST 24
Finished Feb 07 12:39:20 PM PST 24
Peak memory 194316 kb
Host smart-8344f9cc-3289-49bb-87b2-43859ecba340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621836464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.621836464
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2604277316
Short name T263
Test name
Test status
Simulation time 412033902331 ps
CPU time 1014.68 seconds
Started Feb 07 01:38:27 PM PST 24
Finished Feb 07 01:55:28 PM PST 24
Peak memory 216696 kb
Host smart-83223f2d-c69d-412c-8b3e-a6e824877c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604277316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2604277316
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.2156411345
Short name T15
Test name
Test status
Simulation time 179792348836 ps
CPU time 87.56 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 216540 kb
Host smart-dc6ce820-5e91-4f04-a163-db127c3e1c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156411345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2156411345
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.988795604
Short name T43
Test name
Test status
Simulation time 271568550 ps
CPU time 1.56 seconds
Started Feb 07 12:38:30 PM PST 24
Finished Feb 07 12:38:35 PM PST 24
Peak memory 200100 kb
Host smart-bf3d9584-8a3a-459b-b8b0-f610d6c36209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988795604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.988795604
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1258100399
Short name T142
Test name
Test status
Simulation time 312785709706 ps
CPU time 828.17 seconds
Started Feb 07 01:38:22 PM PST 24
Finished Feb 07 01:52:15 PM PST 24
Peak memory 224892 kb
Host smart-efba2bf3-1019-4a9f-b600-7f85e7476580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258100399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1258100399
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.610918553
Short name T186
Test name
Test status
Simulation time 272791548722 ps
CPU time 850.27 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:48:16 PM PST 24
Peak memory 224960 kb
Host smart-2f9b2755-2fdd-423a-89b8-88bc003b9fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610918553 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.610918553
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.2851718308
Short name T398
Test name
Test status
Simulation time 2198911280816 ps
CPU time 877.29 seconds
Started Feb 07 01:32:57 PM PST 24
Finished Feb 07 01:47:35 PM PST 24
Peak memory 199904 kb
Host smart-c6a0fffd-9acd-495b-b093-95f1be506997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851718308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2851718308
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1492355571
Short name T48
Test name
Test status
Simulation time 37571559 ps
CPU time 0.75 seconds
Started Feb 07 12:38:29 PM PST 24
Finished Feb 07 12:38:34 PM PST 24
Peak memory 196180 kb
Host smart-67ff40b7-b28d-486c-b397-b85cb8936c53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492355571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1492355571
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/default/28.uart_stress_all.1658214287
Short name T135
Test name
Test status
Simulation time 333535419750 ps
CPU time 88.08 seconds
Started Feb 07 01:35:15 PM PST 24
Finished Feb 07 01:36:43 PM PST 24
Peak memory 199896 kb
Host smart-2a6b75df-c82e-4448-b0bd-bc800feca97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658214287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1658214287
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3900730202
Short name T161
Test name
Test status
Simulation time 203898685535 ps
CPU time 292.46 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:41:06 PM PST 24
Peak memory 199944 kb
Host smart-8dd97179-74bc-4b58-b2b0-cb81ce4ce4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900730202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3900730202
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1255150871
Short name T90
Test name
Test status
Simulation time 89307209 ps
CPU time 1.32 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 199280 kb
Host smart-b8bb2f9e-9ed5-4256-bf41-bcd9db1abfde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255150871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1255150871
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.576331295
Short name T143
Test name
Test status
Simulation time 78697017086 ps
CPU time 273.24 seconds
Started Feb 07 01:38:22 PM PST 24
Finished Feb 07 01:43:00 PM PST 24
Peak memory 199964 kb
Host smart-4ab057a6-cf5c-4986-aea0-c302e546f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576331295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.576331295
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.99593659
Short name T351
Test name
Test status
Simulation time 368465128112 ps
CPU time 110.95 seconds
Started Feb 07 01:36:39 PM PST 24
Finished Feb 07 01:38:38 PM PST 24
Peak memory 199972 kb
Host smart-791c2981-cad3-4a11-9051-ee319626949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99593659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.99593659
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1200195531
Short name T413
Test name
Test status
Simulation time 348403686935 ps
CPU time 78.08 seconds
Started Feb 07 01:31:11 PM PST 24
Finished Feb 07 01:32:30 PM PST 24
Peak memory 199940 kb
Host smart-168a8616-d19f-4588-bef7-91b4c7f74dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200195531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1200195531
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3364766695
Short name T397
Test name
Test status
Simulation time 127971979179 ps
CPU time 808.15 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 199924 kb
Host smart-4935b46c-2605-4449-bc9f-8aa4a32b408f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364766695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3364766695
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2063328047
Short name T76
Test name
Test status
Simulation time 177689693 ps
CPU time 0.92 seconds
Started Feb 07 01:30:32 PM PST 24
Finished Feb 07 01:30:36 PM PST 24
Peak memory 217348 kb
Host smart-71eb2088-b16e-4d63-b8f7-e1ef31987f35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063328047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2063328047
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4160330208
Short name T117
Test name
Test status
Simulation time 119363795891 ps
CPU time 108.22 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:40:31 PM PST 24
Peak memory 199988 kb
Host smart-b931f212-431e-4424-a3ae-203db15c7866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160330208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4160330208
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.993981524
Short name T80
Test name
Test status
Simulation time 231987105644 ps
CPU time 236.15 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 01:42:17 PM PST 24
Peak memory 214508 kb
Host smart-362c669d-e254-47b0-b54c-381a4e19ade1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993981524 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.993981524
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1063086807
Short name T3
Test name
Test status
Simulation time 15316431 ps
CPU time 0.59 seconds
Started Feb 07 12:38:32 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 194324 kb
Host smart-b9fc6e0e-4596-4025-9b17-29cdd8029a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063086807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1063086807
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.673191420
Short name T131
Test name
Test status
Simulation time 87621834415 ps
CPU time 133.34 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:41:48 PM PST 24
Peak memory 199964 kb
Host smart-46ef7483-e3a1-4e20-9663-a927e458c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673191420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.673191420
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.279187159
Short name T82
Test name
Test status
Simulation time 295466846443 ps
CPU time 192.18 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 01:41:33 PM PST 24
Peak memory 215920 kb
Host smart-8e4ae0bf-3023-4417-8fa6-2ad05b6ef86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279187159 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.279187159
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2019525573
Short name T47
Test name
Test status
Simulation time 15230813 ps
CPU time 0.7 seconds
Started Feb 07 12:38:43 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 195800 kb
Host smart-6ff2b89f-7bc8-419c-8a01-73320cedbfba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019525573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2019525573
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1057158234
Short name T85
Test name
Test status
Simulation time 145348546 ps
CPU time 1.23 seconds
Started Feb 07 12:38:32 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 198992 kb
Host smart-a63ce2a7-07e4-42b1-9a54-f7992a108980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057158234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1057158234
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1467615234
Short name T327
Test name
Test status
Simulation time 99254068241 ps
CPU time 83.19 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:32:42 PM PST 24
Peak memory 199924 kb
Host smart-47de62b1-8897-432b-9ec9-dfd9bea8a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467615234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1467615234
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.41011638
Short name T18
Test name
Test status
Simulation time 157492755597 ps
CPU time 67.77 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 200004 kb
Host smart-0d9fca66-3d57-4dc4-aeb1-4f02e4b1d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41011638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.41011638
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2692771758
Short name T391
Test name
Test status
Simulation time 26858838 ps
CPU time 0.56 seconds
Started Feb 07 12:39:27 PM PST 24
Finished Feb 07 12:39:29 PM PST 24
Peak memory 194324 kb
Host smart-12fd34c4-6f38-48d1-9483-80a4602960bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692771758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2692771758
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/default/1.uart_alert_test.402917571
Short name T506
Test name
Test status
Simulation time 29057730 ps
CPU time 0.52 seconds
Started Feb 07 01:30:54 PM PST 24
Finished Feb 07 01:30:55 PM PST 24
Peak memory 194340 kb
Host smart-3a84d41f-7504-47b9-9acb-b141c8cc7b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402917571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.402917571
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1321573304
Short name T358
Test name
Test status
Simulation time 829521473711 ps
CPU time 643.47 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:44:29 PM PST 24
Peak memory 224964 kb
Host smart-5e4baedb-07b5-4bab-88dd-c36e8f2c4df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321573304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1321573304
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.583590083
Short name T515
Test name
Test status
Simulation time 148043255663 ps
CPU time 129.9 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:36:47 PM PST 24
Peak memory 199628 kb
Host smart-d664d65a-a950-4c65-9753-cadaab55c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583590083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.583590083
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2300811322
Short name T119
Test name
Test status
Simulation time 78523753736 ps
CPU time 57.06 seconds
Started Feb 07 01:37:05 PM PST 24
Finished Feb 07 01:38:03 PM PST 24
Peak memory 199332 kb
Host smart-8438bcc6-9a9f-4f96-be5c-787d30748327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300811322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2300811322
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3519934825
Short name T318
Test name
Test status
Simulation time 247202778056 ps
CPU time 408.23 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:41:16 PM PST 24
Peak memory 200032 kb
Host smart-fa257dc1-c8ff-4e61-bc75-bd731e5e5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519934825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3519934825
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.21013673
Short name T126
Test name
Test status
Simulation time 150113700987 ps
CPU time 65.51 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:39:37 PM PST 24
Peak memory 199888 kb
Host smart-6a2c1eee-0c42-478e-9af0-f8fdd14f513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21013673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.21013673
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2173335382
Short name T88
Test name
Test status
Simulation time 74892186 ps
CPU time 0.92 seconds
Started Feb 07 12:38:51 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 198816 kb
Host smart-10d2d714-df6c-4b45-aec9-d134636ede4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173335382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2173335382
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3363136965
Short name T157
Test name
Test status
Simulation time 38681008880 ps
CPU time 46.88 seconds
Started Feb 07 01:39:03 PM PST 24
Finished Feb 07 01:39:51 PM PST 24
Peak memory 199920 kb
Host smart-d8c509df-b662-4f2f-b915-af5e2e140521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363136965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3363136965
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1448289556
Short name T159
Test name
Test status
Simulation time 65233826626 ps
CPU time 159.66 seconds
Started Feb 07 01:33:57 PM PST 24
Finished Feb 07 01:36:37 PM PST 24
Peak memory 208300 kb
Host smart-41685904-7972-46a1-9ade-1ee4788c7c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448289556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1448289556
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3168082952
Short name T209
Test name
Test status
Simulation time 106565943041 ps
CPU time 166.87 seconds
Started Feb 07 01:39:55 PM PST 24
Finished Feb 07 01:42:42 PM PST 24
Peak memory 199948 kb
Host smart-e85b11c1-3238-42f4-877f-567f293ea351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168082952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3168082952
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3234778889
Short name T188
Test name
Test status
Simulation time 145788281474 ps
CPU time 128.93 seconds
Started Feb 07 01:34:30 PM PST 24
Finished Feb 07 01:36:46 PM PST 24
Peak memory 199928 kb
Host smart-599c496d-8690-48fc-86ef-30d61e7a0550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234778889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3234778889
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3687220296
Short name T5
Test name
Test status
Simulation time 42844991 ps
CPU time 2.2 seconds
Started Feb 07 12:39:04 PM PST 24
Finished Feb 07 12:39:07 PM PST 24
Peak memory 200112 kb
Host smart-823bb1db-5951-47fb-a4cb-d0cf14802cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687220296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3687220296
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3698073508
Short name T578
Test name
Test status
Simulation time 237248752949 ps
CPU time 389.06 seconds
Started Feb 07 01:33:14 PM PST 24
Finished Feb 07 01:39:43 PM PST 24
Peak memory 199884 kb
Host smart-83bba978-01bf-428a-82ae-89856219e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698073508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3698073508
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.650289050
Short name T361
Test name
Test status
Simulation time 195367910436 ps
CPU time 40.37 seconds
Started Feb 07 01:39:08 PM PST 24
Finished Feb 07 01:39:49 PM PST 24
Peak memory 199980 kb
Host smart-05e7bf52-5aff-4605-a522-0097cd810117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650289050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.650289050
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1217657520
Short name T163
Test name
Test status
Simulation time 48183071395 ps
CPU time 47.5 seconds
Started Feb 07 01:40:31 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 199816 kb
Host smart-00bc2367-72a7-4d04-9171-6fd94a531174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217657520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1217657520
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.2294941775
Short name T384
Test name
Test status
Simulation time 243695710722 ps
CPU time 730.46 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:48:18 PM PST 24
Peak memory 199872 kb
Host smart-514e50c1-ff04-47c5-9daf-95f18e5d8bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294941775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2294941775
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all.3462316289
Short name T347
Test name
Test status
Simulation time 178362336055 ps
CPU time 594.48 seconds
Started Feb 07 01:36:44 PM PST 24
Finished Feb 07 01:46:42 PM PST 24
Peak memory 199920 kb
Host smart-9ba7d885-8f55-4cef-85c4-c8e395368825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462316289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3462316289
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3483515958
Short name T25
Test name
Test status
Simulation time 117608574897 ps
CPU time 173.88 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:39:42 PM PST 24
Peak memory 199912 kb
Host smart-f12acddb-2e79-4d7b-bd6d-12a9ce23af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483515958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3483515958
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2775706678
Short name T195
Test name
Test status
Simulation time 227871945561 ps
CPU time 95.04 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:40:13 PM PST 24
Peak memory 199652 kb
Host smart-ea78bf0f-36d8-4c60-af9d-4760a93f63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775706678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2775706678
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.225144036
Short name T181
Test name
Test status
Simulation time 188106361841 ps
CPU time 21.26 seconds
Started Feb 07 01:39:06 PM PST 24
Finished Feb 07 01:39:28 PM PST 24
Peak memory 199944 kb
Host smart-548ffc28-77d8-403b-b25a-4b20491c5680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225144036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.225144036
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.349564487
Short name T258
Test name
Test status
Simulation time 154594903647 ps
CPU time 51.91 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:32:25 PM PST 24
Peak memory 198700 kb
Host smart-6bdd2237-28e2-4d34-b248-2d5bddfdaf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349564487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.349564487
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1003939526
Short name T343
Test name
Test status
Simulation time 75382224384 ps
CPU time 125.84 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:40:44 PM PST 24
Peak memory 199904 kb
Host smart-6e3a5af4-1a08-4708-aa87-fda7bf5fda9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003939526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1003939526
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1149746061
Short name T307
Test name
Test status
Simulation time 62174053573 ps
CPU time 88.1 seconds
Started Feb 07 01:38:45 PM PST 24
Finished Feb 07 01:40:14 PM PST 24
Peak memory 199736 kb
Host smart-801689e5-bbb6-41d5-81fb-d58feea7bf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149746061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1149746061
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3553062366
Short name T316
Test name
Test status
Simulation time 103922876468 ps
CPU time 40.34 seconds
Started Feb 07 01:38:59 PM PST 24
Finished Feb 07 01:39:40 PM PST 24
Peak memory 199944 kb
Host smart-6c6b8321-fe70-49b3-8cef-0aab653bf1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553062366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3553062366
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1630678060
Short name T269
Test name
Test status
Simulation time 362312784890 ps
CPU time 41.06 seconds
Started Feb 07 01:39:06 PM PST 24
Finished Feb 07 01:39:48 PM PST 24
Peak memory 199948 kb
Host smart-c05d652f-c8d5-427c-a60f-74836a2506df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630678060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1630678060
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.129647797
Short name T315
Test name
Test status
Simulation time 154225661917 ps
CPU time 50.05 seconds
Started Feb 07 01:33:47 PM PST 24
Finished Feb 07 01:34:38 PM PST 24
Peak memory 200016 kb
Host smart-3e070836-e7c7-4f7c-9177-11397e8b01fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129647797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.129647797
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2213311145
Short name T219
Test name
Test status
Simulation time 129874956830 ps
CPU time 115.84 seconds
Started Feb 07 01:39:36 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 199896 kb
Host smart-7ca595b1-4012-49e0-98a7-28c1e1b81039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213311145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2213311145
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2583724467
Short name T274
Test name
Test status
Simulation time 141038316567 ps
CPU time 22.43 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:05 PM PST 24
Peak memory 199676 kb
Host smart-69937e14-5d3d-4965-8609-c87d87d3ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583724467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2583724467
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3811475124
Short name T152
Test name
Test status
Simulation time 131138655474 ps
CPU time 50.89 seconds
Started Feb 07 01:39:54 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 199688 kb
Host smart-5015127e-5143-4aad-ae47-b4e858e1cd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811475124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3811475124
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3250022003
Short name T364
Test name
Test status
Simulation time 129767769576 ps
CPU time 182.82 seconds
Started Feb 07 01:39:53 PM PST 24
Finished Feb 07 01:42:56 PM PST 24
Peak memory 199880 kb
Host smart-a603fcf5-b33a-4190-899e-5f60cea230da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250022003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3250022003
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1158780055
Short name T210
Test name
Test status
Simulation time 59171951941 ps
CPU time 30.18 seconds
Started Feb 07 01:40:02 PM PST 24
Finished Feb 07 01:40:34 PM PST 24
Peak memory 199996 kb
Host smart-beedeac1-6099-4505-8008-11b3b99345bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158780055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1158780055
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2825333896
Short name T206
Test name
Test status
Simulation time 84610408988 ps
CPU time 35.34 seconds
Started Feb 07 01:40:01 PM PST 24
Finished Feb 07 01:40:37 PM PST 24
Peak memory 199928 kb
Host smart-bbd32936-bccc-428e-af00-db64fb6277bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825333896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2825333896
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1535240766
Short name T177
Test name
Test status
Simulation time 9121750178 ps
CPU time 13.88 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:40:42 PM PST 24
Peak memory 199896 kb
Host smart-70154455-47ae-4491-88fc-04a8cb875d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535240766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1535240766
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1058148490
Short name T254
Test name
Test status
Simulation time 17877465364 ps
CPU time 16.83 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:31:49 PM PST 24
Peak memory 199888 kb
Host smart-20cc2051-851d-446c-816c-00bca92da87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058148490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1058148490
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3293037624
Short name T370
Test name
Test status
Simulation time 236313733369 ps
CPU time 373.2 seconds
Started Feb 07 01:30:25 PM PST 24
Finished Feb 07 01:36:44 PM PST 24
Peak memory 216072 kb
Host smart-b1653e3d-cd51-4a73-a937-a393c53dec33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293037624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3293037624
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3082830972
Short name T376
Test name
Test status
Simulation time 363177164097 ps
CPU time 49.89 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:33:44 PM PST 24
Peak memory 199956 kb
Host smart-e44e780d-f35c-4876-9b06-f77a961fb2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082830972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3082830972
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.81983487
Short name T216
Test name
Test status
Simulation time 32003606187 ps
CPU time 49.63 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:33:43 PM PST 24
Peak memory 199572 kb
Host smart-fcf9c40d-1ffa-4bbb-a516-1bf1dd1e662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81983487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.81983487
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1066194134
Short name T160
Test name
Test status
Simulation time 10278390400 ps
CPU time 11.93 seconds
Started Feb 07 01:38:46 PM PST 24
Finished Feb 07 01:38:58 PM PST 24
Peak memory 199924 kb
Host smart-2347df04-e89d-490e-b666-26c292dda33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066194134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1066194134
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.29954968
Short name T230
Test name
Test status
Simulation time 34735675787 ps
CPU time 51.93 seconds
Started Feb 07 01:33:37 PM PST 24
Finished Feb 07 01:34:30 PM PST 24
Peak memory 199964 kb
Host smart-79381365-2cf1-4441-a54e-4747e65cf017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29954968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.29954968
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3289280619
Short name T200
Test name
Test status
Simulation time 12763166805 ps
CPU time 22.13 seconds
Started Feb 07 01:39:11 PM PST 24
Finished Feb 07 01:39:34 PM PST 24
Peak memory 199264 kb
Host smart-dff3843e-82c2-49c6-b8ab-328d60e745c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289280619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3289280619
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3488693984
Short name T156
Test name
Test status
Simulation time 108520848461 ps
CPU time 43.47 seconds
Started Feb 07 01:39:11 PM PST 24
Finished Feb 07 01:39:55 PM PST 24
Peak memory 199220 kb
Host smart-68aafdef-eabc-459f-94fc-fe3056b02e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488693984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3488693984
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1084404406
Short name T382
Test name
Test status
Simulation time 78691394672 ps
CPU time 38.24 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:30 PM PST 24
Peak memory 199896 kb
Host smart-401f8a66-aa5b-4c1d-a019-9a21d6aaf51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084404406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1084404406
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4131803294
Short name T312
Test name
Test status
Simulation time 22872774002 ps
CPU time 7.14 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:00 PM PST 24
Peak memory 199484 kb
Host smart-ac675b00-8ada-47e8-96d3-df4d3fc41345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131803294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4131803294
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3444063317
Short name T1202
Test name
Test status
Simulation time 202182857549 ps
CPU time 23.53 seconds
Started Feb 07 01:40:01 PM PST 24
Finished Feb 07 01:40:26 PM PST 24
Peak memory 199908 kb
Host smart-8bbd29a7-f2ac-403a-9311-48e47103fdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444063317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3444063317
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2588357841
Short name T236
Test name
Test status
Simulation time 169493739598 ps
CPU time 92.13 seconds
Started Feb 07 01:40:06 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 199468 kb
Host smart-05bdb4d5-8492-43f1-8113-0887007fea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588357841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2588357841
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3902614796
Short name T183
Test name
Test status
Simulation time 63536476073 ps
CPU time 30.04 seconds
Started Feb 07 01:40:03 PM PST 24
Finished Feb 07 01:40:34 PM PST 24
Peak memory 199960 kb
Host smart-a23fbb8e-8dab-47ed-9e71-79c1a9462142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902614796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3902614796
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2319631371
Short name T284
Test name
Test status
Simulation time 190052019823 ps
CPU time 38.95 seconds
Started Feb 07 01:40:17 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 199920 kb
Host smart-3fc67128-0e85-47d2-9273-3c2260c9a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319631371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2319631371
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4081811669
Short name T140
Test name
Test status
Simulation time 141692772690 ps
CPU time 64.3 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 199896 kb
Host smart-71eca142-e88b-4d0b-9ceb-506ba1cae5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081811669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4081811669
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1878042940
Short name T916
Test name
Test status
Simulation time 25537131475 ps
CPU time 223.36 seconds
Started Feb 07 01:36:09 PM PST 24
Finished Feb 07 01:39:53 PM PST 24
Peak memory 208308 kb
Host smart-1b85d18d-0c69-49ac-a1d7-c4e528251a44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878042940 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1878042940
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2506561243
Short name T328
Test name
Test status
Simulation time 26788625929 ps
CPU time 6.93 seconds
Started Feb 07 01:38:18 PM PST 24
Finished Feb 07 01:38:26 PM PST 24
Peak memory 199484 kb
Host smart-9ce5f789-92bc-4756-8b77-c7a7857014f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506561243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2506561243
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2745865361
Short name T383
Test name
Test status
Simulation time 351847176634 ps
CPU time 1142.65 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:57:43 PM PST 24
Peak memory 229860 kb
Host smart-be6794e4-0be8-4c84-80e8-3f94a18736f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745865361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2745865361
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1725780954
Short name T466
Test name
Test status
Simulation time 44173802 ps
CPU time 0.58 seconds
Started Feb 07 12:38:52 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 194268 kb
Host smart-a57f4000-57ff-4a41-bf83-bdb0ad04ff5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725780954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1725780954
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3551702900
Short name T204
Test name
Test status
Simulation time 109883889221 ps
CPU time 93.95 seconds
Started Feb 07 01:30:42 PM PST 24
Finished Feb 07 01:32:18 PM PST 24
Peak memory 198568 kb
Host smart-6e6dc53f-89c7-4d4b-8a36-c7a8a1669529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551702900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3551702900
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2166749528
Short name T330
Test name
Test status
Simulation time 161189229417 ps
CPU time 140.66 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:41:03 PM PST 24
Peak memory 200036 kb
Host smart-9a63de66-4731-4526-9a44-15dca9425e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166749528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2166749528
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1451781101
Short name T155
Test name
Test status
Simulation time 244001183019 ps
CPU time 53.56 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:33:48 PM PST 24
Peak memory 199948 kb
Host smart-66f89c8e-5e75-4bf9-903e-2dd95a037710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451781101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1451781101
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.192658893
Short name T386
Test name
Test status
Simulation time 66724195328 ps
CPU time 219.56 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:42:25 PM PST 24
Peak memory 199920 kb
Host smart-2116c407-168f-4145-9ec0-5cf2830101a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192658893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.192658893
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3866845314
Short name T339
Test name
Test status
Simulation time 24675782229 ps
CPU time 37.85 seconds
Started Feb 07 01:38:50 PM PST 24
Finished Feb 07 01:39:29 PM PST 24
Peak memory 199936 kb
Host smart-76e38443-e28b-4f47-a783-266bb49eb9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866845314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3866845314
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3617526280
Short name T268
Test name
Test status
Simulation time 23902916894 ps
CPU time 40.76 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:39:26 PM PST 24
Peak memory 199768 kb
Host smart-08163c7b-b785-4d74-a31f-3017fa9560d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617526280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3617526280
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2182827493
Short name T283
Test name
Test status
Simulation time 71393058502 ps
CPU time 31.68 seconds
Started Feb 07 01:38:46 PM PST 24
Finished Feb 07 01:39:18 PM PST 24
Peak memory 199928 kb
Host smart-670febb7-37dd-48bf-8acb-e1efbee25b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182827493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2182827493
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4093983928
Short name T282
Test name
Test status
Simulation time 100979257720 ps
CPU time 46.23 seconds
Started Feb 07 01:39:00 PM PST 24
Finished Feb 07 01:39:47 PM PST 24
Peak memory 199936 kb
Host smart-b4696c65-d993-4e5a-aba3-b4902b222129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093983928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4093983928
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2846794266
Short name T168
Test name
Test status
Simulation time 100764257644 ps
CPU time 130.43 seconds
Started Feb 07 01:39:05 PM PST 24
Finished Feb 07 01:41:16 PM PST 24
Peak memory 199992 kb
Host smart-517be81e-499a-46c0-b018-f0635960d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846794266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2846794266
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1900124008
Short name T249
Test name
Test status
Simulation time 41729031965 ps
CPU time 19.3 seconds
Started Feb 07 01:39:11 PM PST 24
Finished Feb 07 01:39:31 PM PST 24
Peak memory 199456 kb
Host smart-bc6ef3f3-f7b4-444e-ab2f-d5aeaee638cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900124008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1900124008
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4018359842
Short name T190
Test name
Test status
Simulation time 23915445177 ps
CPU time 22.63 seconds
Started Feb 07 01:39:24 PM PST 24
Finished Feb 07 01:39:47 PM PST 24
Peak memory 199364 kb
Host smart-5c54d99f-0bd7-4641-a2b7-c8f5b3313e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018359842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4018359842
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1162376339
Short name T335
Test name
Test status
Simulation time 8389691320 ps
CPU time 15.77 seconds
Started Feb 07 01:39:19 PM PST 24
Finished Feb 07 01:39:36 PM PST 24
Peak memory 199724 kb
Host smart-e8a5644c-3466-4db4-9de9-c0541492dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162376339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1162376339
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.622121249
Short name T333
Test name
Test status
Simulation time 80285692402 ps
CPU time 47.46 seconds
Started Feb 07 01:34:01 PM PST 24
Finished Feb 07 01:34:49 PM PST 24
Peak memory 199940 kb
Host smart-76271bb4-ad46-4318-b93e-e061a55a23e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622121249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.622121249
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.635000259
Short name T761
Test name
Test status
Simulation time 153403975493 ps
CPU time 63.67 seconds
Started Feb 07 01:33:59 PM PST 24
Finished Feb 07 01:35:04 PM PST 24
Peak memory 199932 kb
Host smart-f7ed442f-4836-4be8-a375-799cbc2ae578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635000259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.635000259
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.727978166
Short name T226
Test name
Test status
Simulation time 25752693273 ps
CPU time 18.85 seconds
Started Feb 07 01:39:40 PM PST 24
Finished Feb 07 01:40:00 PM PST 24
Peak memory 199960 kb
Host smart-e5dbfd71-a16f-45ad-ab1f-e1b5ec609e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727978166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.727978166
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2238213410
Short name T338
Test name
Test status
Simulation time 120373605505 ps
CPU time 14.34 seconds
Started Feb 07 01:34:19 PM PST 24
Finished Feb 07 01:34:41 PM PST 24
Peak memory 199928 kb
Host smart-2775d288-12f0-4578-9160-508df26c1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238213410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2238213410
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2953718937
Short name T439
Test name
Test status
Simulation time 84382062056 ps
CPU time 1238.7 seconds
Started Feb 07 01:34:27 PM PST 24
Finished Feb 07 01:55:13 PM PST 24
Peak memory 216528 kb
Host smart-58e6d1e4-cddf-466f-a469-888a74e67b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953718937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2953718937
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2191712711
Short name T317
Test name
Test status
Simulation time 174766338057 ps
CPU time 73.99 seconds
Started Feb 07 01:39:49 PM PST 24
Finished Feb 07 01:41:03 PM PST 24
Peak memory 199896 kb
Host smart-d0dbdeaa-491b-4408-9856-cf63cd0d4794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191712711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2191712711
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.268141623
Short name T211
Test name
Test status
Simulation time 71371165292 ps
CPU time 116.93 seconds
Started Feb 07 01:39:53 PM PST 24
Finished Feb 07 01:41:50 PM PST 24
Peak memory 199992 kb
Host smart-cce684a4-533d-41b1-a049-6127b7595914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268141623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.268141623
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2648809741
Short name T362
Test name
Test status
Simulation time 75492411148 ps
CPU time 106.39 seconds
Started Feb 07 01:39:51 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 199968 kb
Host smart-0634d2e0-f796-4a08-9eea-6afc897607e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648809741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2648809741
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.357275955
Short name T289
Test name
Test status
Simulation time 117112688746 ps
CPU time 177.61 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:37:35 PM PST 24
Peak memory 199272 kb
Host smart-567017ae-e31b-45ba-a4bf-e934d3c10e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357275955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.357275955
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_stress_all.1223829375
Short name T267
Test name
Test status
Simulation time 331591300363 ps
CPU time 2541.47 seconds
Started Feb 07 01:34:39 PM PST 24
Finished Feb 07 02:17:02 PM PST 24
Peak memory 199912 kb
Host smart-8b1e2f8d-2d03-4d73-8796-0de8e46e2d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223829375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1223829375
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_fifo_full.724538994
Short name T290
Test name
Test status
Simulation time 71248133112 ps
CPU time 49.15 seconds
Started Feb 07 01:34:41 PM PST 24
Finished Feb 07 01:35:31 PM PST 24
Peak memory 199920 kb
Host smart-b086b9d9-192e-45d6-9d26-1cbed1165b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724538994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.724538994
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_stress_all.1197844471
Short name T303
Test name
Test status
Simulation time 96284687780 ps
CPU time 336.62 seconds
Started Feb 07 01:34:43 PM PST 24
Finished Feb 07 01:40:20 PM PST 24
Peak memory 200000 kb
Host smart-9cf1acac-69d1-477c-b5eb-fe58430d79b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197844471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1197844471
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1246600621
Short name T264
Test name
Test status
Simulation time 38575894436 ps
CPU time 81.4 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:41:50 PM PST 24
Peak memory 199916 kb
Host smart-7c416a0b-09f3-4429-92f2-5216845de432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246600621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1246600621
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2570264936
Short name T285
Test name
Test status
Simulation time 96415425086 ps
CPU time 40.89 seconds
Started Feb 07 01:40:22 PM PST 24
Finished Feb 07 01:41:04 PM PST 24
Peak memory 199960 kb
Host smart-9d1f2f0a-4e4b-4de1-aec1-baa9c4f6a75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570264936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2570264936
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.777223654
Short name T323
Test name
Test status
Simulation time 80648205445 ps
CPU time 67.79 seconds
Started Feb 07 01:40:22 PM PST 24
Finished Feb 07 01:41:31 PM PST 24
Peak memory 199944 kb
Host smart-aad534b7-48ab-41e3-b523-8a54e3d506f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777223654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.777223654
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2388302027
Short name T288
Test name
Test status
Simulation time 41686007522 ps
CPU time 17.65 seconds
Started Feb 07 01:40:24 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 199904 kb
Host smart-c90961a2-4be2-4d40-bf09-89b0c58c7cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388302027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2388302027
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1222533291
Short name T287
Test name
Test status
Simulation time 10766785556 ps
CPU time 13.5 seconds
Started Feb 07 01:35:22 PM PST 24
Finished Feb 07 01:35:36 PM PST 24
Peak memory 198136 kb
Host smart-32f89a1b-664f-4b64-bf81-ab5112e6b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222533291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1222533291
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2548255597
Short name T286
Test name
Test status
Simulation time 195616518203 ps
CPU time 53.73 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:37:00 PM PST 24
Peak memory 199888 kb
Host smart-d8c4d677-2c56-44ad-b410-ae230f5725ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548255597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2548255597
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.508172621
Short name T292
Test name
Test status
Simulation time 163301528836 ps
CPU time 1135.26 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:55:09 PM PST 24
Peak memory 225524 kb
Host smart-0706c58d-f51b-4f13-bdad-8bdc124fd5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508172621 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.508172621
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.596213558
Short name T367
Test name
Test status
Simulation time 139176796171 ps
CPU time 378.72 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 215792 kb
Host smart-ad0e0af4-d128-45f7-a2b9-7439b1f78460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596213558 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.596213558
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3846384186
Short name T247
Test name
Test status
Simulation time 44837508980 ps
CPU time 31.39 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:37:21 PM PST 24
Peak memory 199404 kb
Host smart-48962744-8878-4d33-a121-bbd7a6fdaccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846384186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3846384186
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2758883885
Short name T253
Test name
Test status
Simulation time 114223502555 ps
CPU time 330.47 seconds
Started Feb 07 01:37:04 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 216744 kb
Host smart-e8c12ab3-e70a-4c28-897f-242222b88dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758883885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2758883885
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2551889463
Short name T294
Test name
Test status
Simulation time 7801732924 ps
CPU time 7.42 seconds
Started Feb 07 01:37:41 PM PST 24
Finished Feb 07 01:37:49 PM PST 24
Peak memory 198828 kb
Host smart-13be53b8-cbb4-48a5-a6fd-27fbb8cdb8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551889463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2551889463
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4186072671
Short name T291
Test name
Test status
Simulation time 115065868165 ps
CPU time 160.56 seconds
Started Feb 07 01:31:51 PM PST 24
Finished Feb 07 01:34:32 PM PST 24
Peak memory 199788 kb
Host smart-9bef3949-f1b3-420e-8b17-c70bb9ec470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186072671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4186072671
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2201000255
Short name T357
Test name
Test status
Simulation time 48305301015 ps
CPU time 38.87 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:38:51 PM PST 24
Peak memory 200008 kb
Host smart-2e25a23c-cfbf-4388-93f5-f02a87a68819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201000255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2201000255
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.2716016776
Short name T213
Test name
Test status
Simulation time 196684437601 ps
CPU time 308.23 seconds
Started Feb 07 01:32:50 PM PST 24
Finished Feb 07 01:37:59 PM PST 24
Peak memory 199884 kb
Host smart-6173e3bb-4e49-49ec-9952-eb1ef0a3d036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716016776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2716016776
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3873972615
Short name T293
Test name
Test status
Simulation time 327369592810 ps
CPU time 1052.18 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:56:12 PM PST 24
Peak memory 224668 kb
Host smart-78f4e953-1cba-4b6d-9099-d9a5c2a0a9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873972615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3873972615
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.581280481
Short name T1275
Test name
Test status
Simulation time 19550425 ps
CPU time 0.68 seconds
Started Feb 07 12:38:32 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 194748 kb
Host smart-f9c38549-710b-45eb-8ba9-04cf2722e71d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581280481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.581280481
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4200833987
Short name T1250
Test name
Test status
Simulation time 33967112 ps
CPU time 1.46 seconds
Started Feb 07 12:38:36 PM PST 24
Finished Feb 07 12:38:41 PM PST 24
Peak memory 197500 kb
Host smart-0475b909-b5fc-4fb5-9223-988bcd81a3c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200833987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4200833987
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1181485228
Short name T35
Test name
Test status
Simulation time 20481224 ps
CPU time 0.58 seconds
Started Feb 07 12:38:34 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195504 kb
Host smart-f9f06f2a-41a0-4b8b-b6ad-05d5f29668ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181485228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1181485228
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1509807175
Short name T477
Test name
Test status
Simulation time 84507821 ps
CPU time 1.24 seconds
Started Feb 07 12:38:35 PM PST 24
Finished Feb 07 12:38:41 PM PST 24
Peak memory 199980 kb
Host smart-a0c3bf4e-0ca3-47c3-ae09-54c9abd42716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509807175 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1509807175
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2646660677
Short name T462
Test name
Test status
Simulation time 43241188 ps
CPU time 0.65 seconds
Started Feb 07 12:38:36 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195328 kb
Host smart-ee5e632c-742d-4618-91ba-b9e4200b1133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646660677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2646660677
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.638433584
Short name T58
Test name
Test status
Simulation time 17041839 ps
CPU time 0.61 seconds
Started Feb 07 12:38:32 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 194276 kb
Host smart-aa51c47a-752b-4ed1-ab45-6228ccf4a83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638433584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.638433584
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4007215215
Short name T1260
Test name
Test status
Simulation time 58768225 ps
CPU time 0.63 seconds
Started Feb 07 12:38:30 PM PST 24
Finished Feb 07 12:38:34 PM PST 24
Peak memory 195472 kb
Host smart-1785d707-d679-466c-aa68-07bc846b0fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007215215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4007215215
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2009402429
Short name T388
Test name
Test status
Simulation time 383726795 ps
CPU time 1.27 seconds
Started Feb 07 12:38:31 PM PST 24
Finished Feb 07 12:38:36 PM PST 24
Peak memory 199024 kb
Host smart-52a926a4-73d4-49ed-8ae6-30e17de694a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009402429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2009402429
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3973792306
Short name T67
Test name
Test status
Simulation time 20224168 ps
CPU time 0.71 seconds
Started Feb 07 12:38:34 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 194892 kb
Host smart-d3f6a1cd-ec2c-413c-8c99-9d81788e4edd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973792306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3973792306
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.326329751
Short name T479
Test name
Test status
Simulation time 145600261 ps
CPU time 1.66 seconds
Started Feb 07 12:38:31 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 197188 kb
Host smart-261cf8f6-48b7-4cae-9396-672b087bcb90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326329751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.326329751
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2940396018
Short name T34
Test name
Test status
Simulation time 37974346 ps
CPU time 0.56 seconds
Started Feb 07 12:38:34 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195360 kb
Host smart-ed0a9664-938c-414f-a6a9-a5e8de62c5a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940396018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2940396018
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2794567346
Short name T460
Test name
Test status
Simulation time 371879642 ps
CPU time 1.01 seconds
Started Feb 07 12:38:36 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 200140 kb
Host smart-d6829152-4b69-4144-a5ee-b1d8dbdd3841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794567346 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2794567346
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1048028961
Short name T50
Test name
Test status
Simulation time 40297810 ps
CPU time 0.61 seconds
Started Feb 07 12:38:36 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195280 kb
Host smart-f36f22f7-3cc3-4b08-89dc-678ef37388ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048028961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1048028961
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3964871946
Short name T73
Test name
Test status
Simulation time 62486746 ps
CPU time 0.6 seconds
Started Feb 07 12:38:35 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195484 kb
Host smart-545dac02-8c56-4716-96a4-4a67c647b376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964871946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3964871946
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.652140929
Short name T1295
Test name
Test status
Simulation time 36266983 ps
CPU time 1.75 seconds
Started Feb 07 12:38:33 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 200180 kb
Host smart-90f48d79-fb8a-4c2e-9da5-32a92b156fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652140929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.652140929
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.479476207
Short name T107
Test name
Test status
Simulation time 38600671 ps
CPU time 0.67 seconds
Started Feb 07 12:38:56 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 197728 kb
Host smart-4327931d-f2f7-463e-acae-cf4590e270cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479476207 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.479476207
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2905584794
Short name T53
Test name
Test status
Simulation time 35161241 ps
CPU time 0.55 seconds
Started Feb 07 12:38:52 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 195452 kb
Host smart-48ed2809-7824-4b6d-8c71-fbf12c08ec1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905584794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2905584794
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3825281797
Short name T1258
Test name
Test status
Simulation time 39999520 ps
CPU time 0.57 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:54 PM PST 24
Peak memory 194352 kb
Host smart-6ad744dd-0b3c-4a96-8a67-f304573496b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825281797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3825281797
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2098701520
Short name T1248
Test name
Test status
Simulation time 52100273 ps
CPU time 0.62 seconds
Started Feb 07 12:38:52 PM PST 24
Finished Feb 07 12:38:54 PM PST 24
Peak memory 195508 kb
Host smart-c1b2f57c-6ade-4f76-a57e-bb5e64b489ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098701520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2098701520
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3580744604
Short name T8
Test name
Test status
Simulation time 397761914 ps
CPU time 1.58 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:56 PM PST 24
Peak memory 200140 kb
Host smart-84c5886a-4ee1-4d0b-b407-a85a48bcd53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580744604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3580744604
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3951164648
Short name T1246
Test name
Test status
Simulation time 306297073 ps
CPU time 1.49 seconds
Started Feb 07 12:38:55 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 199264 kb
Host smart-8e716253-5e90-4fe5-a3bf-aeea852ee705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951164648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3951164648
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.155953444
Short name T1291
Test name
Test status
Simulation time 89127320 ps
CPU time 0.84 seconds
Started Feb 07 12:38:51 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 199888 kb
Host smart-ca33ecfe-5180-40ee-a545-54ab0ef6131b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155953444 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.155953444
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3411395293
Short name T2
Test name
Test status
Simulation time 49869925 ps
CPU time 0.59 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 195296 kb
Host smart-588ae995-af72-4a98-8f11-e7a89715951f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411395293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3411395293
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3457543075
Short name T74
Test name
Test status
Simulation time 41942693 ps
CPU time 0.63 seconds
Started Feb 07 12:38:56 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 194552 kb
Host smart-89c560ad-0d9d-4937-80dd-e9ae6ad76d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457543075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3457543075
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1232428272
Short name T474
Test name
Test status
Simulation time 114871351 ps
CPU time 1.98 seconds
Started Feb 07 12:38:56 PM PST 24
Finished Feb 07 12:38:59 PM PST 24
Peak memory 200220 kb
Host smart-04562e56-fdf5-44c4-951c-e5050cbbecae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232428272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1232428272
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1486402428
Short name T86
Test name
Test status
Simulation time 308733949 ps
CPU time 1.38 seconds
Started Feb 07 12:38:54 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 199212 kb
Host smart-b7adcd1f-6ef6-4ff0-9f3d-4992ee89155b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486402428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1486402428
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.803948732
Short name T68
Test name
Test status
Simulation time 14578484 ps
CPU time 0.7 seconds
Started Feb 07 12:39:03 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 197532 kb
Host smart-6ac02bf1-bea4-42b0-9197-c4450fd82a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803948732 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.803948732
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2824667171
Short name T455
Test name
Test status
Simulation time 48350437 ps
CPU time 0.58 seconds
Started Feb 07 12:39:02 PM PST 24
Finished Feb 07 12:39:03 PM PST 24
Peak memory 195332 kb
Host smart-9a71cd9f-8268-4d32-80de-e8e3e26949f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824667171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2824667171
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4240697631
Short name T451
Test name
Test status
Simulation time 16254064 ps
CPU time 0.58 seconds
Started Feb 07 12:38:56 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 194264 kb
Host smart-c9828c8b-52fb-4618-becf-664f63033158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240697631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4240697631
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.205977761
Short name T464
Test name
Test status
Simulation time 85251654 ps
CPU time 0.71 seconds
Started Feb 07 12:39:04 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 196960 kb
Host smart-f9afd367-a612-4a2a-9e8f-01201431c9af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205977761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.205977761
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2734172691
Short name T1263
Test name
Test status
Simulation time 95477765 ps
CPU time 1.28 seconds
Started Feb 07 12:38:55 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 200032 kb
Host smart-a9f7dab9-105a-4634-b4ca-fdae4ef1f27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734172691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2734172691
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3237103174
Short name T486
Test name
Test status
Simulation time 264030685 ps
CPU time 1.29 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 199264 kb
Host smart-067168d8-4116-4524-9795-167a58a746d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237103174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3237103174
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1993614464
Short name T1299
Test name
Test status
Simulation time 83201103 ps
CPU time 1.23 seconds
Started Feb 07 12:39:03 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 200020 kb
Host smart-e2487f14-ad39-4473-9c89-2f7ff0806b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993614464 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1993614464
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.454399941
Short name T1293
Test name
Test status
Simulation time 23553605 ps
CPU time 0.61 seconds
Started Feb 07 12:39:02 PM PST 24
Finished Feb 07 12:39:04 PM PST 24
Peak memory 195404 kb
Host smart-52fc720f-29e7-4cdb-b080-26e2275e99af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454399941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.454399941
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.512324360
Short name T390
Test name
Test status
Simulation time 19681506 ps
CPU time 0.54 seconds
Started Feb 07 12:39:04 PM PST 24
Finished Feb 07 12:39:06 PM PST 24
Peak memory 194324 kb
Host smart-da4d46db-1840-4936-a112-da3344662968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512324360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.512324360
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.402223479
Short name T1286
Test name
Test status
Simulation time 24826841 ps
CPU time 0.69 seconds
Started Feb 07 12:39:07 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 196824 kb
Host smart-355dc6e1-a48b-480f-b78d-963393e84148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402223479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.402223479
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1295853333
Short name T465
Test name
Test status
Simulation time 117707804 ps
CPU time 1.5 seconds
Started Feb 07 12:39:03 PM PST 24
Finished Feb 07 12:39:06 PM PST 24
Peak memory 200076 kb
Host smart-7d41c50e-bff4-4f30-b7d7-7a1133f102e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295853333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1295853333
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.347474293
Short name T37
Test name
Test status
Simulation time 582618309 ps
CPU time 1.03 seconds
Started Feb 07 12:39:05 PM PST 24
Finished Feb 07 12:39:07 PM PST 24
Peak memory 198784 kb
Host smart-9adb6648-829e-4930-a399-7a0111d45959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347474293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.347474293
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1598837131
Short name T1273
Test name
Test status
Simulation time 21138937 ps
CPU time 0.93 seconds
Started Feb 07 12:39:06 PM PST 24
Finished Feb 07 12:39:08 PM PST 24
Peak memory 199840 kb
Host smart-82c28307-1510-4400-8e20-5a2a2ef216b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598837131 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1598837131
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1239576764
Short name T463
Test name
Test status
Simulation time 13346862 ps
CPU time 0.6 seconds
Started Feb 07 12:39:07 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 195400 kb
Host smart-69aa1baa-c8cb-4607-a9b4-7aeae74d57a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239576764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1239576764
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1231877504
Short name T1265
Test name
Test status
Simulation time 11382162 ps
CPU time 0.61 seconds
Started Feb 07 12:39:04 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 194236 kb
Host smart-e5cf943c-41d0-494b-9acc-2451bf1bf718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231877504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1231877504
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1175787548
Short name T476
Test name
Test status
Simulation time 23600499 ps
CPU time 0.74 seconds
Started Feb 07 12:39:05 PM PST 24
Finished Feb 07 12:39:07 PM PST 24
Peak memory 196984 kb
Host smart-446e34b1-ac61-4f20-8969-26bf8b581711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175787548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1175787548
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1902271616
Short name T42
Test name
Test status
Simulation time 105190737 ps
CPU time 1.23 seconds
Started Feb 07 12:39:03 PM PST 24
Finished Feb 07 12:39:06 PM PST 24
Peak memory 200136 kb
Host smart-898afc52-da4b-4cfd-a6a6-f4a0c04cd58b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902271616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1902271616
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3021762521
Short name T84
Test name
Test status
Simulation time 81888815 ps
CPU time 1.2 seconds
Started Feb 07 12:39:03 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 199188 kb
Host smart-42d3a328-032d-4f02-9974-559609396ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021762521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3021762521
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2786738550
Short name T39
Test name
Test status
Simulation time 30462384 ps
CPU time 1.21 seconds
Started Feb 07 12:39:07 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 200208 kb
Host smart-71c28efa-4964-4ce4-a0f6-f3635e0c38bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786738550 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2786738550
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1932185328
Short name T55
Test name
Test status
Simulation time 39059508 ps
CPU time 0.58 seconds
Started Feb 07 12:39:05 PM PST 24
Finished Feb 07 12:39:06 PM PST 24
Peak memory 195376 kb
Host smart-80eb5528-c044-4ea0-8e99-5b81722296cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932185328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1932185328
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.694526038
Short name T110
Test name
Test status
Simulation time 26634699 ps
CPU time 0.57 seconds
Started Feb 07 12:39:04 PM PST 24
Finished Feb 07 12:39:05 PM PST 24
Peak memory 194348 kb
Host smart-05b9c2d8-ea02-490b-80ab-b639ab0e9130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694526038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.694526038
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1277355075
Short name T1269
Test name
Test status
Simulation time 15288429 ps
CPU time 0.64 seconds
Started Feb 07 12:39:06 PM PST 24
Finished Feb 07 12:39:07 PM PST 24
Peak memory 195512 kb
Host smart-d6681bd5-1f0e-4264-afa6-2b2fbc364af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277355075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1277355075
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.562050740
Short name T32
Test name
Test status
Simulation time 200878025 ps
CPU time 1.09 seconds
Started Feb 07 12:39:08 PM PST 24
Finished Feb 07 12:39:11 PM PST 24
Peak memory 198852 kb
Host smart-9d413eb6-1b7b-4db2-9cba-6b526ba2e40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562050740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.562050740
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1175091632
Short name T44
Test name
Test status
Simulation time 103879276 ps
CPU time 0.85 seconds
Started Feb 07 12:39:09 PM PST 24
Finished Feb 07 12:39:11 PM PST 24
Peak memory 199844 kb
Host smart-b43c9423-fafb-4a02-8741-8cde0f19a35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175091632 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1175091632
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1164127954
Short name T458
Test name
Test status
Simulation time 84385514 ps
CPU time 0.58 seconds
Started Feb 07 12:39:14 PM PST 24
Finished Feb 07 12:39:15 PM PST 24
Peak memory 195292 kb
Host smart-ad0d4b49-37c9-47c9-8a68-1e30014d4731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164127954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1164127954
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2798721931
Short name T1283
Test name
Test status
Simulation time 57896225 ps
CPU time 0.54 seconds
Started Feb 07 12:39:07 PM PST 24
Finished Feb 07 12:39:08 PM PST 24
Peak memory 194344 kb
Host smart-1a2c2886-e8ba-4270-9da0-b92658200225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798721931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2798721931
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3292486671
Short name T484
Test name
Test status
Simulation time 60677516 ps
CPU time 0.78 seconds
Started Feb 07 12:39:14 PM PST 24
Finished Feb 07 12:39:16 PM PST 24
Peak memory 197016 kb
Host smart-cb7a694a-0248-4830-851c-c0b09107fd85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292486671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3292486671
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2177760790
Short name T461
Test name
Test status
Simulation time 52387044 ps
CPU time 1.34 seconds
Started Feb 07 12:39:14 PM PST 24
Finished Feb 07 12:39:16 PM PST 24
Peak memory 200056 kb
Host smart-ed15816a-e7bd-4230-982e-028e7afaaeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177760790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2177760790
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.645945285
Short name T87
Test name
Test status
Simulation time 173958862 ps
CPU time 1.22 seconds
Started Feb 07 12:39:06 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 198960 kb
Host smart-25a6a11d-3d4e-42f7-aa36-36e294aa98cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645945285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.645945285
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1104716881
Short name T108
Test name
Test status
Simulation time 35020372 ps
CPU time 0.69 seconds
Started Feb 07 12:39:08 PM PST 24
Finished Feb 07 12:39:10 PM PST 24
Peak memory 197872 kb
Host smart-75c2fa1e-a6c4-42b8-9d3c-553a7b47eef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104716881 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1104716881
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3508253186
Short name T10
Test name
Test status
Simulation time 12980858 ps
CPU time 0.61 seconds
Started Feb 07 12:39:08 PM PST 24
Finished Feb 07 12:39:10 PM PST 24
Peak memory 195576 kb
Host smart-69e0ac72-728b-449a-b726-e4b4993d054a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508253186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3508253186
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2388792625
Short name T1240
Test name
Test status
Simulation time 28772016 ps
CPU time 0.53 seconds
Started Feb 07 12:39:09 PM PST 24
Finished Feb 07 12:39:10 PM PST 24
Peak memory 194252 kb
Host smart-599d4572-7fc4-4017-9bd9-5cb43c533f6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388792625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2388792625
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3349295240
Short name T483
Test name
Test status
Simulation time 26950206 ps
CPU time 0.71 seconds
Started Feb 07 12:39:14 PM PST 24
Finished Feb 07 12:39:15 PM PST 24
Peak memory 196712 kb
Host smart-92da4cd1-61ac-405f-b9b0-6663314e5d06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349295240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3349295240
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3978309502
Short name T69
Test name
Test status
Simulation time 291168126 ps
CPU time 1.1 seconds
Started Feb 07 12:39:08 PM PST 24
Finished Feb 07 12:39:11 PM PST 24
Peak memory 199820 kb
Host smart-217f220b-ed40-44f8-8e08-bef4f9329129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978309502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3978309502
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1231554702
Short name T91
Test name
Test status
Simulation time 61608174 ps
CPU time 0.96 seconds
Started Feb 07 12:39:05 PM PST 24
Finished Feb 07 12:39:07 PM PST 24
Peak memory 198952 kb
Host smart-def9965b-4588-47e5-9453-b49e22c31f74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231554702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1231554702
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2498427608
Short name T1242
Test name
Test status
Simulation time 20197431 ps
CPU time 0.74 seconds
Started Feb 07 12:39:18 PM PST 24
Finished Feb 07 12:39:20 PM PST 24
Peak memory 198332 kb
Host smart-39038683-71f5-45af-a3f6-cfd756586612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498427608 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2498427608
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4070093738
Short name T66
Test name
Test status
Simulation time 47918910 ps
CPU time 0.61 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:17 PM PST 24
Peak memory 195308 kb
Host smart-9eb32680-1939-4d09-9673-a0d020146056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070093738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4070093738
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2472764214
Short name T449
Test name
Test status
Simulation time 35794347 ps
CPU time 0.56 seconds
Started Feb 07 12:39:08 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 194344 kb
Host smart-0ace40ff-84a7-4e4a-8ded-16629c3c2fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472764214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2472764214
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2647450229
Short name T1249
Test name
Test status
Simulation time 47951879 ps
CPU time 0.73 seconds
Started Feb 07 12:39:15 PM PST 24
Finished Feb 07 12:39:16 PM PST 24
Peak memory 196924 kb
Host smart-23a3e2c3-fff1-497f-a6e7-705f16644a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647450229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2647450229
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1525047210
Short name T40
Test name
Test status
Simulation time 18357394 ps
CPU time 1 seconds
Started Feb 07 12:39:07 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 199832 kb
Host smart-1260c40b-5ce1-498c-bb51-7aaea6800cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525047210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1525047210
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2551809332
Short name T89
Test name
Test status
Simulation time 277664411 ps
CPU time 1.24 seconds
Started Feb 07 12:39:06 PM PST 24
Finished Feb 07 12:39:09 PM PST 24
Peak memory 199244 kb
Host smart-28251577-e5b8-4b88-b866-ab740f7b8f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551809332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2551809332
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3832414147
Short name T41
Test name
Test status
Simulation time 56420409 ps
CPU time 0.93 seconds
Started Feb 07 12:39:15 PM PST 24
Finished Feb 07 12:39:17 PM PST 24
Peak memory 199988 kb
Host smart-018c9f2d-751e-449a-816f-12bcca2db7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832414147 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3832414147
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1601052776
Short name T52
Test name
Test status
Simulation time 14145766 ps
CPU time 0.6 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 195352 kb
Host smart-353dea0b-8da3-4173-a03d-09d05b0011d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601052776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1601052776
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1943822878
Short name T1280
Test name
Test status
Simulation time 48449476 ps
CPU time 0.56 seconds
Started Feb 07 12:39:15 PM PST 24
Finished Feb 07 12:39:16 PM PST 24
Peak memory 194404 kb
Host smart-f8cced42-38a2-4c88-9733-34288e327651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943822878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1943822878
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2727643506
Short name T1255
Test name
Test status
Simulation time 52510276 ps
CPU time 0.64 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 195556 kb
Host smart-262f3e64-4d33-4d00-baec-c5cbda2e701c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727643506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2727643506
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1945064744
Short name T31
Test name
Test status
Simulation time 37482069 ps
CPU time 1.94 seconds
Started Feb 07 12:39:15 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 200132 kb
Host smart-bb3c7481-cee4-4c69-9828-0d75d13591cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945064744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1945064744
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3287633129
Short name T38
Test name
Test status
Simulation time 195183580 ps
CPU time 0.9 seconds
Started Feb 07 12:39:18 PM PST 24
Finished Feb 07 12:39:19 PM PST 24
Peak memory 198528 kb
Host smart-c60adfda-e8d6-4078-81a7-fd1c2953de6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287633129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3287633129
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3121717948
Short name T6
Test name
Test status
Simulation time 402254390 ps
CPU time 1.46 seconds
Started Feb 07 12:38:30 PM PST 24
Finished Feb 07 12:38:35 PM PST 24
Peak memory 197312 kb
Host smart-8364c506-99fa-440a-81fa-fb5159713413
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121717948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3121717948
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1989269839
Short name T33
Test name
Test status
Simulation time 50737981 ps
CPU time 0.57 seconds
Started Feb 07 12:38:35 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 195352 kb
Host smart-d50fb8b9-d570-404f-8227-2f02ce9b90ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989269839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1989269839
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.319564036
Short name T1282
Test name
Test status
Simulation time 31640027 ps
CPU time 0.79 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 199820 kb
Host smart-28c37872-6be2-444e-b0fd-4d8a28bd007b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319564036 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.319564036
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3155012388
Short name T482
Test name
Test status
Simulation time 14074037 ps
CPU time 0.59 seconds
Started Feb 07 12:38:30 PM PST 24
Finished Feb 07 12:38:33 PM PST 24
Peak memory 195444 kb
Host smart-af2e048f-f086-4c47-a652-85ce0491f428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155012388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3155012388
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3166572502
Short name T1272
Test name
Test status
Simulation time 49754634 ps
CPU time 0.56 seconds
Started Feb 07 12:38:36 PM PST 24
Finished Feb 07 12:38:40 PM PST 24
Peak memory 194252 kb
Host smart-4d54a476-3fcb-41e4-a26e-a06c7a61a7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166572502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3166572502
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1284681184
Short name T57
Test name
Test status
Simulation time 37747867 ps
CPU time 0.64 seconds
Started Feb 07 12:38:45 PM PST 24
Finished Feb 07 12:38:50 PM PST 24
Peak memory 195748 kb
Host smart-bac510a7-f9d7-40ac-801e-28335ec48178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284681184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1284681184
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3836793778
Short name T1274
Test name
Test status
Simulation time 63194027 ps
CPU time 0.92 seconds
Started Feb 07 12:38:32 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 199616 kb
Host smart-76fc7f95-5aff-4793-9f76-993aa612314f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836793778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3836793778
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1753977653
Short name T1253
Test name
Test status
Simulation time 167591624 ps
CPU time 0.88 seconds
Started Feb 07 12:38:30 PM PST 24
Finished Feb 07 12:38:34 PM PST 24
Peak memory 198448 kb
Host smart-e6bc0a2b-c86b-4677-a730-2c6acfdc0715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753977653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1753977653
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2339152390
Short name T1288
Test name
Test status
Simulation time 13012866 ps
CPU time 0.58 seconds
Started Feb 07 12:39:17 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 194300 kb
Host smart-4249df2a-2085-4633-b95e-5d721adf4015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339152390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2339152390
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2411268888
Short name T450
Test name
Test status
Simulation time 52676344 ps
CPU time 0.57 seconds
Started Feb 07 12:39:17 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 194236 kb
Host smart-d649f2ff-7e5d-444c-9f4a-b8aa1537320d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411268888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2411268888
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1148288909
Short name T65
Test name
Test status
Simulation time 52143719 ps
CPU time 0.55 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 194208 kb
Host smart-d35865b9-2efd-4c67-ad40-060948468cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148288909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1148288909
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1228659968
Short name T459
Test name
Test status
Simulation time 39021910 ps
CPU time 0.57 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 194340 kb
Host smart-7da7909d-ca7d-4d28-9696-dee1583fc4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228659968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1228659968
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2331801042
Short name T1279
Test name
Test status
Simulation time 30119636 ps
CPU time 0.55 seconds
Started Feb 07 12:39:14 PM PST 24
Finished Feb 07 12:39:15 PM PST 24
Peak memory 194356 kb
Host smart-f94e4548-e8f3-4804-a218-c789986b1fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331801042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2331801042
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1974351094
Short name T1284
Test name
Test status
Simulation time 16195057 ps
CPU time 0.6 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:18 PM PST 24
Peak memory 194340 kb
Host smart-030090cb-b6ed-47f8-80a4-3154906691e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974351094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1974351094
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2783348059
Short name T468
Test name
Test status
Simulation time 11237434 ps
CPU time 0.56 seconds
Started Feb 07 12:39:16 PM PST 24
Finished Feb 07 12:39:17 PM PST 24
Peak memory 194348 kb
Host smart-d1e2f5df-1f60-4a50-9f3d-643e53e19705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783348059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2783348059
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.857459458
Short name T452
Test name
Test status
Simulation time 15326694 ps
CPU time 0.57 seconds
Started Feb 07 12:39:31 PM PST 24
Finished Feb 07 12:39:33 PM PST 24
Peak memory 194416 kb
Host smart-c1c1f39b-14a2-467a-9d4a-fc2afd38d877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857459458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.857459458
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2923979334
Short name T1285
Test name
Test status
Simulation time 31898117 ps
CPU time 0.56 seconds
Started Feb 07 12:39:31 PM PST 24
Finished Feb 07 12:39:33 PM PST 24
Peak memory 194276 kb
Host smart-6eaa02c0-e464-4bdb-8fd9-8d721f61982f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923979334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2923979334
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3508005701
Short name T56
Test name
Test status
Simulation time 56556277 ps
CPU time 0.74 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 196172 kb
Host smart-e7ca1504-0e4f-43e1-8698-a554965bde30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508005701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3508005701
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3413161818
Short name T46
Test name
Test status
Simulation time 1478264655 ps
CPU time 1.59 seconds
Started Feb 07 12:38:47 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 197776 kb
Host smart-e21a1d4f-cd6c-4f17-a293-9ac40dfa8c5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413161818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3413161818
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.59492984
Short name T1267
Test name
Test status
Simulation time 47944709 ps
CPU time 0.6 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:47 PM PST 24
Peak memory 195352 kb
Host smart-a57a1152-c0db-490c-827e-ee8fc4faa804
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59492984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.59492984
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3698326013
Short name T1257
Test name
Test status
Simulation time 19121292 ps
CPU time 0.69 seconds
Started Feb 07 12:38:45 PM PST 24
Finished Feb 07 12:38:51 PM PST 24
Peak memory 198184 kb
Host smart-67f94819-0d63-47d5-8289-8487864edf41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698326013 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3698326013
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3351797245
Short name T481
Test name
Test status
Simulation time 12483839 ps
CPU time 0.58 seconds
Started Feb 07 12:39:19 PM PST 24
Finished Feb 07 12:39:20 PM PST 24
Peak memory 195452 kb
Host smart-36299006-e9fb-416e-a8c1-19a724c13604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351797245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3351797245
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.19356384
Short name T51
Test name
Test status
Simulation time 111922619 ps
CPU time 0.57 seconds
Started Feb 07 12:38:46 PM PST 24
Finished Feb 07 12:38:51 PM PST 24
Peak memory 194316 kb
Host smart-dd4754d0-64ee-44d6-80c5-7748592e3b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19356384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.19356384
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4283995822
Short name T75
Test name
Test status
Simulation time 62672881 ps
CPU time 0.6 seconds
Started Feb 07 12:38:49 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 195596 kb
Host smart-b5ac0e5a-aafa-41af-8a84-83f2f90b4fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283995822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4283995822
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2103392045
Short name T478
Test name
Test status
Simulation time 286706169 ps
CPU time 1.99 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:48 PM PST 24
Peak memory 200064 kb
Host smart-eb08ac6a-1f2a-43f9-8d47-6dfe0a2812ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103392045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2103392045
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2831057366
Short name T1247
Test name
Test status
Simulation time 140501147 ps
CPU time 0.92 seconds
Started Feb 07 12:38:42 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 199048 kb
Host smart-02de3644-8669-4144-8d9b-5b59a5961555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831057366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2831057366
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1211026723
Short name T467
Test name
Test status
Simulation time 33755476 ps
CPU time 0.55 seconds
Started Feb 07 12:39:33 PM PST 24
Finished Feb 07 12:39:35 PM PST 24
Peak memory 194340 kb
Host smart-205b94a9-0fe7-412a-b042-a2971caa0c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211026723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1211026723
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1224688985
Short name T453
Test name
Test status
Simulation time 14225400 ps
CPU time 0.56 seconds
Started Feb 07 12:39:30 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194344 kb
Host smart-249f3d1f-9595-4417-afae-30031d4d8729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224688985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1224688985
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1881974139
Short name T1245
Test name
Test status
Simulation time 11013198 ps
CPU time 0.57 seconds
Started Feb 07 12:39:31 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194324 kb
Host smart-98f1d0ad-f9a0-44f2-88cc-2972e9710d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881974139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1881974139
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3290793807
Short name T469
Test name
Test status
Simulation time 11247298 ps
CPU time 0.56 seconds
Started Feb 07 12:39:31 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194268 kb
Host smart-be3871d3-c036-47a2-ae89-94d160debb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290793807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3290793807
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2475605957
Short name T1268
Test name
Test status
Simulation time 14913123 ps
CPU time 0.58 seconds
Started Feb 07 12:39:32 PM PST 24
Finished Feb 07 12:39:34 PM PST 24
Peak memory 194340 kb
Host smart-774c2f03-942b-47f1-9ccb-96d331fe2727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475605957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2475605957
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.882278173
Short name T389
Test name
Test status
Simulation time 34208758 ps
CPU time 0.55 seconds
Started Feb 07 12:39:31 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194268 kb
Host smart-8bc8d925-9a40-4a64-a7bd-2df9a56b9e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882278173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.882278173
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2257658119
Short name T1297
Test name
Test status
Simulation time 16460293 ps
CPU time 0.58 seconds
Started Feb 07 12:39:37 PM PST 24
Finished Feb 07 12:39:38 PM PST 24
Peak memory 194304 kb
Host smart-6b015cb5-d02c-4b93-8773-43bc8d14d955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257658119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2257658119
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4114959683
Short name T392
Test name
Test status
Simulation time 48112604 ps
CPU time 0.61 seconds
Started Feb 07 12:39:37 PM PST 24
Finished Feb 07 12:39:38 PM PST 24
Peak memory 194300 kb
Host smart-08f71f7b-5dd3-4139-a919-bdf080fb603d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114959683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4114959683
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.398204575
Short name T471
Test name
Test status
Simulation time 37160748 ps
CPU time 0.58 seconds
Started Feb 07 12:39:30 PM PST 24
Finished Feb 07 12:39:31 PM PST 24
Peak memory 194304 kb
Host smart-5022d904-5a1e-465d-bb04-631d666661a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398204575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.398204575
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2414749039
Short name T473
Test name
Test status
Simulation time 35582122 ps
CPU time 0.54 seconds
Started Feb 07 12:39:27 PM PST 24
Finished Feb 07 12:39:28 PM PST 24
Peak memory 194356 kb
Host smart-335a0f87-0c4f-4d37-b441-05ce0c4797b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414749039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2414749039
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4184879609
Short name T475
Test name
Test status
Simulation time 206313949 ps
CPU time 0.64 seconds
Started Feb 07 12:38:45 PM PST 24
Finished Feb 07 12:38:49 PM PST 24
Peak memory 194776 kb
Host smart-99e1b707-ebff-4125-9635-36673721b0b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184879609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4184879609
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1122464768
Short name T1287
Test name
Test status
Simulation time 181725001 ps
CPU time 1.47 seconds
Started Feb 07 12:38:49 PM PST 24
Finished Feb 07 12:38:53 PM PST 24
Peak memory 197764 kb
Host smart-28683ab4-dee6-4a49-9b20-20d47db4fe97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122464768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1122464768
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.80679511
Short name T1277
Test name
Test status
Simulation time 15786447 ps
CPU time 0.61 seconds
Started Feb 07 12:38:46 PM PST 24
Finished Feb 07 12:38:51 PM PST 24
Peak memory 195336 kb
Host smart-bcee0fe3-b1e9-462e-b441-720480d973a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80679511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.80679511
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2972857089
Short name T1264
Test name
Test status
Simulation time 22821464 ps
CPU time 0.72 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:47 PM PST 24
Peak memory 198752 kb
Host smart-02ca9e40-8c40-4688-84b4-0284de5ad309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972857089 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2972857089
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2327595733
Short name T1244
Test name
Test status
Simulation time 14900575 ps
CPU time 0.58 seconds
Started Feb 07 12:38:43 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 195376 kb
Host smart-0589cae0-d52e-47de-a267-d8ce4fe00544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327595733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2327595733
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1571899121
Short name T1254
Test name
Test status
Simulation time 28617739 ps
CPU time 0.54 seconds
Started Feb 07 12:38:43 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 194336 kb
Host smart-e8a462c3-11b4-42df-87f8-2b1091748b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571899121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1571899121
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4171718867
Short name T1251
Test name
Test status
Simulation time 27551542 ps
CPU time 1.28 seconds
Started Feb 07 12:38:51 PM PST 24
Finished Feb 07 12:38:54 PM PST 24
Peak memory 200032 kb
Host smart-74192073-63ce-4fa3-8817-2be7719d1698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171718867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4171718867
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.223915333
Short name T1239
Test name
Test status
Simulation time 52133341 ps
CPU time 0.95 seconds
Started Feb 07 12:38:46 PM PST 24
Finished Feb 07 12:38:51 PM PST 24
Peak memory 198836 kb
Host smart-e470a9e3-df3c-412f-94f7-e1e64f0d220e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223915333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.223915333
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1128652403
Short name T1298
Test name
Test status
Simulation time 13004233 ps
CPU time 0.58 seconds
Started Feb 07 12:39:33 PM PST 24
Finished Feb 07 12:39:35 PM PST 24
Peak memory 194296 kb
Host smart-26c9985c-6786-407d-a449-21b91cd26ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128652403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1128652403
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2436498644
Short name T470
Test name
Test status
Simulation time 13402225 ps
CPU time 0.57 seconds
Started Feb 07 12:39:32 PM PST 24
Finished Feb 07 12:39:34 PM PST 24
Peak memory 194416 kb
Host smart-3cd201cf-7b4c-4d22-b190-20f105f1f64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436498644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2436498644
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1615868291
Short name T1262
Test name
Test status
Simulation time 45432326 ps
CPU time 0.55 seconds
Started Feb 07 12:39:32 PM PST 24
Finished Feb 07 12:39:34 PM PST 24
Peak memory 194428 kb
Host smart-a6bd42bc-4588-4e77-ad82-58803226703a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615868291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1615868291
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3294185283
Short name T1276
Test name
Test status
Simulation time 18983910 ps
CPU time 0.51 seconds
Started Feb 07 12:39:27 PM PST 24
Finished Feb 07 12:39:29 PM PST 24
Peak memory 194360 kb
Host smart-6475b25a-6cc8-4408-bc85-b83ded84ad1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294185283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3294185283
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.889149699
Short name T1271
Test name
Test status
Simulation time 20353206 ps
CPU time 0.56 seconds
Started Feb 07 12:39:30 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194236 kb
Host smart-25e3be50-f83f-4665-aaaa-0c95ec7300e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889149699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.889149699
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1473331658
Short name T457
Test name
Test status
Simulation time 12414088 ps
CPU time 0.54 seconds
Started Feb 07 12:39:33 PM PST 24
Finished Feb 07 12:39:35 PM PST 24
Peak memory 194404 kb
Host smart-78f34795-66d8-49fd-b299-abfef902295c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473331658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1473331658
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.869623232
Short name T36
Test name
Test status
Simulation time 36480338 ps
CPU time 0.52 seconds
Started Feb 07 12:39:34 PM PST 24
Finished Feb 07 12:39:35 PM PST 24
Peak memory 194340 kb
Host smart-1d44b4f2-040b-42b3-a683-a10e4e00a757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869623232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.869623232
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2046069692
Short name T1256
Test name
Test status
Simulation time 15458174 ps
CPU time 0.56 seconds
Started Feb 07 12:39:30 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194236 kb
Host smart-51b0d50b-a3d7-4cb2-bfc2-9a911c51234d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046069692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2046069692
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3737605592
Short name T4
Test name
Test status
Simulation time 55152425 ps
CPU time 0.58 seconds
Started Feb 07 12:39:30 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 194308 kb
Host smart-daec6f47-71e4-4c5e-9ed7-fbda49fdaa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737605592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3737605592
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1873260233
Short name T1241
Test name
Test status
Simulation time 23178950 ps
CPU time 0.69 seconds
Started Feb 07 12:38:45 PM PST 24
Finished Feb 07 12:38:50 PM PST 24
Peak memory 198208 kb
Host smart-207e8cbf-aa76-4e31-8256-9fcc7c6b3776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873260233 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1873260233
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3891658145
Short name T1294
Test name
Test status
Simulation time 18185562 ps
CPU time 0.66 seconds
Started Feb 07 12:38:43 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 195364 kb
Host smart-b927f956-184f-4879-bc53-e9a5118bb5a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891658145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3891658145
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3928885120
Short name T1266
Test name
Test status
Simulation time 12251093 ps
CPU time 0.55 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 194400 kb
Host smart-74602a6d-f779-4ff3-b2db-aa04558e8a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928885120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3928885120
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2856630865
Short name T109
Test name
Test status
Simulation time 74941624 ps
CPU time 0.66 seconds
Started Feb 07 12:38:42 PM PST 24
Finished Feb 07 12:38:44 PM PST 24
Peak memory 194752 kb
Host smart-1a4cbf52-6fc4-4dda-9231-073c22417147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856630865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2856630865
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3025092232
Short name T485
Test name
Test status
Simulation time 144525524 ps
CPU time 1.44 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 200212 kb
Host smart-4c0e8628-4c17-46b2-a91b-78346200512a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025092232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3025092232
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2382055141
Short name T480
Test name
Test status
Simulation time 394475493 ps
CPU time 1.28 seconds
Started Feb 07 12:38:46 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 199136 kb
Host smart-1ad39914-6188-4055-b980-9fd4e3e2ae8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382055141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2382055141
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1375942331
Short name T1243
Test name
Test status
Simulation time 17612824 ps
CPU time 0.83 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 199884 kb
Host smart-5a27bf8e-f4de-447c-a658-b9b7428f219f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375942331 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1375942331
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4272380741
Short name T1252
Test name
Test status
Simulation time 13452744 ps
CPU time 0.62 seconds
Started Feb 07 12:38:48 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 195328 kb
Host smart-7620be8a-9be7-4de7-9f60-47e94fb0166e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272380741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4272380741
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2067433415
Short name T1259
Test name
Test status
Simulation time 26205760 ps
CPU time 0.58 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 194376 kb
Host smart-8b60c02e-8266-4125-9cac-55f10e5c0e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067433415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2067433415
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.154442808
Short name T1
Test name
Test status
Simulation time 27609253 ps
CPU time 0.63 seconds
Started Feb 07 12:38:48 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 194436 kb
Host smart-afd3d7b3-1618-464c-afbe-3409f58158b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154442808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.154442808
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3786529012
Short name T1290
Test name
Test status
Simulation time 89506655 ps
CPU time 1.9 seconds
Started Feb 07 12:38:42 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 200136 kb
Host smart-f28472cc-2ce7-4a55-addd-4ed01cecc5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786529012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3786529012
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3695601247
Short name T106
Test name
Test status
Simulation time 57251617 ps
CPU time 0.76 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:47 PM PST 24
Peak memory 199904 kb
Host smart-007ca52c-dd31-4ea7-ba20-68f0b2ca4325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695601247 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3695601247
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.857317508
Short name T54
Test name
Test status
Simulation time 54732953 ps
CPU time 0.7 seconds
Started Feb 07 12:38:43 PM PST 24
Finished Feb 07 12:38:45 PM PST 24
Peak memory 195276 kb
Host smart-3a37f29c-c0ed-47b0-a550-b463525c7edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857317508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.857317508
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3388725835
Short name T454
Test name
Test status
Simulation time 20344553 ps
CPU time 0.56 seconds
Started Feb 07 12:38:45 PM PST 24
Finished Feb 07 12:38:47 PM PST 24
Peak memory 194296 kb
Host smart-2b368399-c492-42bf-8a19-1ebd89178e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388725835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3388725835
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1515837119
Short name T1292
Test name
Test status
Simulation time 34742819 ps
CPU time 0.59 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:46 PM PST 24
Peak memory 195720 kb
Host smart-555cc2ba-2d74-4241-9e63-6d78fddc3068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515837119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1515837119
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1757102637
Short name T456
Test name
Test status
Simulation time 104728544 ps
CPU time 2.09 seconds
Started Feb 07 12:38:51 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 200008 kb
Host smart-05423884-b5f0-441c-a26f-14f7ba4218d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757102637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1757102637
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2057569284
Short name T387
Test name
Test status
Simulation time 193561960 ps
CPU time 0.9 seconds
Started Feb 07 12:38:49 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 198908 kb
Host smart-11baff9b-13c0-49b2-83fe-17ce7047dcf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057569284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2057569284
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2128535499
Short name T49
Test name
Test status
Simulation time 42348528 ps
CPU time 0.6 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 195440 kb
Host smart-54d53a54-cb2f-4ee6-a346-f4c1f9a16d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128535499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2128535499
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1601322980
Short name T1296
Test name
Test status
Simulation time 40421162 ps
CPU time 0.55 seconds
Started Feb 07 12:38:55 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 194300 kb
Host smart-b471d39f-295c-4036-90a5-12627f801004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601322980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1601322980
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.167618095
Short name T1281
Test name
Test status
Simulation time 18144565 ps
CPU time 0.67 seconds
Started Feb 07 12:38:52 PM PST 24
Finished Feb 07 12:38:54 PM PST 24
Peak memory 197696 kb
Host smart-cd531c90-fb9e-43d1-bcd7-a7aa07880301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167618095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.167618095
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3885434478
Short name T1289
Test name
Test status
Simulation time 95878577 ps
CPU time 1.66 seconds
Started Feb 07 12:38:44 PM PST 24
Finished Feb 07 12:38:47 PM PST 24
Peak memory 200160 kb
Host smart-dcd71b7a-ea2c-4823-aea6-862cee442726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885434478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3885434478
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2028593450
Short name T1270
Test name
Test status
Simulation time 204645783 ps
CPU time 1.08 seconds
Started Feb 07 12:38:54 PM PST 24
Finished Feb 07 12:38:57 PM PST 24
Peak memory 200160 kb
Host smart-402e464e-d234-45ae-81b1-868b51c9389b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028593450 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2028593450
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4066458053
Short name T1261
Test name
Test status
Simulation time 24094477 ps
CPU time 0.61 seconds
Started Feb 07 12:38:54 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 195416 kb
Host smart-0d112aba-3b89-4a24-ba79-d880129db466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066458053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4066458053
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.769562208
Short name T1238
Test name
Test status
Simulation time 27565997 ps
CPU time 0.56 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 194464 kb
Host smart-7bac7ad9-d7cd-4f19-9a73-29519d925e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769562208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.769562208
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2861020750
Short name T472
Test name
Test status
Simulation time 12581647 ps
CPU time 0.64 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 195468 kb
Host smart-f4da32a1-13d2-402f-ad89-5e04ae434713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861020750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2861020750
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1179033075
Short name T45
Test name
Test status
Simulation time 27305876 ps
CPU time 1.29 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:55 PM PST 24
Peak memory 200208 kb
Host smart-3197ba13-b206-4dde-ba4e-a29fc9cc7be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179033075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1179033075
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3481740113
Short name T1278
Test name
Test status
Simulation time 66687833 ps
CPU time 1.29 seconds
Started Feb 07 12:38:53 PM PST 24
Finished Feb 07 12:38:56 PM PST 24
Peak memory 199480 kb
Host smart-0e1cde24-1a9c-49e2-aaa0-065435d07b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481740113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3481740113
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1909696855
Short name T866
Test name
Test status
Simulation time 75506657 ps
CPU time 0.55 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:30:37 PM PST 24
Peak memory 195312 kb
Host smart-feff76b0-04b7-43e6-8bed-c2237eab84a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909696855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1909696855
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3238115595
Short name T1090
Test name
Test status
Simulation time 117582163721 ps
CPU time 47.12 seconds
Started Feb 07 01:30:15 PM PST 24
Finished Feb 07 01:31:10 PM PST 24
Peak memory 199984 kb
Host smart-7cb84870-9dae-4e87-81f1-ac5c540b390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238115595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3238115595
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1514064092
Short name T796
Test name
Test status
Simulation time 70081471232 ps
CPU time 58.42 seconds
Started Feb 07 01:30:14 PM PST 24
Finished Feb 07 01:31:15 PM PST 24
Peak memory 199992 kb
Host smart-5eb1f49b-cc60-4a24-a1aa-4e4b58fb9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514064092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1514064092
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4088950445
Short name T184
Test name
Test status
Simulation time 43979953561 ps
CPU time 85.98 seconds
Started Feb 07 01:30:14 PM PST 24
Finished Feb 07 01:31:43 PM PST 24
Peak memory 199952 kb
Host smart-b38ab9a1-0feb-4ff2-b5ab-c35425d6f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088950445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4088950445
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2645408901
Short name T559
Test name
Test status
Simulation time 539244031629 ps
CPU time 889.8 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:45:27 PM PST 24
Peak memory 199836 kb
Host smart-a170af75-85ec-4047-b1f7-86b9306f576f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645408901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2645408901
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1655474986
Short name T952
Test name
Test status
Simulation time 67452376129 ps
CPU time 302.7 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:35:39 PM PST 24
Peak memory 200032 kb
Host smart-d00f3614-92a0-487e-bd7b-fd2bb6ae7029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655474986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1655474986
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1655636193
Short name T703
Test name
Test status
Simulation time 482364294 ps
CPU time 0.9 seconds
Started Feb 07 01:30:34 PM PST 24
Finished Feb 07 01:30:38 PM PST 24
Peak memory 196328 kb
Host smart-f91ac481-aa98-4666-bac4-3663e4d7240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655636193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1655636193
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.625834676
Short name T821
Test name
Test status
Simulation time 143678265589 ps
CPU time 280.17 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:35:17 PM PST 24
Peak memory 200276 kb
Host smart-ea6875af-f5cb-4917-808f-269a63927b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625834676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.625834676
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.805611312
Short name T720
Test name
Test status
Simulation time 19287788723 ps
CPU time 155.49 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:33:12 PM PST 24
Peak memory 199952 kb
Host smart-fad18706-27ac-4719-927a-45b2fc3a6f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805611312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.805611312
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3076824286
Short name T854
Test name
Test status
Simulation time 1585384396 ps
CPU time 6.19 seconds
Started Feb 07 01:30:26 PM PST 24
Finished Feb 07 01:30:37 PM PST 24
Peak memory 197816 kb
Host smart-7cf2342c-481d-4476-91d7-3500dbbab30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076824286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3076824286
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3293059389
Short name T914
Test name
Test status
Simulation time 69812968506 ps
CPU time 29.04 seconds
Started Feb 07 01:30:27 PM PST 24
Finished Feb 07 01:31:03 PM PST 24
Peak memory 198944 kb
Host smart-aff66faf-4324-42c8-9032-f270fd0ba0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293059389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3293059389
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.511957100
Short name T409
Test name
Test status
Simulation time 3327446078 ps
CPU time 3.08 seconds
Started Feb 07 01:30:35 PM PST 24
Finished Feb 07 01:30:40 PM PST 24
Peak memory 195364 kb
Host smart-f947b10e-9de1-43f3-9341-8431a34d41c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511957100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.511957100
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.332632288
Short name T723
Test name
Test status
Simulation time 552938471 ps
CPU time 1.57 seconds
Started Feb 07 01:30:14 PM PST 24
Finished Feb 07 01:30:18 PM PST 24
Peak memory 198224 kb
Host smart-0d3a810b-b7f9-4159-9995-f1e50921d9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332632288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.332632288
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1505911602
Short name T608
Test name
Test status
Simulation time 24577386580 ps
CPU time 44.12 seconds
Started Feb 07 01:30:37 PM PST 24
Finished Feb 07 01:31:21 PM PST 24
Peak memory 199904 kb
Host smart-3302fd3b-ade5-458f-a73d-3c97f57de6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505911602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1505911602
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1930950057
Short name T775
Test name
Test status
Simulation time 6953275306 ps
CPU time 19.91 seconds
Started Feb 07 01:30:27 PM PST 24
Finished Feb 07 01:30:51 PM PST 24
Peak memory 199576 kb
Host smart-744eec70-ea1a-4205-903d-83ec5ed36dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930950057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1930950057
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2818666644
Short name T890
Test name
Test status
Simulation time 41112732720 ps
CPU time 80.08 seconds
Started Feb 07 01:30:14 PM PST 24
Finished Feb 07 01:31:37 PM PST 24
Peak memory 199936 kb
Host smart-c52d6e6a-b240-47e0-b47a-782a6ecfaa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818666644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2818666644
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3910160013
Short name T174
Test name
Test status
Simulation time 140459626724 ps
CPU time 58.07 seconds
Started Feb 07 01:30:36 PM PST 24
Finished Feb 07 01:31:35 PM PST 24
Peak memory 199404 kb
Host smart-99920fa7-76a3-45f4-8cdb-6b281dfd5736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910160013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3910160013
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4286730467
Short name T861
Test name
Test status
Simulation time 63311820992 ps
CPU time 8.46 seconds
Started Feb 07 01:30:37 PM PST 24
Finished Feb 07 01:30:46 PM PST 24
Peak memory 198600 kb
Host smart-21c8f2e6-f9e0-4847-8ed2-31ecc129a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286730467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4286730467
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2335735961
Short name T132
Test name
Test status
Simulation time 115881237577 ps
CPU time 168.09 seconds
Started Feb 07 01:30:42 PM PST 24
Finished Feb 07 01:33:30 PM PST 24
Peak memory 199788 kb
Host smart-c37aac45-f4e5-4169-a3e8-68c455170c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335735961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2335735961
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1076352607
Short name T1129
Test name
Test status
Simulation time 617451485317 ps
CPU time 181.16 seconds
Started Feb 07 01:30:44 PM PST 24
Finished Feb 07 01:33:46 PM PST 24
Peak memory 199160 kb
Host smart-1ce5877c-d692-4be5-995f-e9cd18efec42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076352607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1076352607
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.958788971
Short name T1030
Test name
Test status
Simulation time 106283943818 ps
CPU time 270.02 seconds
Started Feb 07 01:30:51 PM PST 24
Finished Feb 07 01:35:22 PM PST 24
Peak memory 199944 kb
Host smart-b5edbf88-2a7e-4741-93e4-45e8399e8227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958788971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.958788971
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1717373550
Short name T493
Test name
Test status
Simulation time 1969810793 ps
CPU time 2.47 seconds
Started Feb 07 01:30:43 PM PST 24
Finished Feb 07 01:30:46 PM PST 24
Peak memory 196840 kb
Host smart-ccef684a-694c-4c90-a4e8-aac18426541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717373550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1717373550
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.2783599057
Short name T844
Test name
Test status
Simulation time 14016190180 ps
CPU time 195.47 seconds
Started Feb 07 01:30:46 PM PST 24
Finished Feb 07 01:34:02 PM PST 24
Peak memory 199704 kb
Host smart-8ab35a47-ac56-491b-b2bc-48710f51341d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783599057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2783599057
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3607254458
Short name T640
Test name
Test status
Simulation time 4330126289 ps
CPU time 19.42 seconds
Started Feb 07 01:30:42 PM PST 24
Finished Feb 07 01:31:02 PM PST 24
Peak memory 198028 kb
Host smart-71b3d871-aa65-4ae9-861e-39173edfa3c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607254458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3607254458
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.318752661
Short name T1151
Test name
Test status
Simulation time 63817085021 ps
CPU time 75.18 seconds
Started Feb 07 01:30:43 PM PST 24
Finished Feb 07 01:31:59 PM PST 24
Peak memory 199904 kb
Host smart-afea5209-063e-4d6b-9d49-0662f3834efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318752661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.318752661
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.122945590
Short name T622
Test name
Test status
Simulation time 3223543425 ps
CPU time 4.19 seconds
Started Feb 07 01:30:43 PM PST 24
Finished Feb 07 01:30:48 PM PST 24
Peak memory 195640 kb
Host smart-9fc489ef-f3af-408c-84fe-bc47595f5e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122945590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.122945590
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.652586973
Short name T95
Test name
Test status
Simulation time 64204252 ps
CPU time 0.72 seconds
Started Feb 07 01:30:54 PM PST 24
Finished Feb 07 01:30:56 PM PST 24
Peak memory 217216 kb
Host smart-c77c536e-bf28-41eb-808f-03fa0329e76d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652586973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.652586973
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4257682553
Short name T669
Test name
Test status
Simulation time 449788449 ps
CPU time 1.23 seconds
Started Feb 07 01:30:37 PM PST 24
Finished Feb 07 01:30:39 PM PST 24
Peak memory 199064 kb
Host smart-14b9259a-5391-4382-ada8-a8cd6ae1d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257682553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4257682553
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.955949696
Short name T1226
Test name
Test status
Simulation time 43337975043 ps
CPU time 25.83 seconds
Started Feb 07 01:30:53 PM PST 24
Finished Feb 07 01:31:19 PM PST 24
Peak memory 199992 kb
Host smart-b58acd24-1406-49cc-a232-060b85aa938c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955949696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.955949696
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1450201812
Short name T642
Test name
Test status
Simulation time 192126932225 ps
CPU time 585.89 seconds
Started Feb 07 01:30:54 PM PST 24
Finished Feb 07 01:40:41 PM PST 24
Peak memory 216436 kb
Host smart-764ae440-f314-43a3-8246-62ea134c9249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450201812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1450201812
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3581168483
Short name T1082
Test name
Test status
Simulation time 3385538818 ps
CPU time 2.01 seconds
Started Feb 07 01:30:43 PM PST 24
Finished Feb 07 01:30:46 PM PST 24
Peak memory 198596 kb
Host smart-697dcfab-2c16-4c5f-8517-bee3aaca31be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581168483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3581168483
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3179667064
Short name T802
Test name
Test status
Simulation time 9095106140 ps
CPU time 4.24 seconds
Started Feb 07 01:30:36 PM PST 24
Finished Feb 07 01:30:41 PM PST 24
Peak memory 199732 kb
Host smart-9a00671a-47a7-4dda-94c4-3551923d5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179667064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3179667064
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1014922128
Short name T769
Test name
Test status
Simulation time 33631122 ps
CPU time 0.56 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:54 PM PST 24
Peak memory 194292 kb
Host smart-e6cde78e-113c-4b18-9584-4f30a9bd67e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014922128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1014922128
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2891525901
Short name T1161
Test name
Test status
Simulation time 155198101913 ps
CPU time 67.41 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:33:59 PM PST 24
Peak memory 199124 kb
Host smart-88e80441-2ec9-4cba-bca3-eba90ce6cc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891525901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2891525901
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2177915650
Short name T788
Test name
Test status
Simulation time 12524332319 ps
CPU time 32.01 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:33:24 PM PST 24
Peak memory 199696 kb
Host smart-afc8626e-9248-4645-91a9-8c937b756a39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177915650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2177915650
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3398271903
Short name T634
Test name
Test status
Simulation time 134239498662 ps
CPU time 892.93 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:47:47 PM PST 24
Peak memory 199984 kb
Host smart-60bd2e7b-fa34-4fae-b349-9bf4d101eff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398271903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3398271903
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4265494124
Short name T1152
Test name
Test status
Simulation time 9337532946 ps
CPU time 9.86 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:33:03 PM PST 24
Peak memory 199140 kb
Host smart-70735bb0-c161-4046-9461-969df4e915b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265494124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4265494124
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.699519765
Short name T175
Test name
Test status
Simulation time 358634223849 ps
CPU time 73.35 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:34:07 PM PST 24
Peak memory 208280 kb
Host smart-9816c534-f470-4f2c-bdcb-d3aa636050c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699519765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.699519765
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.350532666
Short name T517
Test name
Test status
Simulation time 4163013930 ps
CPU time 64.53 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:33:57 PM PST 24
Peak memory 199808 kb
Host smart-be8f6a95-88a3-45f0-9cee-143d2deebb1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350532666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.350532666
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3958797118
Short name T1125
Test name
Test status
Simulation time 1724881246 ps
CPU time 2.36 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:56 PM PST 24
Peak memory 198040 kb
Host smart-1214b559-e698-4d1a-88b8-ac68e78fd5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958797118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3958797118
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.367522433
Short name T1017
Test name
Test status
Simulation time 70305367355 ps
CPU time 56.86 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:33:49 PM PST 24
Peak memory 199900 kb
Host smart-412677e5-d170-4efb-b406-248dc7ff91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367522433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.367522433
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3471910554
Short name T583
Test name
Test status
Simulation time 3875220497 ps
CPU time 2.15 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:56 PM PST 24
Peak memory 195612 kb
Host smart-befe1047-ad9e-400c-8f23-c6741fcd30e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471910554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3471910554
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3683496722
Short name T817
Test name
Test status
Simulation time 459042851 ps
CPU time 1.54 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:55 PM PST 24
Peak memory 197640 kb
Host smart-adb79cc4-c5b5-46ef-bcf5-678861a6f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683496722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3683496722
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1093074846
Short name T1048
Test name
Test status
Simulation time 818086666450 ps
CPU time 601.28 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:42:54 PM PST 24
Peak memory 200044 kb
Host smart-f3ebb146-9460-4b6a-a543-ca5b2871ffa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093074846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1093074846
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.743246634
Short name T1143
Test name
Test status
Simulation time 116144127815 ps
CPU time 807.6 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 216744 kb
Host smart-bd40536e-604e-4921-82c7-b0b96d027d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743246634 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.743246634
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3666344634
Short name T995
Test name
Test status
Simulation time 828629203 ps
CPU time 2.55 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:32:55 PM PST 24
Peak memory 198028 kb
Host smart-3485dd7f-5176-4419-8d47-f2418fddcc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666344634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3666344634
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2256083534
Short name T872
Test name
Test status
Simulation time 222962593729 ps
CPU time 211.78 seconds
Started Feb 07 01:32:50 PM PST 24
Finished Feb 07 01:36:22 PM PST 24
Peak memory 199936 kb
Host smart-f3bf4d73-1085-4897-8386-b270635b21cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256083534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2256083534
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2116942802
Short name T979
Test name
Test status
Simulation time 180296524040 ps
CPU time 92.81 seconds
Started Feb 07 01:38:36 PM PST 24
Finished Feb 07 01:40:15 PM PST 24
Peak memory 199860 kb
Host smart-b504eb31-9447-4a44-9fec-9d3cdf258b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116942802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2116942802
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.441474921
Short name T1174
Test name
Test status
Simulation time 31153608038 ps
CPU time 52.25 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:39:34 PM PST 24
Peak memory 199896 kb
Host smart-6c759d1b-5460-430d-a601-2d38d3bab821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441474921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.441474921
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1997351931
Short name T571
Test name
Test status
Simulation time 95625382782 ps
CPU time 34.01 seconds
Started Feb 07 01:38:40 PM PST 24
Finished Feb 07 01:39:17 PM PST 24
Peak memory 199520 kb
Host smart-6cf7d898-289a-448e-9a4c-de68d2c2fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997351931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1997351931
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3110351730
Short name T192
Test name
Test status
Simulation time 20914418211 ps
CPU time 11.14 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:38:57 PM PST 24
Peak memory 199700 kb
Host smart-a59b28fe-da05-45fe-93fb-2eff339ab200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110351730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3110351730
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.364699620
Short name T270
Test name
Test status
Simulation time 14085927213 ps
CPU time 24.8 seconds
Started Feb 07 01:38:41 PM PST 24
Finished Feb 07 01:39:08 PM PST 24
Peak memory 199928 kb
Host smart-d82b47c8-6e1d-4fed-9e71-11a56a900700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364699620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.364699620
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.318065354
Short name T134
Test name
Test status
Simulation time 28037769241 ps
CPU time 49.48 seconds
Started Feb 07 01:38:36 PM PST 24
Finished Feb 07 01:39:32 PM PST 24
Peak memory 200000 kb
Host smart-788e8214-a820-4ca5-8d29-75b69ea0ce26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318065354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.318065354
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.934765003
Short name T435
Test name
Test status
Simulation time 18637387198 ps
CPU time 13.57 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:38:56 PM PST 24
Peak memory 197936 kb
Host smart-e2c04ebf-7154-451c-8249-051504aa33b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934765003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.934765003
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4257722798
Short name T1223
Test name
Test status
Simulation time 136273871588 ps
CPU time 54.44 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:39:37 PM PST 24
Peak memory 199924 kb
Host smart-7ff3fb20-8d75-4b23-bb87-b4994c81d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257722798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4257722798
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3101754010
Short name T675
Test name
Test status
Simulation time 31964710 ps
CPU time 0.54 seconds
Started Feb 07 01:32:59 PM PST 24
Finished Feb 07 01:33:01 PM PST 24
Peak memory 194352 kb
Host smart-7bb5926b-16be-40c3-a88c-334e04de7a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101754010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3101754010
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3019486094
Short name T733
Test name
Test status
Simulation time 30195598470 ps
CPU time 11.88 seconds
Started Feb 07 01:32:54 PM PST 24
Finished Feb 07 01:33:06 PM PST 24
Peak memory 199956 kb
Host smart-1078909f-aa40-4097-8b8e-3a4a93cd8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019486094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3019486094
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4121506664
Short name T1020
Test name
Test status
Simulation time 40205595001 ps
CPU time 33.15 seconds
Started Feb 07 01:32:56 PM PST 24
Finished Feb 07 01:33:30 PM PST 24
Peak memory 199752 kb
Host smart-af2eddad-f707-4b69-8b07-7d28fa48d54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121506664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4121506664
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.3240784265
Short name T1004
Test name
Test status
Simulation time 1301483386233 ps
CPU time 1890.26 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 198504 kb
Host smart-648c5cac-e536-4b64-a216-e86099e6a705
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240784265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3240784265
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_loopback.2134599826
Short name T694
Test name
Test status
Simulation time 7812690914 ps
CPU time 9.04 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:33:03 PM PST 24
Peak memory 199224 kb
Host smart-bca41dbd-1877-4fdb-8163-6cc6d3594dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134599826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2134599826
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.390155251
Short name T521
Test name
Test status
Simulation time 60759284779 ps
CPU time 28.64 seconds
Started Feb 07 01:32:54 PM PST 24
Finished Feb 07 01:33:23 PM PST 24
Peak memory 199876 kb
Host smart-114853ca-2ecb-4f09-b2ae-8871ecfb258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390155251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.390155251
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1046769022
Short name T1216
Test name
Test status
Simulation time 21126128837 ps
CPU time 539.68 seconds
Started Feb 07 01:32:55 PM PST 24
Finished Feb 07 01:41:56 PM PST 24
Peak memory 199904 kb
Host smart-8f1b77c3-dd65-42de-9166-953db0fd1880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046769022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1046769022
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3455095529
Short name T1211
Test name
Test status
Simulation time 3341259245 ps
CPU time 25.77 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:33:20 PM PST 24
Peak memory 198144 kb
Host smart-d482756b-1f59-49da-a7ba-31217920c65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455095529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3455095529
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.175252887
Short name T600
Test name
Test status
Simulation time 17520882314 ps
CPU time 31.24 seconds
Started Feb 07 01:32:59 PM PST 24
Finished Feb 07 01:33:32 PM PST 24
Peak memory 199776 kb
Host smart-8e7246d8-a551-4bce-aef6-62f2dd6eb18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175252887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.175252887
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3067831047
Short name T868
Test name
Test status
Simulation time 25042979562 ps
CPU time 30.55 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:33:24 PM PST 24
Peak memory 195448 kb
Host smart-1836edfe-de2e-45e6-b025-e094700aea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067831047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3067831047
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3894436946
Short name T418
Test name
Test status
Simulation time 508281157 ps
CPU time 2.6 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:56 PM PST 24
Peak memory 197664 kb
Host smart-bf6fa179-62fe-4c87-b0f9-17d8a8ff1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894436946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3894436946
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2435694656
Short name T973
Test name
Test status
Simulation time 62072639923 ps
CPU time 328.67 seconds
Started Feb 07 01:32:55 PM PST 24
Finished Feb 07 01:38:25 PM PST 24
Peak memory 208264 kb
Host smart-b716ddf8-d907-4262-a75f-4929a0d92c79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435694656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2435694656
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1905379275
Short name T1225
Test name
Test status
Simulation time 1194223192 ps
CPU time 3.18 seconds
Started Feb 07 01:32:55 PM PST 24
Finished Feb 07 01:32:59 PM PST 24
Peak memory 199304 kb
Host smart-6b26f69c-9a3c-4d5f-8d0b-0262d6fb78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905379275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1905379275
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2106681653
Short name T781
Test name
Test status
Simulation time 51288763877 ps
CPU time 24.04 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:33:18 PM PST 24
Peak memory 199892 kb
Host smart-b153fd4b-6167-4649-822d-bd58bf39c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106681653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2106681653
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.549991300
Short name T137
Test name
Test status
Simulation time 95115751223 ps
CPU time 159.52 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:41:22 PM PST 24
Peak memory 199872 kb
Host smart-2103f0cb-37e9-4be6-8d09-79ed465d6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549991300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.549991300
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2858439854
Short name T1050
Test name
Test status
Simulation time 145120270130 ps
CPU time 58.36 seconds
Started Feb 07 01:38:37 PM PST 24
Finished Feb 07 01:39:41 PM PST 24
Peak memory 199872 kb
Host smart-35f74e14-e607-463e-819e-13c1fd50aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858439854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2858439854
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3704855596
Short name T892
Test name
Test status
Simulation time 123554766382 ps
CPU time 53.53 seconds
Started Feb 07 01:38:43 PM PST 24
Finished Feb 07 01:39:39 PM PST 24
Peak memory 199956 kb
Host smart-af83a268-f743-48fe-a64f-4700badfe909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704855596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3704855596
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1456650455
Short name T167
Test name
Test status
Simulation time 26283741085 ps
CPU time 40.98 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:39:27 PM PST 24
Peak memory 200024 kb
Host smart-35a92a04-d737-4264-927b-a1c43c34e6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456650455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1456650455
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2600512545
Short name T340
Test name
Test status
Simulation time 19224264098 ps
CPU time 10.96 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:38:57 PM PST 24
Peak memory 199236 kb
Host smart-a535fb19-abbd-4b06-9ec5-4aff292f92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600512545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2600512545
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3222355953
Short name T162
Test name
Test status
Simulation time 65600063407 ps
CPU time 145.94 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:41:12 PM PST 24
Peak memory 199924 kb
Host smart-4cdd2628-1ea5-4c77-bc0c-106e53d65626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222355953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3222355953
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.75067235
Short name T577
Test name
Test status
Simulation time 40008518 ps
CPU time 0.54 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:17 PM PST 24
Peak memory 195324 kb
Host smart-a0766e16-346a-40ac-9ce7-dd773110fd92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75067235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.75067235
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.887076424
Short name T684
Test name
Test status
Simulation time 89743100984 ps
CPU time 74.99 seconds
Started Feb 07 01:33:06 PM PST 24
Finished Feb 07 01:34:21 PM PST 24
Peak memory 199912 kb
Host smart-3ca7aedb-aa74-4f42-948a-f9725314d91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887076424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.887076424
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3363864417
Short name T199
Test name
Test status
Simulation time 86476511840 ps
CPU time 134.93 seconds
Started Feb 07 01:33:04 PM PST 24
Finished Feb 07 01:35:20 PM PST 24
Peak memory 199976 kb
Host smart-e702f5f1-1141-45d0-bdcf-7f46752603df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363864417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3363864417
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3099485580
Short name T145
Test name
Test status
Simulation time 48480454000 ps
CPU time 38.53 seconds
Started Feb 07 01:33:06 PM PST 24
Finished Feb 07 01:33:45 PM PST 24
Peak memory 199940 kb
Host smart-fd73da62-2a9b-433f-ac4c-885495fb8b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099485580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3099485580
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1842228804
Short name T433
Test name
Test status
Simulation time 60217135158 ps
CPU time 43.86 seconds
Started Feb 07 01:33:03 PM PST 24
Finished Feb 07 01:33:48 PM PST 24
Peak memory 197848 kb
Host smart-ba7f0310-f983-49f6-a35d-ab86aaa190b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842228804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1842228804
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1399630136
Short name T295
Test name
Test status
Simulation time 75443062834 ps
CPU time 298.53 seconds
Started Feb 07 01:33:01 PM PST 24
Finished Feb 07 01:38:00 PM PST 24
Peak memory 199960 kb
Host smart-9e807006-ca99-4217-a8e0-eb37340244db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399630136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1399630136
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3059916931
Short name T717
Test name
Test status
Simulation time 9945637319 ps
CPU time 7.21 seconds
Started Feb 07 01:33:02 PM PST 24
Finished Feb 07 01:33:09 PM PST 24
Peak memory 199808 kb
Host smart-1c7eadf1-d8cd-489e-ac56-204b65b99115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059916931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3059916931
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3851876012
Short name T838
Test name
Test status
Simulation time 10383410230 ps
CPU time 17.29 seconds
Started Feb 07 01:33:06 PM PST 24
Finished Feb 07 01:33:23 PM PST 24
Peak memory 198736 kb
Host smart-779b0357-9ebc-4704-9c5a-d16e3259002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851876012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3851876012
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.43133286
Short name T115
Test name
Test status
Simulation time 7377577221 ps
CPU time 175 seconds
Started Feb 07 01:33:02 PM PST 24
Finished Feb 07 01:35:58 PM PST 24
Peak memory 199888 kb
Host smart-503271bb-7159-4172-8585-6e9d61bd7452
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43133286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.43133286
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2309099796
Short name T540
Test name
Test status
Simulation time 2058109053 ps
CPU time 6.61 seconds
Started Feb 07 01:33:00 PM PST 24
Finished Feb 07 01:33:08 PM PST 24
Peak memory 197764 kb
Host smart-a8019b1e-dd17-48f4-beb3-af0fbdc71621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309099796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2309099796
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1032540144
Short name T729
Test name
Test status
Simulation time 81324679321 ps
CPU time 30.31 seconds
Started Feb 07 01:33:06 PM PST 24
Finished Feb 07 01:33:37 PM PST 24
Peak memory 199940 kb
Host smart-10683260-905d-45fc-92d9-9d0011f7530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032540144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1032540144
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.28000533
Short name T944
Test name
Test status
Simulation time 6032610941 ps
CPU time 2.91 seconds
Started Feb 07 01:33:01 PM PST 24
Finished Feb 07 01:33:04 PM PST 24
Peak memory 195688 kb
Host smart-e9da1625-1a2d-4ef3-903e-6d02af01482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28000533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.28000533
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4082079358
Short name T555
Test name
Test status
Simulation time 869846386 ps
CPU time 1.95 seconds
Started Feb 07 01:33:02 PM PST 24
Finished Feb 07 01:33:04 PM PST 24
Peak memory 198108 kb
Host smart-76efe4b2-5015-4ad3-b911-e642aa2df1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082079358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4082079358
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3759028507
Short name T396
Test name
Test status
Simulation time 249789721191 ps
CPU time 333.91 seconds
Started Feb 07 01:33:15 PM PST 24
Finished Feb 07 01:38:50 PM PST 24
Peak memory 199976 kb
Host smart-11b2218b-339b-4600-a150-b59f8749c0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759028507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3759028507
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.39715635
Short name T71
Test name
Test status
Simulation time 217538342231 ps
CPU time 871.54 seconds
Started Feb 07 01:33:15 PM PST 24
Finished Feb 07 01:47:47 PM PST 24
Peak memory 224904 kb
Host smart-04f75a90-bb7f-4618-abef-ca5413be4050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715635 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.39715635
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.859184481
Short name T955
Test name
Test status
Simulation time 1198480848 ps
CPU time 4.85 seconds
Started Feb 07 01:32:59 PM PST 24
Finished Feb 07 01:33:05 PM PST 24
Peak memory 198280 kb
Host smart-b4edda9d-c438-4d59-8225-f1695d5242a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859184481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.859184481
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.81714237
Short name T740
Test name
Test status
Simulation time 27197844156 ps
CPU time 49.22 seconds
Started Feb 07 01:33:03 PM PST 24
Finished Feb 07 01:33:53 PM PST 24
Peak memory 199900 kb
Host smart-ec920224-0947-4a37-bd6f-985f5144dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81714237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.81714237
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.757227116
Short name T1169
Test name
Test status
Simulation time 41806582447 ps
CPU time 36.54 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:39:22 PM PST 24
Peak memory 199856 kb
Host smart-da2c98a5-6a04-4e2e-96f1-833b101d09ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757227116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.757227116
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3995978247
Short name T1070
Test name
Test status
Simulation time 45408530570 ps
CPU time 19.69 seconds
Started Feb 07 01:38:48 PM PST 24
Finished Feb 07 01:39:08 PM PST 24
Peak memory 199660 kb
Host smart-95eceaed-1e64-4bf7-82b1-551a87444763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995978247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3995978247
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4038287136
Short name T1212
Test name
Test status
Simulation time 88185379744 ps
CPU time 65.51 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:39:51 PM PST 24
Peak memory 199868 kb
Host smart-561bdb3e-c679-453b-a97f-a415e2e05752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038287136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4038287136
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1815217516
Short name T1191
Test name
Test status
Simulation time 44080818886 ps
CPU time 77.16 seconds
Started Feb 07 01:38:44 PM PST 24
Finished Feb 07 01:40:03 PM PST 24
Peak memory 199968 kb
Host smart-c273132e-901b-42fe-a7a2-d99d6f377b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815217516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1815217516
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.996090588
Short name T858
Test name
Test status
Simulation time 51357680202 ps
CPU time 37.93 seconds
Started Feb 07 01:39:06 PM PST 24
Finished Feb 07 01:39:44 PM PST 24
Peak memory 199376 kb
Host smart-a802cf17-adb3-482f-ac97-f4375641a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996090588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.996090588
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2941052042
Short name T350
Test name
Test status
Simulation time 131187633326 ps
CPU time 233.71 seconds
Started Feb 07 01:39:01 PM PST 24
Finished Feb 07 01:42:55 PM PST 24
Peak memory 199976 kb
Host smart-463408d7-c096-404c-af1b-a453a4512b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941052042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2941052042
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2690786192
Short name T248
Test name
Test status
Simulation time 116454551385 ps
CPU time 35.36 seconds
Started Feb 07 01:38:59 PM PST 24
Finished Feb 07 01:39:35 PM PST 24
Peak memory 199764 kb
Host smart-afc17c67-e6a3-4522-bd17-16b3b96317ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690786192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2690786192
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.571246868
Short name T998
Test name
Test status
Simulation time 57495774 ps
CPU time 0.51 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:17 PM PST 24
Peak memory 194236 kb
Host smart-e1f14769-111c-4d10-b0ca-76d9f91b110c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571246868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.571246868
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1155363850
Short name T636
Test name
Test status
Simulation time 132843238792 ps
CPU time 270.49 seconds
Started Feb 07 01:33:12 PM PST 24
Finished Feb 07 01:37:43 PM PST 24
Peak memory 200012 kb
Host smart-996d59e2-9454-4f1b-bfcc-fb361efb7aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155363850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1155363850
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2160829834
Short name T887
Test name
Test status
Simulation time 80988835197 ps
CPU time 132.78 seconds
Started Feb 07 01:33:15 PM PST 24
Finished Feb 07 01:35:28 PM PST 24
Peak memory 199880 kb
Host smart-8bf861f8-ccee-4e33-8155-36244af72494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160829834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2160829834
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.989952884
Short name T1000
Test name
Test status
Simulation time 82548665394 ps
CPU time 39.68 seconds
Started Feb 07 01:33:17 PM PST 24
Finished Feb 07 01:33:57 PM PST 24
Peak memory 199520 kb
Host smart-1ac74a87-60cc-44f7-9055-53b1f7cc41e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989952884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.989952884
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1068858884
Short name T819
Test name
Test status
Simulation time 1519429840256 ps
CPU time 2518.34 seconds
Started Feb 07 01:33:17 PM PST 24
Finished Feb 07 02:15:16 PM PST 24
Peak memory 199904 kb
Host smart-f9d66f1a-3bca-492e-bdfa-ef9d1e60f498
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068858884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1068858884
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3193496865
Short name T1154
Test name
Test status
Simulation time 87451380376 ps
CPU time 115.13 seconds
Started Feb 07 01:33:13 PM PST 24
Finished Feb 07 01:35:09 PM PST 24
Peak memory 199980 kb
Host smart-5202a8bf-3efe-4f23-a79f-c6c3629a7900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193496865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3193496865
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1250293096
Short name T1022
Test name
Test status
Simulation time 3218306071 ps
CPU time 5.47 seconds
Started Feb 07 01:33:15 PM PST 24
Finished Feb 07 01:33:21 PM PST 24
Peak memory 198668 kb
Host smart-eeda5f29-57c9-4757-b03f-9b222d5e5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250293096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1250293096
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2083324616
Short name T849
Test name
Test status
Simulation time 162131610105 ps
CPU time 319.41 seconds
Started Feb 07 01:33:17 PM PST 24
Finished Feb 07 01:38:37 PM PST 24
Peak memory 200176 kb
Host smart-8afc6cac-3500-4dd7-8310-1a686f8cbbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083324616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2083324616
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3616204677
Short name T693
Test name
Test status
Simulation time 20871197828 ps
CPU time 242.16 seconds
Started Feb 07 01:33:31 PM PST 24
Finished Feb 07 01:37:33 PM PST 24
Peak memory 199960 kb
Host smart-35684067-4ec6-4947-93e4-ef150ce04bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616204677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3616204677
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2367832465
Short name T863
Test name
Test status
Simulation time 28851729318 ps
CPU time 17.54 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:34 PM PST 24
Peak memory 198516 kb
Host smart-d14c4518-7149-4166-ac3e-352eb8ecc6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367832465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2367832465
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4225290989
Short name T638
Test name
Test status
Simulation time 3053999029 ps
CPU time 2.82 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:19 PM PST 24
Peak memory 195344 kb
Host smart-015a2f89-fd8c-4897-9abd-762951f0f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225290989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4225290989
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3639350320
Short name T99
Test name
Test status
Simulation time 5863491417 ps
CPU time 13.64 seconds
Started Feb 07 01:33:18 PM PST 24
Finished Feb 07 01:33:32 PM PST 24
Peak memory 199160 kb
Host smart-020ecf75-5d7c-4071-b7bb-e7218f9a7cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639350320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3639350320
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2244258733
Short name T676
Test name
Test status
Simulation time 159493383341 ps
CPU time 39.12 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:56 PM PST 24
Peak memory 208452 kb
Host smart-c3efd3dc-5f9a-4ae8-a3f5-5b3f7cdc3555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244258733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2244258733
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3703637646
Short name T373
Test name
Test status
Simulation time 203278430776 ps
CPU time 703.17 seconds
Started Feb 07 01:33:17 PM PST 24
Finished Feb 07 01:45:00 PM PST 24
Peak memory 216460 kb
Host smart-3aa7a1fa-5f78-4e3b-a1b9-44116674d3d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703637646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3703637646
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1487937169
Short name T1079
Test name
Test status
Simulation time 927590008 ps
CPU time 2.83 seconds
Started Feb 07 01:33:14 PM PST 24
Finished Feb 07 01:33:18 PM PST 24
Peak memory 198220 kb
Host smart-7515dfc2-d29c-4f72-9b37-22e87a04f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487937169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1487937169
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.604915795
Short name T827
Test name
Test status
Simulation time 37312357825 ps
CPU time 63.62 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:34:20 PM PST 24
Peak memory 200008 kb
Host smart-ee460709-dd1c-4945-bc9a-8b89df376b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604915795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.604915795
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1600631750
Short name T718
Test name
Test status
Simulation time 19765255095 ps
CPU time 12.7 seconds
Started Feb 07 01:39:00 PM PST 24
Finished Feb 07 01:39:14 PM PST 24
Peak memory 199988 kb
Host smart-7c2952aa-a560-4d7f-8795-9804ae96b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600631750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1600631750
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.831061126
Short name T104
Test name
Test status
Simulation time 150190964761 ps
CPU time 224.3 seconds
Started Feb 07 01:38:59 PM PST 24
Finished Feb 07 01:42:44 PM PST 24
Peak memory 199916 kb
Host smart-a8cac7b6-ed25-45ca-bcd2-81cf18e28d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831061126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.831061126
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3141278811
Short name T830
Test name
Test status
Simulation time 100519798399 ps
CPU time 110.17 seconds
Started Feb 07 01:38:59 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 199956 kb
Host smart-3330cd10-cc9c-45f4-abc5-b6575b37fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141278811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3141278811
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1980005802
Short name T203
Test name
Test status
Simulation time 38500412736 ps
CPU time 32.06 seconds
Started Feb 07 01:38:57 PM PST 24
Finished Feb 07 01:39:30 PM PST 24
Peak memory 199968 kb
Host smart-990aa94d-7df0-487d-8d46-78e5ecd28ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980005802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1980005802
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1276408911
Short name T1105
Test name
Test status
Simulation time 26931375477 ps
CPU time 40.17 seconds
Started Feb 07 01:39:00 PM PST 24
Finished Feb 07 01:39:41 PM PST 24
Peak memory 199112 kb
Host smart-77d02d65-2796-443b-a4bf-b88d6324f087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276408911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1276408911
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2054793842
Short name T125
Test name
Test status
Simulation time 110616030883 ps
CPU time 185.85 seconds
Started Feb 07 01:39:05 PM PST 24
Finished Feb 07 01:42:12 PM PST 24
Peak memory 199892 kb
Host smart-5587d6cd-be2b-4433-b819-25c7af5b84ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054793842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2054793842
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2384546191
Short name T575
Test name
Test status
Simulation time 5884554521 ps
CPU time 9.77 seconds
Started Feb 07 01:39:05 PM PST 24
Finished Feb 07 01:39:15 PM PST 24
Peak memory 199428 kb
Host smart-6fb32baa-9cd4-448d-b00f-4c7e5e2faafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384546191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2384546191
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.270925647
Short name T1096
Test name
Test status
Simulation time 39960336 ps
CPU time 0.53 seconds
Started Feb 07 01:33:36 PM PST 24
Finished Feb 07 01:33:37 PM PST 24
Peak memory 194236 kb
Host smart-f7c56801-a83b-4923-9b6e-f74fd98b2be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270925647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.270925647
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4008000262
Short name T1122
Test name
Test status
Simulation time 38099395191 ps
CPU time 11.99 seconds
Started Feb 07 01:33:13 PM PST 24
Finished Feb 07 01:33:26 PM PST 24
Peak memory 199936 kb
Host smart-e43c0b46-7e83-4ab8-84eb-14efe2f556d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008000262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4008000262
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3603974637
Short name T886
Test name
Test status
Simulation time 135864647626 ps
CPU time 60.56 seconds
Started Feb 07 01:33:30 PM PST 24
Finished Feb 07 01:34:31 PM PST 24
Peak memory 199076 kb
Host smart-05285a80-610e-41d5-92d3-2291812bb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603974637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3603974637
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1154930787
Short name T997
Test name
Test status
Simulation time 248254766507 ps
CPU time 1813.78 seconds
Started Feb 07 01:33:14 PM PST 24
Finished Feb 07 02:03:29 PM PST 24
Peak memory 199904 kb
Host smart-a698d03c-ec0c-4884-a55e-7faaec41e4dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154930787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1154930787
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4134719289
Short name T686
Test name
Test status
Simulation time 106551439120 ps
CPU time 574.65 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 199868 kb
Host smart-417a7ae8-6ac6-4966-8ec8-f3708c978bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134719289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4134719289
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.371464624
Short name T683
Test name
Test status
Simulation time 9052045861 ps
CPU time 10.06 seconds
Started Feb 07 01:33:15 PM PST 24
Finished Feb 07 01:33:25 PM PST 24
Peak memory 198440 kb
Host smart-d50b9a14-aaff-4c65-a3a4-d11bbae0ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371464624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.371464624
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.747120098
Short name T503
Test name
Test status
Simulation time 8279459845 ps
CPU time 16.91 seconds
Started Feb 07 01:33:14 PM PST 24
Finished Feb 07 01:33:31 PM PST 24
Peak memory 195960 kb
Host smart-3f83706c-8152-4d3b-93f4-9fae99add8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747120098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.747120098
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2943841603
Short name T609
Test name
Test status
Simulation time 19768709582 ps
CPU time 57.17 seconds
Started Feb 07 01:33:30 PM PST 24
Finished Feb 07 01:34:28 PM PST 24
Peak memory 200020 kb
Host smart-338bffe8-0bcd-4aa8-9ac1-628b30992dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943841603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2943841603
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.62504068
Short name T548
Test name
Test status
Simulation time 2644363482 ps
CPU time 4.34 seconds
Started Feb 07 01:33:16 PM PST 24
Finished Feb 07 01:33:20 PM PST 24
Peak memory 197608 kb
Host smart-127f1872-9d62-498f-b58e-035571c7beab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62504068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.62504068
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.713447760
Short name T906
Test name
Test status
Simulation time 35111127081 ps
CPU time 29.63 seconds
Started Feb 07 01:33:32 PM PST 24
Finished Feb 07 01:34:03 PM PST 24
Peak memory 198700 kb
Host smart-405ea982-6017-479c-8290-ae3eac05452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713447760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.713447760
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3763037014
Short name T102
Test name
Test status
Simulation time 2770284151 ps
CPU time 4.28 seconds
Started Feb 07 01:33:14 PM PST 24
Finished Feb 07 01:33:18 PM PST 24
Peak memory 195288 kb
Host smart-6215c9fc-7f85-48d3-b924-3fd02e36d095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763037014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3763037014
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.779715712
Short name T1195
Test name
Test status
Simulation time 5734280574 ps
CPU time 17.6 seconds
Started Feb 07 01:33:32 PM PST 24
Finished Feb 07 01:33:51 PM PST 24
Peak memory 199116 kb
Host smart-ca7b0a83-02ac-4f6f-8999-f7caa4e46668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779715712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.779715712
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.645754506
Short name T1192
Test name
Test status
Simulation time 496597160351 ps
CPU time 137.86 seconds
Started Feb 07 01:33:29 PM PST 24
Finished Feb 07 01:35:48 PM PST 24
Peak memory 199924 kb
Host smart-4907f4cb-54dc-4e88-ac4c-b54904ec3bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645754506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.645754506
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2323697780
Short name T580
Test name
Test status
Simulation time 27514114627 ps
CPU time 575.42 seconds
Started Feb 07 01:33:31 PM PST 24
Finished Feb 07 01:43:07 PM PST 24
Peak memory 216756 kb
Host smart-097d0d74-40b3-43b7-8d09-4049383bdfe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323697780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2323697780
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1484603628
Short name T708
Test name
Test status
Simulation time 1970347651 ps
CPU time 1.87 seconds
Started Feb 07 01:33:30 PM PST 24
Finished Feb 07 01:33:32 PM PST 24
Peak memory 198244 kb
Host smart-a6bd5b62-54e5-493a-a76d-30f840b1fd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484603628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1484603628
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.350496271
Short name T393
Test name
Test status
Simulation time 62414745444 ps
CPU time 136.39 seconds
Started Feb 07 01:33:13 PM PST 24
Finished Feb 07 01:35:30 PM PST 24
Peak memory 199996 kb
Host smart-40eb5f65-51f7-4604-9422-1f8ae03e6be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350496271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.350496271
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3783263683
Short name T728
Test name
Test status
Simulation time 122789311963 ps
CPU time 196.87 seconds
Started Feb 07 01:39:03 PM PST 24
Finished Feb 07 01:42:21 PM PST 24
Peak memory 200020 kb
Host smart-9b25b4d5-a6e1-46a7-bd73-0a04ecec9a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783263683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3783263683
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1713706181
Short name T655
Test name
Test status
Simulation time 48577426888 ps
CPU time 21.65 seconds
Started Feb 07 01:39:02 PM PST 24
Finished Feb 07 01:39:25 PM PST 24
Peak memory 197808 kb
Host smart-560f0185-fc70-4872-848d-36febda3bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713706181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1713706181
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.872007215
Short name T281
Test name
Test status
Simulation time 87878616175 ps
CPU time 141.9 seconds
Started Feb 07 01:39:06 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 199896 kb
Host smart-415a4f8a-d5da-4b2c-aaba-85046c9bfa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872007215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.872007215
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1345873535
Short name T158
Test name
Test status
Simulation time 50743115425 ps
CPU time 74.68 seconds
Started Feb 07 01:39:04 PM PST 24
Finished Feb 07 01:40:20 PM PST 24
Peak memory 199980 kb
Host smart-32e87bc8-eaa2-4a21-a37f-215a4e306705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345873535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1345873535
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1526871694
Short name T1181
Test name
Test status
Simulation time 66299737025 ps
CPU time 26.53 seconds
Started Feb 07 01:39:05 PM PST 24
Finished Feb 07 01:39:32 PM PST 24
Peak memory 198856 kb
Host smart-fe3cca95-ae06-4347-81c6-a37c44c47c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526871694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1526871694
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4092529847
Short name T260
Test name
Test status
Simulation time 21128671920 ps
CPU time 11.75 seconds
Started Feb 07 01:39:04 PM PST 24
Finished Feb 07 01:39:17 PM PST 24
Peak memory 199408 kb
Host smart-990e770a-8956-49ec-b06c-24fc88e4e142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092529847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4092529847
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.500677462
Short name T214
Test name
Test status
Simulation time 105433233035 ps
CPU time 164.67 seconds
Started Feb 07 01:39:05 PM PST 24
Finished Feb 07 01:41:50 PM PST 24
Peak memory 199988 kb
Host smart-4ebc7f45-ba6a-4cdf-a885-9a193e83823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500677462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.500677462
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2154889398
Short name T497
Test name
Test status
Simulation time 41555501 ps
CPU time 0.55 seconds
Started Feb 07 01:33:43 PM PST 24
Finished Feb 07 01:33:44 PM PST 24
Peak memory 194332 kb
Host smart-12d38cd9-8f2c-4dfc-b35f-ad18bba79ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154889398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2154889398
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1645120075
Short name T814
Test name
Test status
Simulation time 261546957794 ps
CPU time 508.66 seconds
Started Feb 07 01:33:37 PM PST 24
Finished Feb 07 01:42:06 PM PST 24
Peak memory 199916 kb
Host smart-8ca6d18f-0282-45e9-8abe-1eec3e9ddb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645120075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1645120075
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.994834411
Short name T272
Test name
Test status
Simulation time 30379919226 ps
CPU time 47.73 seconds
Started Feb 07 01:33:31 PM PST 24
Finished Feb 07 01:34:19 PM PST 24
Peak memory 199912 kb
Host smart-5aae8570-c23b-439b-840d-3f6a1471771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994834411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.994834411
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.4038874918
Short name T611
Test name
Test status
Simulation time 8950509782 ps
CPU time 18.47 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:34:00 PM PST 24
Peak memory 199132 kb
Host smart-3fd9331e-4799-41c8-93c3-e6d62debc1c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038874918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4038874918
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1669638968
Short name T767
Test name
Test status
Simulation time 94824268274 ps
CPU time 116.23 seconds
Started Feb 07 01:33:39 PM PST 24
Finished Feb 07 01:35:36 PM PST 24
Peak memory 199900 kb
Host smart-52619f8f-f12a-4e13-a801-7622fa1a11c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669638968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1669638968
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1475715159
Short name T1024
Test name
Test status
Simulation time 1466333203 ps
CPU time 0.83 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:33:42 PM PST 24
Peak memory 195432 kb
Host smart-0d3430cf-b467-49ce-a7d0-53960e94ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475715159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1475715159
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3075170025
Short name T829
Test name
Test status
Simulation time 6367322172 ps
CPU time 11.34 seconds
Started Feb 07 01:33:42 PM PST 24
Finished Feb 07 01:33:54 PM PST 24
Peak memory 195728 kb
Host smart-eff243b2-9997-430a-8ce9-d6bc69cb9c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075170025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3075170025
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1907907305
Short name T833
Test name
Test status
Simulation time 12543292008 ps
CPU time 367.45 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:39:49 PM PST 24
Peak memory 199896 kb
Host smart-90cfbc89-cb2f-434b-8571-110e6ac14b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907907305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1907907305
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2335907218
Short name T1164
Test name
Test status
Simulation time 2508620476 ps
CPU time 2.23 seconds
Started Feb 07 01:33:32 PM PST 24
Finished Feb 07 01:33:35 PM PST 24
Peak memory 198368 kb
Host smart-fab8b146-6f30-47c2-87e8-e5e2b5c9fddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335907218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2335907218
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2484191026
Short name T1103
Test name
Test status
Simulation time 51198350211 ps
CPU time 42.06 seconds
Started Feb 07 01:33:42 PM PST 24
Finished Feb 07 01:34:25 PM PST 24
Peak memory 199132 kb
Host smart-dbc9b500-103a-4128-9425-bf239c0a6a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484191026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2484191026
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2641776658
Short name T1133
Test name
Test status
Simulation time 37129894442 ps
CPU time 64.22 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 195680 kb
Host smart-c2426aac-7850-4476-bf41-e41350def12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641776658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2641776658
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3212250526
Short name T1190
Test name
Test status
Simulation time 269300213 ps
CPU time 1.48 seconds
Started Feb 07 01:33:35 PM PST 24
Finished Feb 07 01:33:37 PM PST 24
Peak memory 198004 kb
Host smart-2a1991a0-eb56-400e-b65e-a307c6c4a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212250526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3212250526
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.496546522
Short name T508
Test name
Test status
Simulation time 6811800226 ps
CPU time 11.17 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:33:56 PM PST 24
Peak memory 199836 kb
Host smart-b0de4dfd-51bc-418e-98b1-b973c4c7a5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496546522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.496546522
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3040703955
Short name T416
Test name
Test status
Simulation time 297542290872 ps
CPU time 275.95 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:38:20 PM PST 24
Peak memory 215672 kb
Host smart-5ea7e424-bb77-4a0a-bc5c-696291b9b7bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040703955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3040703955
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2252599709
Short name T1153
Test name
Test status
Simulation time 4173253013 ps
CPU time 1.64 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:33:47 PM PST 24
Peak memory 199040 kb
Host smart-1afc506d-7237-4b22-bcc4-88afaf57c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252599709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2252599709
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3660977675
Short name T1013
Test name
Test status
Simulation time 30332852012 ps
CPU time 11.71 seconds
Started Feb 07 01:33:33 PM PST 24
Finished Feb 07 01:33:45 PM PST 24
Peak memory 199076 kb
Host smart-6595c3d8-8aa0-478f-a8b5-a43fbd80ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660977675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3660977675
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.416859214
Short name T709
Test name
Test status
Simulation time 75229195834 ps
CPU time 127.79 seconds
Started Feb 07 01:39:13 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 199976 kb
Host smart-5b0c1a64-54f4-4258-bf17-d98bb99677e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416859214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.416859214
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.357690223
Short name T895
Test name
Test status
Simulation time 93592238848 ps
CPU time 133.7 seconds
Started Feb 07 01:39:14 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 199712 kb
Host smart-7848301c-a10c-4e8e-8e7f-5f2e824b3a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357690223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.357690223
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2933450403
Short name T407
Test name
Test status
Simulation time 102246642963 ps
CPU time 154.63 seconds
Started Feb 07 01:39:14 PM PST 24
Finished Feb 07 01:41:49 PM PST 24
Peak memory 199744 kb
Host smart-d11774d1-87a6-44bf-b5f9-ba1147df590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933450403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2933450403
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4036501811
Short name T859
Test name
Test status
Simulation time 28788622985 ps
CPU time 50.17 seconds
Started Feb 07 01:39:13 PM PST 24
Finished Feb 07 01:40:04 PM PST 24
Peak memory 199948 kb
Host smart-5b1539c4-d079-4486-b168-49d26832b448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036501811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4036501811
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3707298288
Short name T259
Test name
Test status
Simulation time 33472938331 ps
CPU time 106.43 seconds
Started Feb 07 01:39:13 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 199932 kb
Host smart-313c8fdd-d1e2-43a6-8d33-6d14a6f51de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707298288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3707298288
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.416224170
Short name T1187
Test name
Test status
Simulation time 25732818268 ps
CPU time 43.37 seconds
Started Feb 07 01:39:12 PM PST 24
Finished Feb 07 01:39:56 PM PST 24
Peak memory 199944 kb
Host smart-7561bff1-c7c7-41eb-bd97-d2a400a6f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416224170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.416224170
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2546442375
Short name T301
Test name
Test status
Simulation time 28714902218 ps
CPU time 49.39 seconds
Started Feb 07 01:39:13 PM PST 24
Finished Feb 07 01:40:03 PM PST 24
Peak memory 199916 kb
Host smart-13ff109e-bc59-49a5-a760-b43e0f6592e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546442375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2546442375
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1284059512
Short name T691
Test name
Test status
Simulation time 31615681 ps
CPU time 0.53 seconds
Started Feb 07 01:33:47 PM PST 24
Finished Feb 07 01:33:48 PM PST 24
Peak memory 194340 kb
Host smart-cd6cc950-c6b3-4472-8102-30ae0e852cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284059512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1284059512
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2864008560
Short name T529
Test name
Test status
Simulation time 102369060101 ps
CPU time 37.93 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:34:23 PM PST 24
Peak memory 199892 kb
Host smart-e9ac3787-0c7f-4199-8c70-6903ee380ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864008560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2864008560
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.428870109
Short name T406
Test name
Test status
Simulation time 34365019775 ps
CPU time 47.74 seconds
Started Feb 07 01:33:37 PM PST 24
Finished Feb 07 01:34:25 PM PST 24
Peak memory 199736 kb
Host smart-e4d16113-d3a5-474d-87a1-f9cb6655d0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428870109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.428870109
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.897823094
Short name T725
Test name
Test status
Simulation time 39900857514 ps
CPU time 17.21 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:33:59 PM PST 24
Peak memory 199572 kb
Host smart-2fbfacc1-adea-493e-aa87-4e2c15f0f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897823094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.897823094
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.709610377
Short name T949
Test name
Test status
Simulation time 898195313124 ps
CPU time 500.93 seconds
Started Feb 07 01:33:42 PM PST 24
Finished Feb 07 01:42:03 PM PST 24
Peak memory 199900 kb
Host smart-595f2380-7ee1-47b8-868c-198fd34e8fa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709610377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.709610377
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.409758829
Short name T530
Test name
Test status
Simulation time 121129703315 ps
CPU time 636.2 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:44:22 PM PST 24
Peak memory 199948 kb
Host smart-0fb10477-4fc9-413a-b5cd-f391cd8e20b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409758829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.409758829
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.108234302
Short name T604
Test name
Test status
Simulation time 290733843 ps
CPU time 1.56 seconds
Started Feb 07 01:33:40 PM PST 24
Finished Feb 07 01:33:42 PM PST 24
Peak memory 198136 kb
Host smart-6d0c4f46-18c8-4e8e-8258-f2765d908107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108234302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.108234302
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1540646921
Short name T1034
Test name
Test status
Simulation time 28363679237 ps
CPU time 40.3 seconds
Started Feb 07 01:33:40 PM PST 24
Finished Feb 07 01:34:21 PM PST 24
Peak memory 198736 kb
Host smart-52cd7b94-b48d-4357-bd2a-f6bbf2a3712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540646921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1540646921
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.973952789
Short name T579
Test name
Test status
Simulation time 22533835766 ps
CPU time 1284.44 seconds
Started Feb 07 01:33:42 PM PST 24
Finished Feb 07 01:55:07 PM PST 24
Peak memory 199996 kb
Host smart-6a967912-dd33-4d97-b080-842570734ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973952789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.973952789
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.508294164
Short name T499
Test name
Test status
Simulation time 496947499 ps
CPU time 1.41 seconds
Started Feb 07 01:33:37 PM PST 24
Finished Feb 07 01:33:39 PM PST 24
Peak memory 197468 kb
Host smart-ce18ce75-5c68-40dd-a6b6-cb0afe9d1b4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508294164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.508294164
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2999168878
Short name T616
Test name
Test status
Simulation time 37423688899 ps
CPU time 74.45 seconds
Started Feb 07 01:33:37 PM PST 24
Finished Feb 07 01:34:52 PM PST 24
Peak memory 199896 kb
Host smart-ab689267-ee51-4381-a2f1-128d9a0ef932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999168878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2999168878
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.835598550
Short name T822
Test name
Test status
Simulation time 34635164028 ps
CPU time 57.88 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:34:43 PM PST 24
Peak memory 195660 kb
Host smart-5cd8fc6c-d10c-4cfe-934a-d6832a506c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835598550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.835598550
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1364601451
Short name T650
Test name
Test status
Simulation time 572313104 ps
CPU time 1.69 seconds
Started Feb 07 01:33:40 PM PST 24
Finished Feb 07 01:33:43 PM PST 24
Peak memory 198176 kb
Host smart-e6820137-3ef9-42be-a8dd-e1ba94f0bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364601451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1364601451
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.665666633
Short name T1175
Test name
Test status
Simulation time 479949901 ps
CPU time 2.07 seconds
Started Feb 07 01:33:49 PM PST 24
Finished Feb 07 01:33:52 PM PST 24
Peak memory 198980 kb
Host smart-23952541-94ad-4fd3-8e2d-e70b136e4db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665666633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.665666633
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3687720706
Short name T697
Test name
Test status
Simulation time 226303392392 ps
CPU time 122.14 seconds
Started Feb 07 01:33:41 PM PST 24
Finished Feb 07 01:35:44 PM PST 24
Peak memory 199908 kb
Host smart-b76a2edc-5bf8-4ef3-842a-2ae12e288a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687720706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3687720706
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3847831389
Short name T14
Test name
Test status
Simulation time 13675949336 ps
CPU time 20.29 seconds
Started Feb 07 01:39:21 PM PST 24
Finished Feb 07 01:39:42 PM PST 24
Peak memory 199360 kb
Host smart-5dc3c92e-7ed3-47d9-b829-f8fc512943d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847831389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3847831389
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.522058969
Short name T1234
Test name
Test status
Simulation time 221080458520 ps
CPU time 329.59 seconds
Started Feb 07 01:39:20 PM PST 24
Finished Feb 07 01:44:50 PM PST 24
Peak memory 200032 kb
Host smart-0d52bed3-9e73-42c0-9e6b-453e3276b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522058969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.522058969
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2748024599
Short name T969
Test name
Test status
Simulation time 32357207633 ps
CPU time 42.76 seconds
Started Feb 07 01:39:24 PM PST 24
Finished Feb 07 01:40:07 PM PST 24
Peak memory 199948 kb
Host smart-6f9119a4-d59f-4a4f-9d65-0fcf61c8ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748024599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2748024599
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2501415855
Short name T276
Test name
Test status
Simulation time 16636864070 ps
CPU time 24.89 seconds
Started Feb 07 01:39:22 PM PST 24
Finished Feb 07 01:39:47 PM PST 24
Peak memory 200008 kb
Host smart-3c925018-d0e7-4556-a835-5910c3a529b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501415855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2501415855
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2011002078
Short name T180
Test name
Test status
Simulation time 120806840241 ps
CPU time 26.15 seconds
Started Feb 07 01:39:22 PM PST 24
Finished Feb 07 01:39:49 PM PST 24
Peak memory 199800 kb
Host smart-a7e93826-9a94-4ca8-8a3f-6ede4be84e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011002078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2011002078
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3565689563
Short name T154
Test name
Test status
Simulation time 48378663133 ps
CPU time 33.31 seconds
Started Feb 07 01:39:21 PM PST 24
Finished Feb 07 01:39:55 PM PST 24
Peak memory 199572 kb
Host smart-d40fb5c1-085a-4baa-b6c8-6ab9f6458637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565689563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3565689563
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1059681704
Short name T1178
Test name
Test status
Simulation time 20953779959 ps
CPU time 33.07 seconds
Started Feb 07 01:39:22 PM PST 24
Finished Feb 07 01:39:56 PM PST 24
Peak memory 199948 kb
Host smart-160f52e8-7763-4e01-8eca-02213231d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059681704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1059681704
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3689383073
Short name T231
Test name
Test status
Simulation time 62311652971 ps
CPU time 18.23 seconds
Started Feb 07 01:39:22 PM PST 24
Finished Feb 07 01:39:41 PM PST 24
Peak memory 199988 kb
Host smart-d44a5b88-2b65-450d-a33b-af302532d1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689383073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3689383073
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4244008123
Short name T551
Test name
Test status
Simulation time 31306219 ps
CPU time 0.55 seconds
Started Feb 07 01:33:47 PM PST 24
Finished Feb 07 01:33:48 PM PST 24
Peak memory 194408 kb
Host smart-70a0d56f-c4d3-4c94-b9a8-e5b9eb5e852e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244008123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4244008123
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2464944638
Short name T786
Test name
Test status
Simulation time 76162679133 ps
CPU time 76.28 seconds
Started Feb 07 01:33:48 PM PST 24
Finished Feb 07 01:35:05 PM PST 24
Peak memory 199928 kb
Host smart-f301aba6-fe5f-44d3-8f29-bae61b9d7aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464944638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2464944638
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1134744320
Short name T411
Test name
Test status
Simulation time 192659804457 ps
CPU time 45.48 seconds
Started Feb 07 01:33:46 PM PST 24
Finished Feb 07 01:34:32 PM PST 24
Peak memory 198896 kb
Host smart-965bc5b2-3398-4878-909d-c5c0aedf1bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134744320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1134744320
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.2391861012
Short name T791
Test name
Test status
Simulation time 1491600657556 ps
CPU time 1154.59 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:53:00 PM PST 24
Peak memory 198416 kb
Host smart-c3103db7-a8b2-4d90-9755-ed9f91f9b7ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391861012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2391861012
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.503539429
Short name T978
Test name
Test status
Simulation time 110838522107 ps
CPU time 1067.91 seconds
Started Feb 07 01:33:46 PM PST 24
Finished Feb 07 01:51:34 PM PST 24
Peak memory 200012 kb
Host smart-d486f329-2e2b-4047-a42f-288200432b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503539429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.503539429
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3525991226
Short name T730
Test name
Test status
Simulation time 4841857376 ps
CPU time 13.04 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:33:57 PM PST 24
Peak memory 199792 kb
Host smart-18dcba27-571a-4e9e-9f7d-05af88124e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525991226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3525991226
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3021911503
Short name T789
Test name
Test status
Simulation time 158721855492 ps
CPU time 78.82 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:35:05 PM PST 24
Peak memory 208400 kb
Host smart-e4951d78-e517-414a-9bca-44478fbd926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021911503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3021911503
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3336745076
Short name T1066
Test name
Test status
Simulation time 28056607962 ps
CPU time 76.47 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:35:02 PM PST 24
Peak memory 199988 kb
Host smart-f86c2948-20a7-491d-a6aa-3f35681d0d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336745076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3336745076
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2645426863
Short name T957
Test name
Test status
Simulation time 4244867053 ps
CPU time 9.34 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:33:54 PM PST 24
Peak memory 198456 kb
Host smart-b871501b-8b3e-4b59-84e7-1a5c4270dbf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645426863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2645426863
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4010522308
Short name T920
Test name
Test status
Simulation time 20791248015 ps
CPU time 34.53 seconds
Started Feb 07 01:33:46 PM PST 24
Finished Feb 07 01:34:21 PM PST 24
Peak memory 199716 kb
Host smart-274ec54a-b647-43bd-9a8e-2860bd50cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010522308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4010522308
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2433667623
Short name T1041
Test name
Test status
Simulation time 41152496002 ps
CPU time 34.86 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:34:19 PM PST 24
Peak memory 195688 kb
Host smart-e8c38d49-fab9-40b7-bd9a-ee7b6e9d77bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433667623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2433667623
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4084896638
Short name T541
Test name
Test status
Simulation time 5877556091 ps
CPU time 14.48 seconds
Started Feb 07 01:33:43 PM PST 24
Finished Feb 07 01:33:58 PM PST 24
Peak memory 199260 kb
Host smart-8de69cd9-1821-4ec6-86ad-0061cf49eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084896638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4084896638
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3445692674
Short name T366
Test name
Test status
Simulation time 2488481398794 ps
CPU time 1788.97 seconds
Started Feb 07 01:33:43 PM PST 24
Finished Feb 07 02:03:33 PM PST 24
Peak memory 199904 kb
Host smart-f6dbbd42-9e41-4dda-ba5c-3b2203a6bb2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445692674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3445692674
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3528531587
Short name T934
Test name
Test status
Simulation time 33290328214 ps
CPU time 369.92 seconds
Started Feb 07 01:33:44 PM PST 24
Finished Feb 07 01:39:55 PM PST 24
Peak memory 208284 kb
Host smart-726962ec-7ac6-4482-ba65-8de2f8b34042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528531587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3528531587
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2500189390
Short name T865
Test name
Test status
Simulation time 6866376834 ps
CPU time 30.29 seconds
Started Feb 07 01:33:46 PM PST 24
Finished Feb 07 01:34:17 PM PST 24
Peak memory 199280 kb
Host smart-20d6b840-56ae-4c32-8ce9-3aa96940336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500189390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2500189390
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1283794982
Short name T893
Test name
Test status
Simulation time 12931734404 ps
CPU time 11.46 seconds
Started Feb 07 01:33:46 PM PST 24
Finished Feb 07 01:33:59 PM PST 24
Peak memory 199920 kb
Host smart-276c5dc4-330a-41de-a844-35e5dc5a8fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283794982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1283794982
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1020405189
Short name T427
Test name
Test status
Simulation time 147909441337 ps
CPU time 231.33 seconds
Started Feb 07 01:39:21 PM PST 24
Finished Feb 07 01:43:13 PM PST 24
Peak memory 199932 kb
Host smart-ca596bb3-40b7-421d-9f11-2ecc8281c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020405189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1020405189
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3584207282
Short name T215
Test name
Test status
Simulation time 84483614448 ps
CPU time 70.9 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 199592 kb
Host smart-e00239ed-715d-461c-82b1-a1e1d2ec6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584207282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3584207282
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.4094506838
Short name T250
Test name
Test status
Simulation time 62781661202 ps
CPU time 118.42 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:41:33 PM PST 24
Peak memory 199920 kb
Host smart-d95fe5a0-0fe4-4337-b87f-a161bcbe8838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094506838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.4094506838
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2906887812
Short name T144
Test name
Test status
Simulation time 100396638257 ps
CPU time 38.08 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:40:14 PM PST 24
Peak memory 199876 kb
Host smart-b147ef84-f0fa-4a54-8d1e-1f3ce23f81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906887812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2906887812
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3524680264
Short name T166
Test name
Test status
Simulation time 62546578691 ps
CPU time 26.45 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:40:02 PM PST 24
Peak memory 199736 kb
Host smart-cfa8fdac-0068-405e-a804-e023b890ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524680264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3524680264
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2065195989
Short name T860
Test name
Test status
Simulation time 26475117187 ps
CPU time 34.13 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:40:10 PM PST 24
Peak memory 199988 kb
Host smart-09dc4e7d-71c9-4ba3-ba9e-a35919ec8ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065195989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2065195989
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3886375522
Short name T205
Test name
Test status
Simulation time 111634785976 ps
CPU time 43.28 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:40:18 PM PST 24
Peak memory 199940 kb
Host smart-7b4c3a79-1420-4d3c-ba25-c29150f3548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886375522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3886375522
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1056257704
Short name T239
Test name
Test status
Simulation time 46781767990 ps
CPU time 69.92 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:40:44 PM PST 24
Peak memory 199924 kb
Host smart-0ca1d149-cdf2-45d1-99df-cffda287cfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056257704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1056257704
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.223349203
Short name T806
Test name
Test status
Simulation time 14207104 ps
CPU time 0.56 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:33:57 PM PST 24
Peak memory 194320 kb
Host smart-d1359f3c-c1a4-4313-975e-866fcd8a32f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223349203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.223349203
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1425411687
Short name T875
Test name
Test status
Simulation time 18511415013 ps
CPU time 32.17 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:34:18 PM PST 24
Peak memory 199920 kb
Host smart-3a5f9d7a-439b-4406-a855-f483c36dc38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425411687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1425411687
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3001314982
Short name T1231
Test name
Test status
Simulation time 17479842154 ps
CPU time 29.78 seconds
Started Feb 07 01:33:59 PM PST 24
Finished Feb 07 01:34:30 PM PST 24
Peak memory 199364 kb
Host smart-9fa63cc9-3784-441e-bca5-08013ebff411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001314982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3001314982
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2627628501
Short name T663
Test name
Test status
Simulation time 2322972586884 ps
CPU time 1660.35 seconds
Started Feb 07 01:34:00 PM PST 24
Finished Feb 07 02:01:42 PM PST 24
Peak memory 199024 kb
Host smart-53237d8b-63a1-4c58-a09e-790461c6952c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627628501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2627628501
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1246804422
Short name T1121
Test name
Test status
Simulation time 84975134665 ps
CPU time 328.17 seconds
Started Feb 07 01:33:57 PM PST 24
Finished Feb 07 01:39:25 PM PST 24
Peak memory 200008 kb
Host smart-72253971-fb72-42f6-91ea-7b4997d09cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246804422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1246804422
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1615721503
Short name T11
Test name
Test status
Simulation time 6463979795 ps
CPU time 7.4 seconds
Started Feb 07 01:33:56 PM PST 24
Finished Feb 07 01:34:04 PM PST 24
Peak memory 198116 kb
Host smart-da293636-5391-484a-8a74-b0c6755c4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615721503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1615721503
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3300144417
Short name T428
Test name
Test status
Simulation time 122663583904 ps
CPU time 204.72 seconds
Started Feb 07 01:33:57 PM PST 24
Finished Feb 07 01:37:22 PM PST 24
Peak memory 208396 kb
Host smart-a33a161f-713d-4c2f-87c8-2309d353d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300144417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3300144417
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4068239678
Short name T412
Test name
Test status
Simulation time 23623584746 ps
CPU time 161.76 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:36:37 PM PST 24
Peak memory 199872 kb
Host smart-83cd2bf2-5d90-474a-9643-287f4583f717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068239678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4068239678
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4115990552
Short name T917
Test name
Test status
Simulation time 2072432319 ps
CPU time 20.32 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:34:16 PM PST 24
Peak memory 197836 kb
Host smart-04ccfd28-a057-43e8-a1bc-bb805950d7d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115990552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4115990552
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3699450004
Short name T399
Test name
Test status
Simulation time 46030998066 ps
CPU time 52.11 seconds
Started Feb 07 01:33:56 PM PST 24
Finished Feb 07 01:34:49 PM PST 24
Peak memory 195400 kb
Host smart-dd3a9e1d-5be6-4e70-b9a3-fba56bd896fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699450004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3699450004
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.181368628
Short name T1144
Test name
Test status
Simulation time 733355895 ps
CPU time 1.35 seconds
Started Feb 07 01:33:48 PM PST 24
Finished Feb 07 01:33:50 PM PST 24
Peak memory 198180 kb
Host smart-f992699d-0367-4ad2-a041-afdf2b293b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181368628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.181368628
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3926843372
Short name T17
Test name
Test status
Simulation time 45560671320 ps
CPU time 20.83 seconds
Started Feb 07 01:33:58 PM PST 24
Finished Feb 07 01:34:19 PM PST 24
Peak memory 199880 kb
Host smart-dab24ba3-270e-4f4e-b87a-2c98cc380187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926843372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3926843372
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4209110938
Short name T1116
Test name
Test status
Simulation time 532194057 ps
CPU time 1.81 seconds
Started Feb 07 01:33:59 PM PST 24
Finished Feb 07 01:34:02 PM PST 24
Peak memory 197944 kb
Host smart-f786fd66-30cf-4a68-b5bf-8e1353029c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209110938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4209110938
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4200398583
Short name T810
Test name
Test status
Simulation time 18879175238 ps
CPU time 4.71 seconds
Started Feb 07 01:33:45 PM PST 24
Finished Feb 07 01:33:50 PM PST 24
Peak memory 199904 kb
Host smart-2d5f4b81-e20d-4ec8-a9b9-b50b36f05d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200398583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4200398583
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2477477343
Short name T894
Test name
Test status
Simulation time 290983155272 ps
CPU time 207.1 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:43:02 PM PST 24
Peak memory 199848 kb
Host smart-7e874c90-8e1c-46af-b844-bdf7b1b16e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477477343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2477477343
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2906197927
Short name T1196
Test name
Test status
Simulation time 28113289802 ps
CPU time 10.04 seconds
Started Feb 07 01:39:36 PM PST 24
Finished Feb 07 01:39:47 PM PST 24
Peak memory 197924 kb
Host smart-ba6bc6d3-c164-4e12-831a-bd766edfd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906197927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2906197927
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3133365845
Short name T558
Test name
Test status
Simulation time 52322053250 ps
CPU time 29.97 seconds
Started Feb 07 01:39:40 PM PST 24
Finished Feb 07 01:40:11 PM PST 24
Peak memory 199488 kb
Host smart-387992e5-8cb9-4dde-99fc-b95501b2e22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133365845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3133365845
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3100051048
Short name T1198
Test name
Test status
Simulation time 7719927357 ps
CPU time 6.23 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:39:41 PM PST 24
Peak memory 198912 kb
Host smart-77d6b39e-7465-41a6-9064-d6fa993ecc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100051048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3100051048
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3282335808
Short name T696
Test name
Test status
Simulation time 18614055431 ps
CPU time 14.15 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:39:50 PM PST 24
Peak memory 199900 kb
Host smart-86093a4e-9ad1-4799-bc8c-58a874929f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282335808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3282335808
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1099297072
Short name T1124
Test name
Test status
Simulation time 104260148559 ps
CPU time 47.53 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:30 PM PST 24
Peak memory 199896 kb
Host smart-a10525b8-ea27-4415-afa7-34524f2e79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099297072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1099297072
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2647924744
Short name T122
Test name
Test status
Simulation time 36719671067 ps
CPU time 16.26 seconds
Started Feb 07 01:39:40 PM PST 24
Finished Feb 07 01:39:57 PM PST 24
Peak memory 199928 kb
Host smart-ad35e23d-b2c2-46f0-b52b-5120642b0169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647924744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2647924744
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.545110358
Short name T584
Test name
Test status
Simulation time 86586575769 ps
CPU time 151.77 seconds
Started Feb 07 01:39:35 PM PST 24
Finished Feb 07 01:42:07 PM PST 24
Peak memory 199340 kb
Host smart-d3807e8f-9f0a-477c-a8fc-6215c009e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545110358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.545110358
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2484722896
Short name T191
Test name
Test status
Simulation time 171024250479 ps
CPU time 60.96 seconds
Started Feb 07 01:39:40 PM PST 24
Finished Feb 07 01:40:41 PM PST 24
Peak memory 199932 kb
Host smart-440273b3-4d3d-44a2-884e-b30def474a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484722896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2484722896
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1612171453
Short name T234
Test name
Test status
Simulation time 303444363737 ps
CPU time 60.86 seconds
Started Feb 07 01:39:34 PM PST 24
Finished Feb 07 01:40:35 PM PST 24
Peak memory 199948 kb
Host smart-f3bfe67d-cf2d-4da6-aa50-4f2928052e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612171453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1612171453
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1303421392
Short name T1119
Test name
Test status
Simulation time 46395161 ps
CPU time 0.56 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:34:07 PM PST 24
Peak memory 195296 kb
Host smart-1bc0e1af-58f4-4118-a6b4-697d29a1ee22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303421392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1303421392
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2444122124
Short name T346
Test name
Test status
Simulation time 152877704755 ps
CPU time 67.43 seconds
Started Feb 07 01:33:58 PM PST 24
Finished Feb 07 01:35:06 PM PST 24
Peak memory 199932 kb
Host smart-b72f48a8-e16f-43e6-9aa6-1989be0265ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444122124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2444122124
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4122604265
Short name T171
Test name
Test status
Simulation time 60572315687 ps
CPU time 13.01 seconds
Started Feb 07 01:33:58 PM PST 24
Finished Feb 07 01:34:11 PM PST 24
Peak memory 197504 kb
Host smart-785d2bcf-0b4c-443a-8120-07425f69722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122604265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4122604265
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.615954957
Short name T172
Test name
Test status
Simulation time 28704991562 ps
CPU time 49.57 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 199996 kb
Host smart-f521c377-3c16-4286-9c76-894b0381ad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615954957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.615954957
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4157571460
Short name T1104
Test name
Test status
Simulation time 27399120623 ps
CPU time 4.88 seconds
Started Feb 07 01:34:00 PM PST 24
Finished Feb 07 01:34:06 PM PST 24
Peak memory 197512 kb
Host smart-db80db4a-516a-4148-988c-c822d97cd83c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157571460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4157571460
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.8240776
Short name T1099
Test name
Test status
Simulation time 237460609953 ps
CPU time 148.85 seconds
Started Feb 07 01:34:07 PM PST 24
Finished Feb 07 01:36:37 PM PST 24
Peak memory 199924 kb
Host smart-d819265f-165c-45ce-8851-c643a359bf55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8240776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.8240776
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4001715740
Short name T739
Test name
Test status
Simulation time 6656385285 ps
CPU time 10.53 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:34:16 PM PST 24
Peak memory 196780 kb
Host smart-30e3ba63-ae96-431a-b25a-7209b4aba573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001715740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4001715740
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3519248419
Short name T420
Test name
Test status
Simulation time 231822593577 ps
CPU time 131.45 seconds
Started Feb 07 01:33:59 PM PST 24
Finished Feb 07 01:36:11 PM PST 24
Peak memory 198812 kb
Host smart-b19675f4-b2ab-43a0-a5a8-924e8dc0ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519248419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3519248419
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3569667745
Short name T762
Test name
Test status
Simulation time 10700540393 ps
CPU time 656.26 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:45:02 PM PST 24
Peak memory 199924 kb
Host smart-a84250df-8cc9-465a-83d6-7faff30c268f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569667745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3569667745
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.558593200
Short name T494
Test name
Test status
Simulation time 1499462514 ps
CPU time 4.98 seconds
Started Feb 07 01:33:57 PM PST 24
Finished Feb 07 01:34:03 PM PST 24
Peak memory 197828 kb
Host smart-197504b9-5358-41c6-bbcc-92851dca23ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558593200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.558593200
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2907099622
Short name T826
Test name
Test status
Simulation time 155937588350 ps
CPU time 230.03 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:38:00 PM PST 24
Peak memory 199932 kb
Host smart-ef82a71b-acf1-4036-ae3a-0be5cfe497dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907099622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2907099622
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3961699253
Short name T1159
Test name
Test status
Simulation time 4490371814 ps
CPU time 4.13 seconds
Started Feb 07 01:33:58 PM PST 24
Finished Feb 07 01:34:03 PM PST 24
Peak memory 195724 kb
Host smart-c3703d5f-a952-47fd-b576-e190bbe34fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961699253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3961699253
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3644894769
Short name T20
Test name
Test status
Simulation time 489438279 ps
CPU time 1.9 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:33:57 PM PST 24
Peak memory 198040 kb
Host smart-507a7843-1eb0-4a1e-8541-e161e6ae4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644894769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3644894769
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3000682301
Short name T856
Test name
Test status
Simulation time 342723802864 ps
CPU time 137.49 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:36:24 PM PST 24
Peak memory 200108 kb
Host smart-d87e9504-472a-4a16-a2be-aa0d21a38ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000682301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3000682301
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.602732613
Short name T812
Test name
Test status
Simulation time 7299974509 ps
CPU time 8.34 seconds
Started Feb 07 01:34:08 PM PST 24
Finished Feb 07 01:34:17 PM PST 24
Peak memory 198832 kb
Host smart-85d0e137-34cf-4d03-9472-694429540df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602732613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.602732613
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2663165086
Short name T1200
Test name
Test status
Simulation time 29523736040 ps
CPU time 31.2 seconds
Started Feb 07 01:33:55 PM PST 24
Finished Feb 07 01:34:27 PM PST 24
Peak memory 199976 kb
Host smart-d5a4e432-dc9b-46f1-9184-46d772826289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663165086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2663165086
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3871608507
Short name T341
Test name
Test status
Simulation time 98355364879 ps
CPU time 48.57 seconds
Started Feb 07 01:39:49 PM PST 24
Finished Feb 07 01:40:39 PM PST 24
Peak memory 199920 kb
Host smart-c2c44981-110a-4a7d-a575-8c6f5bc92918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871608507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3871608507
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3568276839
Short name T1083
Test name
Test status
Simulation time 49644616873 ps
CPU time 46.17 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:28 PM PST 24
Peak memory 199896 kb
Host smart-07ef55f3-69f8-4e8c-a713-692116db5db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568276839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3568276839
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3792729918
Short name T129
Test name
Test status
Simulation time 100417956086 ps
CPU time 106.91 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 199860 kb
Host smart-85e3041a-af3b-4ef2-90a4-9a0d879481b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792729918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3792729918
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3813115260
Short name T148
Test name
Test status
Simulation time 82985057156 ps
CPU time 64.8 seconds
Started Feb 07 01:39:53 PM PST 24
Finished Feb 07 01:40:58 PM PST 24
Peak memory 199888 kb
Host smart-080fe3ec-769b-4f25-b2f3-d4aaf6506859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813115260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3813115260
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1182709579
Short name T408
Test name
Test status
Simulation time 180456494585 ps
CPU time 35.69 seconds
Started Feb 07 01:39:41 PM PST 24
Finished Feb 07 01:40:17 PM PST 24
Peak memory 199832 kb
Host smart-f79a6ae6-0ba8-49f4-9c6f-87c4701091d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182709579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1182709579
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1469384135
Short name T1205
Test name
Test status
Simulation time 17830131844 ps
CPU time 34.1 seconds
Started Feb 07 01:39:41 PM PST 24
Finished Feb 07 01:40:16 PM PST 24
Peak memory 199896 kb
Host smart-91bbf420-de32-48fd-98d8-971a0e740353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469384135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1469384135
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2765501624
Short name T178
Test name
Test status
Simulation time 33759593342 ps
CPU time 64.34 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:47 PM PST 24
Peak memory 200032 kb
Host smart-499e3196-2079-4c76-855d-6bdc83e26fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765501624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2765501624
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1256392504
Short name T1086
Test name
Test status
Simulation time 95215868210 ps
CPU time 131.5 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 199960 kb
Host smart-8bb8f721-933d-43ec-94a9-e41fd1adb347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256392504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1256392504
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1181112482
Short name T222
Test name
Test status
Simulation time 13015637485 ps
CPU time 21.66 seconds
Started Feb 07 01:39:39 PM PST 24
Finished Feb 07 01:40:01 PM PST 24
Peak memory 199816 kb
Host smart-2abf8e03-4dfc-4fb0-9d6f-0d66d6b6b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181112482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1181112482
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.119348642
Short name T360
Test name
Test status
Simulation time 165089367381 ps
CPU time 252.55 seconds
Started Feb 07 01:39:43 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 199908 kb
Host smart-f9aa8013-0bf6-410f-a797-f99d0c9bb9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119348642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.119348642
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1276816192
Short name T1080
Test name
Test status
Simulation time 15454028 ps
CPU time 0.56 seconds
Started Feb 07 01:31:23 PM PST 24
Finished Feb 07 01:31:24 PM PST 24
Peak memory 195300 kb
Host smart-c697c958-15a1-4f0c-a2a1-131ccb17fe84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276816192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1276816192
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1168003118
Short name T365
Test name
Test status
Simulation time 59161956558 ps
CPU time 25.08 seconds
Started Feb 07 01:31:24 PM PST 24
Finished Feb 07 01:31:49 PM PST 24
Peak memory 200056 kb
Host smart-94543fcc-b50e-48b4-955f-1a5814b9796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168003118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1168003118
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2084405414
Short name T667
Test name
Test status
Simulation time 28440880069 ps
CPU time 42.45 seconds
Started Feb 07 01:31:08 PM PST 24
Finished Feb 07 01:31:51 PM PST 24
Peak memory 199616 kb
Host smart-b3ef8740-2db6-4c55-b1ea-44f1111a27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084405414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2084405414
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.480429990
Short name T903
Test name
Test status
Simulation time 20745757499 ps
CPU time 14.74 seconds
Started Feb 07 01:31:13 PM PST 24
Finished Feb 07 01:31:28 PM PST 24
Peak memory 196328 kb
Host smart-8cac21f6-17ae-45e5-b7e1-4cc8ae2cb84b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480429990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.480429990
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2120727120
Short name T660
Test name
Test status
Simulation time 176764189013 ps
CPU time 1469.18 seconds
Started Feb 07 01:31:11 PM PST 24
Finished Feb 07 01:55:41 PM PST 24
Peak memory 199900 kb
Host smart-012474b2-0a73-434c-acfa-8dc5726167fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120727120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2120727120
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1299278717
Short name T1060
Test name
Test status
Simulation time 4892796231 ps
CPU time 2.13 seconds
Started Feb 07 01:31:17 PM PST 24
Finished Feb 07 01:31:19 PM PST 24
Peak memory 198852 kb
Host smart-7b13a805-f5f1-49da-969c-01bbe68c7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299278717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1299278717
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3268646034
Short name T803
Test name
Test status
Simulation time 94919143223 ps
CPU time 39.43 seconds
Started Feb 07 01:31:10 PM PST 24
Finished Feb 07 01:31:50 PM PST 24
Peak memory 197152 kb
Host smart-07991131-0a78-4b34-a88a-fe6dfa9ae937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268646034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3268646034
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3440674857
Short name T251
Test name
Test status
Simulation time 13473205058 ps
CPU time 173.12 seconds
Started Feb 07 01:31:12 PM PST 24
Finished Feb 07 01:34:06 PM PST 24
Peak memory 199932 kb
Host smart-4c9e4639-7bcf-4839-abc7-a3e9f28de838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440674857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3440674857
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.724664054
Short name T628
Test name
Test status
Simulation time 2636422805 ps
CPU time 18.89 seconds
Started Feb 07 01:31:19 PM PST 24
Finished Feb 07 01:31:38 PM PST 24
Peak memory 197696 kb
Host smart-ce920214-8989-42c5-867a-1fe2fa8c0e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724664054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.724664054
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1601604910
Short name T792
Test name
Test status
Simulation time 42483004451 ps
CPU time 35.21 seconds
Started Feb 07 01:31:11 PM PST 24
Finished Feb 07 01:31:47 PM PST 24
Peak memory 199208 kb
Host smart-f3497ba1-083e-481d-9ca9-13f2515dbf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601604910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1601604910
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3917160849
Short name T1012
Test name
Test status
Simulation time 3376620347 ps
CPU time 2.84 seconds
Started Feb 07 01:31:13 PM PST 24
Finished Feb 07 01:31:16 PM PST 24
Peak memory 195344 kb
Host smart-2f459f7b-fc5d-4845-96fd-b9d92a48afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917160849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3917160849
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2972203581
Short name T78
Test name
Test status
Simulation time 111786810 ps
CPU time 0.86 seconds
Started Feb 07 01:31:17 PM PST 24
Finished Feb 07 01:31:18 PM PST 24
Peak memory 217400 kb
Host smart-f3bda6a3-256d-4f4a-a922-e35fd9f59a1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972203581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2972203581
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3988727805
Short name T1206
Test name
Test status
Simulation time 429479027 ps
CPU time 1.63 seconds
Started Feb 07 01:30:53 PM PST 24
Finished Feb 07 01:30:55 PM PST 24
Peak memory 197756 kb
Host smart-1582bde7-b184-487c-90e3-594b5f1ffe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988727805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3988727805
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1756493825
Short name T904
Test name
Test status
Simulation time 121397840001 ps
CPU time 403.82 seconds
Started Feb 07 01:31:23 PM PST 24
Finished Feb 07 01:38:07 PM PST 24
Peak memory 208352 kb
Host smart-4a43c1f6-c886-4306-8e5a-28c59a971e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756493825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1756493825
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1920105057
Short name T381
Test name
Test status
Simulation time 208782407422 ps
CPU time 230.04 seconds
Started Feb 07 01:31:12 PM PST 24
Finished Feb 07 01:35:03 PM PST 24
Peak memory 216400 kb
Host smart-b5c6449e-f4d8-4dda-ad57-d3208a7e4adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920105057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1920105057
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.923016629
Short name T588
Test name
Test status
Simulation time 897315169 ps
CPU time 1.93 seconds
Started Feb 07 01:31:12 PM PST 24
Finished Feb 07 01:31:15 PM PST 24
Peak memory 197952 kb
Host smart-b543192f-bd2e-46c6-8fdf-030010e9d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923016629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.923016629
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1139322502
Short name T938
Test name
Test status
Simulation time 21894748433 ps
CPU time 23.86 seconds
Started Feb 07 01:30:52 PM PST 24
Finished Feb 07 01:31:17 PM PST 24
Peak memory 199848 kb
Host smart-f6c3f7c8-45ad-4179-ad31-1c13ba7b8498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139322502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1139322502
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3003860973
Short name T1006
Test name
Test status
Simulation time 24274080 ps
CPU time 0.55 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:34:11 PM PST 24
Peak memory 194316 kb
Host smart-ce69789e-572b-476e-9602-04bbcef51507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003860973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3003860973
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3041868814
Short name T1172
Test name
Test status
Simulation time 138185436506 ps
CPU time 221.85 seconds
Started Feb 07 01:34:07 PM PST 24
Finished Feb 07 01:37:50 PM PST 24
Peak memory 199920 kb
Host smart-1d896c31-0952-4348-9e20-129c42e71f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041868814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3041868814
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2422443066
Short name T379
Test name
Test status
Simulation time 88874214357 ps
CPU time 143.91 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:36:33 PM PST 24
Peak memory 199928 kb
Host smart-3620ca2a-d360-4c93-bb72-4034354292d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422443066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2422443066
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1113970550
Short name T958
Test name
Test status
Simulation time 29870449506 ps
CPU time 23.61 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:34:34 PM PST 24
Peak memory 199796 kb
Host smart-2e3873d7-66d0-4e3f-91a6-4f7d2b514887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113970550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1113970550
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3452105737
Short name T659
Test name
Test status
Simulation time 339488392502 ps
CPU time 132.87 seconds
Started Feb 07 01:34:07 PM PST 24
Finished Feb 07 01:36:21 PM PST 24
Peak memory 198532 kb
Host smart-7816c6a3-a20f-4510-8698-79e66130934b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452105737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3452105737
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2251099083
Short name T1227
Test name
Test status
Simulation time 131760315145 ps
CPU time 387.5 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:40:37 PM PST 24
Peak memory 199996 kb
Host smart-66839ec6-5bab-485b-bee0-dd82a63e406c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251099083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2251099083
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2485642545
Short name T1199
Test name
Test status
Simulation time 11878841945 ps
CPU time 9.56 seconds
Started Feb 07 01:34:09 PM PST 24
Finished Feb 07 01:34:19 PM PST 24
Peak memory 198840 kb
Host smart-9465defd-1b0e-4da3-ae6f-eed88ba2c6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485642545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2485642545
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2780284436
Short name T1170
Test name
Test status
Simulation time 210691793761 ps
CPU time 46.35 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:34:52 PM PST 24
Peak memory 208320 kb
Host smart-f49b37ed-9f66-4687-9263-2068e47fd516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780284436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2780284436
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3607684144
Short name T22
Test name
Test status
Simulation time 13558570021 ps
CPU time 640.8 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:44:46 PM PST 24
Peak memory 199964 kb
Host smart-53f35fac-c8d2-4b07-b650-8e717a09fa5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607684144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3607684144
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2345976460
Short name T554
Test name
Test status
Simulation time 1898288903 ps
CPU time 5.81 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:34:11 PM PST 24
Peak memory 197856 kb
Host smart-feeb03b3-6764-4b3d-b4e2-11f97e066627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345976460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2345976460
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2835976687
Short name T349
Test name
Test status
Simulation time 49847194932 ps
CPU time 13.37 seconds
Started Feb 07 01:34:05 PM PST 24
Finished Feb 07 01:34:19 PM PST 24
Peak memory 199292 kb
Host smart-11bac9fe-235a-4f87-959d-51916f0b9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835976687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2835976687
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.562376834
Short name T1235
Test name
Test status
Simulation time 2358859793 ps
CPU time 4.12 seconds
Started Feb 07 01:34:04 PM PST 24
Finished Feb 07 01:34:09 PM PST 24
Peak memory 195348 kb
Host smart-5d0a2536-faaa-454d-aac0-56a188d060b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562376834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.562376834
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.75786386
Short name T568
Test name
Test status
Simulation time 6198726218 ps
CPU time 13.44 seconds
Started Feb 07 01:34:04 PM PST 24
Finished Feb 07 01:34:18 PM PST 24
Peak memory 199172 kb
Host smart-3c37bf88-b398-4379-90ea-9d8f1c287134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75786386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.75786386
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3554244706
Short name T707
Test name
Test status
Simulation time 227984325077 ps
CPU time 46.61 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:34:53 PM PST 24
Peak memory 199972 kb
Host smart-b577cff7-9d35-4440-a187-a2a8aeb2457a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554244706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3554244706
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3825950367
Short name T968
Test name
Test status
Simulation time 133773740798 ps
CPU time 1119.2 seconds
Started Feb 07 01:34:04 PM PST 24
Finished Feb 07 01:52:44 PM PST 24
Peak memory 216512 kb
Host smart-c41c9931-1d69-4e6e-88a4-09c8c3db784f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825950367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3825950367
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3766129630
Short name T1186
Test name
Test status
Simulation time 3218113474 ps
CPU time 3.18 seconds
Started Feb 07 01:34:04 PM PST 24
Finished Feb 07 01:34:08 PM PST 24
Peak memory 197872 kb
Host smart-c837d959-8de9-4f48-8cc3-303dd08e910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766129630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3766129630
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1880406898
Short name T547
Test name
Test status
Simulation time 90184205145 ps
CPU time 54.03 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:35:01 PM PST 24
Peak memory 199964 kb
Host smart-c4cc6f33-0324-44a5-98c3-d5870b629799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880406898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1880406898
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.413402927
Short name T241
Test name
Test status
Simulation time 19804733667 ps
CPU time 15.04 seconds
Started Feb 07 01:39:43 PM PST 24
Finished Feb 07 01:39:58 PM PST 24
Peak memory 199652 kb
Host smart-7dbd8fba-39b0-43fc-8706-3c18de02c79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413402927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.413402927
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2934612752
Short name T331
Test name
Test status
Simulation time 62251940811 ps
CPU time 15.98 seconds
Started Feb 07 01:39:43 PM PST 24
Finished Feb 07 01:40:00 PM PST 24
Peak memory 199876 kb
Host smart-7f622ce2-673e-4c0d-8bdb-ab80082f5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934612752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2934612752
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4178490312
Short name T692
Test name
Test status
Simulation time 20451326266 ps
CPU time 22.47 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:05 PM PST 24
Peak memory 199836 kb
Host smart-7205869d-0a0c-4437-9ae7-6de637f86b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178490312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4178490312
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2193451863
Short name T1052
Test name
Test status
Simulation time 33897028983 ps
CPU time 19.08 seconds
Started Feb 07 01:39:44 PM PST 24
Finished Feb 07 01:40:03 PM PST 24
Peak memory 199960 kb
Host smart-ebd7f130-4b81-47aa-a16c-2413ab9c4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193451863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2193451863
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1757728311
Short name T647
Test name
Test status
Simulation time 57876439314 ps
CPU time 51.77 seconds
Started Feb 07 01:39:51 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 199992 kb
Host smart-21b14507-b3a1-4ea5-b93c-14049e876e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757728311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1757728311
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3709860518
Short name T1112
Test name
Test status
Simulation time 42584818035 ps
CPU time 33.5 seconds
Started Feb 07 01:39:42 PM PST 24
Finished Feb 07 01:40:16 PM PST 24
Peak memory 198588 kb
Host smart-cc6299e5-31ad-4ab7-b407-8f119feec678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709860518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3709860518
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2993473102
Short name T313
Test name
Test status
Simulation time 74350665320 ps
CPU time 38.19 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:31 PM PST 24
Peak memory 199920 kb
Host smart-04b456b5-6b90-475c-a3d5-ba810a9fcd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993473102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2993473102
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1154531203
Short name T662
Test name
Test status
Simulation time 30348993 ps
CPU time 0.54 seconds
Started Feb 07 01:34:22 PM PST 24
Finished Feb 07 01:34:28 PM PST 24
Peak memory 194392 kb
Host smart-a23555e1-a3eb-4721-83c8-e320ea7766e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154531203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1154531203
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1000359063
Short name T532
Test name
Test status
Simulation time 202368790408 ps
CPU time 177.82 seconds
Started Feb 07 01:34:07 PM PST 24
Finished Feb 07 01:37:05 PM PST 24
Peak memory 199980 kb
Host smart-4cac96f4-976c-4e5f-a9e3-57976fc3371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000359063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1000359063
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2880660004
Short name T238
Test name
Test status
Simulation time 53617992965 ps
CPU time 30.37 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:34:37 PM PST 24
Peak memory 200008 kb
Host smart-7a380a97-5bf2-4458-957e-f4b4eadcfafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880660004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2880660004
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.1671470310
Short name T678
Test name
Test status
Simulation time 85731111409 ps
CPU time 46.17 seconds
Started Feb 07 01:34:30 PM PST 24
Finished Feb 07 01:35:23 PM PST 24
Peak memory 199920 kb
Host smart-16977512-76ff-4ed6-a318-9e171b540a6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671470310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1671470310
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1848533221
Short name T1089
Test name
Test status
Simulation time 143874538444 ps
CPU time 235.77 seconds
Started Feb 07 01:34:18 PM PST 24
Finished Feb 07 01:38:22 PM PST 24
Peak memory 199908 kb
Host smart-cd28a2b5-5c77-465f-826c-8cf33222094e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848533221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1848533221
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2101429020
Short name T432
Test name
Test status
Simulation time 70176293896 ps
CPU time 110.38 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:36:18 PM PST 24
Peak memory 198232 kb
Host smart-7278f288-09a4-400b-9aaf-5f2de5092070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101429020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2101429020
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.548415003
Short name T519
Test name
Test status
Simulation time 20151252947 ps
CPU time 483.55 seconds
Started Feb 07 01:34:26 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 199988 kb
Host smart-31f32787-ad32-40b0-bf57-196384278cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548415003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.548415003
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3690408184
Short name T848
Test name
Test status
Simulation time 168488360109 ps
CPU time 72.6 seconds
Started Feb 07 01:34:24 PM PST 24
Finished Feb 07 01:35:40 PM PST 24
Peak memory 199948 kb
Host smart-24c080fe-5be9-4065-9622-6ec57530fb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690408184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3690408184
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3099557713
Short name T560
Test name
Test status
Simulation time 43037160150 ps
CPU time 67.43 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:35:45 PM PST 24
Peak memory 195684 kb
Host smart-e86bc85b-b28c-4058-aff2-bc0d345d9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099557713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3099557713
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.4079362727
Short name T939
Test name
Test status
Simulation time 5994951669 ps
CPU time 12.06 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:34:18 PM PST 24
Peak memory 198632 kb
Host smart-0d6a83a5-7c8f-4698-946a-f4933187232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079362727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4079362727
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.4060723265
Short name T255
Test name
Test status
Simulation time 872589972487 ps
CPU time 3804.17 seconds
Started Feb 07 01:34:25 PM PST 24
Finished Feb 07 02:37:52 PM PST 24
Peak memory 199936 kb
Host smart-ef4d8c9d-1cbf-4ab8-b03c-93eccc55d271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060723265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4060723265
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.80816660
Short name T507
Test name
Test status
Simulation time 1255005437 ps
CPU time 2.88 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:34:30 PM PST 24
Peak memory 197724 kb
Host smart-1fdeb7a9-610a-47e4-9298-1c523346b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80816660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.80816660
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1441718316
Short name T446
Test name
Test status
Simulation time 34571435630 ps
CPU time 24.42 seconds
Started Feb 07 01:34:06 PM PST 24
Finished Feb 07 01:34:31 PM PST 24
Peak memory 199928 kb
Host smart-129a48bb-b08b-4a7c-8f92-ab4e2d0a4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441718316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1441718316
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2450888770
Short name T218
Test name
Test status
Simulation time 80643055249 ps
CPU time 36.3 seconds
Started Feb 07 01:39:46 PM PST 24
Finished Feb 07 01:40:23 PM PST 24
Peak memory 199948 kb
Host smart-f582c16a-9002-492a-969c-873d669ff2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450888770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2450888770
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4176160317
Short name T1209
Test name
Test status
Simulation time 32320112451 ps
CPU time 53.33 seconds
Started Feb 07 01:39:49 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 199960 kb
Host smart-fc0306c3-834d-468f-97b4-9f91c15ad81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176160317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4176160317
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1817964791
Short name T1027
Test name
Test status
Simulation time 13907230233 ps
CPU time 20.62 seconds
Started Feb 07 01:39:51 PM PST 24
Finished Feb 07 01:40:13 PM PST 24
Peak memory 199108 kb
Host smart-d4784c77-7d0e-408b-8b94-4a5c0b21721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817964791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1817964791
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3896530559
Short name T21
Test name
Test status
Simulation time 95833004151 ps
CPU time 20.03 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:12 PM PST 24
Peak memory 199920 kb
Host smart-b29ece6b-82d4-44eb-aa99-fe3a627382de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896530559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3896530559
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2135384445
Short name T207
Test name
Test status
Simulation time 91661208085 ps
CPU time 38.92 seconds
Started Feb 07 01:39:47 PM PST 24
Finished Feb 07 01:40:26 PM PST 24
Peak memory 200008 kb
Host smart-9eba4ef7-2c6d-4052-a659-9bc48219a3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135384445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2135384445
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2655291496
Short name T320
Test name
Test status
Simulation time 165948233274 ps
CPU time 77.53 seconds
Started Feb 07 01:39:47 PM PST 24
Finished Feb 07 01:41:06 PM PST 24
Peak memory 200040 kb
Host smart-c11772c8-5474-4075-9a23-07b5aba6670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655291496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2655291496
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.337283231
Short name T141
Test name
Test status
Simulation time 21393509862 ps
CPU time 35.67 seconds
Started Feb 07 01:39:54 PM PST 24
Finished Feb 07 01:40:30 PM PST 24
Peak memory 199920 kb
Host smart-e70f5ebc-73f2-477f-a002-8373836a6630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337283231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.337283231
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.854113851
Short name T603
Test name
Test status
Simulation time 83304281 ps
CPU time 0.55 seconds
Started Feb 07 01:34:30 PM PST 24
Finished Feb 07 01:34:37 PM PST 24
Peak memory 195332 kb
Host smart-f85e4bb0-7786-4ab0-9c9e-9e8682628bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854113851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.854113851
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.116496098
Short name T414
Test name
Test status
Simulation time 106575579743 ps
CPU time 79 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:35:47 PM PST 24
Peak memory 199872 kb
Host smart-da178f7f-d5c3-49a9-b01b-60ad786c9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116496098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.116496098
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.341435739
Short name T1177
Test name
Test status
Simulation time 47886403026 ps
CPU time 79.35 seconds
Started Feb 07 01:34:30 PM PST 24
Finished Feb 07 01:35:56 PM PST 24
Peak memory 199820 kb
Host smart-0be8c0e8-dce0-40ce-8ffa-7e40251a988a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341435739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.341435739
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2551543194
Short name T993
Test name
Test status
Simulation time 1895314799581 ps
CPU time 796.63 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:47:44 PM PST 24
Peak memory 199924 kb
Host smart-631f9928-c2c6-48a4-953b-df115b883325
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551543194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2551543194
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.75468348
Short name T883
Test name
Test status
Simulation time 90245267317 ps
CPU time 283.18 seconds
Started Feb 07 01:34:28 PM PST 24
Finished Feb 07 01:39:19 PM PST 24
Peak memory 199864 kb
Host smart-bc42ff5a-2e33-4ded-9dff-e449def48595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75468348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.75468348
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1724169561
Short name T716
Test name
Test status
Simulation time 8753651004 ps
CPU time 24.73 seconds
Started Feb 07 01:34:25 PM PST 24
Finished Feb 07 01:34:52 PM PST 24
Peak memory 199936 kb
Host smart-cc4b8d8c-ed4e-4079-869c-dcf02ea1b635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724169561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1724169561
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3067978114
Short name T1101
Test name
Test status
Simulation time 28550180453 ps
CPU time 11.82 seconds
Started Feb 07 01:34:22 PM PST 24
Finished Feb 07 01:34:39 PM PST 24
Peak memory 198460 kb
Host smart-ad3a5c82-85fa-40fe-b658-ac9c2657dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067978114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3067978114
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.381254338
Short name T743
Test name
Test status
Simulation time 13933741170 ps
CPU time 179.36 seconds
Started Feb 07 01:34:22 PM PST 24
Finished Feb 07 01:37:27 PM PST 24
Peak memory 199856 kb
Host smart-87e9d9bf-7e81-4012-835e-60daff6870cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381254338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.381254338
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.116933383
Short name T441
Test name
Test status
Simulation time 1373060316 ps
CPU time 6.56 seconds
Started Feb 07 01:34:22 PM PST 24
Finished Feb 07 01:34:34 PM PST 24
Peak memory 198096 kb
Host smart-a4384b53-2ec3-416e-a3b2-27cf8b2e3383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116933383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.116933383
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2306041240
Short name T415
Test name
Test status
Simulation time 33412337946 ps
CPU time 49.92 seconds
Started Feb 07 01:34:26 PM PST 24
Finished Feb 07 01:35:24 PM PST 24
Peak memory 195448 kb
Host smart-e74e7b25-b828-4289-990a-a1516ddaf48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306041240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2306041240
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.4123731182
Short name T518
Test name
Test status
Simulation time 5657388101 ps
CPU time 16.15 seconds
Started Feb 07 01:34:24 PM PST 24
Finished Feb 07 01:34:44 PM PST 24
Peak memory 198472 kb
Host smart-b299e31c-b796-4c0d-9e17-f6e3248e791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123731182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.4123731182
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4102378918
Short name T224
Test name
Test status
Simulation time 45272164366 ps
CPU time 71.61 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:35:39 PM PST 24
Peak memory 199992 kb
Host smart-3631b6fd-d3b5-4ee1-8842-a3f8b24fd5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102378918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4102378918
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2513514922
Short name T72
Test name
Test status
Simulation time 119177843324 ps
CPU time 781.18 seconds
Started Feb 07 01:34:25 PM PST 24
Finished Feb 07 01:47:29 PM PST 24
Peak memory 224780 kb
Host smart-cc111930-1221-4663-ad10-e2aa294a18c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513514922 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2513514922
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2747850401
Short name T1233
Test name
Test status
Simulation time 6875064591 ps
CPU time 20.53 seconds
Started Feb 07 01:34:24 PM PST 24
Finished Feb 07 01:34:48 PM PST 24
Peak memory 198804 kb
Host smart-eb37fc15-1a66-41cd-941c-b7293b7f93cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747850401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2747850401
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.388106956
Short name T797
Test name
Test status
Simulation time 56365321091 ps
CPU time 43.75 seconds
Started Feb 07 01:34:26 PM PST 24
Finished Feb 07 01:35:14 PM PST 24
Peak memory 199940 kb
Host smart-2d546a58-ade2-4c61-acb7-c95a1d7584de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388106956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.388106956
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1212640324
Short name T695
Test name
Test status
Simulation time 12507537155 ps
CPU time 23.14 seconds
Started Feb 07 01:39:54 PM PST 24
Finished Feb 07 01:40:18 PM PST 24
Peak memory 199896 kb
Host smart-adcffa1b-6ef2-464d-b0df-7f4f29b40a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212640324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1212640324
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1775305534
Short name T237
Test name
Test status
Simulation time 120959888088 ps
CPU time 186.12 seconds
Started Feb 07 01:39:53 PM PST 24
Finished Feb 07 01:43:00 PM PST 24
Peak memory 199136 kb
Host smart-2a79a10b-b393-4a25-a1de-a5f73ca172c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775305534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1775305534
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3917286816
Short name T624
Test name
Test status
Simulation time 78818358809 ps
CPU time 33.72 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:26 PM PST 24
Peak memory 199900 kb
Host smart-a9062999-3771-400b-a3b2-403635bc8d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917286816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3917286816
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3603803427
Short name T1074
Test name
Test status
Simulation time 32477349069 ps
CPU time 28.01 seconds
Started Feb 07 01:39:55 PM PST 24
Finished Feb 07 01:40:24 PM PST 24
Peak memory 199928 kb
Host smart-0e6e0a3c-48a4-4d75-b374-69a3c34ec0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603803427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3603803427
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3809054421
Short name T748
Test name
Test status
Simulation time 22138331537 ps
CPU time 39.17 seconds
Started Feb 07 01:39:52 PM PST 24
Finished Feb 07 01:40:32 PM PST 24
Peak memory 199912 kb
Host smart-8b8eda6c-8856-45a0-90cf-21693b8561a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809054421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3809054421
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1792462395
Short name T329
Test name
Test status
Simulation time 17282925630 ps
CPU time 13.79 seconds
Started Feb 07 01:39:58 PM PST 24
Finished Feb 07 01:40:12 PM PST 24
Peak memory 199156 kb
Host smart-993a0c61-c355-433f-b35d-d96371758db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792462395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1792462395
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.58921740
Short name T202
Test name
Test status
Simulation time 57868296509 ps
CPU time 47.68 seconds
Started Feb 07 01:39:54 PM PST 24
Finished Feb 07 01:40:42 PM PST 24
Peak memory 199828 kb
Host smart-2944fd14-eedf-4966-b089-8407c2047ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58921740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.58921740
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3705167469
Short name T755
Test name
Test status
Simulation time 21289784 ps
CPU time 0.55 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:34:38 PM PST 24
Peak memory 195304 kb
Host smart-3cbd97d2-9e3a-413a-9a16-d721a96d85ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705167469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3705167469
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2209944240
Short name T576
Test name
Test status
Simulation time 76550890892 ps
CPU time 33.81 seconds
Started Feb 07 01:34:23 PM PST 24
Finished Feb 07 01:35:01 PM PST 24
Peak memory 199580 kb
Host smart-70e7fdb6-05b0-4378-b864-93d573e87448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209944240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2209944240
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2777221959
Short name T809
Test name
Test status
Simulation time 191997216324 ps
CPU time 151.35 seconds
Started Feb 07 01:34:24 PM PST 24
Finished Feb 07 01:36:59 PM PST 24
Peak memory 200016 kb
Host smart-72ac61d8-f6e9-4157-9cf2-20f498e86111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777221959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2777221959
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.691465586
Short name T698
Test name
Test status
Simulation time 25021388450 ps
CPU time 18.68 seconds
Started Feb 07 01:34:34 PM PST 24
Finished Feb 07 01:34:56 PM PST 24
Peak memory 199208 kb
Host smart-a6cd0921-a5ce-4d09-81c1-3944a09b68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691465586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.691465586
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3000344960
Short name T23
Test name
Test status
Simulation time 527800967287 ps
CPU time 897.62 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:49:35 PM PST 24
Peak memory 199948 kb
Host smart-d7a3e66d-e90d-466f-834c-71d4f7a220bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000344960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3000344960
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3499199225
Short name T556
Test name
Test status
Simulation time 58499883424 ps
CPU time 342.01 seconds
Started Feb 07 01:34:33 PM PST 24
Finished Feb 07 01:40:20 PM PST 24
Peak memory 199984 kb
Host smart-3ca9bc00-f1c8-4796-a789-4e24cdf14b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499199225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3499199225
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_noise_filter.765587203
Short name T649
Test name
Test status
Simulation time 154661912299 ps
CPU time 65.79 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:35:43 PM PST 24
Peak memory 199620 kb
Host smart-0010c5c0-ca54-437b-893b-a067b786926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765587203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.765587203
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2871425788
Short name T501
Test name
Test status
Simulation time 13054263607 ps
CPU time 46.67 seconds
Started Feb 07 01:34:35 PM PST 24
Finished Feb 07 01:35:24 PM PST 24
Peak memory 199852 kb
Host smart-2f6776c0-7d68-40b9-a30f-a0f26d297b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871425788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2871425788
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.784352242
Short name T929
Test name
Test status
Simulation time 2734243604 ps
CPU time 8.36 seconds
Started Feb 07 01:34:33 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 198148 kb
Host smart-4b8397f7-80a7-4067-b9e2-d834330b0a6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784352242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.784352242
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3296838871
Short name T835
Test name
Test status
Simulation time 61602111849 ps
CPU time 47.07 seconds
Started Feb 07 01:34:33 PM PST 24
Finished Feb 07 01:35:25 PM PST 24
Peak memory 199676 kb
Host smart-d489082c-4fde-4b1c-9462-5eef22e64436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296838871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3296838871
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3529887231
Short name T492
Test name
Test status
Simulation time 3249479562 ps
CPU time 6.24 seconds
Started Feb 07 01:34:34 PM PST 24
Finished Feb 07 01:34:44 PM PST 24
Peak memory 195320 kb
Host smart-dcf4337b-eff2-40de-bc57-fc18c7ab4af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529887231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3529887231
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3832521079
Short name T1127
Test name
Test status
Simulation time 488671994 ps
CPU time 2.3 seconds
Started Feb 07 01:34:29 PM PST 24
Finished Feb 07 01:34:39 PM PST 24
Peak memory 198092 kb
Host smart-034098c3-3730-4da2-9c21-35bfa13f78d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832521079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3832521079
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3069526170
Short name T970
Test name
Test status
Simulation time 310899441577 ps
CPU time 491.84 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:42:49 PM PST 24
Peak memory 199992 kb
Host smart-4c21b04d-b678-4ee1-b2ee-172bdf156e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069526170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3069526170
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4073543345
Short name T63
Test name
Test status
Simulation time 28273680369 ps
CPU time 278.26 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:39:16 PM PST 24
Peak memory 208316 kb
Host smart-076a7501-3d86-4b05-98e6-3c8a5a410eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073543345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4073543345
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3412497723
Short name T882
Test name
Test status
Simulation time 1134621943 ps
CPU time 5.16 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:34:43 PM PST 24
Peak memory 198772 kb
Host smart-0dc85d07-707e-42ba-b764-0e56655bf6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412497723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3412497723
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3209876023
Short name T128
Test name
Test status
Simulation time 66843286140 ps
CPU time 31.33 seconds
Started Feb 07 01:34:28 PM PST 24
Finished Feb 07 01:35:07 PM PST 24
Peak memory 199836 kb
Host smart-c5ba1af2-3392-43b6-9a76-786a7a6595c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209876023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3209876023
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1161378199
Short name T302
Test name
Test status
Simulation time 13797507957 ps
CPU time 22.18 seconds
Started Feb 07 01:40:03 PM PST 24
Finished Feb 07 01:40:26 PM PST 24
Peak memory 199620 kb
Host smart-746ba291-a5cf-4ffc-bdc0-a6c451bcbf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161378199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1161378199
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1296740024
Short name T1176
Test name
Test status
Simulation time 74780572689 ps
CPU time 27.2 seconds
Started Feb 07 01:40:04 PM PST 24
Finished Feb 07 01:40:32 PM PST 24
Peak memory 199772 kb
Host smart-2a895ac8-0e3d-4ba4-a7c6-2adb18659a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296740024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1296740024
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1889605716
Short name T528
Test name
Test status
Simulation time 40433345232 ps
CPU time 110.66 seconds
Started Feb 07 01:40:01 PM PST 24
Finished Feb 07 01:41:53 PM PST 24
Peak memory 200036 kb
Host smart-59875a9a-f002-4963-bc22-4f3c2820a3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889605716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1889605716
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3448572642
Short name T907
Test name
Test status
Simulation time 24066533267 ps
CPU time 15.06 seconds
Started Feb 07 01:40:03 PM PST 24
Finished Feb 07 01:40:19 PM PST 24
Peak memory 199796 kb
Host smart-20b3fd51-d311-46aa-8136-90b68991ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448572642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3448572642
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4218046476
Short name T118
Test name
Test status
Simulation time 80263744291 ps
CPU time 22.34 seconds
Started Feb 07 01:40:02 PM PST 24
Finished Feb 07 01:40:24 PM PST 24
Peak memory 199936 kb
Host smart-47657d1e-4cdb-453f-bb7a-fd5dd7d98026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218046476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4218046476
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2942668876
Short name T758
Test name
Test status
Simulation time 52952086269 ps
CPU time 36.74 seconds
Started Feb 07 01:40:01 PM PST 24
Finished Feb 07 01:40:38 PM PST 24
Peak memory 199924 kb
Host smart-8ee862a0-8836-4ee9-9847-ee8c0bd12a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942668876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2942668876
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2015516789
Short name T1158
Test name
Test status
Simulation time 17988621 ps
CPU time 0.57 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:35:07 PM PST 24
Peak memory 195176 kb
Host smart-062d8e6b-dbcb-42be-bb10-8eb1a0929d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015516789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2015516789
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.132048866
Short name T841
Test name
Test status
Simulation time 124618458173 ps
CPU time 45.72 seconds
Started Feb 07 01:34:35 PM PST 24
Finished Feb 07 01:35:24 PM PST 24
Peak memory 199992 kb
Host smart-a3c89086-608a-4b5b-a324-674082951cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132048866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.132048866
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.354769439
Short name T369
Test name
Test status
Simulation time 46893968688 ps
CPU time 64.81 seconds
Started Feb 07 01:34:34 PM PST 24
Finished Feb 07 01:35:42 PM PST 24
Peak memory 198940 kb
Host smart-05f69ef0-3f46-4c93-ab54-fcea1db65786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354769439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.354769439
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.4291060961
Short name T590
Test name
Test status
Simulation time 32310314449 ps
CPU time 59.71 seconds
Started Feb 07 01:34:39 PM PST 24
Finished Feb 07 01:35:40 PM PST 24
Peak memory 199536 kb
Host smart-ba13dfc4-9f88-4853-a7b4-178c4032f9cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291060961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4291060961
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2659148501
Short name T704
Test name
Test status
Simulation time 65732457770 ps
CPU time 583.9 seconds
Started Feb 07 01:34:41 PM PST 24
Finished Feb 07 01:44:26 PM PST 24
Peak memory 199980 kb
Host smart-e1082708-cf57-42fc-9adf-724d1a1b902a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659148501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2659148501
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.4099663499
Short name T491
Test name
Test status
Simulation time 2355975678 ps
CPU time 5.16 seconds
Started Feb 07 01:34:40 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 198164 kb
Host smart-f8d20f1f-af22-453d-9baa-b43a53fa4fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099663499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.4099663499
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1168288994
Short name T685
Test name
Test status
Simulation time 3030532906 ps
CPU time 3.57 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:34:41 PM PST 24
Peak memory 196832 kb
Host smart-535bb511-1269-4f8f-a851-bce45ddb58f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168288994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1168288994
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3565734626
Short name T1007
Test name
Test status
Simulation time 29482233619 ps
CPU time 1586.51 seconds
Started Feb 07 01:34:45 PM PST 24
Finished Feb 07 02:01:12 PM PST 24
Peak memory 199940 kb
Host smart-58ce96a4-1bdc-4325-9824-b483eecc4652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565734626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3565734626
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1595434213
Short name T1168
Test name
Test status
Simulation time 3740164711 ps
CPU time 7.53 seconds
Started Feb 07 01:34:35 PM PST 24
Finished Feb 07 01:34:45 PM PST 24
Peak memory 198368 kb
Host smart-4abdae07-eb7e-4509-ab6f-fab2e96a432d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595434213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1595434213
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2139159546
Short name T498
Test name
Test status
Simulation time 5483757839 ps
CPU time 1.48 seconds
Started Feb 07 01:34:31 PM PST 24
Finished Feb 07 01:34:39 PM PST 24
Peak memory 195720 kb
Host smart-b9841c97-e5e0-44be-99ee-1d1663cac3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139159546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2139159546
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2599073435
Short name T999
Test name
Test status
Simulation time 5324247701 ps
CPU time 20.99 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:34:59 PM PST 24
Peak memory 199132 kb
Host smart-b36a9c34-e7f7-4b09-aab8-5d8f6c053201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599073435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2599073435
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.334909089
Short name T1049
Test name
Test status
Simulation time 37694875814 ps
CPU time 737.1 seconds
Started Feb 07 01:34:42 PM PST 24
Finished Feb 07 01:47:00 PM PST 24
Peak memory 214716 kb
Host smart-7a1a2197-69db-405f-9caf-cc66eec3d553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334909089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.334909089
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1075558547
Short name T711
Test name
Test status
Simulation time 6852538859 ps
CPU time 20.81 seconds
Started Feb 07 01:34:32 PM PST 24
Finished Feb 07 01:34:58 PM PST 24
Peak memory 199464 kb
Host smart-e6c729c2-c0ed-46d0-8d26-822247f626b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075558547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1075558547
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.682608177
Short name T927
Test name
Test status
Simulation time 71929506149 ps
CPU time 67.98 seconds
Started Feb 07 01:34:33 PM PST 24
Finished Feb 07 01:35:46 PM PST 24
Peak memory 199852 kb
Host smart-30b687f6-d505-494c-ad8a-72ea95f948cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682608177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.682608177
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3643738147
Short name T266
Test name
Test status
Simulation time 150271300832 ps
CPU time 238.66 seconds
Started Feb 07 01:40:04 PM PST 24
Finished Feb 07 01:44:03 PM PST 24
Peak memory 199756 kb
Host smart-61c3632e-e388-4226-957b-d38b5e5d7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643738147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3643738147
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3094314073
Short name T221
Test name
Test status
Simulation time 46338813718 ps
CPU time 20.07 seconds
Started Feb 07 01:40:02 PM PST 24
Finished Feb 07 01:40:24 PM PST 24
Peak memory 199896 kb
Host smart-ee737339-8c4a-4198-9a01-6bab85a1999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094314073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3094314073
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2610675901
Short name T112
Test name
Test status
Simulation time 72104987647 ps
CPU time 110.25 seconds
Started Feb 07 01:40:03 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 199888 kb
Host smart-da31fea5-8272-4aab-a0a2-fb03240151b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610675901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2610675901
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3924560254
Short name T232
Test name
Test status
Simulation time 68631847958 ps
CPU time 48.62 seconds
Started Feb 07 01:40:01 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 199928 kb
Host smart-42b0c88c-0e0a-4921-94de-14b6469cbca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924560254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3924560254
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2644353147
Short name T124
Test name
Test status
Simulation time 214785883108 ps
CPU time 325.75 seconds
Started Feb 07 01:40:18 PM PST 24
Finished Feb 07 01:45:44 PM PST 24
Peak memory 199944 kb
Host smart-b0f90719-b4a7-4cba-9829-cf755b9b38da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644353147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2644353147
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4267814880
Short name T1062
Test name
Test status
Simulation time 145733007168 ps
CPU time 147.42 seconds
Started Feb 07 01:40:17 PM PST 24
Finished Feb 07 01:42:45 PM PST 24
Peak memory 199932 kb
Host smart-1f1561a9-7185-4e88-bdd3-a134ca449950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267814880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4267814880
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1294046769
Short name T196
Test name
Test status
Simulation time 115643153180 ps
CPU time 510.27 seconds
Started Feb 07 01:40:21 PM PST 24
Finished Feb 07 01:48:52 PM PST 24
Peak memory 199988 kb
Host smart-3acc1c77-2de4-4cc5-a4aa-bfcc3af69f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294046769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1294046769
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1419167500
Short name T732
Test name
Test status
Simulation time 136036110249 ps
CPU time 68.35 seconds
Started Feb 07 01:40:16 PM PST 24
Finished Feb 07 01:41:25 PM PST 24
Peak memory 199952 kb
Host smart-9326b089-e710-4204-90ec-571c3e7d1ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419167500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1419167500
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.465679697
Short name T1081
Test name
Test status
Simulation time 18064252 ps
CPU time 0.55 seconds
Started Feb 07 01:34:41 PM PST 24
Finished Feb 07 01:34:42 PM PST 24
Peak memory 195332 kb
Host smart-88f84842-55a5-476f-a17e-7852735b01c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465679697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.465679697
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1923659938
Short name T275
Test name
Test status
Simulation time 18777442160 ps
CPU time 22.8 seconds
Started Feb 07 01:34:43 PM PST 24
Finished Feb 07 01:35:07 PM PST 24
Peak memory 199024 kb
Host smart-9fc18800-1736-460c-b3ba-e2b1e30cda93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923659938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1923659938
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1010361617
Short name T223
Test name
Test status
Simulation time 93290392522 ps
CPU time 38.75 seconds
Started Feb 07 01:34:42 PM PST 24
Finished Feb 07 01:35:22 PM PST 24
Peak memory 199564 kb
Host smart-9263a85b-3e04-4f26-91d2-f0c6b021e82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010361617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1010361617
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3945431098
Short name T1134
Test name
Test status
Simulation time 922411992577 ps
CPU time 1492.58 seconds
Started Feb 07 01:34:42 PM PST 24
Finished Feb 07 01:59:35 PM PST 24
Peak memory 199620 kb
Host smart-fa5d0228-226c-47b8-b68a-cd68595664ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945431098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3945431098
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2027543033
Short name T596
Test name
Test status
Simulation time 120092730849 ps
CPU time 859.8 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:49:26 PM PST 24
Peak memory 199716 kb
Host smart-42fe230c-eb4f-4673-b552-36f2e8f81c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027543033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2027543033
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2217899973
Short name T1026
Test name
Test status
Simulation time 3374592715 ps
CPU time 2.79 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:35:09 PM PST 24
Peak memory 198284 kb
Host smart-d2d1b61c-24b3-40dd-8db0-3b309cdba283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217899973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2217899973
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3586652016
Short name T1047
Test name
Test status
Simulation time 291856407623 ps
CPU time 158.36 seconds
Started Feb 07 01:34:42 PM PST 24
Finished Feb 07 01:37:21 PM PST 24
Peak memory 208168 kb
Host smart-26971d26-1f45-42d6-91fa-1564d2c44e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586652016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3586652016
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1550834454
Short name T1009
Test name
Test status
Simulation time 3575250284 ps
CPU time 143.63 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:37:29 PM PST 24
Peak memory 199676 kb
Host smart-299b37c6-2145-497c-ac68-7cde7f1b2e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550834454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1550834454
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1612769603
Short name T113
Test name
Test status
Simulation time 43088695308 ps
CPU time 60.51 seconds
Started Feb 07 01:34:44 PM PST 24
Finished Feb 07 01:35:46 PM PST 24
Peak memory 198776 kb
Host smart-558a17bd-89eb-42e7-bb4f-acab88bb2c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612769603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1612769603
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.251468020
Short name T1157
Test name
Test status
Simulation time 3194911195 ps
CPU time 1.55 seconds
Started Feb 07 01:34:43 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 195644 kb
Host smart-c94d9ed2-1467-484d-a9a6-f1b184358816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251468020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.251468020
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1770955384
Short name T1053
Test name
Test status
Simulation time 5834452894 ps
CPU time 14.32 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:35:21 PM PST 24
Peak memory 198944 kb
Host smart-20b92350-a3a9-41ac-a792-f93bcd570234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770955384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1770955384
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4183630725
Short name T884
Test name
Test status
Simulation time 135597633499 ps
CPU time 713.95 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:47:00 PM PST 24
Peak memory 216584 kb
Host smart-f59bc5e8-d16c-4340-bbcf-cca282667987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183630725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4183630725
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1347894683
Short name T1141
Test name
Test status
Simulation time 804823739 ps
CPU time 3.27 seconds
Started Feb 07 01:34:43 PM PST 24
Finished Feb 07 01:34:47 PM PST 24
Peak memory 198192 kb
Host smart-5b549668-1b35-4aa0-a063-fb64eb2b510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347894683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1347894683
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.706276626
Short name T811
Test name
Test status
Simulation time 15578592904 ps
CPU time 13.53 seconds
Started Feb 07 01:34:41 PM PST 24
Finished Feb 07 01:34:55 PM PST 24
Peak memory 196932 kb
Host smart-73f8e41b-a24b-4453-a30e-3481e5325eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706276626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.706276626
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1378572810
Short name T754
Test name
Test status
Simulation time 14055994653 ps
CPU time 23.59 seconds
Started Feb 07 01:40:16 PM PST 24
Finished Feb 07 01:40:40 PM PST 24
Peak memory 198732 kb
Host smart-292681d5-fac9-407d-996a-642421f9f040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378572810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1378572810
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1491013570
Short name T1091
Test name
Test status
Simulation time 88868532653 ps
CPU time 24 seconds
Started Feb 07 01:40:25 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 199128 kb
Host smart-a9ab67a3-92ca-4170-af42-64edd5be8bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491013570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1491013570
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1928186282
Short name T589
Test name
Test status
Simulation time 25875440584 ps
CPU time 24.65 seconds
Started Feb 07 01:40:25 PM PST 24
Finished Feb 07 01:40:52 PM PST 24
Peak memory 199580 kb
Host smart-32dbac7c-41cf-4f78-bbed-0e7e1813e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928186282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1928186282
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2675490136
Short name T194
Test name
Test status
Simulation time 44284173879 ps
CPU time 19.12 seconds
Started Feb 07 01:40:15 PM PST 24
Finished Feb 07 01:40:35 PM PST 24
Peak memory 199564 kb
Host smart-6e484c91-fad9-4e49-902b-edd6341c0505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675490136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2675490136
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.277665301
Short name T319
Test name
Test status
Simulation time 50180940207 ps
CPU time 84.24 seconds
Started Feb 07 01:40:16 PM PST 24
Finished Feb 07 01:41:41 PM PST 24
Peak memory 199880 kb
Host smart-ff61c18a-96d9-45d1-83c5-f27caf965f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277665301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.277665301
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1594096941
Short name T97
Test name
Test status
Simulation time 91091019371 ps
CPU time 136.36 seconds
Started Feb 07 01:40:23 PM PST 24
Finished Feb 07 01:42:41 PM PST 24
Peak memory 199776 kb
Host smart-cefffd5f-ff9b-4b82-b8c6-d17295bcd50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594096941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1594096941
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2160986980
Short name T982
Test name
Test status
Simulation time 222892041158 ps
CPU time 310.06 seconds
Started Feb 07 01:40:24 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 199884 kb
Host smart-dfba7688-1129-467f-8b7f-c6157eb6f096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160986980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2160986980
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2059970258
Short name T629
Test name
Test status
Simulation time 27808839685 ps
CPU time 53.61 seconds
Started Feb 07 01:40:16 PM PST 24
Finished Feb 07 01:41:10 PM PST 24
Peak memory 199704 kb
Host smart-8f12e797-a0e3-4d6b-8aec-24fd3db121eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059970258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2059970258
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.348098149
Short name T852
Test name
Test status
Simulation time 14106927731 ps
CPU time 21.64 seconds
Started Feb 07 01:40:22 PM PST 24
Finished Feb 07 01:40:44 PM PST 24
Peak memory 199956 kb
Host smart-60ba7f7e-758b-4311-8e9a-9872f9d2fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348098149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.348098149
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1133576631
Short name T1210
Test name
Test status
Simulation time 55503348 ps
CPU time 0.54 seconds
Started Feb 07 01:35:20 PM PST 24
Finished Feb 07 01:35:22 PM PST 24
Peak memory 195180 kb
Host smart-9ad5ded4-a673-4626-984a-b3cf21925d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133576631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1133576631
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3751293599
Short name T1201
Test name
Test status
Simulation time 66545218937 ps
CPU time 20.51 seconds
Started Feb 07 01:34:40 PM PST 24
Finished Feb 07 01:35:02 PM PST 24
Peak memory 199944 kb
Host smart-0b01ea02-c900-4b7d-b884-73ab20118d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751293599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3751293599
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3605465459
Short name T101
Test name
Test status
Simulation time 157609062738 ps
CPU time 151.64 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:37:38 PM PST 24
Peak memory 199816 kb
Host smart-5fb0a127-f32b-4bdd-bb34-8886611786b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605465459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3605465459
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1680670584
Short name T1087
Test name
Test status
Simulation time 26896856635 ps
CPU time 45.63 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:35:48 PM PST 24
Peak memory 199724 kb
Host smart-23470cc3-ff3f-4bca-9946-de6f65ba81a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680670584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1680670584
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.87572950
Short name T436
Test name
Test status
Simulation time 48224959193 ps
CPU time 80.97 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:36:27 PM PST 24
Peak memory 199388 kb
Host smart-6d6186c2-2cf9-480b-a4af-19e4c278814c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87572950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.87572950
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.21140418
Short name T585
Test name
Test status
Simulation time 46071194196 ps
CPU time 350.28 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:40:52 PM PST 24
Peak memory 199864 kb
Host smart-ad278ec0-cb34-4715-b431-5a2e332174e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21140418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.21140418
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.70506553
Short name T550
Test name
Test status
Simulation time 2058713451 ps
CPU time 1.54 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:35:04 PM PST 24
Peak memory 196652 kb
Host smart-7a388b35-9547-45df-a90b-5c0c078aa038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70506553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.70506553
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.859296125
Short name T741
Test name
Test status
Simulation time 71956803931 ps
CPU time 61.91 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:36:09 PM PST 24
Peak memory 198708 kb
Host smart-c56a6278-2af7-4b46-8cbb-8f043a859c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859296125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.859296125
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.879222992
Short name T1061
Test name
Test status
Simulation time 12187048930 ps
CPU time 295.4 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:40:01 PM PST 24
Peak memory 199980 kb
Host smart-f4a04aeb-1655-4f92-bb47-6b5536ce9e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879222992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.879222992
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3553751441
Short name T986
Test name
Test status
Simulation time 2890354290 ps
CPU time 13.68 seconds
Started Feb 07 01:35:07 PM PST 24
Finished Feb 07 01:35:22 PM PST 24
Peak memory 197940 kb
Host smart-8894ec7c-aa10-4d6e-ae02-3484b9e79ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553751441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3553751441
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.837864577
Short name T280
Test name
Test status
Simulation time 287714679431 ps
CPU time 27.36 seconds
Started Feb 07 01:35:02 PM PST 24
Finished Feb 07 01:35:31 PM PST 24
Peak memory 199752 kb
Host smart-27151cb0-3bb3-427e-a518-153ff08b78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837864577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.837864577
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.882422375
Short name T1160
Test name
Test status
Simulation time 2926190196 ps
CPU time 0.88 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:35:06 PM PST 24
Peak memory 195344 kb
Host smart-9e86f77c-0133-4292-873c-80fdfd3201d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882422375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.882422375
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3807290468
Short name T574
Test name
Test status
Simulation time 529941410 ps
CPU time 1.35 seconds
Started Feb 07 01:34:40 PM PST 24
Finished Feb 07 01:34:42 PM PST 24
Peak memory 198100 kb
Host smart-58429e69-a753-4992-9cf3-f4688f404c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807290468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3807290468
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.4118259635
Short name T794
Test name
Test status
Simulation time 58277427076 ps
CPU time 116.24 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:36:59 PM PST 24
Peak memory 208380 kb
Host smart-7d37de08-73d6-49b0-b76d-cc09713b4cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118259635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.4118259635
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2459095052
Short name T851
Test name
Test status
Simulation time 52104290707 ps
CPU time 657.14 seconds
Started Feb 07 01:35:04 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 216144 kb
Host smart-18e81308-d88e-4b3e-a2a9-59acfffb5efe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459095052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2459095052
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3658104626
Short name T510
Test name
Test status
Simulation time 815493065 ps
CPU time 2.27 seconds
Started Feb 07 01:34:55 PM PST 24
Finished Feb 07 01:34:59 PM PST 24
Peak memory 197712 kb
Host smart-1b85b691-f5b5-4b0d-965b-b585c934436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658104626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3658104626
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.222664752
Short name T648
Test name
Test status
Simulation time 155219891646 ps
CPU time 410.95 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:41:57 PM PST 24
Peak memory 199720 kb
Host smart-de3ec505-ca8d-4135-bf9f-44bc64b33429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222664752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.222664752
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2147128657
Short name T368
Test name
Test status
Simulation time 35712407583 ps
CPU time 11.81 seconds
Started Feb 07 01:40:19 PM PST 24
Finished Feb 07 01:40:31 PM PST 24
Peak memory 199444 kb
Host smart-8c548f32-c49c-444e-9ffe-3b4ecfedf6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147128657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2147128657
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3867958976
Short name T593
Test name
Test status
Simulation time 110354025641 ps
CPU time 91.59 seconds
Started Feb 07 01:40:29 PM PST 24
Finished Feb 07 01:42:03 PM PST 24
Peak memory 199892 kb
Host smart-b1b188e1-6950-4d7c-bfb1-509f6d2822bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867958976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3867958976
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2306440206
Short name T915
Test name
Test status
Simulation time 78001887805 ps
CPU time 20.01 seconds
Started Feb 07 01:40:22 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 199940 kb
Host smart-b88b2a86-2e1c-4f0c-b459-e8118f42b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306440206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2306440206
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3970437753
Short name T799
Test name
Test status
Simulation time 44066863934 ps
CPU time 74.66 seconds
Started Feb 07 01:40:23 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 199868 kb
Host smart-2b99e06e-2efa-461f-b801-9ad111d642ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970437753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3970437753
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1557661802
Short name T672
Test name
Test status
Simulation time 14106166332 ps
CPU time 15.1 seconds
Started Feb 07 01:40:33 PM PST 24
Finished Feb 07 01:40:52 PM PST 24
Peak memory 199104 kb
Host smart-9fa96097-10bc-4c96-a91d-695ae97c5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557661802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1557661802
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.217232724
Short name T310
Test name
Test status
Simulation time 23643413197 ps
CPU time 39.82 seconds
Started Feb 07 01:40:25 PM PST 24
Finished Feb 07 01:41:07 PM PST 24
Peak memory 199916 kb
Host smart-a991474d-7d8b-4942-a980-7846d10f0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217232724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.217232724
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3598704233
Short name T120
Test name
Test status
Simulation time 35292535798 ps
CPU time 24.52 seconds
Started Feb 07 01:40:23 PM PST 24
Finished Feb 07 01:40:48 PM PST 24
Peak memory 200012 kb
Host smart-50efb684-5452-4bb6-9161-9c1fb1d50638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598704233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3598704233
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3084679830
Short name T612
Test name
Test status
Simulation time 15794063 ps
CPU time 0.54 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:35:04 PM PST 24
Peak memory 195356 kb
Host smart-d4e6f6eb-cb06-4ecd-bc20-edec722038e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084679830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3084679830
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.555925486
Short name T983
Test name
Test status
Simulation time 60113464238 ps
CPU time 77.33 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:36:24 PM PST 24
Peak memory 199688 kb
Host smart-07726b6d-0641-429a-bb20-0e058629dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555925486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.555925486
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.443015567
Short name T688
Test name
Test status
Simulation time 161534098621 ps
CPU time 253.34 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:39:19 PM PST 24
Peak memory 199976 kb
Host smart-d6acf96c-a1c7-44e3-af45-876b9a4a6155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443015567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.443015567
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.624128141
Short name T1088
Test name
Test status
Simulation time 123648311431 ps
CPU time 41.63 seconds
Started Feb 07 01:35:04 PM PST 24
Finished Feb 07 01:35:47 PM PST 24
Peak memory 199904 kb
Host smart-63916a63-f4cb-4689-a788-32900250dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624128141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.624128141
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2774119163
Short name T951
Test name
Test status
Simulation time 17486369750 ps
CPU time 14.92 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:35:22 PM PST 24
Peak memory 198780 kb
Host smart-7c764aa1-b86e-42aa-91e3-efd0c7d8085a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774119163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2774119163
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2536158754
Short name T902
Test name
Test status
Simulation time 130508641209 ps
CPU time 255.76 seconds
Started Feb 07 01:35:00 PM PST 24
Finished Feb 07 01:39:17 PM PST 24
Peak memory 199968 kb
Host smart-ff052763-2feb-4088-809d-c862c2e89337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536158754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2536158754
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2025600557
Short name T505
Test name
Test status
Simulation time 1889139868 ps
CPU time 1.45 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:35:08 PM PST 24
Peak memory 195288 kb
Host smart-5a02dcc3-4dfc-4b0b-a8eb-d500fe3e54b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025600557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2025600557
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2396087225
Short name T673
Test name
Test status
Simulation time 66905039391 ps
CPU time 102.21 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:36:49 PM PST 24
Peak memory 199580 kb
Host smart-7c09a77c-aa9b-4c3e-aecc-0169bcd3804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396087225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2396087225
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1913790499
Short name T960
Test name
Test status
Simulation time 17301758545 ps
CPU time 416.22 seconds
Started Feb 07 01:35:07 PM PST 24
Finished Feb 07 01:42:04 PM PST 24
Peak memory 199888 kb
Host smart-20c0ba75-7474-4072-827a-58aa3c34d7a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913790499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1913790499
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3153381229
Short name T1156
Test name
Test status
Simulation time 141543354906 ps
CPU time 195.09 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:38:22 PM PST 24
Peak memory 199980 kb
Host smart-15e4155d-34f0-44d0-a56b-7bc96ce1c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153381229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3153381229
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1667428569
Short name T645
Test name
Test status
Simulation time 2153492005 ps
CPU time 1.54 seconds
Started Feb 07 01:35:07 PM PST 24
Finished Feb 07 01:35:09 PM PST 24
Peak memory 195336 kb
Host smart-c1cac9bd-1124-4fd2-b95f-7359896ad803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667428569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1667428569
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2273565452
Short name T621
Test name
Test status
Simulation time 90844721 ps
CPU time 0.84 seconds
Started Feb 07 01:35:01 PM PST 24
Finished Feb 07 01:35:02 PM PST 24
Peak memory 196296 kb
Host smart-b18dfe1f-0d5b-4f2a-8c45-f805c3c16e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273565452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2273565452
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.53396735
Short name T377
Test name
Test status
Simulation time 227316594761 ps
CPU time 68.59 seconds
Started Feb 07 01:35:02 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 199912 kb
Host smart-e77e7c9d-1dd2-48b5-b0bd-93a051b348a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53396735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.53396735
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3916130829
Short name T963
Test name
Test status
Simulation time 40255189428 ps
CPU time 503.97 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:43:29 PM PST 24
Peak memory 216320 kb
Host smart-03097c56-fa73-4b7b-8723-b973532307bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916130829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3916130829
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.214891021
Short name T504
Test name
Test status
Simulation time 846116209 ps
CPU time 3.8 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:35:11 PM PST 24
Peak memory 197812 kb
Host smart-1fb97f47-49ac-4b41-a71b-fcb4d761c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214891021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.214891021
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1890192745
Short name T404
Test name
Test status
Simulation time 201252009097 ps
CPU time 23 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:35:30 PM PST 24
Peak memory 199916 kb
Host smart-dd8e8447-67d2-405e-a77a-9f785e0463a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890192745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1890192745
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3918592927
Short name T173
Test name
Test status
Simulation time 81709290024 ps
CPU time 33.67 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 199688 kb
Host smart-4e905cf9-61fc-4188-b97c-5428d8f270a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918592927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3918592927
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.4293706141
Short name T182
Test name
Test status
Simulation time 30891562332 ps
CPU time 12.48 seconds
Started Feb 07 01:40:29 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 199868 kb
Host smart-c1c16717-3664-4afc-b16a-5db221281cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293706141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4293706141
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1453685883
Short name T1015
Test name
Test status
Simulation time 96447164329 ps
CPU time 40.14 seconds
Started Feb 07 01:40:30 PM PST 24
Finished Feb 07 01:41:12 PM PST 24
Peak memory 199916 kb
Host smart-a4b006b5-60ed-460c-8269-cb429173afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453685883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1453685883
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.981093422
Short name T701
Test name
Test status
Simulation time 78129869654 ps
CPU time 71.35 seconds
Started Feb 07 01:40:25 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 199784 kb
Host smart-444e2178-9d96-40fd-94ea-6294dde40c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981093422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.981093422
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2335638689
Short name T935
Test name
Test status
Simulation time 20555517818 ps
CPU time 18.25 seconds
Started Feb 07 01:40:30 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 197792 kb
Host smart-d07942d8-c90d-49f6-a4f8-d9dbc6db2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335638689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2335638689
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.914320515
Short name T375
Test name
Test status
Simulation time 115346009398 ps
CPU time 217.43 seconds
Started Feb 07 01:40:24 PM PST 24
Finished Feb 07 01:44:03 PM PST 24
Peak memory 199928 kb
Host smart-19f931ab-8099-4e35-b58a-c18fe087c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914320515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.914320515
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3645662068
Short name T337
Test name
Test status
Simulation time 38495497554 ps
CPU time 15.1 seconds
Started Feb 07 01:40:23 PM PST 24
Finished Feb 07 01:40:39 PM PST 24
Peak memory 199668 kb
Host smart-06fff95b-e60e-4679-82a4-8be41f784ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645662068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3645662068
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.807427635
Short name T1095
Test name
Test status
Simulation time 204732356808 ps
CPU time 176.26 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:43:25 PM PST 24
Peak memory 199932 kb
Host smart-4cbeab8d-1fa8-438e-8047-74cc24f2aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807427635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.807427635
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1819668487
Short name T840
Test name
Test status
Simulation time 22832547 ps
CPU time 0.54 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:35:15 PM PST 24
Peak memory 195220 kb
Host smart-dd739de3-99c8-44f8-b4c3-edc6ad400dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819668487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1819668487
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3581843054
Short name T514
Test name
Test status
Simulation time 124739848427 ps
CPU time 54.28 seconds
Started Feb 07 01:35:00 PM PST 24
Finished Feb 07 01:35:55 PM PST 24
Peak memory 199880 kb
Host smart-fc4a8e7c-90dd-4be2-a76c-28b1fe15beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581843054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3581843054
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2918610615
Short name T502
Test name
Test status
Simulation time 29296306797 ps
CPU time 12.98 seconds
Started Feb 07 01:35:05 PM PST 24
Finished Feb 07 01:35:19 PM PST 24
Peak memory 199908 kb
Host smart-6d53d2e6-c98b-4f0c-8fc5-009eea0be01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918610615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2918610615
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1682598182
Short name T139
Test name
Test status
Simulation time 20039561053 ps
CPU time 18.79 seconds
Started Feb 07 01:35:06 PM PST 24
Finished Feb 07 01:35:26 PM PST 24
Peak memory 200004 kb
Host smart-a57ade45-a7c5-4ce2-8e6e-5371da78087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682598182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1682598182
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.38140360
Short name T552
Test name
Test status
Simulation time 1164265332630 ps
CPU time 1952.21 seconds
Started Feb 07 01:35:12 PM PST 24
Finished Feb 07 02:07:45 PM PST 24
Peak memory 199968 kb
Host smart-9bfa269f-ded9-498a-99df-e9fedf422c47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38140360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.38140360
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2883698420
Short name T1204
Test name
Test status
Simulation time 162197948474 ps
CPU time 386.08 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:41:40 PM PST 24
Peak memory 199860 kb
Host smart-a05fe0b2-37ad-4eba-a251-31f0369732b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883698420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2883698420
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1857260302
Short name T745
Test name
Test status
Simulation time 5579579569 ps
CPU time 6.34 seconds
Started Feb 07 01:35:09 PM PST 24
Finished Feb 07 01:35:16 PM PST 24
Peak memory 198868 kb
Host smart-7256e3f8-6456-4631-98a4-6bc69b1c9ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857260302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1857260302
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.924175094
Short name T1072
Test name
Test status
Simulation time 34352908051 ps
CPU time 62.57 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:36:16 PM PST 24
Peak memory 199156 kb
Host smart-e007e8f8-978b-4367-a733-304d2e6ac74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924175094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.924175094
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1244396569
Short name T870
Test name
Test status
Simulation time 17790223989 ps
CPU time 270.43 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:39:44 PM PST 24
Peak memory 199908 kb
Host smart-55c1f79c-6edf-47a5-b293-e0c76df79533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244396569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1244396569
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1969404657
Short name T1237
Test name
Test status
Simulation time 2954774349 ps
CPU time 6.19 seconds
Started Feb 07 01:35:09 PM PST 24
Finished Feb 07 01:35:16 PM PST 24
Peak memory 198204 kb
Host smart-b8435b10-4c4b-473e-a513-7e7fba69e8fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969404657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1969404657
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4198438955
Short name T715
Test name
Test status
Simulation time 25540797892 ps
CPU time 31.3 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:35:45 PM PST 24
Peak memory 199920 kb
Host smart-4d763dac-74b3-41e5-b722-b2a0b7bec767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198438955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4198438955
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3560090531
Short name T635
Test name
Test status
Simulation time 2089232964 ps
CPU time 3.45 seconds
Started Feb 07 01:35:10 PM PST 24
Finished Feb 07 01:35:14 PM PST 24
Peak memory 195280 kb
Host smart-6faa1cd6-2b0d-443b-b3e9-2cb3fc7be5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560090531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3560090531
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2244934637
Short name T702
Test name
Test status
Simulation time 94160125 ps
CPU time 0.84 seconds
Started Feb 07 01:35:04 PM PST 24
Finished Feb 07 01:35:06 PM PST 24
Peak memory 196640 kb
Host smart-8e11972e-e5c6-48d6-a506-86df8ed4d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244934637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2244934637
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1193886761
Short name T644
Test name
Test status
Simulation time 24993788267 ps
CPU time 202.86 seconds
Started Feb 07 01:35:10 PM PST 24
Finished Feb 07 01:38:34 PM PST 24
Peak memory 216680 kb
Host smart-602e0a4b-4462-4629-904a-91bca46f4c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193886761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1193886761
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1045433253
Short name T878
Test name
Test status
Simulation time 802343424 ps
CPU time 3.21 seconds
Started Feb 07 01:35:14 PM PST 24
Finished Feb 07 01:35:18 PM PST 24
Peak memory 198792 kb
Host smart-05b9e8aa-11d5-460b-856b-28a63c7911c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045433253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1045433253
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2425244645
Short name T763
Test name
Test status
Simulation time 104699742486 ps
CPU time 27.8 seconds
Started Feb 07 01:35:08 PM PST 24
Finished Feb 07 01:35:37 PM PST 24
Peak memory 199944 kb
Host smart-5ed0b260-97f3-4dba-9fd5-06d25c8bcb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425244645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2425244645
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3387433606
Short name T298
Test name
Test status
Simulation time 24247674818 ps
CPU time 38.91 seconds
Started Feb 07 01:40:29 PM PST 24
Finished Feb 07 01:41:10 PM PST 24
Peak memory 200000 kb
Host smart-a27ecb2c-3b82-47cc-9853-e3201a125a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387433606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3387433606
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3234630145
Short name T855
Test name
Test status
Simulation time 138399305397 ps
CPU time 49.2 seconds
Started Feb 07 01:40:23 PM PST 24
Finished Feb 07 01:41:14 PM PST 24
Peak memory 199716 kb
Host smart-9a346f9a-a6d9-4a99-a23d-3d3eda3f3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234630145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3234630145
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2980337478
Short name T1232
Test name
Test status
Simulation time 41580664115 ps
CPU time 16.66 seconds
Started Feb 07 01:40:27 PM PST 24
Finished Feb 07 01:40:45 PM PST 24
Peak memory 200012 kb
Host smart-e0c14646-6bc7-47ce-97e3-670e0332eedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980337478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2980337478
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3954559293
Short name T225
Test name
Test status
Simulation time 132706541013 ps
CPU time 22.24 seconds
Started Feb 07 01:40:27 PM PST 24
Finished Feb 07 01:40:51 PM PST 24
Peak memory 199232 kb
Host smart-ef7f05de-6ca3-4747-8021-54ea18e520d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954559293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3954559293
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2667136002
Short name T1118
Test name
Test status
Simulation time 87981068335 ps
CPU time 40.2 seconds
Started Feb 07 01:40:25 PM PST 24
Finished Feb 07 01:41:07 PM PST 24
Peak memory 199280 kb
Host smart-ccda0dce-b9b2-46f8-a1d0-1f826d4d830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667136002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2667136002
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3067780491
Short name T271
Test name
Test status
Simulation time 30945350201 ps
CPU time 51.79 seconds
Started Feb 07 01:40:26 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 199724 kb
Host smart-bc7a25f0-f648-444c-afef-bcebb6bbf1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067780491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3067780491
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3672624884
Short name T193
Test name
Test status
Simulation time 55517119189 ps
CPU time 13.04 seconds
Started Feb 07 01:40:33 PM PST 24
Finished Feb 07 01:40:55 PM PST 24
Peak memory 199836 kb
Host smart-9cd38708-128d-4d48-bd6d-6ff5748eb91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672624884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3672624884
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2478997352
Short name T1014
Test name
Test status
Simulation time 47217081 ps
CPU time 0.54 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:35:24 PM PST 24
Peak memory 195352 kb
Host smart-930961cf-1f17-4d04-b62a-d700be05af10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478997352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2478997352
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1212422910
Short name T681
Test name
Test status
Simulation time 152097042650 ps
CPU time 116.13 seconds
Started Feb 07 01:35:14 PM PST 24
Finished Feb 07 01:37:11 PM PST 24
Peak memory 199892 kb
Host smart-379ebead-1740-415a-9c71-48c6426ba483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212422910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1212422910
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3908205202
Short name T1037
Test name
Test status
Simulation time 20439479806 ps
CPU time 36.47 seconds
Started Feb 07 01:35:10 PM PST 24
Finished Feb 07 01:35:47 PM PST 24
Peak memory 199376 kb
Host smart-182c6eb8-eb11-4761-95f6-86e4e63efc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908205202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3908205202
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.585085426
Short name T114
Test name
Test status
Simulation time 137875916676 ps
CPU time 65.31 seconds
Started Feb 07 01:35:21 PM PST 24
Finished Feb 07 01:36:27 PM PST 24
Peak memory 199892 kb
Host smart-e1e2cf69-4061-429e-bb7b-03a30352eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585085426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.585085426
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1099744320
Short name T1064
Test name
Test status
Simulation time 2232672614105 ps
CPU time 861.16 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:49:45 PM PST 24
Peak memory 199832 kb
Host smart-65dbb387-476d-47a9-be91-912933d04b9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099744320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1099744320
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.246633575
Short name T1100
Test name
Test status
Simulation time 173222305819 ps
CPU time 1200.21 seconds
Started Feb 07 01:35:22 PM PST 24
Finished Feb 07 01:55:22 PM PST 24
Peak memory 200012 kb
Host smart-ee1292b4-980c-4d5c-8691-eba103ae3788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246633575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.246633575
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3813362656
Short name T1109
Test name
Test status
Simulation time 3659035781 ps
CPU time 5.61 seconds
Started Feb 07 01:35:21 PM PST 24
Finished Feb 07 01:35:28 PM PST 24
Peak memory 195560 kb
Host smart-e523d08c-c789-480b-af64-284b156b4868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813362656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3813362656
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3077837711
Short name T766
Test name
Test status
Simulation time 12326689613 ps
CPU time 22.18 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:35:46 PM PST 24
Peak memory 198080 kb
Host smart-2eac6aa0-0748-4ad4-9999-b2fefaf9a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077837711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3077837711
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4148693256
Short name T926
Test name
Test status
Simulation time 15115390529 ps
CPU time 185.58 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:38:30 PM PST 24
Peak memory 199904 kb
Host smart-5e593624-bb64-4d08-9893-312bfa9d3f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148693256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4148693256
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1848924475
Short name T975
Test name
Test status
Simulation time 3184039470 ps
CPU time 18.96 seconds
Started Feb 07 01:35:22 PM PST 24
Finished Feb 07 01:35:42 PM PST 24
Peak memory 198276 kb
Host smart-4e9afc1e-66e0-43de-ae68-d7711852fddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848924475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1848924475
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2791110260
Short name T1137
Test name
Test status
Simulation time 187170511329 ps
CPU time 374.02 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 199840 kb
Host smart-745a0941-bd5b-48e8-91b9-8918b3093c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791110260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2791110260
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1428053510
Short name T966
Test name
Test status
Simulation time 34932372375 ps
CPU time 48.02 seconds
Started Feb 07 01:35:24 PM PST 24
Finished Feb 07 01:36:13 PM PST 24
Peak memory 195720 kb
Host smart-4c7b246a-d191-4ae8-8f24-87fd4e415bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428053510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1428053510
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1956830684
Short name T804
Test name
Test status
Simulation time 707485435 ps
CPU time 1.41 seconds
Started Feb 07 01:35:10 PM PST 24
Finished Feb 07 01:35:12 PM PST 24
Peak memory 198244 kb
Host smart-3929aabd-fb99-4768-8da9-16a64f2555bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956830684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1956830684
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.893613719
Short name T971
Test name
Test status
Simulation time 1649857303822 ps
CPU time 1636.95 seconds
Started Feb 07 01:35:28 PM PST 24
Finished Feb 07 02:02:46 PM PST 24
Peak memory 216484 kb
Host smart-f4f229bd-d7d6-45a8-ba04-b7f8e0f9b193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893613719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.893613719
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.4089594970
Short name T321
Test name
Test status
Simulation time 127876207365 ps
CPU time 386.48 seconds
Started Feb 07 01:35:26 PM PST 24
Finished Feb 07 01:41:53 PM PST 24
Peak memory 216424 kb
Host smart-c8b4a149-d6b9-4dc1-b12b-292efaf012db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089594970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.4089594970
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4139638530
Short name T1123
Test name
Test status
Simulation time 1375667089 ps
CPU time 3.14 seconds
Started Feb 07 01:35:24 PM PST 24
Finished Feb 07 01:35:28 PM PST 24
Peak memory 198796 kb
Host smart-cc4efa1d-5b1b-454b-8507-7dac4f3dde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139638530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4139638530
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2449993581
Short name T405
Test name
Test status
Simulation time 86111423160 ps
CPU time 147.97 seconds
Started Feb 07 01:35:13 PM PST 24
Finished Feb 07 01:37:42 PM PST 24
Peak memory 199812 kb
Host smart-6001345c-d4e8-4cc5-8908-4ac835323420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449993581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2449993581
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2050260804
Short name T123
Test name
Test status
Simulation time 81600688144 ps
CPU time 35.7 seconds
Started Feb 07 01:40:34 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 199888 kb
Host smart-948e7b86-0d60-46ed-86dc-c6251fae340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050260804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2050260804
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2693889453
Short name T823
Test name
Test status
Simulation time 77187953507 ps
CPU time 108.81 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:42:33 PM PST 24
Peak memory 199708 kb
Host smart-d8725956-dba4-4414-b0a3-63d6caf986bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693889453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2693889453
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3977495178
Short name T336
Test name
Test status
Simulation time 349983846319 ps
CPU time 28.4 seconds
Started Feb 07 01:40:39 PM PST 24
Finished Feb 07 01:41:13 PM PST 24
Peak memory 199836 kb
Host smart-5fc9639e-cda4-4f4a-940c-0b8ed7f64bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977495178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3977495178
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3181742203
Short name T277
Test name
Test status
Simulation time 56698852577 ps
CPU time 35.46 seconds
Started Feb 07 01:40:39 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 199668 kb
Host smart-e1be3d1c-892f-4270-a573-dbf9531fc19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181742203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3181742203
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.137445884
Short name T689
Test name
Test status
Simulation time 60411599416 ps
CPU time 71.68 seconds
Started Feb 07 01:40:32 PM PST 24
Finished Feb 07 01:41:45 PM PST 24
Peak memory 199508 kb
Host smart-a627a4ad-80f4-4b61-b573-93c250cf18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137445884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.137445884
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2884450772
Short name T257
Test name
Test status
Simulation time 32235219112 ps
CPU time 51.01 seconds
Started Feb 07 01:40:42 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 199296 kb
Host smart-4f258631-b7eb-4fd9-a622-308da9e7c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884450772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2884450772
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.465091097
Short name T1019
Test name
Test status
Simulation time 128371183513 ps
CPU time 224.63 seconds
Started Feb 07 01:40:34 PM PST 24
Finished Feb 07 01:44:29 PM PST 24
Peak memory 199852 kb
Host smart-dc07dbd4-2891-47df-87ee-da717122c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465091097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.465091097
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1406035795
Short name T314
Test name
Test status
Simulation time 67767492369 ps
CPU time 11.53 seconds
Started Feb 07 01:40:38 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 199932 kb
Host smart-9456341a-2672-4ed0-b1b4-12cd76df5267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406035795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1406035795
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1015075545
Short name T1219
Test name
Test status
Simulation time 249096582099 ps
CPU time 101.35 seconds
Started Feb 07 01:40:30 PM PST 24
Finished Feb 07 01:42:14 PM PST 24
Peak memory 199904 kb
Host smart-04d75ff0-adb8-4688-ace6-7e1cabb8dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015075545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1015075545
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.935817173
Short name T217
Test name
Test status
Simulation time 16414253510 ps
CPU time 9.55 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:40:54 PM PST 24
Peak memory 199940 kb
Host smart-4c2bd73d-bc17-4a1c-9d05-ae0674dc9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935817173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.935817173
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2163863953
Short name T526
Test name
Test status
Simulation time 84802661 ps
CPU time 0.56 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:31:31 PM PST 24
Peak memory 195332 kb
Host smart-f605f894-50bf-48de-b42a-bcb8af9c3e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163863953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2163863953
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2078911174
Short name T342
Test name
Test status
Simulation time 87189388839 ps
CPU time 24.3 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:31:43 PM PST 24
Peak memory 199460 kb
Host smart-fe4a894b-f566-4c2c-988b-32be9d8f036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078911174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2078911174
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1761953865
Short name T1028
Test name
Test status
Simulation time 44522490251 ps
CPU time 16.27 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:31:35 PM PST 24
Peak memory 199792 kb
Host smart-72b0f7a2-b215-49dd-8e87-c5f26a6e9376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761953865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1761953865
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1414897653
Short name T726
Test name
Test status
Simulation time 163631482390 ps
CPU time 217.5 seconds
Started Feb 07 01:31:23 PM PST 24
Finished Feb 07 01:35:01 PM PST 24
Peak memory 199888 kb
Host smart-237ed1ec-ae7e-4596-bf29-3866436fdeff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414897653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1414897653
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1269326702
Short name T847
Test name
Test status
Simulation time 84691512191 ps
CPU time 718.99 seconds
Started Feb 07 01:31:27 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 199888 kb
Host smart-186dc5f2-e840-40d0-bedb-93aceeec873f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269326702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1269326702
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1228511695
Short name T654
Test name
Test status
Simulation time 11176007716 ps
CPU time 20.21 seconds
Started Feb 07 01:31:27 PM PST 24
Finished Feb 07 01:31:48 PM PST 24
Peak memory 199900 kb
Host smart-16c6ebc6-d930-420a-8e1b-e226005ffb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228511695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1228511695
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3731142354
Short name T899
Test name
Test status
Simulation time 87716442769 ps
CPU time 37.29 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:31:56 PM PST 24
Peak memory 199448 kb
Host smart-2cebda60-d74a-475b-a1e2-b0aa9d66e0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731142354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3731142354
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2015138126
Short name T699
Test name
Test status
Simulation time 9645592905 ps
CPU time 55.5 seconds
Started Feb 07 01:31:28 PM PST 24
Finished Feb 07 01:32:24 PM PST 24
Peak memory 199908 kb
Host smart-4306da29-a654-4f10-9899-28aa576d5560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015138126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2015138126
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.531862850
Short name T853
Test name
Test status
Simulation time 2652488745 ps
CPU time 24.72 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:31:43 PM PST 24
Peak memory 198240 kb
Host smart-81232af5-113a-405e-bfea-fd234ccbcf68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531862850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.531862850
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2158199472
Short name T787
Test name
Test status
Simulation time 191181295163 ps
CPU time 253.48 seconds
Started Feb 07 01:31:28 PM PST 24
Finished Feb 07 01:35:42 PM PST 24
Peak memory 199928 kb
Host smart-1985c3bc-6743-4426-a883-0142c3a9a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158199472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2158199472
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1583417528
Short name T1142
Test name
Test status
Simulation time 56322037173 ps
CPU time 21.67 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:31:52 PM PST 24
Peak memory 195376 kb
Host smart-c670ad1f-38c3-46a4-8d3b-d16084b6e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583417528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1583417528
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3221506442
Short name T96
Test name
Test status
Simulation time 37404744 ps
CPU time 0.73 seconds
Started Feb 07 01:31:28 PM PST 24
Finished Feb 07 01:31:29 PM PST 24
Peak memory 217260 kb
Host smart-ee1ab82d-efd9-454f-b606-55c9aa146473
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221506442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3221506442
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.277492699
Short name T815
Test name
Test status
Simulation time 6201040272 ps
CPU time 10.75 seconds
Started Feb 07 01:31:18 PM PST 24
Finished Feb 07 01:31:30 PM PST 24
Peak memory 199180 kb
Host smart-1fd802e3-68a3-49da-a121-cce34ecb75ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277492699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.277492699
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.306593794
Short name T639
Test name
Test status
Simulation time 85146346022 ps
CPU time 79.38 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:32:49 PM PST 24
Peak memory 199936 kb
Host smart-f5420147-012c-4678-8186-6b2a55cdfb81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306593794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.306593794
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2255547262
Short name T1093
Test name
Test status
Simulation time 72615217669 ps
CPU time 283.33 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:36:13 PM PST 24
Peak memory 214196 kb
Host smart-9051f720-9be9-46ef-a49d-e74cf0133f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255547262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2255547262
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4025896134
Short name T573
Test name
Test status
Simulation time 6837209168 ps
CPU time 17.05 seconds
Started Feb 07 01:31:26 PM PST 24
Finished Feb 07 01:31:44 PM PST 24
Peak memory 199388 kb
Host smart-6098156c-3853-489f-a075-9155b9be67ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025896134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4025896134
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3311713198
Short name T798
Test name
Test status
Simulation time 38437522562 ps
CPU time 37.33 seconds
Started Feb 07 01:31:17 PM PST 24
Finished Feb 07 01:31:54 PM PST 24
Peak memory 199884 kb
Host smart-5c436593-6589-41f8-90a9-24d0e6298667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311713198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3311713198
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3052319961
Short name T94
Test name
Test status
Simulation time 79530986 ps
CPU time 0.53 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:04 PM PST 24
Peak memory 195340 kb
Host smart-dde8f338-71d7-4750-86b5-bf8c42c425df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052319961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3052319961
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1503887094
Short name T1073
Test name
Test status
Simulation time 290582989428 ps
CPU time 1825.79 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 02:05:50 PM PST 24
Peak memory 200032 kb
Host smart-4026dc08-75ef-43d4-949e-b83768e050b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503887094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1503887094
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1333580735
Short name T1098
Test name
Test status
Simulation time 255314909790 ps
CPU time 97.82 seconds
Started Feb 07 01:35:29 PM PST 24
Finished Feb 07 01:37:07 PM PST 24
Peak memory 199964 kb
Host smart-279ac616-2fe3-4905-8d9a-455125aeb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333580735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1333580735
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2960979643
Short name T447
Test name
Test status
Simulation time 1869746946223 ps
CPU time 688.63 seconds
Started Feb 07 01:35:22 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 198340 kb
Host smart-c0ba0b0c-8d70-4acd-81fa-533c204441cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960979643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2960979643
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3820882980
Short name T606
Test name
Test status
Simulation time 335605949709 ps
CPU time 230.84 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:39:54 PM PST 24
Peak memory 199912 kb
Host smart-1e02b459-da6b-40c9-af3f-cb2bd8cc61fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820882980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3820882980
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1612752010
Short name T534
Test name
Test status
Simulation time 9425491345 ps
CPU time 7.11 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 199380 kb
Host smart-158c9012-3630-4b03-a96c-881928dcd46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612752010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1612752010
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1803679589
Short name T512
Test name
Test status
Simulation time 43592481733 ps
CPU time 6.71 seconds
Started Feb 07 01:36:00 PM PST 24
Finished Feb 07 01:36:07 PM PST 24
Peak memory 198276 kb
Host smart-5a81dd33-2c1a-4f33-b197-ac434f78b1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803679589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1803679589
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2622262466
Short name T533
Test name
Test status
Simulation time 19087629491 ps
CPU time 1187.83 seconds
Started Feb 07 01:35:48 PM PST 24
Finished Feb 07 01:55:37 PM PST 24
Peak memory 199872 kb
Host smart-38d23a9f-539a-4d1c-9ede-3d8b47daeed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622262466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2622262466
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.305069077
Short name T784
Test name
Test status
Simulation time 1376311741 ps
CPU time 2.67 seconds
Started Feb 07 01:35:23 PM PST 24
Finished Feb 07 01:35:26 PM PST 24
Peak memory 197344 kb
Host smart-37de80a5-34cb-4f3a-be99-b8d76ba93141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305069077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.305069077
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2293537291
Short name T185
Test name
Test status
Simulation time 51448127768 ps
CPU time 42.04 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:45 PM PST 24
Peak memory 199928 kb
Host smart-21c98411-61a4-489b-9830-9b3a3032f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293537291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2293537291
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4087362376
Short name T1023
Test name
Test status
Simulation time 2367006703 ps
CPU time 4.07 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:07 PM PST 24
Peak memory 195324 kb
Host smart-c37ec32a-f292-4eda-8087-dfad3aa0dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087362376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4087362376
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.894758013
Short name T661
Test name
Test status
Simulation time 107778593 ps
CPU time 0.87 seconds
Started Feb 07 01:35:21 PM PST 24
Finished Feb 07 01:35:23 PM PST 24
Peak memory 196516 kb
Host smart-c610df79-102f-4cd0-b3b5-c517faeaabfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894758013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.894758013
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1890760937
Short name T1179
Test name
Test status
Simulation time 30628583834 ps
CPU time 610.2 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:46:13 PM PST 24
Peak memory 216776 kb
Host smart-c94c17d7-ccaa-4311-8234-0d0d00351727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890760937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1890760937
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4145449683
Short name T509
Test name
Test status
Simulation time 678579901 ps
CPU time 2.87 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 199196 kb
Host smart-d5245a46-0069-4a47-a76a-eb7755987f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145449683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4145449683
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.198781125
Short name T523
Test name
Test status
Simulation time 66984272528 ps
CPU time 40.84 seconds
Started Feb 07 01:35:20 PM PST 24
Finished Feb 07 01:36:02 PM PST 24
Peak memory 199876 kb
Host smart-da0fcac8-641a-40a8-b206-73b4fef2043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198781125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.198781125
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.178504526
Short name T1057
Test name
Test status
Simulation time 11568448 ps
CPU time 0.56 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:04 PM PST 24
Peak memory 195292 kb
Host smart-5c4dc3ed-d19a-422a-83cc-840598e22778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178504526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.178504526
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1721622115
Short name T344
Test name
Test status
Simulation time 78086628573 ps
CPU time 29.21 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:33 PM PST 24
Peak memory 199968 kb
Host smart-ab08ae0e-e2a9-4c62-a0a3-1df301d7095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721622115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1721622115
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2440957169
Short name T359
Test name
Test status
Simulation time 60140439568 ps
CPU time 20.82 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:26 PM PST 24
Peak memory 199896 kb
Host smart-3d1e25a1-6d01-4226-8e4e-685519387730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440957169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2440957169
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2960523606
Short name T273
Test name
Test status
Simulation time 171748593468 ps
CPU time 57.72 seconds
Started Feb 07 01:36:01 PM PST 24
Finished Feb 07 01:37:00 PM PST 24
Peak memory 199888 kb
Host smart-e03271f5-0830-4659-9e47-2aac2c95837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960523606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2960523606
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.969613374
Short name T434
Test name
Test status
Simulation time 12710181637 ps
CPU time 10.7 seconds
Started Feb 07 01:35:48 PM PST 24
Finished Feb 07 01:35:59 PM PST 24
Peak memory 196256 kb
Host smart-875e30f0-c14f-4c3d-bd03-1fe9b774d8b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969613374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.969613374
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.675251990
Short name T1197
Test name
Test status
Simulation time 84617080537 ps
CPU time 444.44 seconds
Started Feb 07 01:36:01 PM PST 24
Finished Feb 07 01:43:26 PM PST 24
Peak memory 199932 kb
Host smart-02554482-457c-4ced-aebb-6452f78ed1af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675251990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.675251990
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1652134458
Short name T569
Test name
Test status
Simulation time 4464422751 ps
CPU time 7.34 seconds
Started Feb 07 01:35:49 PM PST 24
Finished Feb 07 01:35:57 PM PST 24
Peak memory 198992 kb
Host smart-36f45a9f-0400-4b12-b79b-6dcccee2962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652134458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1652134458
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1549797885
Short name T1071
Test name
Test status
Simulation time 160814302892 ps
CPU time 137.2 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:38:20 PM PST 24
Peak memory 200216 kb
Host smart-f422c254-3e52-4b1e-ab34-d5d7a34750c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549797885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1549797885
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1447313850
Short name T832
Test name
Test status
Simulation time 25847120391 ps
CPU time 297.38 seconds
Started Feb 07 01:36:01 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 199944 kb
Host smart-1db30a61-9984-4752-8e93-e958d9a45802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447313850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1447313850
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3651353057
Short name T752
Test name
Test status
Simulation time 2716837726 ps
CPU time 22.65 seconds
Started Feb 07 01:36:03 PM PST 24
Finished Feb 07 01:36:26 PM PST 24
Peak memory 197656 kb
Host smart-44e078fc-b675-4a14-89b6-e738b42c527c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651353057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3651353057
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3865720624
Short name T374
Test name
Test status
Simulation time 148660863570 ps
CPU time 57.74 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:37:03 PM PST 24
Peak memory 199956 kb
Host smart-87b374a2-56bc-419d-80c4-98df7268671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865720624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3865720624
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.960747873
Short name T1021
Test name
Test status
Simulation time 2985191573 ps
CPU time 1.67 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:05 PM PST 24
Peak memory 195236 kb
Host smart-3f4f59ab-4e97-4336-b4da-8270e74bda65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960747873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.960747873
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.858350932
Short name T734
Test name
Test status
Simulation time 716959906 ps
CPU time 1.98 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:05 PM PST 24
Peak memory 197636 kb
Host smart-646bcfec-7aba-4198-ad2a-92450f7b6b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858350932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.858350932
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1361892337
Short name T842
Test name
Test status
Simulation time 348291787568 ps
CPU time 644.72 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 200000 kb
Host smart-3eb0ce9d-935e-4c1d-a7a7-d3c2209bf18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361892337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1361892337
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2333905856
Short name T940
Test name
Test status
Simulation time 96971629966 ps
CPU time 855.29 seconds
Started Feb 07 01:35:48 PM PST 24
Finished Feb 07 01:50:04 PM PST 24
Peak memory 224900 kb
Host smart-0a88341e-d111-4021-820c-208553f2b583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333905856 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2333905856
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3640359637
Short name T933
Test name
Test status
Simulation time 2256357225 ps
CPU time 3.1 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 198388 kb
Host smart-f72b974b-a2c0-427e-ba5f-d43df9aba320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640359637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3640359637
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1334631497
Short name T846
Test name
Test status
Simulation time 22371848833 ps
CPU time 32.44 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:35 PM PST 24
Peak memory 199800 kb
Host smart-a4bb8ebc-9a28-431e-91bb-47206cfe357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334631497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1334631497
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3443984634
Short name T598
Test name
Test status
Simulation time 18737846 ps
CPU time 0.56 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 194156 kb
Host smart-7c011b5b-5c29-45a0-9171-4c9422866444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443984634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3443984634
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.455881518
Short name T1131
Test name
Test status
Simulation time 88522614731 ps
CPU time 65.31 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:37:09 PM PST 24
Peak memory 199876 kb
Host smart-215088c8-b88e-45f7-8102-65d07b6afa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455881518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.455881518
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2976294259
Short name T136
Test name
Test status
Simulation time 244699590385 ps
CPU time 93.11 seconds
Started Feb 07 01:36:03 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 199848 kb
Host smart-3869b878-4ad8-4cc7-a536-762b7ce63969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976294259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2976294259
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1835501329
Short name T1140
Test name
Test status
Simulation time 100411717359 ps
CPU time 175.26 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:38:58 PM PST 24
Peak memory 200020 kb
Host smart-d35d4c16-6ac6-4199-95bd-6566b28d91f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835501329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1835501329
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1026073650
Short name T901
Test name
Test status
Simulation time 224831330732 ps
CPU time 351.5 seconds
Started Feb 07 01:36:03 PM PST 24
Finished Feb 07 01:41:55 PM PST 24
Peak memory 199776 kb
Host smart-84467fca-d264-487b-bc91-1a0c94a94a0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026073650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1026073650
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2402846824
Short name T756
Test name
Test status
Simulation time 73150693750 ps
CPU time 358.99 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:42:06 PM PST 24
Peak memory 199976 kb
Host smart-e7838052-c926-4b18-bf25-1286b8e7262c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402846824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2402846824
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.225307368
Short name T1185
Test name
Test status
Simulation time 1761918358 ps
CPU time 1.41 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:05 PM PST 24
Peak memory 197704 kb
Host smart-c088fb2d-9008-4838-942a-1a88157e3742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225307368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.225307368
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2125316057
Short name T444
Test name
Test status
Simulation time 108721913877 ps
CPU time 214.37 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:39:39 PM PST 24
Peak memory 208412 kb
Host smart-f6dbe093-949c-4d6b-8feb-80856ec2b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125316057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2125316057
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2856505422
Short name T760
Test name
Test status
Simulation time 13391444763 ps
CPU time 646.66 seconds
Started Feb 07 01:36:03 PM PST 24
Finished Feb 07 01:46:51 PM PST 24
Peak memory 199928 kb
Host smart-3bbe04f6-f870-46b6-bdb2-2512f460e60c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856505422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2856505422
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3654084187
Short name T29
Test name
Test status
Simulation time 5898869321 ps
CPU time 47.76 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:52 PM PST 24
Peak memory 198012 kb
Host smart-9e3f67d8-e817-4cb7-9a45-4d4bd7427fff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654084187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3654084187
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4149776883
Short name T179
Test name
Test status
Simulation time 177224751328 ps
CPU time 639.72 seconds
Started Feb 07 01:36:01 PM PST 24
Finished Feb 07 01:46:41 PM PST 24
Peak memory 199888 kb
Host smart-346baee3-1c54-4397-81c9-6171915f21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149776883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4149776883
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.339838029
Short name T535
Test name
Test status
Simulation time 1425984763 ps
CPU time 3.07 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:08 PM PST 24
Peak memory 195312 kb
Host smart-57edbd16-0e80-4b6f-ba79-e3930877f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339838029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.339838029
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1980694661
Short name T727
Test name
Test status
Simulation time 449263156 ps
CPU time 2.5 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 198160 kb
Host smart-315f18e6-67d6-4bd9-bec7-ecce325ef231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980694661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1980694661
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1375605380
Short name T371
Test name
Test status
Simulation time 118450732046 ps
CPU time 327.45 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 226344 kb
Host smart-429e6719-2d46-40a6-85c3-b3b01751c39e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375605380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1375605380
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1237429226
Short name T425
Test name
Test status
Simulation time 2808403904 ps
CPU time 2.25 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:36:09 PM PST 24
Peak memory 198360 kb
Host smart-40f75198-f63a-4933-8397-3346a6c8a0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237429226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1237429226
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.854103654
Short name T165
Test name
Test status
Simulation time 102953241602 ps
CPU time 42.18 seconds
Started Feb 07 01:36:00 PM PST 24
Finished Feb 07 01:36:43 PM PST 24
Peak memory 199924 kb
Host smart-0198d147-93df-49e1-82ac-cc6b9761ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854103654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.854103654
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4235889096
Short name T1008
Test name
Test status
Simulation time 13620332 ps
CPU time 0.57 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:05 PM PST 24
Peak memory 195300 kb
Host smart-63eafe15-04ca-467b-90f8-a3dc3682a764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235889096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4235889096
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1825444204
Short name T1149
Test name
Test status
Simulation time 16917348707 ps
CPU time 9.23 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 199928 kb
Host smart-7344b953-4ffa-4083-800d-1c8359c493d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825444204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1825444204
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4131559843
Short name T356
Test name
Test status
Simulation time 227421365031 ps
CPU time 57.14 seconds
Started Feb 07 01:36:01 PM PST 24
Finished Feb 07 01:36:59 PM PST 24
Peak memory 199944 kb
Host smart-ee480c0e-1825-4e17-b96c-41ade3dbcbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131559843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4131559843
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.511556466
Short name T1207
Test name
Test status
Simulation time 16583207700 ps
CPU time 12.75 seconds
Started Feb 07 01:36:10 PM PST 24
Finished Feb 07 01:36:23 PM PST 24
Peak memory 199616 kb
Host smart-25d8026e-d3ca-4df3-b8c9-9bd5a4261204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511556466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.511556466
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.193347533
Short name T400
Test name
Test status
Simulation time 107032437206 ps
CPU time 60.34 seconds
Started Feb 07 01:36:02 PM PST 24
Finished Feb 07 01:37:04 PM PST 24
Peak memory 199992 kb
Host smart-0a73dbf2-b0c3-4266-b965-263200ec7447
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193347533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.193347533
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3752436333
Short name T864
Test name
Test status
Simulation time 125379556354 ps
CPU time 221.86 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:39:49 PM PST 24
Peak memory 199968 kb
Host smart-15692e56-98cb-4bae-b3a1-9b30b5d7446c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752436333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3752436333
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3187716825
Short name T923
Test name
Test status
Simulation time 1571720739 ps
CPU time 3.34 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:10 PM PST 24
Peak memory 198904 kb
Host smart-616ec24c-6774-4de5-b59d-155f38424b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187716825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3187716825
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2917157711
Short name T1188
Test name
Test status
Simulation time 138875957892 ps
CPU time 73.13 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:37:18 PM PST 24
Peak memory 200176 kb
Host smart-964ddef8-3571-4a05-bb9e-d99309b33647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917157711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2917157711
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1117326497
Short name T869
Test name
Test status
Simulation time 4041916396 ps
CPU time 243.53 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:40:16 PM PST 24
Peak memory 199844 kb
Host smart-924d7219-16d9-481b-a38f-7a341e18aa23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117326497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1117326497
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.658792383
Short name T1097
Test name
Test status
Simulation time 1908736024 ps
CPU time 4.99 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:10 PM PST 24
Peak memory 197740 kb
Host smart-3d780525-1800-4100-99a8-e3cb4251cb4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658792383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.658792383
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.784876937
Short name T345
Test name
Test status
Simulation time 109454356034 ps
CPU time 46.08 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:36:53 PM PST 24
Peak memory 199864 kb
Host smart-07298a4c-2372-4f01-a9b2-d5d09d522a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784876937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.784876937
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2785480935
Short name T905
Test name
Test status
Simulation time 38303276449 ps
CPU time 43.11 seconds
Started Feb 07 01:36:03 PM PST 24
Finished Feb 07 01:36:47 PM PST 24
Peak memory 195704 kb
Host smart-6e9f9446-22e5-490d-bcf6-f6e03648f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785480935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2785480935
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1324954991
Short name T1045
Test name
Test status
Simulation time 717128421 ps
CPU time 1.38 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 198156 kb
Host smart-9c34da15-1d53-43a2-b82c-1424866ab22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324954991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1324954991
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.4040480575
Short name T419
Test name
Test status
Simulation time 643699369319 ps
CPU time 373.39 seconds
Started Feb 07 01:36:10 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 200160 kb
Host smart-0059a912-02cc-4c8e-a65d-2b2c154ea75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040480575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4040480575
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1429592811
Short name T60
Test name
Test status
Simulation time 403465204923 ps
CPU time 805.8 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:49:31 PM PST 24
Peak memory 224940 kb
Host smart-762b7ebe-d218-4b6d-8c41-0e923383f9bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429592811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1429592811
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2647596574
Short name T1068
Test name
Test status
Simulation time 391090076 ps
CPU time 1.43 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:06 PM PST 24
Peak memory 198728 kb
Host smart-8ccf0ec3-36d1-48bc-b69b-9917ec35de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647596574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2647596574
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2550313404
Short name T941
Test name
Test status
Simulation time 25495732155 ps
CPU time 41.19 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:48 PM PST 24
Peak memory 199808 kb
Host smart-0b5b8a49-bef9-49f9-a8f1-e8360f52fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550313404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2550313404
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1219588372
Short name T824
Test name
Test status
Simulation time 21845050 ps
CPU time 0.55 seconds
Started Feb 07 01:36:08 PM PST 24
Finished Feb 07 01:36:09 PM PST 24
Peak memory 195352 kb
Host smart-c95d0fc5-4cb1-4f94-8206-6cd795d3ea41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219588372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1219588372
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3356879001
Short name T1135
Test name
Test status
Simulation time 9098201490 ps
CPU time 6.99 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 198132 kb
Host smart-c569b7e5-d09b-4bc3-8c0b-441abd445b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356879001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3356879001
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.495001909
Short name T1236
Test name
Test status
Simulation time 13542088229 ps
CPU time 21.03 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:26 PM PST 24
Peak memory 199608 kb
Host smart-b00b4bd3-cd7a-4d44-902f-e740c9d35b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495001909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.495001909
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3365723821
Short name T448
Test name
Test status
Simulation time 1185819480996 ps
CPU time 2070.86 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 02:10:35 PM PST 24
Peak memory 199960 kb
Host smart-fe383305-6784-42cc-ad85-bff2a7b153cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365723821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3365723821
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2971389613
Short name T778
Test name
Test status
Simulation time 64312464049 ps
CPU time 96.15 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:37:44 PM PST 24
Peak memory 199880 kb
Host smart-665efbcf-54bc-4ab5-9af7-57bb943da991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971389613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2971389613
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2624742365
Short name T921
Test name
Test status
Simulation time 2934118204 ps
CPU time 4.11 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 198684 kb
Host smart-fd31d228-c6e0-4127-9921-9781e0e6b3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624742365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2624742365
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.799486820
Short name T395
Test name
Test status
Simulation time 71937737952 ps
CPU time 131.91 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:38:20 PM PST 24
Peak memory 199856 kb
Host smart-36adf02e-79d8-4f78-afb8-6a621abcc6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799486820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.799486820
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1434185336
Short name T570
Test name
Test status
Simulation time 27209626275 ps
CPU time 618.25 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 199792 kb
Host smart-aaa88dda-ddb4-4b92-a09b-81693130ebcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434185336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1434185336
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3252338730
Short name T490
Test name
Test status
Simulation time 3670840458 ps
CPU time 6.7 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:36:12 PM PST 24
Peak memory 197808 kb
Host smart-81fa78b4-cac2-483d-8002-a4edbb81c436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252338730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3252338730
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1798009536
Short name T805
Test name
Test status
Simulation time 32355481975 ps
CPU time 28.13 seconds
Started Feb 07 01:36:06 PM PST 24
Finished Feb 07 01:36:35 PM PST 24
Peak memory 199784 kb
Host smart-ac2df1bf-0e80-41f7-98ae-c3d2c65ea529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798009536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1798009536
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1383468745
Short name T710
Test name
Test status
Simulation time 2989960583 ps
CPU time 1.97 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:07 PM PST 24
Peak memory 195268 kb
Host smart-57594038-d635-414e-a549-6e8a7e410a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383468745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1383468745
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.872415082
Short name T837
Test name
Test status
Simulation time 648914384 ps
CPU time 2.83 seconds
Started Feb 07 01:36:05 PM PST 24
Finished Feb 07 01:36:09 PM PST 24
Peak memory 197680 kb
Host smart-5b777d83-469d-4be5-9e7e-2110125da6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872415082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.872415082
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.536723289
Short name T536
Test name
Test status
Simulation time 6997090371 ps
CPU time 20.52 seconds
Started Feb 07 01:36:07 PM PST 24
Finished Feb 07 01:36:28 PM PST 24
Peak memory 199596 kb
Host smart-9cc46774-0607-4a65-8ffd-9151bbadaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536723289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.536723289
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2659659236
Short name T430
Test name
Test status
Simulation time 26067815404 ps
CPU time 59.39 seconds
Started Feb 07 01:36:04 PM PST 24
Finished Feb 07 01:37:05 PM PST 24
Peak memory 199940 kb
Host smart-4141f92b-9cda-4278-bdbb-6f408380f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659659236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2659659236
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4226273760
Short name T924
Test name
Test status
Simulation time 89665555 ps
CPU time 0.55 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:15 PM PST 24
Peak memory 195036 kb
Host smart-997633bd-8628-4a70-88e3-5847a8b767f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226273760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4226273760
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3474879205
Short name T656
Test name
Test status
Simulation time 83026660482 ps
CPU time 30.69 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:45 PM PST 24
Peak memory 199964 kb
Host smart-27f9d839-99ab-4757-aba6-2d649e362362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474879205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3474879205
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.836941979
Short name T889
Test name
Test status
Simulation time 145566936198 ps
CPU time 110.13 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:38:04 PM PST 24
Peak memory 199888 kb
Host smart-6821b6dc-dbf8-440d-bf97-17d5d244403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836941979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.836941979
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2734648420
Short name T121
Test name
Test status
Simulation time 18227593223 ps
CPU time 8.73 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:36:22 PM PST 24
Peak memory 199968 kb
Host smart-ddc160ad-d295-47c3-993d-c0a4fcc1c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734648420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2734648420
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1437626700
Short name T1180
Test name
Test status
Simulation time 64591430811 ps
CPU time 87.95 seconds
Started Feb 07 01:36:09 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 199840 kb
Host smart-7c7a916b-304f-4df9-910e-44a3e56bba2a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437626700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1437626700
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2879132455
Short name T800
Test name
Test status
Simulation time 111569688900 ps
CPU time 370.71 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 199908 kb
Host smart-478bd2af-f748-478d-a30e-5f7e934ca0be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879132455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2879132455
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3089970441
Short name T764
Test name
Test status
Simulation time 346309878 ps
CPU time 1.21 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:36:15 PM PST 24
Peak memory 196592 kb
Host smart-aae45aa9-e921-4f73-b554-c58faef46eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089970441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3089970441
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.705046641
Short name T668
Test name
Test status
Simulation time 33025985408 ps
CPU time 54.32 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:37:09 PM PST 24
Peak memory 199704 kb
Host smart-083479e0-33e4-4b72-9abb-3bb19e4eeb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705046641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.705046641
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3190250253
Short name T862
Test name
Test status
Simulation time 12892473241 ps
CPU time 63.58 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:37:20 PM PST 24
Peak memory 199988 kb
Host smart-807c4649-58f4-4f3b-87d5-4c06e2410708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190250253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3190250253
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3503503384
Short name T83
Test name
Test status
Simulation time 2680709831 ps
CPU time 18.04 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:33 PM PST 24
Peak memory 197636 kb
Host smart-9320b51d-c131-4451-8bac-509f00ff5213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503503384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3503503384
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2308705543
Short name T777
Test name
Test status
Simulation time 25340789286 ps
CPU time 20.95 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:36:37 PM PST 24
Peak memory 199136 kb
Host smart-2bfe3f6f-3f04-4107-b906-01939463ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308705543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2308705543
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1121383536
Short name T652
Test name
Test status
Simulation time 554786231 ps
CPU time 1.55 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:36:18 PM PST 24
Peak memory 195300 kb
Host smart-de8e9a32-11ca-40aa-b807-453f35ea4ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121383536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1121383536
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.371602296
Short name T565
Test name
Test status
Simulation time 5363974750 ps
CPU time 19.24 seconds
Started Feb 07 01:36:09 PM PST 24
Finished Feb 07 01:36:29 PM PST 24
Peak memory 199388 kb
Host smart-e0eec66c-9055-4504-a718-08c7617707ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371602296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.371602296
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.30784341
Short name T252
Test name
Test status
Simulation time 436269135231 ps
CPU time 1134.52 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:55:09 PM PST 24
Peak memory 199812 kb
Host smart-52cbcba3-a0d3-4b88-af61-6e957dd95127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.30784341
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.4247078620
Short name T372
Test name
Test status
Simulation time 605680827675 ps
CPU time 585.36 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 213272 kb
Host smart-096a8978-445b-4af7-8d77-fa0cbe0d9785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247078620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.4247078620
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3520383705
Short name T782
Test name
Test status
Simulation time 7020965504 ps
CPU time 20.28 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:34 PM PST 24
Peak memory 199300 kb
Host smart-b9714ed0-b0b6-4a75-bdd1-b4d1c16d9085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520383705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3520383705
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3043786883
Short name T1055
Test name
Test status
Simulation time 147133450432 ps
CPU time 288.22 seconds
Started Feb 07 01:36:08 PM PST 24
Finished Feb 07 01:40:57 PM PST 24
Peak memory 199908 kb
Host smart-817b6ab2-ca53-485d-a4be-7b4841b08c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043786883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3043786883
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2954171080
Short name T759
Test name
Test status
Simulation time 17850052 ps
CPU time 0.54 seconds
Started Feb 07 01:36:17 PM PST 24
Finished Feb 07 01:36:18 PM PST 24
Peak memory 195320 kb
Host smart-41feb10b-27ed-46b8-9376-97c866f7ecf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954171080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2954171080
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1299121291
Short name T300
Test name
Test status
Simulation time 120495732541 ps
CPU time 87.79 seconds
Started Feb 07 01:36:11 PM PST 24
Finished Feb 07 01:37:40 PM PST 24
Peak memory 199936 kb
Host smart-daa1bf93-c1d1-4b74-892d-08ec6a4304c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299121291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1299121291
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2668599254
Short name T261
Test name
Test status
Simulation time 171260602170 ps
CPU time 22.93 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:36:36 PM PST 24
Peak memory 199996 kb
Host smart-3814d8c1-febb-4cba-9120-893b1f70510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668599254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2668599254
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.501408851
Short name T1194
Test name
Test status
Simulation time 250328815562 ps
CPU time 557.82 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:45:31 PM PST 24
Peak memory 199920 kb
Host smart-3f911c9e-def7-45cd-a2e0-30a51de090c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501408851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.501408851
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1580551507
Short name T1075
Test name
Test status
Simulation time 49641564435 ps
CPU time 148.94 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:38:45 PM PST 24
Peak memory 199828 kb
Host smart-3d88da0c-56df-4b1b-ba23-5a34600603d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580551507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1580551507
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.951503641
Short name T900
Test name
Test status
Simulation time 10616612577 ps
CPU time 7.36 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:22 PM PST 24
Peak memory 198864 kb
Host smart-74423042-5788-486c-97d9-e7b0ca840add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951503641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.951503641
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3193010590
Short name T825
Test name
Test status
Simulation time 29117509104 ps
CPU time 53.86 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:37:07 PM PST 24
Peak memory 198504 kb
Host smart-605e78f4-a7fa-4b00-9861-5a318d6e02c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193010590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3193010590
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.978996431
Short name T674
Test name
Test status
Simulation time 5425592464 ps
CPU time 279.46 seconds
Started Feb 07 01:36:12 PM PST 24
Finished Feb 07 01:40:52 PM PST 24
Peak memory 199912 kb
Host smart-86a3d77b-7766-4e01-8743-8ae97fd158d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978996431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.978996431
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2184540782
Short name T1132
Test name
Test status
Simulation time 2026295088 ps
CPU time 3.34 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:18 PM PST 24
Peak memory 197420 kb
Host smart-7ed86f37-3b5f-40bc-b698-fde31ee74f0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184540782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2184540782
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3116086419
Short name T1108
Test name
Test status
Simulation time 116631548805 ps
CPU time 48.61 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:37:02 PM PST 24
Peak memory 199736 kb
Host smart-1cc18412-51a6-4720-95ad-3b0e6686f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116086419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3116086419
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3028287372
Short name T992
Test name
Test status
Simulation time 4247578422 ps
CPU time 2.18 seconds
Started Feb 07 01:36:13 PM PST 24
Finished Feb 07 01:36:15 PM PST 24
Peak memory 195464 kb
Host smart-e95a926e-6e04-4137-8d4b-8bb430276600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028287372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3028287372
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2883153195
Short name T746
Test name
Test status
Simulation time 710854805 ps
CPU time 1.89 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:16 PM PST 24
Peak memory 197872 kb
Host smart-22b38b14-7deb-4e32-83c0-c4d35dedd637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883153195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2883153195
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.491894499
Short name T981
Test name
Test status
Simulation time 6901286297 ps
CPU time 10.72 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:36:28 PM PST 24
Peak memory 199292 kb
Host smart-7c9e54f1-4f60-4f9d-b978-601b91d8a5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491894499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.491894499
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.275842388
Short name T753
Test name
Test status
Simulation time 80315840737 ps
CPU time 71.31 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:37:28 PM PST 24
Peak memory 199872 kb
Host smart-ac5df4dc-d2f1-48ce-aede-50d693c1c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275842388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.275842388
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3918739367
Short name T1065
Test name
Test status
Simulation time 25272454 ps
CPU time 0.55 seconds
Started Feb 07 01:36:29 PM PST 24
Finished Feb 07 01:36:38 PM PST 24
Peak memory 195368 kb
Host smart-3dc127e7-64a4-4d2c-96c8-9cf15c162db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918739367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3918739367
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1132148807
Short name T421
Test name
Test status
Simulation time 99811449454 ps
CPU time 40.66 seconds
Started Feb 07 01:36:18 PM PST 24
Finished Feb 07 01:36:59 PM PST 24
Peak memory 199972 kb
Host smart-fbd249f4-431c-4883-8f91-d0afde81ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132148807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1132148807
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1487979302
Short name T100
Test name
Test status
Simulation time 303176783331 ps
CPU time 21.53 seconds
Started Feb 07 01:36:17 PM PST 24
Finished Feb 07 01:36:39 PM PST 24
Peak memory 199100 kb
Host smart-deacbc51-c5e9-49d5-ab82-abaa73124ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487979302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1487979302
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3888671041
Short name T801
Test name
Test status
Simulation time 192223559185 ps
CPU time 84.73 seconds
Started Feb 07 01:36:17 PM PST 24
Finished Feb 07 01:37:43 PM PST 24
Peak memory 199968 kb
Host smart-ec053e18-7598-40b4-b134-7ddb43d5c21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888671041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3888671041
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.219477934
Short name T867
Test name
Test status
Simulation time 60482386621 ps
CPU time 78.26 seconds
Started Feb 07 01:36:18 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 199888 kb
Host smart-2d6f2f1c-9347-4a24-93cb-b52298f9e1a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219477934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.219477934
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3105197619
Short name T780
Test name
Test status
Simulation time 131628296699 ps
CPU time 225.45 seconds
Started Feb 07 01:36:30 PM PST 24
Finished Feb 07 01:40:23 PM PST 24
Peak memory 199920 kb
Host smart-3097e26b-595b-4773-82d5-1d2fefe82986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105197619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3105197619
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.10074320
Short name T1163
Test name
Test status
Simulation time 3905550382 ps
CPU time 9.43 seconds
Started Feb 07 01:36:30 PM PST 24
Finished Feb 07 01:36:47 PM PST 24
Peak memory 198828 kb
Host smart-0dd5b384-b630-4c20-b2d1-2a2e557f1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10074320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.10074320
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3515051813
Short name T610
Test name
Test status
Simulation time 63491588497 ps
CPU time 97.78 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:37:54 PM PST 24
Peak memory 199476 kb
Host smart-376ec45d-5055-4291-9f8a-cc97b840d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515051813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3515051813
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2998903040
Short name T774
Test name
Test status
Simulation time 17069666619 ps
CPU time 205.02 seconds
Started Feb 07 01:36:25 PM PST 24
Finished Feb 07 01:39:51 PM PST 24
Peak memory 199908 kb
Host smart-d3bd06f5-8822-410a-8655-1ff23b2854f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998903040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2998903040
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2894493247
Short name T522
Test name
Test status
Simulation time 3691336465 ps
CPU time 18.25 seconds
Started Feb 07 01:36:16 PM PST 24
Finished Feb 07 01:36:35 PM PST 24
Peak memory 198316 kb
Host smart-8b36dd9a-df15-4787-bda8-303dd6b6b811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894493247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2894493247
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1276385348
Short name T909
Test name
Test status
Simulation time 9121911102 ps
CPU time 16.06 seconds
Started Feb 07 01:36:27 PM PST 24
Finished Feb 07 01:36:48 PM PST 24
Peak memory 199612 kb
Host smart-5ad0ab60-68f2-46c6-867a-3b692131457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276385348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1276385348
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1070484692
Short name T943
Test name
Test status
Simulation time 47183395048 ps
CPU time 19.29 seconds
Started Feb 07 01:36:29 PM PST 24
Finished Feb 07 01:36:57 PM PST 24
Peak memory 195428 kb
Host smart-6869d7fe-1d59-4ce2-8024-c5cbdb9beb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070484692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1070484692
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3695885146
Short name T897
Test name
Test status
Simulation time 89038876 ps
CPU time 0.94 seconds
Started Feb 07 01:36:14 PM PST 24
Finished Feb 07 01:36:16 PM PST 24
Peak memory 197800 kb
Host smart-4ef67676-e7a7-4f4f-9656-56250538992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695885146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3695885146
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.49873425
Short name T442
Test name
Test status
Simulation time 5596372546 ps
CPU time 119.28 seconds
Started Feb 07 01:36:31 PM PST 24
Finished Feb 07 01:38:37 PM PST 24
Peak memory 199916 kb
Host smart-9174b72d-8a90-4062-9e0d-fdb46258f2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49873425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.49873425
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1759987236
Short name T440
Test name
Test status
Simulation time 83830664948 ps
CPU time 255.41 seconds
Started Feb 07 01:36:26 PM PST 24
Finished Feb 07 01:40:43 PM PST 24
Peak memory 216708 kb
Host smart-593e558d-8c21-4c57-aaf2-645d8ab1b0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759987236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1759987236
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.951980415
Short name T721
Test name
Test status
Simulation time 631436070 ps
CPU time 1.59 seconds
Started Feb 07 01:36:27 PM PST 24
Finished Feb 07 01:36:30 PM PST 24
Peak memory 198016 kb
Host smart-5ab8ed1f-bd47-4cf9-93ea-729898a49daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951980415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.951980415
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3175703306
Short name T147
Test name
Test status
Simulation time 52308389794 ps
CPU time 49.03 seconds
Started Feb 07 01:36:17 PM PST 24
Finished Feb 07 01:37:07 PM PST 24
Peak memory 199916 kb
Host smart-0a3e1772-ccad-4a47-a001-2559a94390b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175703306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3175703306
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3550933711
Short name T962
Test name
Test status
Simulation time 39250841 ps
CPU time 0.56 seconds
Started Feb 07 01:36:40 PM PST 24
Finished Feb 07 01:36:47 PM PST 24
Peak memory 195356 kb
Host smart-93d63f6e-b56c-4e3e-9cea-9f096aa2e263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550933711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3550933711
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.468866067
Short name T240
Test name
Test status
Simulation time 128730457209 ps
CPU time 56.07 seconds
Started Feb 07 01:36:30 PM PST 24
Finished Feb 07 01:37:34 PM PST 24
Peak memory 199988 kb
Host smart-173ed952-4b6f-4f25-9b7e-a2c647ab0abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468866067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.468866067
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1330370568
Short name T380
Test name
Test status
Simulation time 134970004744 ps
CPU time 53.55 seconds
Started Feb 07 01:36:26 PM PST 24
Finished Feb 07 01:37:21 PM PST 24
Peak memory 199892 kb
Host smart-0f851589-45c8-4eb6-9a9c-e06bd226dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330370568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1330370568
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2924621294
Short name T1214
Test name
Test status
Simulation time 17656219852 ps
CPU time 28.41 seconds
Started Feb 07 01:36:29 PM PST 24
Finished Feb 07 01:37:05 PM PST 24
Peak memory 199644 kb
Host smart-ba947984-2bc5-4f8a-8dea-e8af5695992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924621294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2924621294
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3495732412
Short name T572
Test name
Test status
Simulation time 33089551453 ps
CPU time 37.06 seconds
Started Feb 07 01:36:27 PM PST 24
Finished Feb 07 01:37:06 PM PST 24
Peak memory 199976 kb
Host smart-df56e71e-f3fc-444c-851e-9360ee09f660
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495732412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3495732412
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.597626804
Short name T776
Test name
Test status
Simulation time 92775435684 ps
CPU time 672.89 seconds
Started Feb 07 01:36:25 PM PST 24
Finished Feb 07 01:47:39 PM PST 24
Peak memory 199952 kb
Host smart-6858116e-28e8-420d-a463-9bf3d8b3ec69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597626804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.597626804
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1613133488
Short name T544
Test name
Test status
Simulation time 8190986856 ps
CPU time 16.57 seconds
Started Feb 07 01:36:33 PM PST 24
Finished Feb 07 01:36:59 PM PST 24
Peak memory 198972 kb
Host smart-2582326a-61d6-4c51-974e-b0b566dfa3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613133488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1613133488
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2354994443
Short name T278
Test name
Test status
Simulation time 94935050735 ps
CPU time 47.24 seconds
Started Feb 07 01:36:31 PM PST 24
Finished Feb 07 01:37:25 PM PST 24
Peak memory 199652 kb
Host smart-a14cbbf6-c6be-41d3-a86a-9145a2fb5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354994443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2354994443
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4177166869
Short name T607
Test name
Test status
Simulation time 6847750003 ps
CPU time 383.68 seconds
Started Feb 07 01:36:30 PM PST 24
Finished Feb 07 01:43:01 PM PST 24
Peak memory 199956 kb
Host smart-dbad736d-8cbb-435c-ac4a-14ba1869fe95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177166869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4177166869
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3815029873
Short name T496
Test name
Test status
Simulation time 2103378051 ps
CPU time 11.72 seconds
Started Feb 07 01:36:26 PM PST 24
Finished Feb 07 01:36:39 PM PST 24
Peak memory 197788 kb
Host smart-c6992d9a-8836-433e-8e95-b6f7f51baaba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815029873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3815029873
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2720125214
Short name T242
Test name
Test status
Simulation time 46461280255 ps
CPU time 67.35 seconds
Started Feb 07 01:36:27 PM PST 24
Finished Feb 07 01:37:39 PM PST 24
Peak memory 198868 kb
Host smart-34016bc7-6c06-4549-b7f9-dc2b142c5eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720125214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2720125214
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1982047140
Short name T1146
Test name
Test status
Simulation time 6342130425 ps
CPU time 3.17 seconds
Started Feb 07 01:36:26 PM PST 24
Finished Feb 07 01:36:30 PM PST 24
Peak memory 195692 kb
Host smart-9e0f77f6-33d2-41a9-b6bf-961e1dc9512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982047140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1982047140
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3030351457
Short name T445
Test name
Test status
Simulation time 5887253222 ps
CPU time 8.17 seconds
Started Feb 07 01:36:29 PM PST 24
Finished Feb 07 01:36:45 PM PST 24
Peak memory 199776 kb
Host smart-ffa01ffe-ed08-4884-acca-0be858b58515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030351457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3030351457
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1778989982
Short name T1147
Test name
Test status
Simulation time 462152776530 ps
CPU time 63.14 seconds
Started Feb 07 01:36:26 PM PST 24
Finished Feb 07 01:37:31 PM PST 24
Peak memory 208308 kb
Host smart-eb7e669e-5c40-460a-b3fb-e40f8e9edd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778989982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1778989982
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.380023904
Short name T614
Test name
Test status
Simulation time 89275699301 ps
CPU time 324.18 seconds
Started Feb 07 01:36:29 PM PST 24
Finished Feb 07 01:42:02 PM PST 24
Peak memory 216664 kb
Host smart-35690164-50e5-4791-b613-064ce26c7b6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380023904 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.380023904
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3595627297
Short name T1165
Test name
Test status
Simulation time 6152738881 ps
CPU time 14.71 seconds
Started Feb 07 01:36:31 PM PST 24
Finished Feb 07 01:36:52 PM PST 24
Peak memory 199312 kb
Host smart-af763199-f05b-4e91-8bf6-ed49e31b5374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595627297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3595627297
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.525124761
Short name T1107
Test name
Test status
Simulation time 51997896846 ps
CPU time 12.51 seconds
Started Feb 07 01:36:31 PM PST 24
Finished Feb 07 01:36:50 PM PST 24
Peak memory 199912 kb
Host smart-d4520b34-56dc-411f-b5ba-e19741323ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525124761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.525124761
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1489656552
Short name T1003
Test name
Test status
Simulation time 17315776 ps
CPU time 0.53 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:36:50 PM PST 24
Peak memory 194320 kb
Host smart-6bc4c023-8582-4f11-a3f2-fa47db4abc8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489656552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1489656552
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4281982157
Short name T818
Test name
Test status
Simulation time 116595382685 ps
CPU time 44.45 seconds
Started Feb 07 01:36:44 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 199740 kb
Host smart-6658634e-e0bb-48a8-bab8-6061b662ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281982157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4281982157
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.708696710
Short name T1010
Test name
Test status
Simulation time 121841492896 ps
CPU time 119.96 seconds
Started Feb 07 01:36:40 PM PST 24
Finished Feb 07 01:38:47 PM PST 24
Peak memory 199188 kb
Host smart-2d7e6002-dd8d-4893-948f-9b5176c5c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708696710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.708696710
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2731447884
Short name T1215
Test name
Test status
Simulation time 221640291277 ps
CPU time 38.81 seconds
Started Feb 07 01:36:40 PM PST 24
Finished Feb 07 01:37:26 PM PST 24
Peak memory 199876 kb
Host smart-69a1cd21-9580-491d-ab67-488b87c2ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731447884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2731447884
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1526129143
Short name T1224
Test name
Test status
Simulation time 286352313747 ps
CPU time 395.52 seconds
Started Feb 07 01:36:41 PM PST 24
Finished Feb 07 01:43:22 PM PST 24
Peak memory 198492 kb
Host smart-2edcd8f9-3b06-468d-a907-491832b60420
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526129143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1526129143
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1397161994
Short name T1035
Test name
Test status
Simulation time 191266415032 ps
CPU time 1240.74 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 199996 kb
Host smart-063e3bf0-959c-4ac6-9d14-e610829a6051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397161994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1397161994
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1782312232
Short name T816
Test name
Test status
Simulation time 2811696720 ps
CPU time 5.04 seconds
Started Feb 07 01:36:38 PM PST 24
Finished Feb 07 01:36:49 PM PST 24
Peak memory 197676 kb
Host smart-e60def4c-6763-41be-9b45-ee87a55a2bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782312232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1782312232
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2214154349
Short name T744
Test name
Test status
Simulation time 58463703179 ps
CPU time 93.38 seconds
Started Feb 07 01:36:41 PM PST 24
Finished Feb 07 01:38:20 PM PST 24
Peak memory 198588 kb
Host smart-f62e48e8-9edc-4344-8c70-fa8f3d8f1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214154349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2214154349
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2260837830
Short name T1162
Test name
Test status
Simulation time 29415138250 ps
CPU time 198.5 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:40:08 PM PST 24
Peak memory 199876 kb
Host smart-45140d6a-7c60-4958-96b5-18927644cd29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260837830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2260837830
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1132741618
Short name T643
Test name
Test status
Simulation time 3465179134 ps
CPU time 27.51 seconds
Started Feb 07 01:36:41 PM PST 24
Finished Feb 07 01:37:14 PM PST 24
Peak memory 198136 kb
Host smart-7c4c290f-5e09-4f9c-ba87-6de200a04b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132741618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1132741618
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.852824413
Short name T1025
Test name
Test status
Simulation time 3485756723 ps
CPU time 2.07 seconds
Started Feb 07 01:36:39 PM PST 24
Finished Feb 07 01:36:49 PM PST 24
Peak memory 195336 kb
Host smart-9f67e7c4-6ee8-4f25-918f-c2cf85191b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852824413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.852824413
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2999774616
Short name T431
Test name
Test status
Simulation time 5326409550 ps
CPU time 13.1 seconds
Started Feb 07 01:36:40 PM PST 24
Finished Feb 07 01:37:00 PM PST 24
Peak memory 198568 kb
Host smart-70af119c-ba37-4b47-aeae-976f36a1a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999774616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2999774616
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2109835180
Short name T423
Test name
Test status
Simulation time 397001499 ps
CPU time 1.53 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:36:51 PM PST 24
Peak memory 197960 kb
Host smart-0b75a093-baa3-42ad-b75b-4da3fed67140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109835180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2109835180
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3971200763
Short name T587
Test name
Test status
Simulation time 119325253542 ps
CPU time 167.09 seconds
Started Feb 07 01:36:39 PM PST 24
Finished Feb 07 01:39:34 PM PST 24
Peak memory 199864 kb
Host smart-a7801914-46d9-4c4c-92c2-939ad19d206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971200763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3971200763
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1255854946
Short name T553
Test name
Test status
Simulation time 32216912 ps
CPU time 0.55 seconds
Started Feb 07 01:31:31 PM PST 24
Finished Feb 07 01:31:32 PM PST 24
Peak memory 195332 kb
Host smart-abc1bf8d-addf-430d-b615-9a66240d473e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255854946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1255854946
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3852464811
Short name T627
Test name
Test status
Simulation time 334825762009 ps
CPU time 57.93 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:32:28 PM PST 24
Peak memory 199828 kb
Host smart-f7877982-f6af-413b-8fbb-dfbaa5018bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852464811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3852464811
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2242320199
Short name T1084
Test name
Test status
Simulation time 55666919276 ps
CPU time 82.91 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:32:54 PM PST 24
Peak memory 199856 kb
Host smart-6c357827-00f9-4761-87a8-9e36f2924dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242320199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2242320199
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2120662282
Short name T843
Test name
Test status
Simulation time 47838290353 ps
CPU time 24.88 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:31:55 PM PST 24
Peak memory 199920 kb
Host smart-dd8e4b33-ab15-4ea7-a37a-b989110b2963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120662282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2120662282
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2753524868
Short name T953
Test name
Test status
Simulation time 554942698018 ps
CPU time 436.61 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:38:47 PM PST 24
Peak memory 198300 kb
Host smart-05d4e527-5767-4895-8431-15c17bf33e72
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753524868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2753524868
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.425053285
Short name T808
Test name
Test status
Simulation time 217346352314 ps
CPU time 193.42 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:34:46 PM PST 24
Peak memory 199892 kb
Host smart-915d3f5e-0ad1-4b2d-b9fc-9feb72a49e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425053285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.425053285
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_noise_filter.466847002
Short name T1051
Test name
Test status
Simulation time 158078807299 ps
CPU time 42.2 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:32:12 PM PST 24
Peak memory 197912 kb
Host smart-520f9197-a584-476f-89f0-dca3dbfb1bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466847002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.466847002
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3920172562
Short name T1183
Test name
Test status
Simulation time 8754323742 ps
CPU time 136.86 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:33:47 PM PST 24
Peak memory 199892 kb
Host smart-2e662dce-e7a1-41de-9a7a-e6c7170d3817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920172562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3920172562
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1696063777
Short name T1056
Test name
Test status
Simulation time 1395209185 ps
CPU time 14.49 seconds
Started Feb 07 01:31:33 PM PST 24
Finished Feb 07 01:31:48 PM PST 24
Peak memory 197832 kb
Host smart-7e75dcb1-a1f1-4cc9-9ba6-094a399c738f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696063777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1696063777
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4011259109
Short name T348
Test name
Test status
Simulation time 150458634031 ps
CPU time 113.4 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:33:23 PM PST 24
Peak memory 199940 kb
Host smart-991ed07a-c9f5-459b-b457-ca26acc7f588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011259109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4011259109
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.123256398
Short name T785
Test name
Test status
Simulation time 34005052357 ps
CPU time 53.91 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:32:27 PM PST 24
Peak memory 195656 kb
Host smart-fe9eaade-250d-4333-966b-208c2c4dd80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123256398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.123256398
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2432635954
Short name T77
Test name
Test status
Simulation time 522852632 ps
CPU time 0.94 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:31:34 PM PST 24
Peak memory 217404 kb
Host smart-a1bc7d3c-9fd1-4e6e-acca-8f827df166cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432635954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2432635954
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4247622363
Short name T945
Test name
Test status
Simulation time 6201791955 ps
CPU time 5.76 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:31:37 PM PST 24
Peak memory 198652 kb
Host smart-abee8fa6-9231-4df8-bb35-7a7e7b25cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247622363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4247622363
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3382881635
Short name T632
Test name
Test status
Simulation time 230873344720 ps
CPU time 338.48 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:37:11 PM PST 24
Peak memory 208364 kb
Host smart-14142058-873f-4ec4-9b3d-6ae06c3b8d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382881635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3382881635
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2624098773
Short name T59
Test name
Test status
Simulation time 35839893472 ps
CPU time 598.18 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:41:31 PM PST 24
Peak memory 209180 kb
Host smart-3bad8845-7832-4044-b0b4-b39257fc3de5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624098773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2624098773
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1374097056
Short name T839
Test name
Test status
Simulation time 961526957 ps
CPU time 3.59 seconds
Started Feb 07 01:31:33 PM PST 24
Finished Feb 07 01:31:37 PM PST 24
Peak memory 199404 kb
Host smart-425a55e9-ef30-40b8-97f3-8099e690d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374097056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1374097056
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3649196820
Short name T910
Test name
Test status
Simulation time 4604989569 ps
CPU time 10.71 seconds
Started Feb 07 01:31:28 PM PST 24
Finished Feb 07 01:31:39 PM PST 24
Peak memory 199328 kb
Host smart-e013eace-8f26-4187-9a3c-439ed0d2ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649196820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3649196820
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2164790591
Short name T511
Test name
Test status
Simulation time 74231691 ps
CPU time 0.55 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:36:50 PM PST 24
Peak memory 195400 kb
Host smart-aa723745-b5a1-45b6-8c63-990638bbaf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164790591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2164790591
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_intr.2526891259
Short name T658
Test name
Test status
Simulation time 330999260439 ps
CPU time 42.15 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:37:31 PM PST 24
Peak memory 198444 kb
Host smart-6a60a4fb-29a9-4577-bcec-3556086ccc2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526891259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2526891259
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3664429034
Short name T680
Test name
Test status
Simulation time 119441419595 ps
CPU time 253.17 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 200004 kb
Host smart-e4f616b6-b9b2-4f78-81de-1840e5a21f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664429034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3664429034
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3670091886
Short name T488
Test name
Test status
Simulation time 7917938176 ps
CPU time 4.55 seconds
Started Feb 07 01:36:44 PM PST 24
Finished Feb 07 01:36:52 PM PST 24
Peak memory 199228 kb
Host smart-a82b669b-deec-48c2-b440-02d3cbadff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670091886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3670091886
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2794110134
Short name T1059
Test name
Test status
Simulation time 44820897644 ps
CPU time 25.73 seconds
Started Feb 07 01:36:48 PM PST 24
Finished Feb 07 01:37:16 PM PST 24
Peak memory 199000 kb
Host smart-b74fa0e8-3210-4afa-a423-e7a5a4b09a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794110134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2794110134
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1853985932
Short name T1039
Test name
Test status
Simulation time 14925201437 ps
CPU time 189.2 seconds
Started Feb 07 01:36:44 PM PST 24
Finished Feb 07 01:39:57 PM PST 24
Peak memory 199920 kb
Host smart-eb354e06-e8f7-49a8-9c7d-fd81e038d421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853985932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1853985932
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3180905679
Short name T1213
Test name
Test status
Simulation time 480357585 ps
CPU time 1.58 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:36:51 PM PST 24
Peak memory 197708 kb
Host smart-c3e11ab1-8973-45cf-9037-467a35cee4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3180905679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3180905679
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3286930798
Short name T151
Test name
Test status
Simulation time 101152685739 ps
CPU time 159.87 seconds
Started Feb 07 01:36:49 PM PST 24
Finished Feb 07 01:39:30 PM PST 24
Peak memory 199892 kb
Host smart-aa17fb49-7a5d-4b2c-8fe9-3343e87f0d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286930798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3286930798
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1705834611
Short name T567
Test name
Test status
Simulation time 1518733046 ps
CPU time 1.29 seconds
Started Feb 07 01:36:44 PM PST 24
Finished Feb 07 01:36:49 PM PST 24
Peak memory 195236 kb
Host smart-daa03f78-d320-4970-b964-e2127f5202ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705834611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1705834611
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3112344704
Short name T1036
Test name
Test status
Simulation time 6210045575 ps
CPU time 14.72 seconds
Started Feb 07 01:36:45 PM PST 24
Finished Feb 07 01:37:03 PM PST 24
Peak memory 198600 kb
Host smart-2b8fd90d-a98d-4f47-aadb-ebc37f675692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112344704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3112344704
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1904534790
Short name T620
Test name
Test status
Simulation time 379282395344 ps
CPU time 172.39 seconds
Started Feb 07 01:36:47 PM PST 24
Finished Feb 07 01:39:42 PM PST 24
Peak memory 199992 kb
Host smart-8a8a3cf3-d1e4-498d-aa89-106af8dfd105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904534790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1904534790
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.555511254
Short name T879
Test name
Test status
Simulation time 35802386699 ps
CPU time 755.45 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:49:25 PM PST 24
Peak memory 216680 kb
Host smart-962aeca5-39ce-4e66-bfad-05ae00237da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555511254 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.555511254
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.509438217
Short name T1217
Test name
Test status
Simulation time 739293078 ps
CPU time 1.33 seconds
Started Feb 07 01:36:47 PM PST 24
Finished Feb 07 01:36:51 PM PST 24
Peak memory 197820 kb
Host smart-f1263fc2-7212-4a8d-9c5d-af921d13c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509438217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.509438217
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4236755742
Short name T988
Test name
Test status
Simulation time 69226733591 ps
CPU time 90.22 seconds
Started Feb 07 01:36:47 PM PST 24
Finished Feb 07 01:38:20 PM PST 24
Peak memory 199936 kb
Host smart-9500caac-6a85-478b-83d2-80dddb03f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236755742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4236755742
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2973914208
Short name T524
Test name
Test status
Simulation time 54118964 ps
CPU time 0.53 seconds
Started Feb 07 01:36:59 PM PST 24
Finished Feb 07 01:37:01 PM PST 24
Peak memory 194232 kb
Host smart-742e2a01-837a-4026-9f5a-1f10fbc36545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973914208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2973914208
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3797740369
Short name T543
Test name
Test status
Simulation time 83787319053 ps
CPU time 141.72 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:39:11 PM PST 24
Peak memory 199916 kb
Host smart-de272231-350a-4cc8-99cd-570d97c56d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797740369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3797740369
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3848588191
Short name T265
Test name
Test status
Simulation time 88643800569 ps
CPU time 40.27 seconds
Started Feb 07 01:36:58 PM PST 24
Finished Feb 07 01:37:40 PM PST 24
Peak memory 199740 kb
Host smart-440eaa90-22b0-4c79-9093-19d68de3b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848588191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3848588191
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1044087912
Short name T187
Test name
Test status
Simulation time 14732880443 ps
CPU time 7.25 seconds
Started Feb 07 01:36:55 PM PST 24
Finished Feb 07 01:37:03 PM PST 24
Peak memory 198448 kb
Host smart-da640f5a-f094-4f7b-a748-e952a23b4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044087912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1044087912
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1295860307
Short name T228
Test name
Test status
Simulation time 1500130926863 ps
CPU time 2391.53 seconds
Started Feb 07 01:37:00 PM PST 24
Finished Feb 07 02:16:52 PM PST 24
Peak memory 199432 kb
Host smart-afc8be2a-8773-4404-8f2d-d27121c4272f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295860307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1295860307
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2496852728
Short name T742
Test name
Test status
Simulation time 149202794962 ps
CPU time 347.87 seconds
Started Feb 07 01:36:55 PM PST 24
Finished Feb 07 01:42:44 PM PST 24
Peak memory 199924 kb
Host smart-a5da16ee-60ad-4e11-bc88-9b2bcf93d799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496852728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2496852728
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.397599649
Short name T487
Test name
Test status
Simulation time 9277824633 ps
CPU time 25.53 seconds
Started Feb 07 01:36:56 PM PST 24
Finished Feb 07 01:37:23 PM PST 24
Peak memory 199124 kb
Host smart-3b1f9a6d-4a7f-4305-af55-5bbf252d5cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397599649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.397599649
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1956145198
Short name T586
Test name
Test status
Simulation time 145568060625 ps
CPU time 35.34 seconds
Started Feb 07 01:36:57 PM PST 24
Finished Feb 07 01:37:33 PM PST 24
Peak memory 208240 kb
Host smart-6409e9a5-81d1-45cd-91d3-439d36419f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956145198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1956145198
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.239827406
Short name T1031
Test name
Test status
Simulation time 11364034617 ps
CPU time 112.27 seconds
Started Feb 07 01:36:53 PM PST 24
Finished Feb 07 01:38:46 PM PST 24
Peak memory 199964 kb
Host smart-08e77056-11d7-4e0d-9282-dfaf137c2b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239827406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.239827406
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2698793560
Short name T984
Test name
Test status
Simulation time 169328593 ps
CPU time 0.75 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:36:56 PM PST 24
Peak memory 196408 kb
Host smart-1420d513-e43e-4477-b187-c417e8cc9083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698793560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2698793560
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.912082318
Short name T687
Test name
Test status
Simulation time 109815292195 ps
CPU time 174.92 seconds
Started Feb 07 01:36:52 PM PST 24
Finished Feb 07 01:39:48 PM PST 24
Peak memory 198708 kb
Host smart-2e365b49-3e37-42fe-b442-805f9e75eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912082318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.912082318
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.218712824
Short name T651
Test name
Test status
Simulation time 3874863331 ps
CPU time 6.5 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:37:01 PM PST 24
Peak memory 195648 kb
Host smart-5218dd8a-039f-4bf6-8ab8-11300e4fd32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218712824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.218712824
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2979030238
Short name T562
Test name
Test status
Simulation time 85715513 ps
CPU time 0.86 seconds
Started Feb 07 01:36:46 PM PST 24
Finished Feb 07 01:36:50 PM PST 24
Peak memory 196440 kb
Host smart-f3a41d9a-036f-4969-9c0b-7aa11fefb6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979030238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2979030238
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2380003457
Short name T836
Test name
Test status
Simulation time 894047898941 ps
CPU time 1543.17 seconds
Started Feb 07 01:36:59 PM PST 24
Finished Feb 07 02:02:43 PM PST 24
Peak memory 199836 kb
Host smart-7f6557cc-b8c2-40c1-997e-35073db0f111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380003457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2380003457
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.4001926989
Short name T737
Test name
Test status
Simulation time 8172214451 ps
CPU time 11.65 seconds
Started Feb 07 01:36:55 PM PST 24
Finished Feb 07 01:37:08 PM PST 24
Peak memory 199612 kb
Host smart-e97d1aff-cf7b-4814-96ab-0d9333c52b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001926989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.4001926989
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.796114900
Short name T911
Test name
Test status
Simulation time 9240041146 ps
CPU time 13.41 seconds
Started Feb 07 01:36:47 PM PST 24
Finished Feb 07 01:37:03 PM PST 24
Peak memory 196568 kb
Host smart-47a34252-a7cf-43c8-9f1a-1e3178685ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796114900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.796114900
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3403595447
Short name T1005
Test name
Test status
Simulation time 45193122 ps
CPU time 0.58 seconds
Started Feb 07 01:36:53 PM PST 24
Finished Feb 07 01:36:54 PM PST 24
Peak memory 195320 kb
Host smart-c8eff5bb-35a7-49ae-9b97-77ec8b3b1921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403595447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3403595447
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2920911716
Short name T877
Test name
Test status
Simulation time 133846910296 ps
CPU time 193.33 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:40:08 PM PST 24
Peak memory 199948 kb
Host smart-46fcf939-53a9-476e-9f0d-082f0ed7fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920911716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2920911716
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4224499566
Short name T928
Test name
Test status
Simulation time 36334857111 ps
CPU time 76.13 seconds
Started Feb 07 01:36:57 PM PST 24
Finished Feb 07 01:38:14 PM PST 24
Peak memory 199960 kb
Host smart-a5ca9ee9-c7d4-4888-a631-b3eb5c464cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224499566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4224499566
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3353339656
Short name T592
Test name
Test status
Simulation time 20971446752 ps
CPU time 17.58 seconds
Started Feb 07 01:36:58 PM PST 24
Finished Feb 07 01:37:17 PM PST 24
Peak memory 199712 kb
Host smart-9e5ed13a-fad8-4dd7-bde0-82fb3db7e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353339656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3353339656
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1622000263
Short name T1054
Test name
Test status
Simulation time 1099501418762 ps
CPU time 901.37 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:51:56 PM PST 24
Peak memory 199888 kb
Host smart-b325f76d-15ca-4a7f-8d1f-90cbfebf0a54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622000263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1622000263
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2776428119
Short name T1040
Test name
Test status
Simulation time 153733345893 ps
CPU time 453.81 seconds
Started Feb 07 01:36:56 PM PST 24
Finished Feb 07 01:44:31 PM PST 24
Peak memory 200004 kb
Host smart-19b09f4f-50fa-4e4e-9892-d3ff76dd3905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776428119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2776428119
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1871173117
Short name T513
Test name
Test status
Simulation time 3977620996 ps
CPU time 9.75 seconds
Started Feb 07 01:36:55 PM PST 24
Finished Feb 07 01:37:05 PM PST 24
Peak memory 199080 kb
Host smart-ddf02b5c-0d27-4daf-a9da-7860eecdb2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871173117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1871173117
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1250493065
Short name T1148
Test name
Test status
Simulation time 133557362333 ps
CPU time 58.92 seconds
Started Feb 07 01:36:55 PM PST 24
Finished Feb 07 01:37:55 PM PST 24
Peak memory 208136 kb
Host smart-564c99e3-721e-496f-b104-25e69bf05095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250493065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1250493065
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2011337031
Short name T1110
Test name
Test status
Simulation time 14734006090 ps
CPU time 773.91 seconds
Started Feb 07 01:36:57 PM PST 24
Finished Feb 07 01:49:52 PM PST 24
Peak memory 199740 kb
Host smart-bb1ac05c-4aa2-4596-a0a3-e730e5cb9697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011337031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2011337031
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.579320393
Short name T279
Test name
Test status
Simulation time 30404015614 ps
CPU time 49.05 seconds
Started Feb 07 01:36:59 PM PST 24
Finished Feb 07 01:37:49 PM PST 24
Peak memory 199736 kb
Host smart-7d3f9fb1-e5b9-42d5-b69f-da61214d1f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579320393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.579320393
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4075722076
Short name T871
Test name
Test status
Simulation time 2547331642 ps
CPU time 0.97 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:36:55 PM PST 24
Peak memory 195360 kb
Host smart-11e6bb6a-22b3-4f96-80b1-4b31feb4445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075722076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4075722076
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4257704052
Short name T1029
Test name
Test status
Simulation time 5763094319 ps
CPU time 20.11 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:37:14 PM PST 24
Peak memory 199888 kb
Host smart-0061103e-fe92-4bb3-80f7-c51af14851d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257704052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4257704052
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2584214195
Short name T176
Test name
Test status
Simulation time 101007714443 ps
CPU time 204.85 seconds
Started Feb 07 01:36:56 PM PST 24
Finished Feb 07 01:40:22 PM PST 24
Peak memory 200168 kb
Host smart-9f4666b2-293b-47c8-9d0f-ac2368164ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584214195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2584214195
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1696091424
Short name T401
Test name
Test status
Simulation time 67358077243 ps
CPU time 456.95 seconds
Started Feb 07 01:36:56 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 215384 kb
Host smart-e4aa84b3-7eca-46b6-81ef-f85f1a417bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696091424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1696091424
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3996904963
Short name T885
Test name
Test status
Simulation time 3481517174 ps
CPU time 1.63 seconds
Started Feb 07 01:36:54 PM PST 24
Finished Feb 07 01:36:57 PM PST 24
Peak memory 198140 kb
Host smart-252854b1-45f3-4ec4-9fe9-cecbec16a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996904963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3996904963
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2715942255
Short name T516
Test name
Test status
Simulation time 19700874918 ps
CPU time 39.77 seconds
Started Feb 07 01:36:56 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 199928 kb
Host smart-2e7070d4-3b9b-4e5e-a94e-6f5f3f7214e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715942255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2715942255
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1110779914
Short name T820
Test name
Test status
Simulation time 32401692 ps
CPU time 0.61 seconds
Started Feb 07 01:37:05 PM PST 24
Finished Feb 07 01:37:07 PM PST 24
Peak memory 195344 kb
Host smart-95bf8eb3-33af-4c9a-8181-a073ae7eb6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110779914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1110779914
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2252240420
Short name T947
Test name
Test status
Simulation time 146463237224 ps
CPU time 225.44 seconds
Started Feb 07 01:37:02 PM PST 24
Finished Feb 07 01:40:49 PM PST 24
Peak memory 199900 kb
Host smart-b768292b-cb27-4188-bad3-bcbaf467fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252240420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2252240420
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3499333091
Short name T1184
Test name
Test status
Simulation time 147805055994 ps
CPU time 246.59 seconds
Started Feb 07 01:37:08 PM PST 24
Finished Feb 07 01:41:15 PM PST 24
Peak memory 199800 kb
Host smart-fbbf9701-1277-49cc-8054-5b58c907e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499333091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3499333091
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_intr.106156014
Short name T977
Test name
Test status
Simulation time 54805211794 ps
CPU time 44.48 seconds
Started Feb 07 01:37:03 PM PST 24
Finished Feb 07 01:37:49 PM PST 24
Peak memory 199928 kb
Host smart-d7b13e63-5764-4897-be9e-810dd7fa5b54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106156014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.106156014
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3937838313
Short name T116
Test name
Test status
Simulation time 98836726749 ps
CPU time 588.04 seconds
Started Feb 07 01:37:04 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 199960 kb
Host smart-9ba46ca0-ce41-461d-8ff3-752ecb697bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937838313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3937838313
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4009536585
Short name T597
Test name
Test status
Simulation time 13316144701 ps
CPU time 14.85 seconds
Started Feb 07 01:37:04 PM PST 24
Finished Feb 07 01:37:20 PM PST 24
Peak memory 198648 kb
Host smart-2bb79526-1455-48bb-8c55-4f0d2b62c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009536585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4009536585
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.797864051
Short name T149
Test name
Test status
Simulation time 11651744599 ps
CPU time 15.11 seconds
Started Feb 07 01:37:09 PM PST 24
Finished Feb 07 01:37:25 PM PST 24
Peak memory 195892 kb
Host smart-784f9a1f-0857-49f0-b13a-a834035f0b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797864051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.797864051
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.202473785
Short name T679
Test name
Test status
Simulation time 12982755919 ps
CPU time 705.23 seconds
Started Feb 07 01:37:04 PM PST 24
Finished Feb 07 01:48:51 PM PST 24
Peak memory 200032 kb
Host smart-f526cf64-b890-4c7b-a950-0be06f49d645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202473785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.202473785
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.146114738
Short name T714
Test name
Test status
Simulation time 1852847910 ps
CPU time 2.05 seconds
Started Feb 07 01:37:05 PM PST 24
Finished Feb 07 01:37:08 PM PST 24
Peak memory 197708 kb
Host smart-d26cca72-ec56-4e64-8665-8ea26fe12c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146114738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.146114738
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3998418024
Short name T937
Test name
Test status
Simulation time 193023209353 ps
CPU time 71.75 seconds
Started Feb 07 01:37:06 PM PST 24
Finished Feb 07 01:38:19 PM PST 24
Peak memory 198776 kb
Host smart-ab048b1d-52f9-453a-9dc6-fde20223229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998418024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3998418024
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3494017807
Short name T591
Test name
Test status
Simulation time 2096497780 ps
CPU time 2.08 seconds
Started Feb 07 01:37:04 PM PST 24
Finished Feb 07 01:37:08 PM PST 24
Peak memory 195256 kb
Host smart-1c0cf937-8d10-42b4-a899-74fa91d1fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494017807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3494017807
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3784980495
Short name T615
Test name
Test status
Simulation time 11586067337 ps
CPU time 25.18 seconds
Started Feb 07 01:37:06 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 198892 kb
Host smart-51d23959-ad0f-4963-b1d8-c00106e00d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784980495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3784980495
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.288620297
Short name T891
Test name
Test status
Simulation time 81475487132 ps
CPU time 138.59 seconds
Started Feb 07 01:37:02 PM PST 24
Finished Feb 07 01:39:22 PM PST 24
Peak memory 199928 kb
Host smart-c54dc5a4-d6ce-46a9-b6b0-9fff45f37c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288620297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.288620297
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3842522062
Short name T495
Test name
Test status
Simulation time 1241354663 ps
CPU time 4.32 seconds
Started Feb 07 01:37:03 PM PST 24
Finished Feb 07 01:37:08 PM PST 24
Peak memory 197652 kb
Host smart-6a4b3f11-76e4-46c8-beb5-0e2ecdee9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842522062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3842522062
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.836328657
Short name T1171
Test name
Test status
Simulation time 46308445958 ps
CPU time 62.02 seconds
Started Feb 07 01:37:08 PM PST 24
Finished Feb 07 01:38:11 PM PST 24
Peak memory 200000 kb
Host smart-cbf7d1be-1dde-4263-bb1e-c14563370ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836328657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.836328657
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1006526719
Short name T1208
Test name
Test status
Simulation time 40831379 ps
CPU time 0.54 seconds
Started Feb 07 01:37:22 PM PST 24
Finished Feb 07 01:37:23 PM PST 24
Peak memory 195344 kb
Host smart-ea7815c9-0265-42df-86cb-bbeaf36cb384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006526719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1006526719
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2181651502
Short name T208
Test name
Test status
Simulation time 31336643114 ps
CPU time 42.04 seconds
Started Feb 07 01:37:26 PM PST 24
Finished Feb 07 01:38:09 PM PST 24
Peak memory 199960 kb
Host smart-7bf277f3-a2df-4d1e-b9b8-74dc5afe2ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181651502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2181651502
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1170107583
Short name T633
Test name
Test status
Simulation time 132628123392 ps
CPU time 56.19 seconds
Started Feb 07 01:37:15 PM PST 24
Finished Feb 07 01:38:12 PM PST 24
Peak memory 199872 kb
Host smart-d0552190-aa9c-4fd2-ad47-65261c06cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170107583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1170107583
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.746613144
Short name T305
Test name
Test status
Simulation time 12386934464 ps
CPU time 25.52 seconds
Started Feb 07 01:37:20 PM PST 24
Finished Feb 07 01:37:46 PM PST 24
Peak memory 199968 kb
Host smart-a65190e7-ba64-4894-8f5e-64d09e5b2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746613144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.746613144
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.428657009
Short name T974
Test name
Test status
Simulation time 12916319820 ps
CPU time 44.5 seconds
Started Feb 07 01:37:22 PM PST 24
Finished Feb 07 01:38:07 PM PST 24
Peak memory 199928 kb
Host smart-91439933-e863-49e6-877a-31ceba00874a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428657009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.428657009
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1170023121
Short name T1218
Test name
Test status
Simulation time 187775816611 ps
CPU time 550.59 seconds
Started Feb 07 01:37:22 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 200004 kb
Host smart-634346c2-73ad-4278-93be-3f373c01d214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170023121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1170023121
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1963640924
Short name T925
Test name
Test status
Simulation time 6511835294 ps
CPU time 2.48 seconds
Started Feb 07 01:37:18 PM PST 24
Finished Feb 07 01:37:21 PM PST 24
Peak memory 198632 kb
Host smart-851e9dbf-afe8-49d9-8340-397a6949b547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963640924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1963640924
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1855174532
Short name T965
Test name
Test status
Simulation time 19352953436 ps
CPU time 32.64 seconds
Started Feb 07 01:37:26 PM PST 24
Finished Feb 07 01:37:59 PM PST 24
Peak memory 198360 kb
Host smart-17a09af1-c24b-4cab-8719-076237dc107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855174532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1855174532
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.590584830
Short name T719
Test name
Test status
Simulation time 8104539729 ps
CPU time 474.34 seconds
Started Feb 07 01:37:23 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 199872 kb
Host smart-2f760fc9-111a-4eef-9476-0c04904d48b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590584830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.590584830
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2404989492
Short name T1092
Test name
Test status
Simulation time 1487751517 ps
CPU time 6.09 seconds
Started Feb 07 01:37:21 PM PST 24
Finished Feb 07 01:37:28 PM PST 24
Peak memory 197516 kb
Host smart-f1f89d4f-44a4-4b4a-b0f2-be5cde841bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404989492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2404989492
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.112151793
Short name T989
Test name
Test status
Simulation time 91968642556 ps
CPU time 34.53 seconds
Started Feb 07 01:37:23 PM PST 24
Finished Feb 07 01:37:59 PM PST 24
Peak memory 199220 kb
Host smart-62957cd9-9384-4a1c-995e-60312c34f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112151793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.112151793
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.440890927
Short name T618
Test name
Test status
Simulation time 686549356 ps
CPU time 1.13 seconds
Started Feb 07 01:37:27 PM PST 24
Finished Feb 07 01:37:28 PM PST 24
Peak memory 195256 kb
Host smart-e41ef87b-b4e0-43e2-819f-7d8db43b4286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440890927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.440890927
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3328901483
Short name T417
Test name
Test status
Simulation time 695690489 ps
CPU time 4.92 seconds
Started Feb 07 01:37:22 PM PST 24
Finished Feb 07 01:37:28 PM PST 24
Peak memory 198428 kb
Host smart-07b7d884-23d5-456d-b665-5720d2c0bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328901483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3328901483
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2175664199
Short name T1111
Test name
Test status
Simulation time 421800974690 ps
CPU time 1598.07 seconds
Started Feb 07 01:37:22 PM PST 24
Finished Feb 07 02:04:01 PM PST 24
Peak memory 199920 kb
Host smart-644d3511-bc7a-4849-9ebf-cd26837475c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175664199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2175664199
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3900514644
Short name T304
Test name
Test status
Simulation time 109926371549 ps
CPU time 226.17 seconds
Started Feb 07 01:37:16 PM PST 24
Finished Feb 07 01:41:03 PM PST 24
Peak memory 208324 kb
Host smart-cfd310a3-e3b7-4676-900d-d6744bc7894b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900514644 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3900514644
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.226244442
Short name T1063
Test name
Test status
Simulation time 1418453489 ps
CPU time 2.41 seconds
Started Feb 07 01:37:23 PM PST 24
Finished Feb 07 01:37:26 PM PST 24
Peak memory 198324 kb
Host smart-28e6ebed-124c-45fc-9b71-8619b23c3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226244442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.226244442
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1357926246
Short name T671
Test name
Test status
Simulation time 19994896449 ps
CPU time 16.97 seconds
Started Feb 07 01:37:20 PM PST 24
Finished Feb 07 01:37:38 PM PST 24
Peak memory 199920 kb
Host smart-b8761718-1a7d-48af-8a06-3766d477bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357926246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1357926246
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1354673949
Short name T1076
Test name
Test status
Simulation time 22364702 ps
CPU time 0.58 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 195316 kb
Host smart-4e5d6ee0-002e-4901-9def-27fd7442662a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354673949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1354673949
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.602517462
Short name T641
Test name
Test status
Simulation time 8946089775 ps
CPU time 12.66 seconds
Started Feb 07 01:37:28 PM PST 24
Finished Feb 07 01:37:42 PM PST 24
Peak memory 199360 kb
Host smart-7e4b0984-46da-474e-9323-4d3de63290d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602517462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.602517462
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2913749831
Short name T385
Test name
Test status
Simulation time 39844476924 ps
CPU time 47.86 seconds
Started Feb 07 01:37:28 PM PST 24
Finished Feb 07 01:38:17 PM PST 24
Peak memory 199912 kb
Host smart-0f3504ac-7dbf-47d9-988f-943070109957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913749831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2913749831
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4143258485
Short name T334
Test name
Test status
Simulation time 85276536472 ps
CPU time 33.13 seconds
Started Feb 07 01:37:27 PM PST 24
Finished Feb 07 01:38:02 PM PST 24
Peak memory 199988 kb
Host smart-2faff547-6302-48cb-a9c9-36231db794ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143258485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4143258485
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.125512804
Short name T24
Test name
Test status
Simulation time 196291554033 ps
CPU time 136.63 seconds
Started Feb 07 01:37:28 PM PST 24
Finished Feb 07 01:39:46 PM PST 24
Peak memory 199952 kb
Host smart-2de242e1-6d8b-4706-a5b9-744053881709
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125512804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.125512804
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1255383291
Short name T566
Test name
Test status
Simulation time 38630689890 ps
CPU time 215.84 seconds
Started Feb 07 01:37:25 PM PST 24
Finished Feb 07 01:41:02 PM PST 24
Peak memory 199964 kb
Host smart-91edd7db-7b8b-4054-ae3b-276507a88fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255383291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1255383291
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2041394137
Short name T1126
Test name
Test status
Simulation time 5456351537 ps
CPU time 3.12 seconds
Started Feb 07 01:37:27 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 198184 kb
Host smart-088ce594-76e5-4637-a8d2-0a1475673994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041394137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2041394137
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2777094282
Short name T857
Test name
Test status
Simulation time 32268974867 ps
CPU time 55.67 seconds
Started Feb 07 01:37:23 PM PST 24
Finished Feb 07 01:38:19 PM PST 24
Peak memory 198428 kb
Host smart-731f6ff6-093e-448c-bc31-282843b5995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777094282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2777094282
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1602476655
Short name T564
Test name
Test status
Simulation time 7621608169 ps
CPU time 91.57 seconds
Started Feb 07 01:37:27 PM PST 24
Finished Feb 07 01:39:00 PM PST 24
Peak memory 199844 kb
Host smart-2d43dfdc-9e3d-4397-94c3-81d989f3f94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602476655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1602476655
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2529205484
Short name T976
Test name
Test status
Simulation time 1663630032 ps
CPU time 5 seconds
Started Feb 07 01:37:23 PM PST 24
Finished Feb 07 01:37:29 PM PST 24
Peak memory 197528 kb
Host smart-71a2e123-26c8-45a2-805c-9decb0a8a870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529205484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2529205484
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3157806231
Short name T771
Test name
Test status
Simulation time 319120190078 ps
CPU time 485.45 seconds
Started Feb 07 01:37:28 PM PST 24
Finished Feb 07 01:45:35 PM PST 24
Peak memory 199936 kb
Host smart-175229c3-55b2-4fc6-be6c-9852f1a8c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157806231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3157806231
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3738198086
Short name T980
Test name
Test status
Simulation time 3700160440 ps
CPU time 3.58 seconds
Started Feb 07 01:37:28 PM PST 24
Finished Feb 07 01:37:33 PM PST 24
Peak memory 195624 kb
Host smart-e078435b-fab3-41b8-bb25-c79b86e94a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738198086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3738198086
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3466900101
Short name T964
Test name
Test status
Simulation time 740220438 ps
CPU time 1.53 seconds
Started Feb 07 01:37:30 PM PST 24
Finished Feb 07 01:37:32 PM PST 24
Peak memory 197984 kb
Host smart-b0aa5180-1006-45a3-9149-d1126f4cf784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466900101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3466900101
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.667792696
Short name T538
Test name
Test status
Simulation time 10416339954 ps
CPU time 33.58 seconds
Started Feb 07 01:37:30 PM PST 24
Finished Feb 07 01:38:05 PM PST 24
Peak memory 215464 kb
Host smart-b37f457f-c57a-475c-a565-9a9d737b23f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667792696 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.667792696
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2823589379
Short name T1136
Test name
Test status
Simulation time 6498106269 ps
CPU time 19.8 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:37:52 PM PST 24
Peak memory 199284 kb
Host smart-8ea6e764-a32c-4f03-b5c1-2c6780fef6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823589379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2823589379
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2140712436
Short name T908
Test name
Test status
Simulation time 159175600739 ps
CPU time 121.93 seconds
Started Feb 07 01:37:27 PM PST 24
Finished Feb 07 01:39:31 PM PST 24
Peak memory 199824 kb
Host smart-5760dbd1-69e4-4e91-b976-b9df78533b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140712436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2140712436
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2947529495
Short name T912
Test name
Test status
Simulation time 34719544 ps
CPU time 0.57 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 195356 kb
Host smart-ede328ed-ac52-4ac5-9c93-d7027fb9fe26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947529495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2947529495
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3987286579
Short name T834
Test name
Test status
Simulation time 70228467356 ps
CPU time 23.99 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:38:02 PM PST 24
Peak memory 199900 kb
Host smart-93ba26f2-43ee-407f-9038-8af663473b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987286579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3987286579
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3030427600
Short name T705
Test name
Test status
Simulation time 18648272275 ps
CPU time 35.04 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:38:13 PM PST 24
Peak memory 199876 kb
Host smart-7ae29774-73bb-41a0-91ec-3e37cd25d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030427600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3030427600
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2739486406
Short name T613
Test name
Test status
Simulation time 24015165845 ps
CPU time 35.92 seconds
Started Feb 07 01:37:34 PM PST 24
Finished Feb 07 01:38:10 PM PST 24
Peak memory 199880 kb
Host smart-af4f1524-023b-4f24-857a-09c8790c3513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739486406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2739486406
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.772948847
Short name T1229
Test name
Test status
Simulation time 787659506203 ps
CPU time 527.67 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 199140 kb
Host smart-abbd80cb-4fcd-4d86-b67b-c093cee78d9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772948847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.772948847
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1244041389
Short name T542
Test name
Test status
Simulation time 130620577941 ps
CPU time 278.74 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:42:16 PM PST 24
Peak memory 199980 kb
Host smart-91c7820c-a6fd-4dbd-8e0c-f440db666a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244041389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1244041389
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2308970206
Short name T197
Test name
Test status
Simulation time 77962470984 ps
CPU time 121.94 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:39:39 PM PST 24
Peak memory 200248 kb
Host smart-e9a029ac-7c1c-4cd8-99fe-f63149e5039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308970206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2308970206
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1595509426
Short name T918
Test name
Test status
Simulation time 8242176393 ps
CPU time 445.59 seconds
Started Feb 07 01:37:33 PM PST 24
Finished Feb 07 01:44:59 PM PST 24
Peak memory 199868 kb
Host smart-706f1b78-8498-455b-b84c-47499ad8915f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595509426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1595509426
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.4046259050
Short name T27
Test name
Test status
Simulation time 2621640023 ps
CPU time 8.93 seconds
Started Feb 07 01:37:34 PM PST 24
Finished Feb 07 01:37:44 PM PST 24
Peak memory 198244 kb
Host smart-c914f24a-0277-4768-b6b2-79f0463a9068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046259050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4046259050
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2427739600
Short name T1166
Test name
Test status
Simulation time 264254724904 ps
CPU time 145.22 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:40:03 PM PST 24
Peak memory 200004 kb
Host smart-4f148e02-3d0f-4694-be68-c5ffe3802f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427739600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2427739600
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2001239548
Short name T1042
Test name
Test status
Simulation time 4844732218 ps
CPU time 5.5 seconds
Started Feb 07 01:37:34 PM PST 24
Finished Feb 07 01:37:40 PM PST 24
Peak memory 195688 kb
Host smart-e7d12005-11aa-44a9-a48d-25f0e46b05a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001239548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2001239548
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3453272420
Short name T779
Test name
Test status
Simulation time 690796074 ps
CPU time 2.09 seconds
Started Feb 07 01:37:32 PM PST 24
Finished Feb 07 01:37:35 PM PST 24
Peak memory 197608 kb
Host smart-50faeb0e-f91f-4b08-ac84-56dd48e10f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453272420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3453272420
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.275038563
Short name T81
Test name
Test status
Simulation time 168037281201 ps
CPU time 389.27 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 199968 kb
Host smart-8fd576da-ac60-49b6-9fa4-415ba7aa5226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275038563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.275038563
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.900927570
Short name T1150
Test name
Test status
Simulation time 106439732243 ps
CPU time 220.02 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:41:12 PM PST 24
Peak memory 216448 kb
Host smart-64f52218-b048-4c6d-9ff4-2417e7027e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900927570 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.900927570
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.899919123
Short name T1033
Test name
Test status
Simulation time 321100818 ps
CPU time 1.38 seconds
Started Feb 07 01:37:35 PM PST 24
Finished Feb 07 01:37:37 PM PST 24
Peak memory 197656 kb
Host smart-1916104e-c55a-4ee3-abdc-149680018e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899919123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.899919123
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1352837885
Short name T531
Test name
Test status
Simulation time 22304646803 ps
CPU time 35.76 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:38:08 PM PST 24
Peak memory 199892 kb
Host smart-dc7c2c29-9997-413d-8355-459d1002c69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352837885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1352837885
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2924149842
Short name T93
Test name
Test status
Simulation time 45461068 ps
CPU time 0.57 seconds
Started Feb 07 01:37:44 PM PST 24
Finished Feb 07 01:37:45 PM PST 24
Peak memory 195368 kb
Host smart-d69f6ca8-fe90-47fe-9d81-269924bd4bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924149842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2924149842
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2978438669
Short name T770
Test name
Test status
Simulation time 36914192420 ps
CPU time 15.68 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:37:47 PM PST 24
Peak memory 199796 kb
Host smart-c087bef5-8eeb-485f-bd5c-14801f842e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978438669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2978438669
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3330831788
Short name T537
Test name
Test status
Simulation time 45696905621 ps
CPU time 71.22 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:38:49 PM PST 24
Peak memory 199932 kb
Host smart-6dabb9d0-0b02-47e3-93ae-2bd439dbd6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330831788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3330831788
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1062094017
Short name T646
Test name
Test status
Simulation time 131460072864 ps
CPU time 53.17 seconds
Started Feb 07 01:37:32 PM PST 24
Finished Feb 07 01:38:26 PM PST 24
Peak memory 199696 kb
Host smart-b7c9544e-2199-4987-917b-f1b8e8182b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062094017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1062094017
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1306701651
Short name T682
Test name
Test status
Simulation time 144896364279 ps
CPU time 813.76 seconds
Started Feb 07 01:37:42 PM PST 24
Finished Feb 07 01:51:16 PM PST 24
Peak memory 199932 kb
Host smart-3111c46a-0d9b-4d41-92af-c6d3de98fddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306701651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1306701651
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.4258747728
Short name T527
Test name
Test status
Simulation time 8164338392 ps
CPU time 6.7 seconds
Started Feb 07 01:37:34 PM PST 24
Finished Feb 07 01:37:41 PM PST 24
Peak memory 198144 kb
Host smart-aa8e914f-8199-4f6a-b5b1-648bd04debe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258747728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4258747728
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1256717153
Short name T402
Test name
Test status
Simulation time 226796245740 ps
CPU time 239.94 seconds
Started Feb 07 01:37:37 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 199312 kb
Host smart-9f6b4d66-ebd4-40b6-a03c-d2c6dc460bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256717153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1256717153
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1019759359
Short name T557
Test name
Test status
Simulation time 6930279875 ps
CPU time 244.94 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:41:42 PM PST 24
Peak memory 199936 kb
Host smart-2f2623b5-6e74-4c95-9e2e-1e32e2fddd55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019759359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1019759359
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2933112246
Short name T324
Test name
Test status
Simulation time 161079412088 ps
CPU time 242.82 seconds
Started Feb 07 01:37:38 PM PST 24
Finished Feb 07 01:41:41 PM PST 24
Peak memory 199160 kb
Host smart-20f49731-2acf-464c-9f61-f5a8a4c348b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933112246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2933112246
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3895379819
Short name T103
Test name
Test status
Simulation time 678156678 ps
CPU time 1.7 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:37:39 PM PST 24
Peak memory 195248 kb
Host smart-52a0f91b-6f36-43a6-ac3b-3b9be10ca678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895379819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3895379819
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.73004373
Short name T772
Test name
Test status
Simulation time 499940169 ps
CPU time 1.71 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:37:39 PM PST 24
Peak memory 198036 kb
Host smart-e06b5781-cd4f-4ea2-ba8e-125d6472c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73004373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.73004373
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1770304925
Short name T599
Test name
Test status
Simulation time 184682738943 ps
CPU time 339.52 seconds
Started Feb 07 01:37:44 PM PST 24
Finished Feb 07 01:43:24 PM PST 24
Peak memory 199948 kb
Host smart-221e117f-c6b4-41f5-9b7f-33ff0f1d48c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770304925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1770304925
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2602048383
Short name T355
Test name
Test status
Simulation time 664918673763 ps
CPU time 789.21 seconds
Started Feb 07 01:37:44 PM PST 24
Finished Feb 07 01:50:54 PM PST 24
Peak memory 224940 kb
Host smart-f8d73317-8a74-47f3-b0b4-6e62ae0d8625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602048383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2602048383
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2782350261
Short name T1018
Test name
Test status
Simulation time 5977515310 ps
CPU time 1.42 seconds
Started Feb 07 01:37:36 PM PST 24
Finished Feb 07 01:37:38 PM PST 24
Peak memory 198968 kb
Host smart-1571cfd6-fca5-43cc-9581-07cbe13f0f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782350261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2782350261
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.793885667
Short name T394
Test name
Test status
Simulation time 84517530498 ps
CPU time 84.95 seconds
Started Feb 07 01:37:31 PM PST 24
Finished Feb 07 01:38:57 PM PST 24
Peak memory 199936 kb
Host smart-221abfe7-df05-4d42-be02-8e642055d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793885667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.793885667
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2936055901
Short name T520
Test name
Test status
Simulation time 49854285 ps
CPU time 0.6 seconds
Started Feb 07 01:37:45 PM PST 24
Finished Feb 07 01:37:46 PM PST 24
Peak memory 195340 kb
Host smart-19190aa5-5655-496b-8ce5-6e923b629d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936055901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2936055901
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2733046431
Short name T932
Test name
Test status
Simulation time 247455551115 ps
CPU time 85.48 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:39:06 PM PST 24
Peak memory 199588 kb
Host smart-d3ac579d-f164-48e3-bb05-33410ec32463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733046431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2733046431
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2665109025
Short name T845
Test name
Test status
Simulation time 199692502426 ps
CPU time 309.43 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:42:50 PM PST 24
Peak memory 199964 kb
Host smart-3cc7da51-8109-4815-9d64-709944853b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665109025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2665109025
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2155506278
Short name T936
Test name
Test status
Simulation time 152245747526 ps
CPU time 12.41 seconds
Started Feb 07 01:37:41 PM PST 24
Finished Feb 07 01:37:54 PM PST 24
Peak memory 199972 kb
Host smart-9831b723-67c1-4f1a-bd4b-21167a2a1476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155506278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2155506278
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3422958919
Short name T26
Test name
Test status
Simulation time 373070745575 ps
CPU time 444.85 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:45:06 PM PST 24
Peak memory 199888 kb
Host smart-7f716413-53fb-4249-8a09-94f638d2db19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422958919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3422958919
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.300354495
Short name T959
Test name
Test status
Simulation time 129197819439 ps
CPU time 210.36 seconds
Started Feb 07 01:37:42 PM PST 24
Finished Feb 07 01:41:13 PM PST 24
Peak memory 199932 kb
Host smart-8d2297e6-890c-4a85-a565-1e1f4e75725d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300354495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.300354495
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.518440403
Short name T489
Test name
Test status
Simulation time 1039873629 ps
CPU time 1.75 seconds
Started Feb 07 01:37:44 PM PST 24
Finished Feb 07 01:37:46 PM PST 24
Peak memory 195340 kb
Host smart-37fbc36b-27ff-4e16-ad42-e14def5c9f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518440403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.518440403
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.490528745
Short name T950
Test name
Test status
Simulation time 73772194337 ps
CPU time 133.83 seconds
Started Feb 07 01:37:39 PM PST 24
Finished Feb 07 01:39:54 PM PST 24
Peak memory 197660 kb
Host smart-5b880f84-a1e2-4cdb-892e-9afe9be45972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490528745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.490528745
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4201529379
Short name T111
Test name
Test status
Simulation time 12096620458 ps
CPU time 139.47 seconds
Started Feb 07 01:37:44 PM PST 24
Finished Feb 07 01:40:05 PM PST 24
Peak memory 199904 kb
Host smart-02bc8ef0-9696-47b5-841e-7b854c9eae13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201529379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4201529379
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2100656373
Short name T595
Test name
Test status
Simulation time 1539349260 ps
CPU time 4.1 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:37:45 PM PST 24
Peak memory 197916 kb
Host smart-ffcdb60d-d9d2-49d3-9e44-5f797a1b4b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100656373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2100656373
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2646196452
Short name T378
Test name
Test status
Simulation time 93330049374 ps
CPU time 28.31 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:38:09 PM PST 24
Peak memory 199936 kb
Host smart-9af70886-5e98-48d7-9de6-e928dee66012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646196452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2646196452
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2993258614
Short name T735
Test name
Test status
Simulation time 1917139242 ps
CPU time 1.31 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:37:42 PM PST 24
Peak memory 195092 kb
Host smart-2a825a6e-b176-4ea8-a1e9-febe9e2dae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993258614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2993258614
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.909311159
Short name T990
Test name
Test status
Simulation time 707117107 ps
CPU time 4.27 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:37:45 PM PST 24
Peak memory 197936 kb
Host smart-7388fe2c-f86b-46f4-841e-525a29a5bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909311159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.909311159
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2453744633
Short name T1145
Test name
Test status
Simulation time 272813409678 ps
CPU time 995.38 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:54:16 PM PST 24
Peak memory 199988 kb
Host smart-fd497868-e070-4da7-8113-30f09c83a068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453744633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2453744633
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1679984394
Short name T64
Test name
Test status
Simulation time 113542721631 ps
CPU time 506.39 seconds
Started Feb 07 01:37:40 PM PST 24
Finished Feb 07 01:46:07 PM PST 24
Peak memory 216664 kb
Host smart-8ddc8ea9-e00f-49eb-88b1-ffc92723aa20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679984394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1679984394
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.60667774
Short name T987
Test name
Test status
Simulation time 842466714 ps
CPU time 2.81 seconds
Started Feb 07 01:37:39 PM PST 24
Finished Feb 07 01:37:43 PM PST 24
Peak memory 199108 kb
Host smart-1ca98d88-b228-4353-be38-d395f6394524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60667774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.60667774
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1652071769
Short name T738
Test name
Test status
Simulation time 97155568342 ps
CPU time 17.56 seconds
Started Feb 07 01:37:38 PM PST 24
Finished Feb 07 01:37:57 PM PST 24
Peak memory 199972 kb
Host smart-545ce9c6-48e8-4ab2-b21a-48238e2ca668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652071769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1652071769
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1698625545
Short name T92
Test name
Test status
Simulation time 15006866 ps
CPU time 0.56 seconds
Started Feb 07 01:37:51 PM PST 24
Finished Feb 07 01:37:52 PM PST 24
Peak memory 195304 kb
Host smart-3762fd88-7715-4b16-bfe7-edfa9047e7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698625545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1698625545
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.330568733
Short name T881
Test name
Test status
Simulation time 229797690045 ps
CPU time 362.41 seconds
Started Feb 07 01:37:43 PM PST 24
Finished Feb 07 01:43:46 PM PST 24
Peak memory 199296 kb
Host smart-b07ad0e8-1dea-49ad-b2cd-b268c669315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330568733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.330568733
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3362430004
Short name T653
Test name
Test status
Simulation time 109920469833 ps
CPU time 86.05 seconds
Started Feb 07 01:37:49 PM PST 24
Finished Feb 07 01:39:15 PM PST 24
Peak memory 198952 kb
Host smart-0adcd73e-521e-4154-a43e-a3e3dd450a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362430004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3362430004
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2930608440
Short name T229
Test name
Test status
Simulation time 509856580093 ps
CPU time 100.09 seconds
Started Feb 07 01:37:50 PM PST 24
Finished Feb 07 01:39:31 PM PST 24
Peak memory 199988 kb
Host smart-8fd1d758-5c1a-4c7b-aa85-7e9c323e3c21
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930608440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2930608440
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3425973108
Short name T296
Test name
Test status
Simulation time 110572948829 ps
CPU time 746.1 seconds
Started Feb 07 01:37:47 PM PST 24
Finished Feb 07 01:50:14 PM PST 24
Peak memory 199864 kb
Host smart-1a02557a-bcb9-4946-a45b-e0a465f5cf4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425973108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3425973108
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1433308064
Short name T105
Test name
Test status
Simulation time 2316925799 ps
CPU time 4.37 seconds
Started Feb 07 01:37:51 PM PST 24
Finished Feb 07 01:37:56 PM PST 24
Peak memory 198040 kb
Host smart-60a766ec-c2da-45a4-b339-25ac6b1583b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433308064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1433308064
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3772296249
Short name T625
Test name
Test status
Simulation time 113841468404 ps
CPU time 44.53 seconds
Started Feb 07 01:37:55 PM PST 24
Finished Feb 07 01:38:40 PM PST 24
Peak memory 199688 kb
Host smart-bcf20961-000a-401a-be84-22fc6a7f6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772296249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3772296249
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3952126518
Short name T549
Test name
Test status
Simulation time 7807187314 ps
CPU time 494.42 seconds
Started Feb 07 01:37:57 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 199916 kb
Host smart-d0e415e7-60ed-4181-9236-67b1a2a43e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952126518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3952126518
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.744516425
Short name T539
Test name
Test status
Simulation time 115847910 ps
CPU time 0.72 seconds
Started Feb 07 01:37:52 PM PST 24
Finished Feb 07 01:37:53 PM PST 24
Peak memory 195324 kb
Host smart-37359ff6-0722-4809-9f35-936520249833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744516425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.744516425
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3097267814
Short name T1173
Test name
Test status
Simulation time 7215958619 ps
CPU time 15.74 seconds
Started Feb 07 01:37:53 PM PST 24
Finished Feb 07 01:38:09 PM PST 24
Peak memory 199928 kb
Host smart-2e685a80-17b0-40c1-aa5a-fcf4b8b0f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097267814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3097267814
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1838811992
Short name T1193
Test name
Test status
Simulation time 35078401108 ps
CPU time 61.64 seconds
Started Feb 07 01:37:54 PM PST 24
Finished Feb 07 01:38:56 PM PST 24
Peak memory 195688 kb
Host smart-d45f068b-a02b-4bc6-bfb6-1e7bc4657b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838811992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1838811992
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2232762155
Short name T793
Test name
Test status
Simulation time 502585951 ps
CPU time 3.38 seconds
Started Feb 07 01:37:41 PM PST 24
Finished Feb 07 01:37:45 PM PST 24
Peak memory 199192 kb
Host smart-fa350e31-ad01-4490-8d83-0fbf76a5dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232762155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2232762155
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.856622010
Short name T1032
Test name
Test status
Simulation time 76209841978 ps
CPU time 138.22 seconds
Started Feb 07 01:37:51 PM PST 24
Finished Feb 07 01:40:10 PM PST 24
Peak memory 199984 kb
Host smart-63c67e0d-506d-4626-bb56-177dcfc01741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856622010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.856622010
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1098305924
Short name T1094
Test name
Test status
Simulation time 37283393397 ps
CPU time 376.46 seconds
Started Feb 07 01:37:48 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 214308 kb
Host smart-84f84e31-32aa-46b6-9a57-c09fa31f7055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098305924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1098305924
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1069275375
Short name T722
Test name
Test status
Simulation time 10048629267 ps
CPU time 1.91 seconds
Started Feb 07 01:37:55 PM PST 24
Finished Feb 07 01:37:57 PM PST 24
Peak memory 198760 kb
Host smart-e131430c-9d98-42a4-ad3b-7538bbd30648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069275375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1069275375
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.115089925
Short name T807
Test name
Test status
Simulation time 136974502616 ps
CPU time 212.19 seconds
Started Feb 07 01:37:43 PM PST 24
Finished Feb 07 01:41:16 PM PST 24
Peak memory 200012 kb
Host smart-630ac556-b064-4aaa-97c4-eebe499dc021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115089925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.115089925
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.481083493
Short name T757
Test name
Test status
Simulation time 21955197 ps
CPU time 0.53 seconds
Started Feb 07 01:31:52 PM PST 24
Finished Feb 07 01:31:53 PM PST 24
Peak memory 195336 kb
Host smart-ba5ac970-77a2-473e-a9cb-732918f6bf56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481083493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.481083493
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.255306765
Short name T666
Test name
Test status
Simulation time 135562229655 ps
CPU time 217.36 seconds
Started Feb 07 01:31:30 PM PST 24
Finished Feb 07 01:35:08 PM PST 24
Peak memory 199816 kb
Host smart-e120ac0e-c2e1-4ac4-8201-487ac4d59c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255306765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.255306765
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_intr.1515920112
Short name T563
Test name
Test status
Simulation time 1278013548319 ps
CPU time 1020.23 seconds
Started Feb 07 01:31:42 PM PST 24
Finished Feb 07 01:48:43 PM PST 24
Peak memory 199936 kb
Host smart-eb2f0b38-2134-4bdc-9acb-817289ca6b67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515920112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1515920112
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1123368383
Short name T768
Test name
Test status
Simulation time 267212163873 ps
CPU time 141.93 seconds
Started Feb 07 01:31:42 PM PST 24
Finished Feb 07 01:34:05 PM PST 24
Peak memory 199872 kb
Host smart-5a239b3f-67de-40fe-8ac6-d8d0c89d9aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123368383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1123368383
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1050298295
Short name T670
Test name
Test status
Simulation time 2458140538 ps
CPU time 2.81 seconds
Started Feb 07 01:31:42 PM PST 24
Finished Feb 07 01:31:46 PM PST 24
Peak memory 198340 kb
Host smart-0ba11abb-ab2f-400c-a3f9-a1229cc9cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050298295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1050298295
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3526192171
Short name T16
Test name
Test status
Simulation time 127490841540 ps
CPU time 94.42 seconds
Started Feb 07 01:31:41 PM PST 24
Finished Feb 07 01:33:16 PM PST 24
Peak memory 208356 kb
Host smart-e7a064dc-ea3d-4a26-a724-d5a9e78d6f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526192171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3526192171
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2888177049
Short name T1228
Test name
Test status
Simulation time 20766959200 ps
CPU time 1160.85 seconds
Started Feb 07 01:31:45 PM PST 24
Finished Feb 07 01:51:06 PM PST 24
Peak memory 199928 kb
Host smart-1dee0a8e-887c-4dc7-870d-d6b653e02844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888177049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2888177049
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1021795136
Short name T626
Test name
Test status
Simulation time 4018855984 ps
CPU time 10.88 seconds
Started Feb 07 01:31:40 PM PST 24
Finished Feb 07 01:31:52 PM PST 24
Peak memory 198516 kb
Host smart-6f9d7cd3-c3bb-4537-89b6-eb9115770717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021795136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1021795136
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2373504226
Short name T749
Test name
Test status
Simulation time 105225807274 ps
CPU time 165.62 seconds
Started Feb 07 01:31:40 PM PST 24
Finished Feb 07 01:34:26 PM PST 24
Peak memory 199916 kb
Host smart-4d46ce0e-f26a-4070-892a-d78e81b16b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373504226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2373504226
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4010491044
Short name T422
Test name
Test status
Simulation time 34324169978 ps
CPU time 11.96 seconds
Started Feb 07 01:31:45 PM PST 24
Finished Feb 07 01:31:58 PM PST 24
Peak memory 195700 kb
Host smart-1f17e6c9-b6f7-476f-86aa-998d7e7fa24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010491044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4010491044
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.968842284
Short name T424
Test name
Test status
Simulation time 627243236 ps
CPU time 2.5 seconds
Started Feb 07 01:31:29 PM PST 24
Finished Feb 07 01:31:32 PM PST 24
Peak memory 198184 kb
Host smart-98719cce-6422-4f8c-91bf-538f06222ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968842284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.968842284
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.820557912
Short name T62
Test name
Test status
Simulation time 158572780449 ps
CPU time 736.9 seconds
Started Feb 07 01:31:42 PM PST 24
Finished Feb 07 01:44:00 PM PST 24
Peak memory 224896 kb
Host smart-893bd6eb-a40a-4ce0-9906-f0963123c40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820557912 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.820557912
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1870723834
Short name T1058
Test name
Test status
Simulation time 1795830796 ps
CPU time 1.87 seconds
Started Feb 07 01:31:40 PM PST 24
Finished Feb 07 01:31:42 PM PST 24
Peak memory 198012 kb
Host smart-1e00c944-8507-4ed9-a47e-a2f027285b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870723834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1870723834
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1694424749
Short name T972
Test name
Test status
Simulation time 10769013412 ps
CPU time 9.37 seconds
Started Feb 07 01:31:32 PM PST 24
Finished Feb 07 01:31:42 PM PST 24
Peak memory 198844 kb
Host smart-5edc97df-211e-41f0-a3df-8719af01d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694424749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1694424749
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2973359523
Short name T235
Test name
Test status
Simulation time 29194814155 ps
CPU time 20.88 seconds
Started Feb 07 01:37:51 PM PST 24
Finished Feb 07 01:38:13 PM PST 24
Peak memory 200060 kb
Host smart-623a582b-8b49-48c6-b5c2-7ec93022acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973359523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2973359523
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2125670600
Short name T70
Test name
Test status
Simulation time 103702014505 ps
CPU time 284.87 seconds
Started Feb 07 01:37:49 PM PST 24
Finished Feb 07 01:42:34 PM PST 24
Peak memory 216420 kb
Host smart-b6091cde-a8c3-463c-9553-14c5942f7abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125670600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2125670600
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1260767813
Short name T545
Test name
Test status
Simulation time 33611455699 ps
CPU time 53.12 seconds
Started Feb 07 01:37:54 PM PST 24
Finished Feb 07 01:38:48 PM PST 24
Peak memory 199744 kb
Host smart-23b30d94-ee96-41b4-a946-ea46f3040f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260767813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1260767813
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3907012309
Short name T747
Test name
Test status
Simulation time 49034710275 ps
CPU time 301.51 seconds
Started Feb 07 01:37:50 PM PST 24
Finished Feb 07 01:42:52 PM PST 24
Peak memory 215888 kb
Host smart-20acb211-1922-4140-b689-61aaea42ad50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907012309 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3907012309
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.564714216
Short name T244
Test name
Test status
Simulation time 156224045536 ps
CPU time 254.78 seconds
Started Feb 07 01:37:53 PM PST 24
Finished Feb 07 01:42:08 PM PST 24
Peak memory 200012 kb
Host smart-8cfbb788-34e3-4fcd-ae3d-4620027e5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564714216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.564714216
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2730281416
Short name T813
Test name
Test status
Simulation time 26184381531 ps
CPU time 272.17 seconds
Started Feb 07 01:37:56 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 212628 kb
Host smart-3c014313-db55-4f22-b356-22f0fef24662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730281416 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2730281416
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1506277585
Short name T169
Test name
Test status
Simulation time 113585640852 ps
CPU time 174.34 seconds
Started Feb 07 01:37:51 PM PST 24
Finished Feb 07 01:40:45 PM PST 24
Peak memory 199936 kb
Host smart-46c08dc8-5cdf-4030-99d2-096e9c791f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506277585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1506277585
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3313750805
Short name T138
Test name
Test status
Simulation time 96049527268 ps
CPU time 747.08 seconds
Started Feb 07 01:37:52 PM PST 24
Finished Feb 07 01:50:20 PM PST 24
Peak memory 216744 kb
Host smart-bce519e5-6651-49f2-94f0-e83a2a47af2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313750805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3313750805
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3592294919
Short name T170
Test name
Test status
Simulation time 140422422481 ps
CPU time 53.95 seconds
Started Feb 07 01:37:54 PM PST 24
Finished Feb 07 01:38:49 PM PST 24
Peak memory 199980 kb
Host smart-a195dc1e-46f8-4405-b3da-57fbeeb0af1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592294919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3592294919
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2026510780
Short name T164
Test name
Test status
Simulation time 40549021252 ps
CPU time 42.02 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:38:53 PM PST 24
Peak memory 199976 kb
Host smart-4bd65871-dcb3-48f5-9517-2d56b474a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026510780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2026510780
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3349313942
Short name T880
Test name
Test status
Simulation time 74567813095 ps
CPU time 1086.65 seconds
Started Feb 07 01:38:17 PM PST 24
Finished Feb 07 01:56:24 PM PST 24
Peak memory 226324 kb
Host smart-72f67ff1-534a-4b61-a82e-2b3779eb0c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349313942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3349313942
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1831058419
Short name T1102
Test name
Test status
Simulation time 89658458726 ps
CPU time 26.62 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:38:38 PM PST 24
Peak memory 199172 kb
Host smart-59e6fb2c-c35f-4388-b878-cbc37379bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831058419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1831058419
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3498422313
Short name T1114
Test name
Test status
Simulation time 25172090855 ps
CPU time 273.93 seconds
Started Feb 07 01:38:12 PM PST 24
Finished Feb 07 01:42:47 PM PST 24
Peak memory 215660 kb
Host smart-a0e05c03-f758-4145-84b2-b00d84345893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498422313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3498422313
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1160908125
Short name T1115
Test name
Test status
Simulation time 40717370885 ps
CPU time 71.53 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:39:23 PM PST 24
Peak memory 199920 kb
Host smart-f85922a2-5005-431f-97d4-7a2f674d8b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160908125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1160908125
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.907015144
Short name T1167
Test name
Test status
Simulation time 222430904985 ps
CPU time 1588.89 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 02:04:51 PM PST 24
Peak memory 223808 kb
Host smart-431f9ba8-1971-44b6-b42b-b905ce23ca2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907015144 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.907015144
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.521679124
Short name T212
Test name
Test status
Simulation time 130316924398 ps
CPU time 99.51 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:39:51 PM PST 24
Peak memory 199972 kb
Host smart-902fb69a-bc56-464d-aa6e-b3be6c86555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521679124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.521679124
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3508873329
Short name T1120
Test name
Test status
Simulation time 115166292399 ps
CPU time 279.1 seconds
Started Feb 07 01:38:19 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 214724 kb
Host smart-15cd018f-4527-4d98-9a41-c785239e4c98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508873329 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3508873329
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2789908139
Short name T127
Test name
Test status
Simulation time 32982326939 ps
CPU time 13.25 seconds
Started Feb 07 01:38:12 PM PST 24
Finished Feb 07 01:38:26 PM PST 24
Peak memory 199984 kb
Host smart-5c6521fa-e1e8-467a-a05f-700218665976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789908139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2789908139
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1700100527
Short name T201
Test name
Test status
Simulation time 242230118290 ps
CPU time 734.3 seconds
Started Feb 07 01:38:21 PM PST 24
Finished Feb 07 01:50:36 PM PST 24
Peak memory 230076 kb
Host smart-e7fff74b-7bd7-43b1-876c-93447c8f3a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700100527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1700100527
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.713000200
Short name T873
Test name
Test status
Simulation time 25456494 ps
CPU time 0.53 seconds
Started Feb 07 01:32:07 PM PST 24
Finished Feb 07 01:32:15 PM PST 24
Peak memory 195216 kb
Host smart-4534c22b-321e-4f82-b752-81083640a464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713000200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.713000200
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2253677265
Short name T1128
Test name
Test status
Simulation time 21352805705 ps
CPU time 34.9 seconds
Started Feb 07 01:31:51 PM PST 24
Finished Feb 07 01:32:27 PM PST 24
Peak memory 199976 kb
Host smart-e1d89f83-40fe-40ab-aaa1-00ec98fa7b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253677265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2253677265
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.206572802
Short name T98
Test name
Test status
Simulation time 18874139160 ps
CPU time 14.88 seconds
Started Feb 07 01:31:51 PM PST 24
Finished Feb 07 01:32:06 PM PST 24
Peak memory 199660 kb
Host smart-7e394f0a-cb74-40ad-bdd8-925951272e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206572802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.206572802
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3665489583
Short name T429
Test name
Test status
Simulation time 507158864823 ps
CPU time 716.96 seconds
Started Feb 07 01:31:59 PM PST 24
Finished Feb 07 01:43:56 PM PST 24
Peak memory 199980 kb
Host smart-b4f4bcf2-b3aa-4e5b-be48-06cca34990c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665489583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3665489583
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.15519898
Short name T1067
Test name
Test status
Simulation time 80931955960 ps
CPU time 359.38 seconds
Started Feb 07 01:32:12 PM PST 24
Finished Feb 07 01:38:16 PM PST 24
Peak memory 199988 kb
Host smart-6323dae6-1002-4554-9d67-2670eb95ddac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15519898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.15519898
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2336978587
Short name T931
Test name
Test status
Simulation time 4274648561 ps
CPU time 7.61 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:32:22 PM PST 24
Peak memory 195656 kb
Host smart-6a2af57b-fabe-4d3e-88a0-4a3bb1aa3d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336978587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2336978587
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.525930960
Short name T582
Test name
Test status
Simulation time 26468871418 ps
CPU time 19.2 seconds
Started Feb 07 01:31:50 PM PST 24
Finished Feb 07 01:32:10 PM PST 24
Peak memory 198188 kb
Host smart-fdbdd7cc-91d1-418b-a773-b7d07ebacad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525930960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.525930960
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1560544593
Short name T706
Test name
Test status
Simulation time 18918439896 ps
CPU time 972.7 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:48:27 PM PST 24
Peak memory 199856 kb
Host smart-de433381-6342-47a5-84fc-fd9b4791dbf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560544593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1560544593
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1236828583
Short name T1085
Test name
Test status
Simulation time 292032417353 ps
CPU time 247.15 seconds
Started Feb 07 01:31:51 PM PST 24
Finished Feb 07 01:35:59 PM PST 24
Peak memory 198784 kb
Host smart-809d9ecf-0b14-4820-97c0-4f8ea1adc05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236828583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1236828583
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2748849889
Short name T1038
Test name
Test status
Simulation time 6036971221 ps
CPU time 9.8 seconds
Started Feb 07 01:31:51 PM PST 24
Finished Feb 07 01:32:01 PM PST 24
Peak memory 195720 kb
Host smart-c1abba5d-40f2-42be-8599-9347329a73cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748849889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2748849889
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4249212483
Short name T1011
Test name
Test status
Simulation time 278080666 ps
CPU time 1.07 seconds
Started Feb 07 01:31:50 PM PST 24
Finished Feb 07 01:31:51 PM PST 24
Peak memory 197672 kb
Host smart-108024fd-ce4f-4302-885f-c1abc02f0ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249212483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4249212483
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1221108752
Short name T1106
Test name
Test status
Simulation time 207953504415 ps
CPU time 913.84 seconds
Started Feb 07 01:32:09 PM PST 24
Finished Feb 07 01:47:29 PM PST 24
Peak memory 215952 kb
Host smart-5256f5d0-88dc-470e-95c9-3bad1a55e1bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221108752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1221108752
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3351819879
Short name T913
Test name
Test status
Simulation time 87218152832 ps
CPU time 1036.03 seconds
Started Feb 07 01:32:09 PM PST 24
Finished Feb 07 01:49:31 PM PST 24
Peak memory 226808 kb
Host smart-29b7cd71-4687-4be7-b258-ddbbd36a6470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351819879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3351819879
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3018182236
Short name T888
Test name
Test status
Simulation time 1847334223 ps
CPU time 1.65 seconds
Started Feb 07 01:32:20 PM PST 24
Finished Feb 07 01:32:26 PM PST 24
Peak memory 198032 kb
Host smart-a2b1fe3a-906c-482a-a788-8f910400df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018182236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3018182236
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.975645003
Short name T657
Test name
Test status
Simulation time 72732302672 ps
CPU time 127.24 seconds
Started Feb 07 01:31:52 PM PST 24
Finished Feb 07 01:34:00 PM PST 24
Peak memory 199968 kb
Host smart-7da10f85-4808-4375-9ce7-d7322fd53cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975645003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.975645003
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.666790893
Short name T605
Test name
Test status
Simulation time 28641747664 ps
CPU time 41.6 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:38:53 PM PST 24
Peak memory 199936 kb
Host smart-597d3b97-8fc0-49a5-addb-33f14543ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666790893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.666790893
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3619748234
Short name T61
Test name
Test status
Simulation time 82404969456 ps
CPU time 1561.41 seconds
Started Feb 07 01:38:10 PM PST 24
Finished Feb 07 02:04:12 PM PST 24
Peak memory 224728 kb
Host smart-0294381d-723d-4ed5-8a03-81ed545c1eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619748234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3619748234
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2355088110
Short name T1002
Test name
Test status
Simulation time 20827745075 ps
CPU time 33.37 seconds
Started Feb 07 01:38:10 PM PST 24
Finished Feb 07 01:38:44 PM PST 24
Peak memory 199944 kb
Host smart-7ddbcbef-9bdc-4a77-910f-2a43b6f0e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355088110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2355088110
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1388465613
Short name T198
Test name
Test status
Simulation time 56271973068 ps
CPU time 1140.88 seconds
Started Feb 07 01:38:17 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 216492 kb
Host smart-ef54730b-03d7-4099-af32-3f431e70810e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388465613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1388465613
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3419967375
Short name T233
Test name
Test status
Simulation time 52154304957 ps
CPU time 111.1 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:40:02 PM PST 24
Peak memory 199992 kb
Host smart-9bdd5696-9cc6-4236-8171-130fac53a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419967375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3419967375
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4138628560
Short name T690
Test name
Test status
Simulation time 24259397662 ps
CPU time 290.73 seconds
Started Feb 07 01:38:17 PM PST 24
Finished Feb 07 01:43:08 PM PST 24
Peak memory 210612 kb
Host smart-036f23ba-aa43-4a31-84fa-8b0e7bcc9dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138628560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4138628560
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.471282828
Short name T1069
Test name
Test status
Simulation time 124236036433 ps
CPU time 31.6 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:39:03 PM PST 24
Peak memory 199964 kb
Host smart-d5eeb427-4ed8-4e4e-bf2d-1e628c4950b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471282828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.471282828
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1348487611
Short name T783
Test name
Test status
Simulation time 62307562585 ps
CPU time 367.71 seconds
Started Feb 07 01:38:17 PM PST 24
Finished Feb 07 01:44:25 PM PST 24
Peak memory 216704 kb
Host smart-e253ed26-a339-4347-bae3-6ac50651128f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348487611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1348487611
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1927316657
Short name T245
Test name
Test status
Simulation time 34318932635 ps
CPU time 57.16 seconds
Started Feb 07 01:38:21 PM PST 24
Finished Feb 07 01:39:19 PM PST 24
Peak memory 199852 kb
Host smart-cf9daa4e-40c8-4163-b8d3-e0cb9e6ec455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927316657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1927316657
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1462795674
Short name T437
Test name
Test status
Simulation time 130299120376 ps
CPU time 677.86 seconds
Started Feb 07 01:38:21 PM PST 24
Finished Feb 07 01:49:40 PM PST 24
Peak memory 210612 kb
Host smart-0fb19f88-2505-46f7-8b8e-0dd7dec72aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462795674 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1462795674
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2282901847
Short name T130
Test name
Test status
Simulation time 156939253714 ps
CPU time 37.02 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:38:49 PM PST 24
Peak memory 199876 kb
Host smart-51782e17-be06-4b98-8acf-f99ee7dfb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282901847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2282901847
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1518455766
Short name T322
Test name
Test status
Simulation time 310710944953 ps
CPU time 1004.66 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 01:55:06 PM PST 24
Peak memory 226588 kb
Host smart-128c378c-0ae5-4690-befb-36a5e0eddc75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518455766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1518455766
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2345764611
Short name T831
Test name
Test status
Simulation time 74533911949 ps
CPU time 419.29 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 01:45:20 PM PST 24
Peak memory 215444 kb
Host smart-50047bf1-8e69-44a4-a505-93d1f784afe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345764611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2345764611
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3191327542
Short name T311
Test name
Test status
Simulation time 154408812002 ps
CPU time 167.29 seconds
Started Feb 07 01:38:11 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 199964 kb
Host smart-99eff272-6e82-4b5b-a6a8-9fd0897a459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191327542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3191327542
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3472489201
Short name T220
Test name
Test status
Simulation time 61519525281 ps
CPU time 570.09 seconds
Started Feb 07 01:38:17 PM PST 24
Finished Feb 07 01:47:48 PM PST 24
Peak memory 216388 kb
Host smart-08e970cc-ccbf-45a2-b409-9924fa346e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472489201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3472489201
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.979211583
Short name T664
Test name
Test status
Simulation time 14088951 ps
CPU time 0.55 seconds
Started Feb 07 01:32:11 PM PST 24
Finished Feb 07 01:32:17 PM PST 24
Peak memory 194424 kb
Host smart-71bcb260-1299-4c84-91b7-7ac1e329a6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979211583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.979211583
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2899346530
Short name T736
Test name
Test status
Simulation time 103128427699 ps
CPU time 84.92 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:33:40 PM PST 24
Peak memory 199700 kb
Host smart-d5d0ab4d-be08-47d2-913e-8609e6ba4234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899346530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2899346530
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1428864381
Short name T898
Test name
Test status
Simulation time 14718643719 ps
CPU time 22.2 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:32:37 PM PST 24
Peak memory 199072 kb
Host smart-194db41b-5625-4052-a1de-045a04feca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428864381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1428864381
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3636053873
Short name T243
Test name
Test status
Simulation time 44401982225 ps
CPU time 32.29 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:32:47 PM PST 24
Peak memory 199960 kb
Host smart-c7cd7575-8e3e-4de4-a2fa-d6858c6c68d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636053873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3636053873
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1691860709
Short name T1230
Test name
Test status
Simulation time 34348823266 ps
CPU time 97.37 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:33:52 PM PST 24
Peak memory 199908 kb
Host smart-aa3df6f0-026e-46a8-bf0c-902d8fce157b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691860709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1691860709
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2578384819
Short name T994
Test name
Test status
Simulation time 55331267008 ps
CPU time 106.66 seconds
Started Feb 07 01:32:10 PM PST 24
Finished Feb 07 01:34:02 PM PST 24
Peak memory 199928 kb
Host smart-5e6bff99-c6fb-4f71-a600-93b997e844e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578384819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2578384819
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3128985675
Short name T1221
Test name
Test status
Simulation time 4335380288 ps
CPU time 4.58 seconds
Started Feb 07 01:32:17 PM PST 24
Finished Feb 07 01:32:28 PM PST 24
Peak memory 197964 kb
Host smart-68c7a9b9-c592-4aa7-aa7e-0c1fd90fcda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128985675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3128985675
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1947305059
Short name T1046
Test name
Test status
Simulation time 10226213550 ps
CPU time 17.61 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:32:32 PM PST 24
Peak memory 194632 kb
Host smart-de062d10-f2c8-4254-b7ee-9951f5523cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947305059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1947305059
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.713876505
Short name T410
Test name
Test status
Simulation time 15449736726 ps
CPU time 110.6 seconds
Started Feb 07 01:32:10 PM PST 24
Finished Feb 07 01:34:07 PM PST 24
Peak memory 199940 kb
Host smart-70a2db50-89dd-47d4-aef1-bc2c338e4c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713876505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.713876505
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3373580013
Short name T750
Test name
Test status
Simulation time 2321120114 ps
CPU time 16.07 seconds
Started Feb 07 01:32:09 PM PST 24
Finished Feb 07 01:32:31 PM PST 24
Peak memory 198164 kb
Host smart-b1143939-9ef0-4700-9962-a2c4a019b1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373580013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3373580013
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3032322431
Short name T991
Test name
Test status
Simulation time 30935874145 ps
CPU time 34.75 seconds
Started Feb 07 01:32:14 PM PST 24
Finished Feb 07 01:32:51 PM PST 24
Peak memory 198888 kb
Host smart-35ff4e2d-3954-4acb-807f-70e1151491c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032322431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3032322431
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1207686152
Short name T617
Test name
Test status
Simulation time 4342520186 ps
CPU time 2.2 seconds
Started Feb 07 01:32:11 PM PST 24
Finished Feb 07 01:32:19 PM PST 24
Peak memory 195692 kb
Host smart-fe24761d-53d3-4e74-a8f2-87557f92d113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207686152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1207686152
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.292531662
Short name T623
Test name
Test status
Simulation time 6049294895 ps
CPU time 21.47 seconds
Started Feb 07 01:32:09 PM PST 24
Finished Feb 07 01:32:36 PM PST 24
Peak memory 198640 kb
Host smart-8c6bead2-c4d2-4f7f-b84f-f7b79bfb7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292531662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.292531662
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1096831944
Short name T876
Test name
Test status
Simulation time 260404561634 ps
CPU time 1020.52 seconds
Started Feb 07 01:32:14 PM PST 24
Finished Feb 07 01:49:19 PM PST 24
Peak memory 200152 kb
Host smart-7d3c6c23-ed7e-43fa-9a60-edb29f9362a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096831944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1096831944
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3165633881
Short name T581
Test name
Test status
Simulation time 25849788504 ps
CPU time 164.71 seconds
Started Feb 07 01:32:17 PM PST 24
Finished Feb 07 01:35:09 PM PST 24
Peak memory 215780 kb
Host smart-120fa9e9-eff2-44cd-9bb8-cdfa768ecacd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165633881 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3165633881
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.296097486
Short name T619
Test name
Test status
Simulation time 7442191999 ps
CPU time 14.55 seconds
Started Feb 07 01:32:09 PM PST 24
Finished Feb 07 01:32:29 PM PST 24
Peak memory 199300 kb
Host smart-49809c06-8658-49b4-950f-d067c28da211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296097486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.296097486
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.4239992472
Short name T712
Test name
Test status
Simulation time 122566633185 ps
CPU time 59.22 seconds
Started Feb 07 01:32:08 PM PST 24
Finished Feb 07 01:33:14 PM PST 24
Peak memory 200020 kb
Host smart-f5df9767-310c-4bfc-aa11-f6bfff3e9399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239992472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4239992472
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4128136733
Short name T1203
Test name
Test status
Simulation time 81255261614 ps
CPU time 191.4 seconds
Started Feb 07 01:38:20 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 199780 kb
Host smart-46b75315-e370-45d3-aaa2-1eef8e8002a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128136733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4128136733
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.731359282
Short name T1001
Test name
Test status
Simulation time 163971560436 ps
CPU time 492.33 seconds
Started Feb 07 01:38:18 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 212976 kb
Host smart-dd8a1542-4286-4a59-916f-1bffd54855b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731359282 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.731359282
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1214947919
Short name T256
Test name
Test status
Simulation time 120662669975 ps
CPU time 611.91 seconds
Started Feb 07 01:38:26 PM PST 24
Finished Feb 07 01:48:44 PM PST 24
Peak memory 224904 kb
Host smart-0355220c-e5ce-40f3-badb-14026f400369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214947919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1214947919
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3335920756
Short name T308
Test name
Test status
Simulation time 150233093583 ps
CPU time 379.83 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:44:52 PM PST 24
Peak memory 199940 kb
Host smart-bcca0e60-3afb-415e-85ba-90fa7feb1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335920756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3335920756
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3839435888
Short name T948
Test name
Test status
Simulation time 233499238123 ps
CPU time 110.42 seconds
Started Feb 07 01:38:22 PM PST 24
Finished Feb 07 01:40:17 PM PST 24
Peak memory 216748 kb
Host smart-b93319c6-35ea-4391-8cf3-0939a795f5a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839435888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3839435888
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.776134643
Short name T246
Test name
Test status
Simulation time 75596716606 ps
CPU time 64.4 seconds
Started Feb 07 01:38:23 PM PST 24
Finished Feb 07 01:39:36 PM PST 24
Peak memory 199960 kb
Host smart-85feae67-33b3-4c08-bba6-ec37e4e851ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776134643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.776134643
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.924204111
Short name T637
Test name
Test status
Simulation time 176370955301 ps
CPU time 353.03 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:44:34 PM PST 24
Peak memory 216724 kb
Host smart-7799389c-b6a0-4846-976c-957def1b582c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924204111 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.924204111
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2902493309
Short name T850
Test name
Test status
Simulation time 49903780624 ps
CPU time 46.36 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:39:18 PM PST 24
Peak memory 199864 kb
Host smart-684ac619-878c-4ebd-9e1e-57a4e827db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902493309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2902493309
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.927437332
Short name T561
Test name
Test status
Simulation time 26006062085 ps
CPU time 8.11 seconds
Started Feb 07 01:38:21 PM PST 24
Finished Feb 07 01:38:30 PM PST 24
Peak memory 199792 kb
Host smart-12a1a2a6-7bc0-4c6a-ba9a-0483a5bd25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927437332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.927437332
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3159812730
Short name T954
Test name
Test status
Simulation time 115140414060 ps
CPU time 607.33 seconds
Started Feb 07 01:38:19 PM PST 24
Finished Feb 07 01:48:27 PM PST 24
Peak memory 216660 kb
Host smart-45233794-e0df-417d-9746-51b204e324ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159812730 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3159812730
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.632100541
Short name T1138
Test name
Test status
Simulation time 167692158003 ps
CPU time 72.61 seconds
Started Feb 07 01:38:22 PM PST 24
Finished Feb 07 01:39:40 PM PST 24
Peak memory 199960 kb
Host smart-5ec0eb8d-df25-412b-a1d9-a4c2292310f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632100541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.632100541
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2073030383
Short name T828
Test name
Test status
Simulation time 318416565053 ps
CPU time 1178.34 seconds
Started Feb 07 01:38:19 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 231760 kb
Host smart-3538339f-f3b1-4c8b-bd35-230d48dac2eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073030383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2073030383
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3303796878
Short name T363
Test name
Test status
Simulation time 102125138015 ps
CPU time 47.38 seconds
Started Feb 07 01:38:23 PM PST 24
Finished Feb 07 01:39:19 PM PST 24
Peak memory 199940 kb
Host smart-b6f577f7-20e7-4a8a-8f67-28483bd5b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303796878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3303796878
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1904903164
Short name T426
Test name
Test status
Simulation time 25561979596 ps
CPU time 237.96 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 215840 kb
Host smart-ab6b34a1-9915-4aaa-b4b4-e07b821abf2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904903164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1904903164
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.912900227
Short name T189
Test name
Test status
Simulation time 118948640661 ps
CPU time 74.41 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:39:46 PM PST 24
Peak memory 200000 kb
Host smart-c20ce10f-491e-4887-9e2f-25d061fb7fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912900227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.912900227
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4044616047
Short name T326
Test name
Test status
Simulation time 41641503900 ps
CPU time 738.38 seconds
Started Feb 07 01:38:26 PM PST 24
Finished Feb 07 01:50:50 PM PST 24
Peak memory 216336 kb
Host smart-90fc400b-0a8c-4e7b-ba85-849344462163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044616047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4044616047
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3500296355
Short name T325
Test name
Test status
Simulation time 46271901260 ps
CPU time 17.64 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:38:49 PM PST 24
Peak memory 199304 kb
Host smart-a786192b-41b2-48c4-a572-dc46d93dd4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500296355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3500296355
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4105807730
Short name T942
Test name
Test status
Simulation time 199116826617 ps
CPU time 630.58 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:49:02 PM PST 24
Peak memory 224932 kb
Host smart-0dce5101-b021-4c11-80d7-922795c17ea7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105807730 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4105807730
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4060062964
Short name T677
Test name
Test status
Simulation time 28029060 ps
CPU time 0.55 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:32:50 PM PST 24
Peak memory 195360 kb
Host smart-6aa86c5a-deaf-464d-ac3f-294b0bc9d3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060062964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4060062964
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1178167958
Short name T1139
Test name
Test status
Simulation time 140638686310 ps
CPU time 36.15 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:26 PM PST 24
Peak memory 199864 kb
Host smart-9c5d6b69-600c-4fb5-998e-1a2963768a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178167958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1178167958
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4218816603
Short name T354
Test name
Test status
Simulation time 32444970615 ps
CPU time 54.68 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:45 PM PST 24
Peak memory 199812 kb
Host smart-c57b02cf-494a-465e-af6b-dfdc745dc737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218816603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4218816603
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3884447321
Short name T1016
Test name
Test status
Simulation time 44604789489 ps
CPU time 45.81 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:33:35 PM PST 24
Peak memory 199896 kb
Host smart-e75424fc-8897-478d-83b7-c7a319d41ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884447321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3884447321
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1841694796
Short name T500
Test name
Test status
Simulation time 31730722571 ps
CPU time 4.69 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:32:54 PM PST 24
Peak memory 197748 kb
Host smart-8b4b2c8b-ab3c-415d-860b-fd45e4d12eb6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841694796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1841694796
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3836913968
Short name T1220
Test name
Test status
Simulation time 154207330519 ps
CPU time 368.11 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:39:00 PM PST 24
Peak memory 199916 kb
Host smart-1f1ad973-1f2f-47a7-949b-4139474c2e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836913968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3836913968
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3576312215
Short name T443
Test name
Test status
Simulation time 9570746782 ps
CPU time 11 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:01 PM PST 24
Peak memory 200004 kb
Host smart-db335c09-59fb-4ccc-96a0-93438df89f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576312215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3576312215
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3172103909
Short name T790
Test name
Test status
Simulation time 63604963664 ps
CPU time 105.31 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:34:35 PM PST 24
Peak memory 200200 kb
Host smart-4bdb2d0d-11d7-41f7-bdd3-3df6a2bb792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172103909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3172103909
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.786799118
Short name T874
Test name
Test status
Simulation time 28611251863 ps
CPU time 828.96 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 199904 kb
Host smart-ae53afcf-d921-46cb-83f4-c5a4b6a54f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786799118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.786799118
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.395103955
Short name T594
Test name
Test status
Simulation time 460159943 ps
CPU time 3.79 seconds
Started Feb 07 01:32:50 PM PST 24
Finished Feb 07 01:32:54 PM PST 24
Peak memory 197528 kb
Host smart-1312bd4d-3e9e-4e8b-8fe8-b74e225d2945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395103955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.395103955
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3470609739
Short name T713
Test name
Test status
Simulation time 26937452945 ps
CPU time 25.82 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:16 PM PST 24
Peak memory 200020 kb
Host smart-6401b59a-bf8a-43ec-9da4-001f27c91bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470609739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3470609739
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.507030442
Short name T1043
Test name
Test status
Simulation time 36874418300 ps
CPU time 18.27 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:08 PM PST 24
Peak memory 195388 kb
Host smart-1a053205-67f3-40a6-a3e4-26fdfc722cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507030442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.507030442
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3053720072
Short name T1155
Test name
Test status
Simulation time 312583563 ps
CPU time 0.98 seconds
Started Feb 07 01:32:17 PM PST 24
Finished Feb 07 01:32:25 PM PST 24
Peak memory 197728 kb
Host smart-b76c5f5b-6d42-4717-92a8-958d67a7fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053720072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3053720072
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1494771240
Short name T896
Test name
Test status
Simulation time 48248224989 ps
CPU time 536.43 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:41:48 PM PST 24
Peak memory 215932 kb
Host smart-4e47089e-09c2-44fe-b0dd-0fa42415c68c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494771240 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1494771240
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1838079334
Short name T919
Test name
Test status
Simulation time 1603999729 ps
CPU time 2.93 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:32:52 PM PST 24
Peak memory 199212 kb
Host smart-f088913f-372c-4545-96f4-b6115bddddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838079334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1838079334
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3531372764
Short name T967
Test name
Test status
Simulation time 262318227927 ps
CPU time 64.59 seconds
Started Feb 07 01:32:11 PM PST 24
Finished Feb 07 01:33:21 PM PST 24
Peak memory 199920 kb
Host smart-20cde23e-56f4-40ad-8521-a24de8465471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531372764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3531372764
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.713535250
Short name T930
Test name
Test status
Simulation time 17578996666 ps
CPU time 30.46 seconds
Started Feb 07 01:38:23 PM PST 24
Finished Feb 07 01:39:02 PM PST 24
Peak memory 199704 kb
Host smart-0b61fa6d-9e34-4203-adfd-041f3f55745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713535250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.713535250
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1725483304
Short name T438
Test name
Test status
Simulation time 20158365863 ps
CPU time 457.25 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 216092 kb
Host smart-b3909bb5-a6c9-495a-9039-d7e3bb42e43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725483304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1725483304
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1243778121
Short name T299
Test name
Test status
Simulation time 101313926440 ps
CPU time 49.45 seconds
Started Feb 07 01:38:19 PM PST 24
Finished Feb 07 01:39:10 PM PST 24
Peak memory 199952 kb
Host smart-ad2d2f06-c7a6-42a1-bb88-064207977f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243778121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1243778121
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1463670327
Short name T332
Test name
Test status
Simulation time 112971478158 ps
CPU time 524.24 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:47:16 PM PST 24
Peak memory 211808 kb
Host smart-87c6f04a-4f38-4090-b9bd-4eb6ff67cde0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463670327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1463670327
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.134015696
Short name T150
Test name
Test status
Simulation time 27368302179 ps
CPU time 51.02 seconds
Started Feb 07 01:38:28 PM PST 24
Finished Feb 07 01:39:25 PM PST 24
Peak memory 199992 kb
Host smart-a8edc8b0-8149-4482-b9dd-f025ba0d13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134015696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.134015696
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3034293346
Short name T922
Test name
Test status
Simulation time 392891135841 ps
CPU time 865.67 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:52:58 PM PST 24
Peak memory 224900 kb
Host smart-53c1ce60-d472-46cc-a37e-4a867ec9496a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034293346 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3034293346
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3630244615
Short name T765
Test name
Test status
Simulation time 121913953954 ps
CPU time 46.17 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:39:18 PM PST 24
Peak memory 199628 kb
Host smart-727dc3e7-0b7a-444e-a822-1230c0693eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630244615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3630244615
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1862487635
Short name T1078
Test name
Test status
Simulation time 134573154083 ps
CPU time 581.93 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:48:14 PM PST 24
Peak memory 208508 kb
Host smart-d94ad90b-d82c-45a3-aa17-c275c8b8628d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862487635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1862487635
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3604211968
Short name T961
Test name
Test status
Simulation time 68579250262 ps
CPU time 36.16 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:39:08 PM PST 24
Peak memory 199676 kb
Host smart-947573c8-f887-487f-a4ad-2cf9e50e3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604211968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3604211968
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.761894893
Short name T602
Test name
Test status
Simulation time 70144308870 ps
CPU time 200.54 seconds
Started Feb 07 01:38:23 PM PST 24
Finished Feb 07 01:41:52 PM PST 24
Peak memory 216632 kb
Host smart-aff0e023-897b-4a90-9414-b0ea81a173c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761894893 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.761894893
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.345088608
Short name T146
Test name
Test status
Simulation time 41695208251 ps
CPU time 65.84 seconds
Started Feb 07 01:38:23 PM PST 24
Finished Feb 07 01:39:38 PM PST 24
Peak memory 199936 kb
Host smart-d16f948c-52e8-4511-ad4f-c248dca952d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345088608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.345088608
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.509826888
Short name T700
Test name
Test status
Simulation time 7101666224 ps
CPU time 23.28 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:38:55 PM PST 24
Peak memory 208504 kb
Host smart-5128b4f7-e74f-4f41-ae60-adf66f8c4fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509826888 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.509826888
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3621668981
Short name T12
Test name
Test status
Simulation time 65805053611 ps
CPU time 37.34 seconds
Started Feb 07 01:38:33 PM PST 24
Finished Feb 07 01:39:18 PM PST 24
Peak memory 199552 kb
Host smart-98fb7407-f865-4641-b62a-6d79e77f4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621668981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3621668981
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3519248609
Short name T30
Test name
Test status
Simulation time 27372960374 ps
CPU time 390.85 seconds
Started Feb 07 01:38:24 PM PST 24
Finished Feb 07 01:45:03 PM PST 24
Peak memory 214840 kb
Host smart-2579c3c1-34ec-47b0-813f-b9f13db85c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519248609 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3519248609
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.271821665
Short name T353
Test name
Test status
Simulation time 156941028327 ps
CPU time 51.67 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:39:23 PM PST 24
Peak memory 199956 kb
Host smart-e0902c5f-c277-4361-85f4-1997cfdb96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271821665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.271821665
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2609215585
Short name T773
Test name
Test status
Simulation time 285504122555 ps
CPU time 767.83 seconds
Started Feb 07 01:38:21 PM PST 24
Finished Feb 07 01:51:10 PM PST 24
Peak memory 224968 kb
Host smart-2804778b-c48e-49c2-8aac-ae47497c0b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609215585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2609215585
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.950918538
Short name T262
Test name
Test status
Simulation time 15651422938 ps
CPU time 22.02 seconds
Started Feb 07 01:38:25 PM PST 24
Finished Feb 07 01:38:54 PM PST 24
Peak memory 198084 kb
Host smart-3ee9a80a-5cf3-4a07-88d4-5b159da400cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950918538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.950918538
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1334917363
Short name T1077
Test name
Test status
Simulation time 64580401810 ps
CPU time 54.81 seconds
Started Feb 07 01:38:33 PM PST 24
Finished Feb 07 01:39:36 PM PST 24
Peak memory 199896 kb
Host smart-cabe3ffb-585e-48a2-a160-9f3239aa3f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334917363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1334917363
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.628367979
Short name T546
Test name
Test status
Simulation time 68136209 ps
CPU time 0.55 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:32:54 PM PST 24
Peak memory 195388 kb
Host smart-637e30c1-165b-4a59-ae74-58bf653b1b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628367979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.628367979
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.982978571
Short name T985
Test name
Test status
Simulation time 126289334247 ps
CPU time 93.41 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:34:25 PM PST 24
Peak memory 199852 kb
Host smart-aeab1734-94bf-4a0c-a67c-b1eb0e3ae24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982978571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.982978571
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2504039394
Short name T403
Test name
Test status
Simulation time 139718760597 ps
CPU time 194.18 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:36:03 PM PST 24
Peak memory 199812 kb
Host smart-f6ec1fe1-a755-4b1e-add3-0447988c73b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504039394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2504039394
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.23252988
Short name T309
Test name
Test status
Simulation time 12809145909 ps
CPU time 26.18 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:16 PM PST 24
Peak memory 199876 kb
Host smart-697e7481-d50e-4be4-895c-692efd17bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23252988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.23252988
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1566158471
Short name T665
Test name
Test status
Simulation time 431977903586 ps
CPU time 661.05 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:43:53 PM PST 24
Peak memory 200008 kb
Host smart-31f3ebc0-a3a4-43cb-a0e0-90423769aff3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566158471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1566158471
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.91566255
Short name T731
Test name
Test status
Simulation time 119515595748 ps
CPU time 127.59 seconds
Started Feb 07 01:32:53 PM PST 24
Finished Feb 07 01:35:02 PM PST 24
Peak memory 199936 kb
Host smart-f63b0767-68c2-4c61-872d-622b9a8b453b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91566255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.91566255
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1339204197
Short name T1130
Test name
Test status
Simulation time 90626306846 ps
CPU time 109.26 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:34:39 PM PST 24
Peak memory 200192 kb
Host smart-039b3f17-94b0-4735-ad9c-6150b67b9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339204197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1339204197
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.572441636
Short name T1044
Test name
Test status
Simulation time 3533378053 ps
CPU time 198.85 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:36:13 PM PST 24
Peak memory 199916 kb
Host smart-2e07df69-4a86-4cc3-ad8e-861e791708a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572441636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.572441636
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1861678806
Short name T28
Test name
Test status
Simulation time 46006946465 ps
CPU time 28.28 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:33:20 PM PST 24
Peak memory 199984 kb
Host smart-fdf85f81-26fc-4580-904a-520fdb26e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861678806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1861678806
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1052866665
Short name T946
Test name
Test status
Simulation time 23053710032 ps
CPU time 7.82 seconds
Started Feb 07 01:32:48 PM PST 24
Finished Feb 07 01:32:57 PM PST 24
Peak memory 195716 kb
Host smart-3d8caa69-11e1-4470-bf17-d4e85d9f4886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052866665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1052866665
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.246612815
Short name T630
Test name
Test status
Simulation time 124545840 ps
CPU time 1.09 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:32:51 PM PST 24
Peak memory 197708 kb
Host smart-2ef93350-842c-427b-a0b5-def3a2b47a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246612815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.246612815
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2389283718
Short name T1113
Test name
Test status
Simulation time 114519093336 ps
CPU time 450.41 seconds
Started Feb 07 01:32:51 PM PST 24
Finished Feb 07 01:40:22 PM PST 24
Peak memory 208392 kb
Host smart-a04de36c-51b7-4caf-93f5-118bf21d99aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389283718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2389283718
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3315683579
Short name T751
Test name
Test status
Simulation time 75722596845 ps
CPU time 1065.58 seconds
Started Feb 07 01:32:50 PM PST 24
Finished Feb 07 01:50:37 PM PST 24
Peak memory 216616 kb
Host smart-710dea97-3614-4eb5-9d2e-9331a52c234b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315683579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3315683579
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2499054534
Short name T19
Test name
Test status
Simulation time 6326345833 ps
CPU time 21.96 seconds
Started Feb 07 01:32:52 PM PST 24
Finished Feb 07 01:33:16 PM PST 24
Peak memory 199320 kb
Host smart-4ad183b9-36f7-47af-b84c-b11afb50dd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499054534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2499054534
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2914605307
Short name T1182
Test name
Test status
Simulation time 41265579027 ps
CPU time 58.25 seconds
Started Feb 07 01:32:49 PM PST 24
Finished Feb 07 01:33:48 PM PST 24
Peak memory 199924 kb
Host smart-f1f17f80-4bbb-4d3c-8d41-1d2554a8534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914605307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2914605307
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4277341300
Short name T525
Test name
Test status
Simulation time 15745384237 ps
CPU time 14.14 seconds
Started Feb 07 01:38:33 PM PST 24
Finished Feb 07 01:38:55 PM PST 24
Peak memory 199056 kb
Host smart-6b7877ad-1f96-47ac-ab04-ab0851bceafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277341300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4277341300
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1605510713
Short name T1117
Test name
Test status
Simulation time 153527233690 ps
CPU time 881.57 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:53:18 PM PST 24
Peak memory 216308 kb
Host smart-6e2d1b14-7f04-493b-9959-6086dc86403e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605510713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1605510713
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3272434109
Short name T297
Test name
Test status
Simulation time 89446513804 ps
CPU time 45.22 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:39:22 PM PST 24
Peak memory 199908 kb
Host smart-661a487c-3e20-4886-8a0e-681a5f8dcfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272434109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3272434109
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4267441433
Short name T153
Test name
Test status
Simulation time 11326686105 ps
CPU time 8.85 seconds
Started Feb 07 01:38:30 PM PST 24
Finished Feb 07 01:38:46 PM PST 24
Peak memory 199228 kb
Host smart-a37e05f3-b4de-4ebc-83e3-a288f0314534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267441433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4267441433
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3894016746
Short name T795
Test name
Test status
Simulation time 176428518996 ps
CPU time 158.3 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:41:19 PM PST 24
Peak memory 208144 kb
Host smart-97583317-050a-4380-9882-f66b7e4ca6bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894016746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3894016746
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1493610667
Short name T724
Test name
Test status
Simulation time 86043819248 ps
CPU time 32.36 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:39:13 PM PST 24
Peak memory 199780 kb
Host smart-140c580e-3d4a-44c1-b4b0-0973ba3be28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493610667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1493610667
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1260865296
Short name T1222
Test name
Test status
Simulation time 13375053621 ps
CPU time 112.59 seconds
Started Feb 07 01:38:28 PM PST 24
Finished Feb 07 01:40:26 PM PST 24
Peak memory 216080 kb
Host smart-0190b32b-84c5-4ad6-9d9f-fc74bb7d2f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260865296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1260865296
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.424478575
Short name T306
Test name
Test status
Simulation time 32463040629 ps
CPU time 46.76 seconds
Started Feb 07 01:38:26 PM PST 24
Finished Feb 07 01:39:19 PM PST 24
Peak memory 199976 kb
Host smart-9554da4a-bc52-4144-b0e3-fbe982c6ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424478575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.424478575
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3986836886
Short name T601
Test name
Test status
Simulation time 60915324352 ps
CPU time 687.35 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:50:08 PM PST 24
Peak memory 215836 kb
Host smart-90dfe501-b413-4dcf-9493-e5508822f80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986836886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3986836886
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1803395167
Short name T956
Test name
Test status
Simulation time 21156856904 ps
CPU time 22.14 seconds
Started Feb 07 01:38:35 PM PST 24
Finished Feb 07 01:39:04 PM PST 24
Peak memory 199724 kb
Host smart-43df37d8-6119-4bde-a9eb-8e789a0fc79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803395167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1803395167
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2419225537
Short name T996
Test name
Test status
Simulation time 68946762504 ps
CPU time 228.26 seconds
Started Feb 07 01:38:32 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 216636 kb
Host smart-3db7e9d0-3e36-4617-8e13-1c12976f86a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419225537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2419225537
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2226323177
Short name T227
Test name
Test status
Simulation time 148998315290 ps
CPU time 57.42 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:39:34 PM PST 24
Peak memory 199840 kb
Host smart-dd6cfa84-dcdc-49ae-8295-55effaa9bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226323177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2226323177
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3837801884
Short name T631
Test name
Test status
Simulation time 32907726320 ps
CPU time 321.68 seconds
Started Feb 07 01:38:26 PM PST 24
Finished Feb 07 01:43:54 PM PST 24
Peak memory 207812 kb
Host smart-1fa87945-1420-4297-bfed-0bc0fcd8984b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837801884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3837801884
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2910785087
Short name T352
Test name
Test status
Simulation time 259221375474 ps
CPU time 410.68 seconds
Started Feb 07 01:38:31 PM PST 24
Finished Feb 07 01:45:30 PM PST 24
Peak memory 216408 kb
Host smart-07afd378-1637-499b-9347-1ddbffbeac99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910785087 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2910785087
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1867848954
Short name T1189
Test name
Test status
Simulation time 76321890926 ps
CPU time 163.2 seconds
Started Feb 07 01:38:39 PM PST 24
Finished Feb 07 01:41:26 PM PST 24
Peak memory 199924 kb
Host smart-6beb0010-0429-45b6-9f34-7d62b2764dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867848954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1867848954
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1206053032
Short name T133
Test name
Test status
Simulation time 67369703197 ps
CPU time 157.31 seconds
Started Feb 07 01:38:41 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 216072 kb
Host smart-cbeab8a3-efe4-4f96-90cc-70a89080ebe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206053032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1206053032
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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