Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97972	1			T1	13		T2	10		T3	151
all_values[1]	97972	1			T1	13		T2	10		T3	151
all_values[2]	97972	1			T1	13		T2	10		T3	151
all_values[3]	97972	1			T1	13		T2	10		T3	151
all_values[4]	97972	1			T1	13		T2	10		T3	151
all_values[5]	97972	1			T1	13		T2	10		T3	151
all_values[6]	97972	1			T1	13		T2	10		T3	151
all_values[7]	97972	1			T1	13		T2	10		T3	151

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390586

1

T1

43

T2

46

T3

471

auto[1]

393190

1

T1

61

T2

34

T3

737

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

768532

1

T1

95

T2

71

T3

1195

auto[1]

15244

1

T1

9

T2

9

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	44045	1			T3	3		T4	4		T7	3
all_values[0]	auto[0]	auto[1]	2309	1			T3	3		T4	3		T7	4
all_values[0]	auto[1]	auto[0]	49517	1			T1	8		T2	7		T3	140
all_values[0]	auto[1]	auto[1]	2101	1			T1	5		T2	3		T3	5
all_values[1]	auto[0]	auto[0]	52420	1			T1	9		T2	5		T3	145
all_values[1]	auto[0]	auto[1]	2259	1			T1	1		T2	3		T3	1
all_values[1]	auto[1]	auto[0]	41599	1			T1	1		T2	1		T3	5
all_values[1]	auto[1]	auto[1]	1694	1			T1	2		T2	1		T7	1
all_values[2]	auto[0]	auto[0]	44370	1			T1	4		T2	6		T3	130
all_values[2]	auto[0]	auto[1]	2296	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	49110	1			T1	8		T2	2		T3	17
all_values[2]	auto[1]	auto[1]	2196	1			T2	1		T3	3		T4	4
all_values[3]	auto[0]	auto[0]	46714	1			T1	5		T2	10		T3	12
all_values[3]	auto[0]	auto[1]	198	1			T19	1		T29	1		T37	1
all_values[3]	auto[1]	auto[0]	50870	1			T1	8		T3	139		T4	23
all_values[3]	auto[1]	auto[1]	190	1			T19	2		T29	4		T16	3
all_values[4]	auto[0]	auto[0]	48319	1			T1	5		T2	4		T3	4
all_values[4]	auto[0]	auto[1]	351	1			T16	4		T37	4		T39	2
all_values[4]	auto[1]	auto[0]	48939	1			T1	8		T2	6		T3	147
all_values[4]	auto[1]	auto[1]	363	1			T29	1		T91	3		T38	2
all_values[5]	auto[0]	auto[0]	50213	1			T1	10		T2	7		T3	7
all_values[5]	auto[0]	auto[1]	153	1			T19	5		T29	4		T37	2
all_values[5]	auto[1]	auto[0]	47441	1			T1	3		T2	3		T3	144
all_values[5]	auto[1]	auto[1]	165	1			T29	2		T28	3		T38	2
all_values[6]	auto[0]	auto[0]	48044	1			T1	8		T2	7		T3	18
all_values[6]	auto[0]	auto[1]	144	1			T29	1		T28	3		T37	2
all_values[6]	auto[1]	auto[0]	49615	1			T1	5		T2	3		T3	133
all_values[6]	auto[1]	auto[1]	169	1			T19	2		T29	4		T28	1
all_values[7]	auto[0]	auto[0]	48466	1			T2	3		T3	147		T4	4
all_values[7]	auto[0]	auto[1]	285	1			T19	1		T29	17		T323	1
all_values[7]	auto[1]	auto[0]	48850	1			T1	13		T2	7		T3	4
all_values[7]	auto[1]	auto[1]	371	1			T8	3		T15	2		T19	4