Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2202

1

T1

1

T2

1

T3

1

auto[UartRx]

2202

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4050	1			T1	2		T2	2		T3	2
values[1]	43	1			T13	1		T28	1		T38	1
values[2]	32	1			T19	2		T42	2		T20	1
values[3]	31	1			T13	1		T19	1		T38	1
values[4]	50	1			T19	3		T28	2		T37	1
values[5]	32	1			T13	1		T28	1		T37	1
values[6]	28	1			T19	1		T37	1		T38	3
values[7]	36	1			T28	1		T37	2		T38	1
values[8]	26	1			T42	3		T24	1		T95	1
values[9]	20	1			T19	2		T40	2		T41	2
values[10]	40	1			T19	1		T37	1		T39	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2075	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	15	1			T13	1		T28	1		T42	1
auto[UartTx]	values[2]	14	1			T19	1		T42	2		T307	1
auto[UartTx]	values[3]	9	1			T19	1		T42	1		T434	1
auto[UartTx]	values[4]	15	1			T19	1		T28	1		T38	1
auto[UartTx]	values[5]	11	1			T13	1		T20	1		T411	1
auto[UartTx]	values[6]	10	1			T19	1		T37	1		T38	2
auto[UartTx]	values[7]	15	1			T37	1		T38	1		T39	1
auto[UartTx]	values[8]	10	1			T42	1		T386	1		T434	1
auto[UartTx]	values[9]	10	1			T40	1		T41	1		T42	1
auto[UartTx]	values[10]	9	1			T19	1		T411	1		T435	1
auto[UartRx]	values[0]	1975	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	28	1			T38	1		T40	1		T42	3
auto[UartRx]	values[2]	18	1			T19	1		T20	1		T395	1
auto[UartRx]	values[3]	22	1			T13	1		T38	1		T40	1
auto[UartRx]	values[4]	35	1			T19	2		T28	1		T37	1
auto[UartRx]	values[5]	21	1			T28	1		T37	1		T38	2
auto[UartRx]	values[6]	18	1			T38	1		T39	2		T24	2
auto[UartRx]	values[7]	21	1			T28	1		T37	1		T40	1
auto[UartRx]	values[8]	16	1			T42	2		T24	1		T95	1
auto[UartRx]	values[9]	10	1			T19	2		T40	1		T41	1
auto[UartRx]	values[10]	31	1			T37	1		T39	2		T18	1