Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1746	1			T2	2		T3	2		T6	9
auto[BaudRate115200]	1908	1			T1	4		T2	1		T3	2
auto[BaudRate230400]	1620	1			T1	2		T2	1		T4	2
auto[BaudRate128Kbps]	1682	1			T3	2		T4	1		T6	6
auto[BaudRate256Kbps]	1836	1			T1	3		T2	1		T3	1
auto[BaudRate1Mbps]	1497	1			T6	3		T7	2		T8	1
auto[BaudRate1p5Mbps]	1089	1			T2	1		T3	2		T7	5

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1181	1			T15	10		T26	39		T291	8
freqs[25]	1030	1			T36	10		T47	7		T21	7
freqs[48]	721	1			T305	7		T323	9		T101	6
freqs[50]	553	1			T49	1		T152	6		T126	10
freqs[100]	1040	1			T50	6		T25	24		T45	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	169	1			T26	3		T23	3		T404	1
auto[BaudRate9600]	freqs[25]	139	1			T36	2		T21	5		T436	1
auto[BaudRate9600]	freqs[48]	110	1			T323	2		T42	2		T121	1
auto[BaudRate9600]	freqs[50]	78	1			T126	1		T389	2		T18	4
auto[BaudRate9600]	freqs[100]	153	1			T50	2		T45	1		T46	3
auto[BaudRate115200]	freqs[24]	198	1			T15	2		T26	3		T309	2
auto[BaudRate115200]	freqs[25]	144	1			T47	1		T21	2		T436	1
auto[BaudRate115200]	freqs[48]	130	1			T305	1		T323	1		T101	1
auto[BaudRate115200]	freqs[50]	90	1			T126	1		T389	4		T18	3
auto[BaudRate115200]	freqs[100]	153	1			T25	6		T46	1		T16	1
auto[BaudRate230400]	freqs[24]	182	1			T15	1		T26	3		T309	1
auto[BaudRate230400]	freqs[25]	119	1			T403	1		T314	3		T320	2
auto[BaudRate230400]	freqs[48]	113	1			T305	3		T101	3		T42	6
auto[BaudRate230400]	freqs[50]	88	1			T49	1		T152	1		T126	1
auto[BaudRate230400]	freqs[100]	116	1			T50	1		T45	3		T46	1
auto[BaudRate128Kbps]	freqs[24]	170	1			T15	3		T26	6		T309	1
auto[BaudRate128Kbps]	freqs[25]	184	1			T36	1		T47	1		T403	1
auto[BaudRate128Kbps]	freqs[48]	87	1			T323	3		T42	3		T121	2
auto[BaudRate128Kbps]	freqs[50]	67	1			T152	1		T126	2		T389	2
auto[BaudRate128Kbps]	freqs[100]	151	1			T50	1		T25	3		T45	1
auto[BaudRate256Kbps]	freqs[24]	188	1			T15	1		T26	6		T291	1
auto[BaudRate256Kbps]	freqs[25]	174	1			T36	3		T47	3		T403	2
auto[BaudRate256Kbps]	freqs[48]	88	1			T305	1		T42	7		T121	1
auto[BaudRate256Kbps]	freqs[50]	68	1			T152	3		T126	2		T389	1
auto[BaudRate256Kbps]	freqs[100]	183	1			T25	9		T45	1		T237	4
auto[BaudRate1Mbps]	freqs[24]	187	1			T15	2		T26	15		T291	3
auto[BaudRate1Mbps]	freqs[25]	181	1			T36	3		T47	1		T403	1
auto[BaudRate1Mbps]	freqs[48]	95	1			T305	1		T323	2		T42	7
auto[BaudRate1Mbps]	freqs[50]	54	1			T389	1		T18	2		T433	2
auto[BaudRate1Mbps]	freqs[100]	154	1			T25	6		T45	3		T347	3
auto[BaudRate1p5Mbps]	freqs[25]	89	1			T36	1		T47	1		T314	1
auto[BaudRate1p5Mbps]	freqs[48]	98	1			T305	1		T323	1		T101	2
auto[BaudRate1p5Mbps]	freqs[50]	108	1			T152	1		T126	3		T389	3
auto[BaudRate1p5Mbps]	freqs[100]	130	1			T50	2		T46	1		T174	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded