Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
0 |
8 |
100.00 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
0 |
8 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_watermark_lvl
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1521 |
1 |
|
|
T4 |
2 |
|
T27 |
1 |
|
T26 |
1 |
all_levels[1] |
457 |
1 |
|
|
T2 |
1 |
|
T14 |
11 |
|
T15 |
1 |
all_levels[2] |
311 |
1 |
|
|
T2 |
2 |
|
T9 |
1 |
|
T36 |
2 |
all_levels[3] |
347 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T14 |
1 |
all_levels[4] |
468 |
1 |
|
|
T1 |
3 |
|
T47 |
1 |
|
T52 |
1 |
all_levels[5] |
186 |
1 |
|
|
T50 |
2 |
|
T237 |
3 |
|
T51 |
2 |
all_levels[6] |
483 |
1 |
|
|
T3 |
1 |
|
T48 |
1 |
|
T237 |
1 |
all_levels[7] |
177 |
1 |
|
|
T15 |
1 |
|
T36 |
5 |
|
T13 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |