Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1521 1 T4 2 T27 1 T26 1
all_levels[1] 457 1 T2 1 T14 11 T15 1
all_levels[2] 311 1 T2 2 T9 1 T36 2
all_levels[3] 347 1 T2 1 T7 1 T14 1
all_levels[4] 468 1 T1 3 T47 1 T52 1
all_levels[5] 186 1 T50 2 T237 3 T51 2
all_levels[6] 483 1 T3 1 T48 1 T237 1
all_levels[7] 177 1 T15 1 T36 5 T13 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%