Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97972	1			T1	13		T2	10		T3	151
all_pins[1]	97972	1			T1	13		T2	10		T3	151
all_pins[2]	97972	1			T1	13		T2	10		T3	151
all_pins[3]	97972	1			T1	13		T2	10		T3	151
all_pins[4]	97972	1			T1	13		T2	10		T3	151
all_pins[5]	97972	1			T1	13		T2	10		T3	151
all_pins[6]	97972	1			T1	13		T2	10		T3	151
all_pins[7]	97972	1			T1	13		T2	10		T3	151

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	775849	1			T1	96		T2	75		T3	1200
values[0x1]	7927	1			T1	8		T2	5		T3	8
transitions[0x0=>0x1]	7156	1			T1	6		T2	5		T3	8
transitions[0x1=>0x0]	7170	1			T1	6		T2	5		T3	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95803	1			T1	8		T2	7		T3	146
all_pins[0]	values[0x1]	2169	1			T1	5		T2	3		T3	5
all_pins[0]	transitions[0x0=>0x1]	1907	1			T1	3		T2	3		T3	5
all_pins[0]	transitions[0x1=>0x0]	1430	1			T2	1		T7	1		T14	11
all_pins[1]	values[0x0]	96280	1			T1	11		T2	9		T3	151
all_pins[1]	values[0x1]	1692	1			T1	2		T2	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	1452	1			T1	2		T2	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	2011	1			T2	1		T3	3		T4	4
all_pins[2]	values[0x0]	95721	1			T1	13		T2	9		T3	148
all_pins[2]	values[0x1]	2251	1			T2	1		T3	3		T4	4
all_pins[2]	transitions[0x0=>0x1]	2211	1			T2	1		T3	3		T4	4
all_pins[2]	transitions[0x1=>0x0]	150	1			T19	2		T29	1		T16	3
all_pins[3]	values[0x0]	97782	1			T1	13		T2	10		T3	151
all_pins[3]	values[0x1]	190	1			T19	2		T29	4		T16	3
all_pins[3]	transitions[0x0=>0x1]	164	1			T19	2		T29	4		T16	3
all_pins[3]	transitions[0x1=>0x0]	337	1			T29	1		T91	3		T38	2
all_pins[4]	values[0x0]	97609	1			T1	13		T2	10		T3	151
all_pins[4]	values[0x1]	363	1			T29	1		T91	3		T38	2
all_pins[4]	transitions[0x0=>0x1]	326	1			T29	1		T91	3		T39	4
all_pins[4]	transitions[0x1=>0x0]	158	1			T29	2		T28	3		T108	1
all_pins[5]	values[0x0]	97777	1			T1	13		T2	10		T3	151
all_pins[5]	values[0x1]	195	1			T29	2		T28	3		T38	2
all_pins[5]	transitions[0x0=>0x1]	149	1			T29	1		T28	2		T103	2
all_pins[5]	transitions[0x1=>0x0]	650	1			T1	1		T7	1		T9	3
all_pins[6]	values[0x0]	97276	1			T1	12		T2	10		T3	151
all_pins[6]	values[0x1]	696	1			T1	1		T7	1		T9	3
all_pins[6]	transitions[0x0=>0x1]	642	1			T1	1		T7	1		T9	3
all_pins[6]	transitions[0x1=>0x0]	317	1			T8	3		T15	2		T19	4
all_pins[7]	values[0x0]	97601	1			T1	13		T2	10		T3	151
all_pins[7]	values[0x1]	371	1			T8	3		T15	2		T19	4
all_pins[7]	transitions[0x0=>0x1]	305	1			T8	3		T15	2		T19	1
all_pins[7]	transitions[0x1=>0x0]	2117	1			T1	5		T2	3		T3	5