Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	661	1			T19	7		T29	7		T28	4
all_values[1]	661	1			T19	7		T29	7		T28	4
all_values[2]	661	1			T19	7		T29	7		T28	4
all_values[3]	661	1			T19	7		T29	7		T28	4
all_values[4]	661	1			T19	7		T29	7		T28	4
all_values[5]	661	1			T19	7		T29	7		T28	4
all_values[6]	661	1			T19	7		T29	7		T28	4
all_values[7]	661	1			T19	7		T29	7		T28	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2826

1

T19

24

T29

23

T28

14

auto[1]

2462

1

T19

32

T29

33

T28

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2079

1

T19

21

T29

14

T28

10

auto[1]

3209

1

T19

35

T29

42

T28

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3149

1

T19

32

T29

31

T28

17

auto[1]

2139

1

T19

24

T29

25

T28

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	128	1			T19	1		T29	1		T37	6
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T19	1		T29	1		T103	1
all_values[0]	auto[0]	auto[1]	auto[0]	117	1			T29	2		T28	1		T91	2
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T19	1		T29	1		T28	1
all_values[0]	auto[1]	auto[0]	auto[1]	155	1			T19	2		T29	1		T28	1
all_values[0]	auto[1]	auto[1]	auto[1]	116	1			T19	2		T29	1		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	136	1			T19	1		T29	1		T28	1
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T29	1		T37	1		T39	2
all_values[1]	auto[0]	auto[1]	auto[0]	128	1			T19	1		T29	1		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	67	1			T19	1		T29	2		T28	1
all_values[1]	auto[1]	auto[0]	auto[1]	150	1			T37	3		T91	2		T38	2
all_values[1]	auto[1]	auto[1]	auto[1]	106	1			T19	4		T29	2		T28	2
all_values[2]	auto[0]	auto[0]	auto[0]	136	1			T19	2		T91	2		T38	2
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T19	1		T29	1		T37	2
all_values[2]	auto[0]	auto[1]	auto[0]	122	1			T19	3		T91	2		T38	2
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T29	2		T28	1		T37	2
all_values[2]	auto[1]	auto[0]	auto[1]	143	1			T19	1		T29	1		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	122	1			T29	3		T28	1		T37	5
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T29	1		T37	4		T91	1
all_values[3]	auto[0]	auto[0]	auto[1]	55	1			T29	1		T37	1		T24	4
all_values[3]	auto[0]	auto[1]	auto[0]	117	1			T19	2		T28	1		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T29	2		T28	1
all_values[3]	auto[1]	auto[0]	auto[1]	137	1			T19	1		T28	1		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	124	1			T19	3		T29	3		T28	1
all_values[4]	auto[0]	auto[0]	auto[0]	142	1			T19	3		T29	4		T28	3
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T37	2		T39	1		T108	1
all_values[4]	auto[0]	auto[1]	auto[0]	121	1			T19	2		T29	1		T37	4
all_values[4]	auto[0]	auto[1]	auto[1]	58	1			T91	2		T38	1		T103	1
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T19	1		T29	1		T28	1
all_values[4]	auto[1]	auto[1]	auto[1]	112	1			T19	1		T29	1		T37	1
all_values[5]	auto[0]	auto[0]	auto[0]	155	1			T19	1		T29	1		T37	2
all_values[5]	auto[0]	auto[0]	auto[1]	66	1			T19	2		T29	4		T37	1
all_values[5]	auto[0]	auto[1]	auto[0]	102	1			T28	1		T37	4		T91	1
all_values[5]	auto[0]	auto[1]	auto[1]	69	1			T28	2		T38	1		T108	1
all_values[5]	auto[1]	auto[0]	auto[1]	148	1			T19	3		T37	2		T39	2
all_values[5]	auto[1]	auto[1]	auto[1]	121	1			T19	1		T29	2		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	127	1			T19	3		T29	1		T37	3
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T19	1		T28	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T19	1		T29	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T29	1		T37	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	157	1			T28	1		T37	4		T91	1
all_values[6]	auto[1]	auto[1]	auto[1]	122	1			T19	2		T29	4		T28	2
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T28	2		T37	3		T91	2
all_values[7]	auto[0]	auto[0]	auto[1]	50	1			T103	1		T24	4		T386	2
all_values[7]	auto[0]	auto[1]	auto[0]	119	1			T19	1		T28	1		T37	2
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T19	3		T29	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	139	1			T29	3		T28	1		T37	1
all_values[7]	auto[1]	auto[1]	auto[1]	120	1			T19	3		T29	3		T37	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal