Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	119551	1			T1	56		T2	20		T3	1
all_values[1]	119551	1			T1	56		T2	20		T3	1
all_values[2]	119551	1			T1	56		T2	20		T3	1
all_values[3]	119551	1			T1	56		T2	20		T3	1
all_values[4]	119551	1			T1	56		T2	20		T3	1
all_values[5]	119551	1			T1	56		T2	20		T3	1
all_values[6]	119551	1			T1	56		T2	20		T3	1
all_values[7]	119551	1			T1	56		T2	20		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

473873

1

T1

268

T2

108

T3

3

auto[1]

482535

1

T1

180

T2

52

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941229

1

T1

431

T2

148

T3

8

auto[1]

15179

1

T1

17

T2

12

T4

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63115	1			T1	47		T2	1		T4	346
all_values[0]	auto[0]	auto[1]	2376	1			T1	4		T2	3		T4	2
all_values[0]	auto[1]	auto[0]	51861	1			T1	3		T2	15		T3	1
all_values[0]	auto[1]	auto[1]	2199	1			T1	2		T2	1		T4	2
all_values[1]	auto[0]	auto[0]	54351	1			T1	54		T2	15		T4	357
all_values[1]	auto[0]	auto[1]	1945	1			T1	2		T2	3		T6	3
all_values[1]	auto[1]	auto[0]	61255	1			T2	2		T3	1		T4	437
all_values[1]	auto[1]	auto[1]	2000	1			T83	3		T34	5		T12	15
all_values[2]	auto[0]	auto[0]	57632	1			T1	47		T2	15		T3	1
all_values[2]	auto[0]	auto[1]	2400	1			T1	9		T2	5		T4	2
all_values[2]	auto[1]	auto[0]	57361	1			T4	750		T5	50		T6	5
all_values[2]	auto[1]	auto[1]	2158	1			T4	2		T6	4		T7	3
all_values[3]	auto[0]	auto[0]	58722	1			T2	16		T4	342		T5	5
all_values[3]	auto[0]	auto[1]	153	1			T14	1		T25	1		T15	1
all_values[3]	auto[1]	auto[0]	60529	1			T1	56		T2	4		T3	1
all_values[3]	auto[1]	auto[1]	147	1			T35	4		T36	1		T16	2
all_values[4]	auto[0]	auto[0]	56319	1			T1	5		T2	12		T3	1
all_values[4]	auto[0]	auto[1]	338	1			T84	1		T36	3		T16	37
all_values[4]	auto[1]	auto[0]	62507	1			T1	51		T2	8		T4	211
all_values[4]	auto[1]	auto[1]	387	1			T18	5		T14	27		T27	2
all_values[5]	auto[0]	auto[0]	60468	1			T1	50		T2	16		T4	272
all_values[5]	auto[0]	auto[1]	117	1			T25	2		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	58841	1			T1	6		T2	4		T3	1
all_values[5]	auto[1]	auto[1]	125	1			T27	2		T25	2		T35	6
all_values[6]	auto[0]	auto[0]	53613	1			T1	50		T2	4		T3	1
all_values[6]	auto[0]	auto[1]	114	1			T25	2		T36	3		T113	3
all_values[6]	auto[1]	auto[0]	65715	1			T1	6		T2	16		T4	400
all_values[6]	auto[1]	auto[1]	109	1			T25	2		T35	1		T113	4
all_values[7]	auto[0]	auto[0]	61898	1			T2	18		T4	5		T5	81
all_values[7]	auto[0]	auto[1]	312	1			T12	2		T18	2		T84	2
all_values[7]	auto[1]	auto[0]	57042	1			T1	56		T2	2		T3	1
all_values[7]	auto[1]	auto[1]	299	1			T366	1		T27	3		T331	1