Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1640	1			T1	1		T2	2		T5	4
auto[BaudRate115200]	1819	1			T2	2		T4	2		T8	1
auto[BaudRate230400]	1562	1			T1	1		T2	1		T3	3
auto[BaudRate128Kbps]	1597	1			T2	1		T4	1		T5	1
auto[BaudRate256Kbps]	1864	1			T1	2		T2	3		T4	1
auto[BaudRate1Mbps]	1483	1			T3	3		T4	2		T7	2
auto[BaudRate1p5Mbps]	1109	1			T1	2		T3	3		T4	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1119	1			T9	6		T83	10		T34	7
freqs[25]	747	1			T4	8		T15	13		T228	34
freqs[48]	392	1			T121	9		T455	27		T145	5
freqs[50]	609	1			T1	6		T116	10		T406	7
freqs[100]	1022	1			T5	7		T10	7		T24	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	167	1			T83	1		T34	2		T166	3
auto[BaudRate9600]	freqs[25]	109	1			T15	4		T228	4		T138	2
auto[BaudRate9600]	freqs[48]	48	1			T455	3		T145	1		T433	1
auto[BaudRate9600]	freqs[50]	73	1			T1	1		T456	1		T424	1
auto[BaudRate9600]	freqs[100]	136	1			T5	4		T10	1		T24	2
auto[BaudRate115200]	freqs[24]	199	1			T9	1		T83	3		T34	1
auto[BaudRate115200]	freqs[25]	123	1			T4	2		T15	2		T228	4
auto[BaudRate115200]	freqs[48]	63	1			T455	9		T145	2		T331	1
auto[BaudRate115200]	freqs[50]	93	1			T172	1		T424	1		T457	6
auto[BaudRate115200]	freqs[100]	186	1			T10	1		T24	2		T42	1
auto[BaudRate230400]	freqs[24]	168	1			T9	3		T83	2		T34	2
auto[BaudRate230400]	freqs[25]	101	1			T15	1		T228	6		T138	2
auto[BaudRate230400]	freqs[48]	46	1			T121	1		T145	1		T139	1
auto[BaudRate230400]	freqs[50]	79	1			T1	1		T116	1		T172	1
auto[BaudRate230400]	freqs[100]	142	1			T5	1		T24	1		T18	3
auto[BaudRate128Kbps]	freqs[24]	150	1			T83	1		T34	1		T166	2
auto[BaudRate128Kbps]	freqs[25]	116	1			T4	1		T15	3		T228	2
auto[BaudRate128Kbps]	freqs[48]	70	1			T121	2		T455	9		T433	1
auto[BaudRate128Kbps]	freqs[50]	80	1			T116	2		T172	1		T456	3
auto[BaudRate128Kbps]	freqs[100]	126	1			T5	1		T10	1		T24	2
auto[BaudRate256Kbps]	freqs[24]	174	1			T9	1		T83	1		T166	3
auto[BaudRate256Kbps]	freqs[25]	124	1			T4	1		T15	1		T228	14
auto[BaudRate256Kbps]	freqs[48]	47	1			T121	2		T455	3		T331	1
auto[BaudRate256Kbps]	freqs[50]	104	1			T1	2		T116	3		T406	1
auto[BaudRate256Kbps]	freqs[100]	126	1			T5	1		T24	1		T292	3
auto[BaudRate1Mbps]	freqs[24]	169	1			T9	1		T83	1		T166	3
auto[BaudRate1Mbps]	freqs[25]	110	1			T4	2		T228	2		T138	1
auto[BaudRate1Mbps]	freqs[48]	57	1			T121	1		T331	1		T430	1
auto[BaudRate1Mbps]	freqs[50]	96	1			T116	2		T406	2		T456	3
auto[BaudRate1Mbps]	freqs[100]	151	1			T10	3		T24	2		T42	1
auto[BaudRate1p5Mbps]	freqs[25]	64	1			T4	2		T15	2		T228	2
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T121	3		T455	3		T145	1
auto[BaudRate1p5Mbps]	freqs[50]	84	1			T1	2		T116	2		T406	4
auto[BaudRate1p5Mbps]	freqs[100]	155	1			T10	1		T214	2		T366	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded