Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1527 1 T8 1 T83 1 T24 1
all_levels[1] 456 1 T17 1 T34 3 T12 2
all_levels[2] 335 1 T82 1 T83 2 T12 2
all_levels[3] 255 1 T2 1 T6 2 T115 1
all_levels[4] 460 1 T1 2 T2 2 T34 5
all_levels[5] 288 1 T6 1 T121 2 T170 1
all_levels[6] 441 1 T14 124 T418 3 T27 1
all_levels[7] 178 1 T48 2 T27 2 T276 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%