Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	119551	1			T1	56		T2	20		T3	1
all_pins[1]	119551	1			T1	56		T2	20		T3	1
all_pins[2]	119551	1			T1	56		T2	20		T3	1
all_pins[3]	119551	1			T1	56		T2	20		T3	1
all_pins[4]	119551	1			T1	56		T2	20		T3	1
all_pins[5]	119551	1			T1	56		T2	20		T3	1
all_pins[6]	119551	1			T1	56		T2	20		T3	1
all_pins[7]	119551	1			T1	56		T2	20		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	948243	1			T1	444		T2	157		T3	8
values[0x1]	8165	1			T1	4		T2	3		T4	4
transitions[0x0=>0x1]	7470	1			T1	4		T2	3		T4	4
transitions[0x1=>0x0]	7480	1			T1	4		T2	3		T4	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	117294	1			T1	54		T2	19		T3	1
all_pins[0]	values[0x1]	2257	1			T1	2		T2	1		T4	2
all_pins[0]	transitions[0x0=>0x1]	2009	1			T1	2		T2	1		T4	2
all_pins[0]	transitions[0x1=>0x0]	1752	1			T83	3		T34	5		T12	12
all_pins[1]	values[0x0]	117551	1			T1	56		T2	20		T3	1
all_pins[1]	values[0x1]	2000	1			T83	3		T34	5		T12	15
all_pins[1]	transitions[0x0=>0x1]	1779	1			T83	2		T34	5		T12	15
all_pins[1]	transitions[0x1=>0x0]	1998	1			T4	2		T6	4		T7	3
all_pins[2]	values[0x0]	117332	1			T1	56		T2	20		T3	1
all_pins[2]	values[0x1]	2219	1			T4	2		T6	4		T7	3
all_pins[2]	transitions[0x0=>0x1]	2194	1			T4	2		T6	4		T7	3
all_pins[2]	transitions[0x1=>0x0]	122	1			T35	4		T36	1		T16	2
all_pins[3]	values[0x0]	119404	1			T1	56		T2	20		T3	1
all_pins[3]	values[0x1]	147	1			T35	4		T36	1		T16	2
all_pins[3]	transitions[0x0=>0x1]	117	1			T35	4		T36	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	357	1			T18	5		T14	27		T27	2
all_pins[4]	values[0x0]	119164	1			T1	56		T2	20		T3	1
all_pins[4]	values[0x1]	387	1			T18	5		T14	27		T27	2
all_pins[4]	transitions[0x0=>0x1]	338	1			T18	4		T14	27		T27	2
all_pins[4]	transitions[0x1=>0x0]	120	1			T27	2		T25	1		T35	6
all_pins[5]	values[0x0]	119382	1			T1	56		T2	20		T3	1
all_pins[5]	values[0x1]	169	1			T18	1		T27	2		T25	2
all_pins[5]	transitions[0x0=>0x1]	137	1			T18	1		T27	2		T25	2
all_pins[5]	transitions[0x1=>0x0]	655	1			T1	2		T2	2		T6	1
all_pins[6]	values[0x0]	118864	1			T1	54		T2	18		T3	1
all_pins[6]	values[0x1]	687	1			T1	2		T2	2		T6	1
all_pins[6]	transitions[0x0=>0x1]	641	1			T1	2		T2	2		T6	1
all_pins[6]	transitions[0x1=>0x0]	253	1			T366	1		T27	3		T327	3
all_pins[7]	values[0x0]	119252	1			T1	56		T2	20		T3	1
all_pins[7]	values[0x1]	299	1			T366	1		T27	3		T331	1
all_pins[7]	transitions[0x0=>0x1]	255	1			T366	1		T27	2		T331	1
all_pins[7]	transitions[0x1=>0x0]	2223	1			T1	2		T2	1		T4	2