Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T27	4		T25	4		T35	7
all_values[1]	500	1			T27	4		T25	4		T35	7
all_values[2]	500	1			T27	4		T25	4		T35	7
all_values[3]	500	1			T27	4		T25	4		T35	7
all_values[4]	500	1			T27	4		T25	4		T35	7
all_values[5]	500	1			T27	4		T25	4		T35	7
all_values[6]	500	1			T27	4		T25	4		T35	7
all_values[7]	500	1			T27	4		T25	4		T35	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2168

1

T27

23

T25

21

T35

21

auto[1]

1832

1

T27

9

T25

11

T35

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1622

1

T27

16

T25

10

T35

20

auto[1]

2378

1

T27

16

T25

22

T35

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2409

1

T27

22

T25

18

T35

30

auto[1]

1591

1

T27

10

T25

14

T35

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	103	1			T35	1		T36	1		T113	1
all_values[0]	auto[0]	auto[0]	auto[1]	58	1			T27	1		T25	1		T36	1
all_values[0]	auto[0]	auto[1]	auto[0]	93	1			T35	1		T36	1		T113	7
all_values[0]	auto[0]	auto[1]	auto[1]	49	1			T113	3		T103	2		T107	1
all_values[0]	auto[1]	auto[0]	auto[1]	95	1			T27	1		T25	1		T35	1
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T27	2		T25	2		T35	4
all_values[1]	auto[0]	auto[0]	auto[0]	116	1			T27	1		T25	1		T35	1
all_values[1]	auto[0]	auto[0]	auto[1]	43	1			T27	2		T113	1		T103	1
all_values[1]	auto[0]	auto[1]	auto[0]	107	1			T35	3		T36	4		T113	2
all_values[1]	auto[0]	auto[1]	auto[1]	48	1			T25	1		T113	3		T103	1
all_values[1]	auto[1]	auto[0]	auto[1]	112	1			T27	1		T25	2		T35	1
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T35	2		T113	3		T103	4
all_values[2]	auto[0]	auto[0]	auto[0]	127	1			T27	3		T25	3		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	54	1			T35	1		T103	2		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	79	1			T25	1		T35	2		T113	6
all_values[2]	auto[0]	auto[1]	auto[1]	41	1			T107	1		T39	1		T40	1
all_values[2]	auto[1]	auto[0]	auto[1]	122	1			T27	1		T35	2		T36	1
all_values[2]	auto[1]	auto[1]	auto[1]	77	1			T35	1		T113	1		T103	1
all_values[3]	auto[0]	auto[0]	auto[0]	127	1			T27	2		T25	1		T35	1
all_values[3]	auto[0]	auto[0]	auto[1]	39	1			T25	1		T35	2		T36	1
all_values[3]	auto[0]	auto[1]	auto[0]	100	1			T27	1		T25	1		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	44	1			T35	1		T41	1		T402	2
all_values[3]	auto[1]	auto[0]	auto[1]	93	1			T27	1		T25	1		T35	1
all_values[3]	auto[1]	auto[1]	auto[1]	97	1			T35	2		T36	1		T113	6
all_values[4]	auto[0]	auto[0]	auto[0]	107	1			T27	1		T35	5		T113	1
all_values[4]	auto[0]	auto[0]	auto[1]	52	1			T36	3		T113	3		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	77	1			T27	1		T25	2		T113	2
all_values[4]	auto[0]	auto[1]	auto[1]	54	1			T27	1		T113	1		T103	1
all_values[4]	auto[1]	auto[0]	auto[1]	117	1			T25	1		T35	1		T113	4
all_values[4]	auto[1]	auto[1]	auto[1]	93	1			T27	1		T25	1		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	109	1			T27	1		T113	3		T103	1
all_values[5]	auto[0]	auto[0]	auto[1]	48	1			T25	1		T113	2		T39	3
all_values[5]	auto[0]	auto[1]	auto[0]	88	1			T36	1		T113	5		T103	2
all_values[5]	auto[0]	auto[1]	auto[1]	50	1			T27	1		T25	1		T35	3
all_values[5]	auto[1]	auto[0]	auto[1]	109	1			T27	1		T25	1		T35	1
all_values[5]	auto[1]	auto[1]	auto[1]	96	1			T27	1		T25	1		T35	3
all_values[6]	auto[0]	auto[0]	auto[0]	110	1			T27	4		T35	2		T113	4
all_values[6]	auto[0]	auto[0]	auto[1]	51	1			T25	1		T36	1		T113	1
all_values[6]	auto[0]	auto[1]	auto[0]	81	1			T35	1		T36	1		T113	2
all_values[6]	auto[0]	auto[1]	auto[1]	52	1			T25	1		T35	1		T113	2
all_values[6]	auto[1]	auto[0]	auto[1]	115	1			T25	2		T36	2		T113	3
all_values[6]	auto[1]	auto[1]	auto[1]	91	1			T35	3		T113	3		T103	1
all_values[7]	auto[0]	auto[0]	auto[0]	108	1			T27	2		T25	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[1]	40	1			T25	1		T113	1		T103	2
all_values[7]	auto[0]	auto[1]	auto[0]	90	1			T35	2		T36	2		T113	3
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T27	1		T35	2		T113	5
all_values[7]	auto[1]	auto[0]	auto[1]	113	1			T27	1		T25	2		T103	3
all_values[7]	auto[1]	auto[1]	auto[1]	85	1			T35	3		T113	6		T103	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal