Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.79 98.45 100.00 99.76 100.00 97.54


Total test records in report: 1237
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T1047 /workspace/coverage/default/8.uart_tx_ovrd.2161146122 Feb 21 03:48:36 PM PST 24 Feb 21 03:48:53 PM PST 24 6203915735 ps
T1048 /workspace/coverage/default/42.uart_intr.729709707 Feb 21 03:50:50 PM PST 24 Feb 21 03:55:53 PM PST 24 197876229496 ps
T1049 /workspace/coverage/default/21.uart_rx_start_bit_filter.811781534 Feb 21 03:48:50 PM PST 24 Feb 21 03:48:52 PM PST 24 6774159272 ps
T273 /workspace/coverage/default/256.uart_fifo_reset.611511768 Feb 21 03:53:36 PM PST 24 Feb 21 03:54:02 PM PST 24 191936180524 ps
T1050 /workspace/coverage/default/24.uart_long_xfer_wo_dly.885691427 Feb 21 03:49:04 PM PST 24 Feb 21 03:55:31 PM PST 24 121432903607 ps
T1051 /workspace/coverage/default/3.uart_smoke.287024930 Feb 21 03:47:43 PM PST 24 Feb 21 03:48:00 PM PST 24 5482995537 ps
T390 /workspace/coverage/default/34.uart_fifo_full.2878137810 Feb 21 03:49:49 PM PST 24 Feb 21 03:50:08 PM PST 24 32136448608 ps
T1052 /workspace/coverage/default/183.uart_fifo_reset.3700358655 Feb 21 03:52:36 PM PST 24 Feb 21 03:52:41 PM PST 24 17870978731 ps
T1053 /workspace/coverage/default/31.uart_fifo_full.3636500570 Feb 21 03:49:44 PM PST 24 Feb 21 03:52:53 PM PST 24 104787189184 ps
T298 /workspace/coverage/default/13.uart_rx_parity_err.2235465029 Feb 21 03:48:40 PM PST 24 Feb 21 03:48:59 PM PST 24 20209788962 ps
T1054 /workspace/coverage/default/11.uart_smoke.4219326520 Feb 21 03:48:34 PM PST 24 Feb 21 03:48:36 PM PST 24 523836554 ps
T1055 /workspace/coverage/default/130.uart_fifo_reset.1275830532 Feb 21 03:52:06 PM PST 24 Feb 21 03:52:22 PM PST 24 33270603925 ps
T1056 /workspace/coverage/default/7.uart_stress_all.271299860 Feb 21 03:48:05 PM PST 24 Feb 21 03:54:03 PM PST 24 193657017464 ps
T1057 /workspace/coverage/default/186.uart_fifo_reset.2678923459 Feb 21 03:52:36 PM PST 24 Feb 21 03:54:11 PM PST 24 91973268294 ps
T396 /workspace/coverage/default/87.uart_fifo_reset.1631107757 Feb 21 03:51:51 PM PST 24 Feb 21 03:52:05 PM PST 24 32157493347 ps
T1058 /workspace/coverage/default/4.uart_tx_rx.1007656622 Feb 21 03:47:54 PM PST 24 Feb 21 03:48:55 PM PST 24 57650977770 ps
T1059 /workspace/coverage/default/133.uart_fifo_reset.2372590204 Feb 21 03:52:08 PM PST 24 Feb 21 03:52:41 PM PST 24 21176224351 ps
T1060 /workspace/coverage/default/29.uart_smoke.696990119 Feb 21 03:49:30 PM PST 24 Feb 21 03:49:55 PM PST 24 6283059246 ps
T1061 /workspace/coverage/default/38.uart_loopback.3651323834 Feb 21 03:50:05 PM PST 24 Feb 21 03:50:19 PM PST 24 8978619501 ps
T1062 /workspace/coverage/default/29.uart_rx_start_bit_filter.406168291 Feb 21 03:49:33 PM PST 24 Feb 21 03:49:42 PM PST 24 37956631298 ps
T355 /workspace/coverage/default/94.uart_fifo_reset.3851023974 Feb 21 03:51:52 PM PST 24 Feb 21 03:52:04 PM PST 24 6818368177 ps
T1063 /workspace/coverage/default/72.uart_fifo_reset.967860868 Feb 21 03:51:41 PM PST 24 Feb 21 03:55:34 PM PST 24 140511987528 ps
T1064 /workspace/coverage/default/15.uart_stress_all.1224183899 Feb 21 03:48:35 PM PST 24 Feb 21 04:00:25 PM PST 24 386686073175 ps
T1065 /workspace/coverage/default/10.uart_long_xfer_wo_dly.2181975553 Feb 21 03:48:22 PM PST 24 Feb 21 03:51:54 PM PST 24 77028522686 ps
T1066 /workspace/coverage/default/49.uart_alert_test.1237763066 Feb 21 03:51:20 PM PST 24 Feb 21 03:51:21 PM PST 24 40700244 ps
T1067 /workspace/coverage/default/36.uart_fifo_full.1885506130 Feb 21 03:49:57 PM PST 24 Feb 21 03:57:27 PM PST 24 274990943786 ps
T381 /workspace/coverage/default/213.uart_fifo_reset.1537472497 Feb 21 03:52:47 PM PST 24 Feb 21 03:52:56 PM PST 24 17827216442 ps
T184 /workspace/coverage/default/230.uart_fifo_reset.2899646406 Feb 21 03:53:13 PM PST 24 Feb 21 03:55:03 PM PST 24 124537422220 ps
T1068 /workspace/coverage/default/39.uart_loopback.725162919 Feb 21 03:50:26 PM PST 24 Feb 21 03:50:33 PM PST 24 7771416014 ps
T1069 /workspace/coverage/default/101.uart_fifo_reset.3903660893 Feb 21 03:52:07 PM PST 24 Feb 21 03:52:23 PM PST 24 21405843339 ps
T307 /workspace/coverage/default/2.uart_fifo_reset.2000232577 Feb 21 03:47:40 PM PST 24 Feb 21 03:48:54 PM PST 24 45357868356 ps
T1070 /workspace/coverage/default/79.uart_fifo_reset.1215575800 Feb 21 03:51:36 PM PST 24 Feb 21 03:52:47 PM PST 24 93265392484 ps
T1071 /workspace/coverage/default/5.uart_rx_start_bit_filter.1645901736 Feb 21 03:47:58 PM PST 24 Feb 21 03:48:10 PM PST 24 24927606973 ps
T1072 /workspace/coverage/default/42.uart_tx_rx.2226118462 Feb 21 03:50:50 PM PST 24 Feb 21 03:51:48 PM PST 24 44005870254 ps
T1073 /workspace/coverage/default/25.uart_alert_test.3928560958 Feb 21 03:49:06 PM PST 24 Feb 21 03:49:07 PM PST 24 17923820 ps
T1074 /workspace/coverage/default/14.uart_rx_oversample.3570195960 Feb 21 03:48:52 PM PST 24 Feb 21 03:49:00 PM PST 24 1764170063 ps
T1075 /workspace/coverage/default/0.uart_perf.3565051228 Feb 21 03:47:36 PM PST 24 Feb 21 03:58:55 PM PST 24 12218129378 ps
T1076 /workspace/coverage/default/0.uart_fifo_overflow.3100712617 Feb 21 03:47:47 PM PST 24 Feb 21 03:50:04 PM PST 24 81454563230 ps
T1077 /workspace/coverage/default/25.uart_perf.1021870289 Feb 21 03:49:10 PM PST 24 Feb 21 03:59:17 PM PST 24 10963323287 ps
T1078 /workspace/coverage/default/18.uart_stress_all.92818342 Feb 21 03:48:51 PM PST 24 Feb 21 03:54:43 PM PST 24 254714822483 ps
T1079 /workspace/coverage/default/26.uart_tx_rx.1903579304 Feb 21 03:49:30 PM PST 24 Feb 21 03:50:41 PM PST 24 21483109878 ps
T1080 /workspace/coverage/default/31.uart_rx_parity_err.2824849990 Feb 21 03:49:43 PM PST 24 Feb 21 03:50:25 PM PST 24 90218798329 ps
T1081 /workspace/coverage/default/25.uart_loopback.3272758521 Feb 21 03:49:02 PM PST 24 Feb 21 03:49:08 PM PST 24 5210895557 ps
T1082 /workspace/coverage/default/96.uart_fifo_reset.2910467862 Feb 21 03:51:57 PM PST 24 Feb 21 03:52:10 PM PST 24 12505090059 ps
T1083 /workspace/coverage/default/7.uart_tx_rx.1733894494 Feb 21 03:48:08 PM PST 24 Feb 21 03:49:30 PM PST 24 53722696685 ps
T1084 /workspace/coverage/default/34.uart_tx_rx.3694167389 Feb 21 03:49:46 PM PST 24 Feb 21 03:49:58 PM PST 24 26683807719 ps
T1085 /workspace/coverage/default/26.uart_intr.3324862910 Feb 21 03:49:06 PM PST 24 Feb 21 03:49:19 PM PST 24 13393360422 ps
T1086 /workspace/coverage/default/2.uart_perf.3297352792 Feb 21 03:47:55 PM PST 24 Feb 21 03:52:05 PM PST 24 17482145786 ps
T1087 /workspace/coverage/default/3.uart_rx_oversample.3769545488 Feb 21 03:47:43 PM PST 24 Feb 21 03:47:47 PM PST 24 1165262122 ps
T60 /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2465691420 Feb 21 03:51:25 PM PST 24 Feb 21 04:13:43 PM PST 24 515824642666 ps
T1088 /workspace/coverage/default/0.uart_tx_ovrd.2118383641 Feb 21 03:47:42 PM PST 24 Feb 21 03:47:58 PM PST 24 13558490889 ps
T1089 /workspace/coverage/default/194.uart_fifo_reset.286210041 Feb 21 03:52:41 PM PST 24 Feb 21 03:53:54 PM PST 24 43846286945 ps
T1090 /workspace/coverage/default/110.uart_fifo_reset.3379609369 Feb 21 03:52:07 PM PST 24 Feb 21 03:54:30 PM PST 24 107532307393 ps
T1091 /workspace/coverage/default/9.uart_loopback.2579398676 Feb 21 03:48:37 PM PST 24 Feb 21 03:48:41 PM PST 24 2336650988 ps
T1092 /workspace/coverage/default/6.uart_fifo_overflow.667018172 Feb 21 03:48:10 PM PST 24 Feb 21 03:49:22 PM PST 24 76398891135 ps
T1093 /workspace/coverage/default/0.uart_rx_parity_err.3377724756 Feb 21 03:47:55 PM PST 24 Feb 21 03:48:13 PM PST 24 102957144586 ps
T1094 /workspace/coverage/default/1.uart_fifo_overflow.2127933114 Feb 21 03:47:48 PM PST 24 Feb 21 03:48:42 PM PST 24 125744089837 ps
T1095 /workspace/coverage/default/18.uart_noise_filter.350327122 Feb 21 03:48:43 PM PST 24 Feb 21 03:49:41 PM PST 24 122128393227 ps
T1096 /workspace/coverage/default/5.uart_smoke.2056636689 Feb 21 03:48:30 PM PST 24 Feb 21 03:48:33 PM PST 24 277932578 ps
T1097 /workspace/coverage/default/25.uart_rx_parity_err.4158444394 Feb 21 03:49:09 PM PST 24 Feb 21 03:49:39 PM PST 24 21294550638 ps
T1098 /workspace/coverage/default/295.uart_fifo_reset.2958468178 Feb 21 03:53:39 PM PST 24 Feb 21 03:56:13 PM PST 24 101995523013 ps
T1099 /workspace/coverage/default/38.uart_alert_test.2891721755 Feb 21 03:50:26 PM PST 24 Feb 21 03:50:27 PM PST 24 14955099 ps
T373 /workspace/coverage/default/173.uart_fifo_reset.2103185702 Feb 21 03:52:26 PM PST 24 Feb 21 03:53:45 PM PST 24 163576917122 ps
T1100 /workspace/coverage/default/25.uart_rx_start_bit_filter.773892506 Feb 21 03:49:09 PM PST 24 Feb 21 03:49:26 PM PST 24 30912418243 ps
T1101 /workspace/coverage/default/29.uart_long_xfer_wo_dly.4251702974 Feb 21 03:49:43 PM PST 24 Feb 21 03:52:43 PM PST 24 105997955682 ps
T1102 /workspace/coverage/default/13.uart_fifo_full.4142162316 Feb 21 03:48:38 PM PST 24 Feb 21 03:50:11 PM PST 24 47695502947 ps
T394 /workspace/coverage/default/1.uart_fifo_reset.2094992447 Feb 21 03:47:44 PM PST 24 Feb 21 03:48:29 PM PST 24 65164067155 ps
T1103 /workspace/coverage/default/27.uart_perf.4174824340 Feb 21 03:49:17 PM PST 24 Feb 21 03:55:14 PM PST 24 13152084051 ps
T1104 /workspace/coverage/default/18.uart_fifo_full.673992427 Feb 21 03:48:43 PM PST 24 Feb 21 03:49:12 PM PST 24 50795640205 ps
T1105 /workspace/coverage/default/2.uart_long_xfer_wo_dly.265500126 Feb 21 03:47:43 PM PST 24 Feb 21 04:02:21 PM PST 24 128961208877 ps
T343 /workspace/coverage/default/131.uart_fifo_reset.343824573 Feb 21 03:52:12 PM PST 24 Feb 21 03:52:55 PM PST 24 108525606547 ps
T98 /workspace/coverage/default/4.uart_sec_cm.4185534650 Feb 21 03:48:06 PM PST 24 Feb 21 03:48:07 PM PST 24 152950599 ps
T1106 /workspace/coverage/cover_reg_top/37.uart_intr_test.2286439556 Feb 21 12:35:09 PM PST 24 Feb 21 12:35:10 PM PST 24 61265303 ps
T73 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2141675280 Feb 21 12:35:13 PM PST 24 Feb 21 12:35:15 PM PST 24 86720962 ps
T87 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3423945553 Feb 21 12:34:37 PM PST 24 Feb 21 12:34:39 PM PST 24 245917823 ps
T88 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.818696996 Feb 21 12:34:56 PM PST 24 Feb 21 12:35:01 PM PST 24 45964738 ps
T1107 /workspace/coverage/cover_reg_top/18.uart_intr_test.3311153505 Feb 21 12:35:25 PM PST 24 Feb 21 12:35:26 PM PST 24 14815023 ps
T74 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3213063192 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 27457986 ps
T1108 /workspace/coverage/cover_reg_top/6.uart_intr_test.3547621995 Feb 21 12:36:13 PM PST 24 Feb 21 12:36:15 PM PST 24 36388598 ps
T89 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2317126691 Feb 21 12:35:34 PM PST 24 Feb 21 12:35:36 PM PST 24 58391247 ps
T75 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2693271213 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:58 PM PST 24 36040906 ps
T1109 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3029927043 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:09 PM PST 24 233429072 ps
T76 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3131167752 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 18727305 ps
T1110 /workspace/coverage/cover_reg_top/3.uart_intr_test.2935403605 Feb 21 12:34:37 PM PST 24 Feb 21 12:34:39 PM PST 24 22672024 ps
T1111 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2780698821 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:51 PM PST 24 227696407 ps
T90 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.604293434 Feb 21 12:35:00 PM PST 24 Feb 21 12:35:04 PM PST 24 69060126 ps
T77 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2836039179 Feb 21 12:34:52 PM PST 24 Feb 21 12:34:58 PM PST 24 30914015 ps
T1112 /workspace/coverage/cover_reg_top/16.uart_intr_test.1453144262 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:56 PM PST 24 17252332 ps
T1113 /workspace/coverage/cover_reg_top/13.uart_intr_test.3022768039 Feb 21 12:34:57 PM PST 24 Feb 21 12:35:01 PM PST 24 23480396 ps
T1114 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3790694815 Feb 21 12:35:36 PM PST 24 Feb 21 12:35:39 PM PST 24 495471578 ps
T1115 /workspace/coverage/cover_reg_top/10.uart_tl_errors.4070132983 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:58 PM PST 24 22740295 ps
T1116 /workspace/coverage/cover_reg_top/17.uart_intr_test.256413987 Feb 21 12:36:45 PM PST 24 Feb 21 12:36:46 PM PST 24 13696675 ps
T78 /workspace/coverage/cover_reg_top/7.uart_csr_rw.53243878 Feb 21 12:34:55 PM PST 24 Feb 21 12:34:59 PM PST 24 22870866 ps
T1117 /workspace/coverage/cover_reg_top/40.uart_intr_test.732880795 Feb 21 12:35:06 PM PST 24 Feb 21 12:35:09 PM PST 24 15851714 ps
T79 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2588248325 Feb 21 12:36:43 PM PST 24 Feb 21 12:36:46 PM PST 24 16789190 ps
T1118 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2245057712 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:58 PM PST 24 16126467 ps
T1119 /workspace/coverage/cover_reg_top/8.uart_csr_rw.537633416 Feb 21 12:34:49 PM PST 24 Feb 21 12:34:56 PM PST 24 26380057 ps
T1120 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2393847162 Feb 21 12:34:54 PM PST 24 Feb 21 12:35:00 PM PST 24 282341741 ps
T61 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3488463438 Feb 21 12:34:45 PM PST 24 Feb 21 12:34:47 PM PST 24 38751396 ps
T1121 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1319774418 Feb 21 12:34:38 PM PST 24 Feb 21 12:34:40 PM PST 24 147954505 ps
T80 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1815521222 Feb 21 12:34:40 PM PST 24 Feb 21 12:34:42 PM PST 24 45161354 ps
T1122 /workspace/coverage/cover_reg_top/4.uart_tl_errors.546129288 Feb 21 12:34:38 PM PST 24 Feb 21 12:34:42 PM PST 24 130102203 ps
T1123 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3936662018 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 144714473 ps
T1124 /workspace/coverage/cover_reg_top/49.uart_intr_test.734730978 Feb 21 12:35:00 PM PST 24 Feb 21 12:35:03 PM PST 24 13068973 ps
T1125 /workspace/coverage/cover_reg_top/43.uart_intr_test.1699119388 Feb 21 12:34:59 PM PST 24 Feb 21 12:35:02 PM PST 24 13559209 ps
T1126 /workspace/coverage/cover_reg_top/48.uart_intr_test.2374252197 Feb 21 12:34:55 PM PST 24 Feb 21 12:34:59 PM PST 24 14596268 ps
T81 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3494327342 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:09 PM PST 24 22466042 ps
T1127 /workspace/coverage/cover_reg_top/44.uart_intr_test.4038900897 Feb 21 12:34:58 PM PST 24 Feb 21 12:35:01 PM PST 24 44049941 ps
T91 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.985350788 Feb 21 12:34:55 PM PST 24 Feb 21 12:35:00 PM PST 24 321833795 ps
T1128 /workspace/coverage/cover_reg_top/5.uart_intr_test.3175414891 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:55 PM PST 24 25330299 ps
T1129 /workspace/coverage/cover_reg_top/35.uart_intr_test.531298249 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:57 PM PST 24 15995994 ps
T62 /workspace/coverage/cover_reg_top/5.uart_csr_rw.166540552 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:57 PM PST 24 13930137 ps
T92 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1424624459 Feb 21 12:35:58 PM PST 24 Feb 21 12:36:10 PM PST 24 69273919 ps
T1130 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1617108927 Feb 21 12:35:58 PM PST 24 Feb 21 12:36:00 PM PST 24 364362089 ps
T1131 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2693562855 Feb 21 12:34:35 PM PST 24 Feb 21 12:34:36 PM PST 24 25314811 ps
T93 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1141528982 Feb 21 12:35:07 PM PST 24 Feb 21 12:35:10 PM PST 24 191948590 ps
T1132 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1386904778 Feb 21 12:34:57 PM PST 24 Feb 21 12:35:01 PM PST 24 356093224 ps
T1133 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1992738326 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 169815168 ps
T1134 /workspace/coverage/cover_reg_top/22.uart_intr_test.2826482231 Feb 21 12:35:08 PM PST 24 Feb 21 12:35:10 PM PST 24 75845410 ps
T1135 /workspace/coverage/cover_reg_top/10.uart_intr_test.53492688 Feb 21 12:34:58 PM PST 24 Feb 21 12:35:01 PM PST 24 11401296 ps
T1136 /workspace/coverage/cover_reg_top/31.uart_intr_test.4131162299 Feb 21 12:35:05 PM PST 24 Feb 21 12:35:09 PM PST 24 15401380 ps
T1137 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3450053680 Feb 21 12:35:13 PM PST 24 Feb 21 12:35:15 PM PST 24 62045803 ps
T1138 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3792631834 Feb 21 12:34:56 PM PST 24 Feb 21 12:34:59 PM PST 24 82554802 ps
T1139 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2776609991 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 22401042 ps
T1140 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1052004908 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:48 PM PST 24 81368861 ps
T1141 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2553897833 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:10 PM PST 24 186798537 ps
T68 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1705381610 Feb 21 12:34:56 PM PST 24 Feb 21 12:35:04 PM PST 24 13964556 ps
T1142 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3760451497 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:49 PM PST 24 19254323 ps
T1143 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2281888350 Feb 21 12:35:01 PM PST 24 Feb 21 12:35:05 PM PST 24 60227841 ps
T1144 /workspace/coverage/cover_reg_top/1.uart_intr_test.1451611625 Feb 21 12:35:34 PM PST 24 Feb 21 12:35:35 PM PST 24 14879159 ps
T94 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2911700274 Feb 21 12:35:12 PM PST 24 Feb 21 12:35:14 PM PST 24 178757305 ps
T63 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.190464302 Feb 21 12:35:51 PM PST 24 Feb 21 12:35:52 PM PST 24 31175671 ps
T1145 /workspace/coverage/cover_reg_top/9.uart_intr_test.844584398 Feb 21 12:34:59 PM PST 24 Feb 21 12:35:02 PM PST 24 22146777 ps
T1146 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3773233471 Feb 21 12:34:32 PM PST 24 Feb 21 12:34:35 PM PST 24 59845811 ps
T1147 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1721859925 Feb 21 12:35:44 PM PST 24 Feb 21 12:35:46 PM PST 24 44752829 ps
T1148 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2485735843 Feb 21 12:34:42 PM PST 24 Feb 21 12:34:44 PM PST 24 147716767 ps
T1149 /workspace/coverage/cover_reg_top/15.uart_tl_errors.805239738 Feb 21 12:34:57 PM PST 24 Feb 21 12:35:02 PM PST 24 22808657 ps
T1150 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1402575912 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:13 PM PST 24 33408907 ps
T1151 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2391241745 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:59 PM PST 24 15771713 ps
T1152 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.681058777 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:51 PM PST 24 452875980 ps
T1153 /workspace/coverage/cover_reg_top/8.uart_intr_test.3625736725 Feb 21 12:35:01 PM PST 24 Feb 21 12:35:05 PM PST 24 25069811 ps
T1154 /workspace/coverage/cover_reg_top/24.uart_intr_test.1313735581 Feb 21 12:35:09 PM PST 24 Feb 21 12:35:10 PM PST 24 18541669 ps
T401 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2239552445 Feb 21 12:35:45 PM PST 24 Feb 21 12:35:46 PM PST 24 244853721 ps
T400 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2012190596 Feb 21 12:36:15 PM PST 24 Feb 21 12:36:17 PM PST 24 131898352 ps
T64 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2754449019 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:50 PM PST 24 29942603 ps
T1155 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.977959689 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 55513741 ps
T1156 /workspace/coverage/cover_reg_top/39.uart_intr_test.1717528082 Feb 21 12:35:25 PM PST 24 Feb 21 12:35:26 PM PST 24 13912254 ps
T1157 /workspace/coverage/cover_reg_top/14.uart_intr_test.791337355 Feb 21 12:35:05 PM PST 24 Feb 21 12:35:09 PM PST 24 48587006 ps
T1158 /workspace/coverage/cover_reg_top/38.uart_intr_test.848090503 Feb 21 12:34:59 PM PST 24 Feb 21 12:35:02 PM PST 24 46442204 ps
T1159 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4012304350 Feb 21 12:35:08 PM PST 24 Feb 21 12:35:16 PM PST 24 103433000 ps
T1160 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2689798897 Feb 21 12:34:58 PM PST 24 Feb 21 12:35:01 PM PST 24 44953216 ps
T1161 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.758247232 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:49 PM PST 24 95763782 ps
T1162 /workspace/coverage/cover_reg_top/20.uart_intr_test.3784236113 Feb 21 12:35:08 PM PST 24 Feb 21 12:35:09 PM PST 24 16574023 ps
T1163 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2777766851 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:56 PM PST 24 65474040 ps
T1164 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2652839373 Feb 21 12:34:56 PM PST 24 Feb 21 12:35:01 PM PST 24 74531829 ps
T1165 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2242644238 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:44 PM PST 24 13112995 ps
T1166 /workspace/coverage/cover_reg_top/27.uart_intr_test.1808066170 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 13802056 ps
T1167 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1756841009 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:58 PM PST 24 69474872 ps
T1168 /workspace/coverage/cover_reg_top/28.uart_intr_test.3613785306 Feb 21 12:35:02 PM PST 24 Feb 21 12:35:08 PM PST 24 140873779 ps
T1169 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2857814802 Feb 21 12:34:55 PM PST 24 Feb 21 12:35:00 PM PST 24 33855292 ps
T1170 /workspace/coverage/cover_reg_top/0.uart_tl_errors.808093567 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:48 PM PST 24 68085568 ps
T1171 /workspace/coverage/cover_reg_top/32.uart_intr_test.3233044449 Feb 21 12:35:19 PM PST 24 Feb 21 12:35:20 PM PST 24 12383038 ps
T65 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1417066891 Feb 21 12:34:39 PM PST 24 Feb 21 12:34:42 PM PST 24 16472355 ps
T1172 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3074621639 Feb 21 12:36:23 PM PST 24 Feb 21 12:36:26 PM PST 24 291957232 ps
T1173 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3912452391 Feb 21 12:35:44 PM PST 24 Feb 21 12:35:46 PM PST 24 49581865 ps
T1174 /workspace/coverage/cover_reg_top/36.uart_intr_test.342148910 Feb 21 12:35:45 PM PST 24 Feb 21 12:35:46 PM PST 24 13092291 ps
T1175 /workspace/coverage/cover_reg_top/25.uart_intr_test.2910060841 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 11148886 ps
T1176 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3466515481 Feb 21 12:34:45 PM PST 24 Feb 21 12:34:48 PM PST 24 1015787750 ps
T1177 /workspace/coverage/cover_reg_top/26.uart_intr_test.888678097 Feb 21 12:34:52 PM PST 24 Feb 21 12:34:58 PM PST 24 36443358 ps
T95 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1692831714 Feb 21 12:34:55 PM PST 24 Feb 21 12:35:00 PM PST 24 93243973 ps
T1178 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1272614399 Feb 21 12:35:00 PM PST 24 Feb 21 12:35:04 PM PST 24 71999094 ps
T1179 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2047633640 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:58 PM PST 24 211406423 ps
T1180 /workspace/coverage/cover_reg_top/42.uart_intr_test.157752795 Feb 21 12:35:34 PM PST 24 Feb 21 12:35:35 PM PST 24 22621524 ps
T1181 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2623382816 Feb 21 12:36:44 PM PST 24 Feb 21 12:36:46 PM PST 24 57295431 ps
T1182 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1105355344 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:59 PM PST 24 66778465 ps
T1183 /workspace/coverage/cover_reg_top/33.uart_intr_test.1407267149 Feb 21 12:35:01 PM PST 24 Feb 21 12:35:05 PM PST 24 95437292 ps
T1184 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3522772281 Feb 21 12:35:16 PM PST 24 Feb 21 12:35:17 PM PST 24 43214480 ps
T1185 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1327693169 Feb 21 12:34:55 PM PST 24 Feb 21 12:34:59 PM PST 24 59434512 ps
T96 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4289421430 Feb 21 12:36:44 PM PST 24 Feb 21 12:36:47 PM PST 24 143736530 ps
T1186 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.560757755 Feb 21 12:34:44 PM PST 24 Feb 21 12:34:47 PM PST 24 148972245 ps
T66 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1253815561 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:49 PM PST 24 142780787 ps
T1187 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2362461116 Feb 21 12:34:52 PM PST 24 Feb 21 12:34:59 PM PST 24 307000706 ps
T1188 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3497917576 Feb 21 12:36:43 PM PST 24 Feb 21 12:36:47 PM PST 24 183884890 ps
T1189 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3014972207 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:09 PM PST 24 26712185 ps
T1190 /workspace/coverage/cover_reg_top/2.uart_intr_test.3267450819 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:49 PM PST 24 30698428 ps
T1191 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1005485696 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:59 PM PST 24 19426917 ps
T1192 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2473550536 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:59 PM PST 24 90863949 ps
T1193 /workspace/coverage/cover_reg_top/4.uart_intr_test.288447857 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:55 PM PST 24 44361068 ps
T1194 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.686041340 Feb 21 12:35:44 PM PST 24 Feb 21 12:35:45 PM PST 24 18223008 ps
T1195 /workspace/coverage/cover_reg_top/34.uart_intr_test.2362123358 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 12530042 ps
T1196 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1034775938 Feb 21 12:35:16 PM PST 24 Feb 21 12:35:17 PM PST 24 48161088 ps
T1197 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1392622215 Feb 21 12:36:23 PM PST 24 Feb 21 12:36:25 PM PST 24 19543737 ps
T1198 /workspace/coverage/cover_reg_top/11.uart_intr_test.2023197553 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:50 PM PST 24 35871179 ps
T1199 /workspace/coverage/cover_reg_top/21.uart_intr_test.2411430032 Feb 21 12:35:05 PM PST 24 Feb 21 12:35:09 PM PST 24 12371614 ps
T1200 /workspace/coverage/cover_reg_top/7.uart_intr_test.2376622697 Feb 21 12:36:24 PM PST 24 Feb 21 12:36:25 PM PST 24 21570793 ps
T1201 /workspace/coverage/cover_reg_top/0.uart_intr_test.3150482655 Feb 21 12:34:29 PM PST 24 Feb 21 12:34:30 PM PST 24 32476096 ps
T1202 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.251184673 Feb 21 12:35:05 PM PST 24 Feb 21 12:35:09 PM PST 24 68522282 ps
T1203 /workspace/coverage/cover_reg_top/47.uart_intr_test.4136942215 Feb 21 12:35:02 PM PST 24 Feb 21 12:35:08 PM PST 24 73705068 ps
T1204 /workspace/coverage/cover_reg_top/14.uart_csr_rw.4052656716 Feb 21 12:35:12 PM PST 24 Feb 21 12:35:13 PM PST 24 16911781 ps
T67 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2906854305 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:55 PM PST 24 41229887 ps
T1205 /workspace/coverage/cover_reg_top/15.uart_intr_test.4007162703 Feb 21 12:35:12 PM PST 24 Feb 21 12:35:13 PM PST 24 18663864 ps
T1206 /workspace/coverage/cover_reg_top/6.uart_csr_rw.643050913 Feb 21 12:34:57 PM PST 24 Feb 21 12:35:01 PM PST 24 29247677 ps
T1207 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1997805542 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:50 PM PST 24 374875189 ps
T1208 /workspace/coverage/cover_reg_top/9.uart_csr_rw.4103455668 Feb 21 12:34:45 PM PST 24 Feb 21 12:34:47 PM PST 24 17406787 ps
T1209 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2021197912 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:44 PM PST 24 20761190 ps
T1210 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2244633307 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:44 PM PST 24 17225372 ps
T1211 /workspace/coverage/cover_reg_top/19.uart_intr_test.697056630 Feb 21 12:36:23 PM PST 24 Feb 21 12:36:25 PM PST 24 40002630 ps
T1212 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1086971798 Feb 21 12:35:08 PM PST 24 Feb 21 12:35:10 PM PST 24 103298396 ps
T1213 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3206940836 Feb 21 12:34:49 PM PST 24 Feb 21 12:34:57 PM PST 24 75099292 ps
T1214 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2219121315 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 56515205 ps
T1215 /workspace/coverage/cover_reg_top/23.uart_intr_test.1168410247 Feb 21 12:35:20 PM PST 24 Feb 21 12:35:21 PM PST 24 38051638 ps
T1216 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.992012371 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 155241462 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2639159696 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:56 PM PST 24 74769753 ps
T70 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2514734992 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:58 PM PST 24 30467774 ps
T71 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4086068250 Feb 21 12:34:49 PM PST 24 Feb 21 12:34:57 PM PST 24 25123306 ps
T1217 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2531123219 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:58 PM PST 24 36387266 ps
T1218 /workspace/coverage/cover_reg_top/30.uart_intr_test.4166861713 Feb 21 12:34:48 PM PST 24 Feb 21 12:34:56 PM PST 24 14802459 ps
T1219 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3626058560 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:44 PM PST 24 15553645 ps
T1220 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2908741727 Feb 21 12:34:52 PM PST 24 Feb 21 12:34:58 PM PST 24 47041707 ps
T1221 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2813568251 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:49 PM PST 24 51811851 ps
T1222 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3260122838 Feb 21 12:35:02 PM PST 24 Feb 21 12:35:08 PM PST 24 15752562 ps
T1223 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2161806343 Feb 21 12:35:01 PM PST 24 Feb 21 12:35:06 PM PST 24 92634671 ps
T1224 /workspace/coverage/cover_reg_top/29.uart_intr_test.3149799475 Feb 21 12:35:01 PM PST 24 Feb 21 12:35:07 PM PST 24 48888189 ps
T1225 /workspace/coverage/cover_reg_top/46.uart_intr_test.732272221 Feb 21 12:34:51 PM PST 24 Feb 21 12:34:58 PM PST 24 45715569 ps
T1226 /workspace/coverage/cover_reg_top/41.uart_intr_test.1667352595 Feb 21 12:35:07 PM PST 24 Feb 21 12:35:09 PM PST 24 59683154 ps
T1227 /workspace/coverage/cover_reg_top/12.uart_intr_test.2401161349 Feb 21 12:35:44 PM PST 24 Feb 21 12:35:45 PM PST 24 87700248 ps
T1228 /workspace/coverage/cover_reg_top/45.uart_intr_test.2975467714 Feb 21 12:35:25 PM PST 24 Feb 21 12:35:26 PM PST 24 13885682 ps
T72 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2088372749 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:09 PM PST 24 61405439 ps
T1229 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3086293114 Feb 21 12:35:04 PM PST 24 Feb 21 12:35:10 PM PST 24 101686008 ps
T1230 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1829053296 Feb 21 12:36:45 PM PST 24 Feb 21 12:36:47 PM PST 24 68322587 ps
T1231 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1163898129 Feb 21 12:35:44 PM PST 24 Feb 21 12:35:45 PM PST 24 130548271 ps
T1232 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2828363901 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:07 PM PST 24 108335553 ps
T1233 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3812547737 Feb 21 12:35:06 PM PST 24 Feb 21 12:35:09 PM PST 24 16686386 ps
T1234 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.257207950 Feb 21 12:34:31 PM PST 24 Feb 21 12:34:32 PM PST 24 104356243 ps
T1235 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3936916630 Feb 21 12:34:54 PM PST 24 Feb 21 12:34:59 PM PST 24 18197907 ps
T1236 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2810805726 Feb 21 12:36:24 PM PST 24 Feb 21 12:36:26 PM PST 24 57684916 ps
T1237 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.230973362 Feb 21 12:35:45 PM PST 24 Feb 21 12:35:46 PM PST 24 25040792 ps

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3215059284
Short name T7
Test name
Test status
Simulation time 87697939244 ps
CPU time 640.87 seconds
Started Feb 21 03:48:57 PM PST 24
Finished Feb 21 03:59:39 PM PST 24
Peak memory 199724 kb
Host smart-650bd43c-8356-4512-9557-1651adf9dc3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215059284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3215059284
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.509806179
Short name T25
Test name
Test status
Simulation time 167875493744 ps
CPU time 451.66 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:59:25 PM PST 24
Peak memory 224536 kb
Host smart-79e7d550-40cc-4af2-acd9-a70d6af8b317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509806179 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.509806179
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.3099178936
Short name T12
Test name
Test status
Simulation time 457245280707 ps
CPU time 2104.07 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 04:26:27 PM PST 24
Peak memory 199644 kb
Host smart-cebe2bd7-a8de-412f-8fce-14639cd2b992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099178936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3099178936
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all.2815576438
Short name T27
Test name
Test status
Simulation time 379611477914 ps
CPU time 246.14 seconds
Started Feb 21 03:49:39 PM PST 24
Finished Feb 21 03:53:46 PM PST 24
Peak memory 199836 kb
Host smart-e0545bd2-47e2-475d-a860-65db4c9905f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815576438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2815576438
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2955125027
Short name T83
Test name
Test status
Simulation time 113365474668 ps
CPU time 53.01 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 199684 kb
Host smart-d944ccec-5c36-475b-9659-2e60dfb2791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955125027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2955125027
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3407691519
Short name T16
Test name
Test status
Simulation time 196923404010 ps
CPU time 314.57 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:54:59 PM PST 24
Peak memory 199624 kb
Host smart-44bceed2-2982-49af-8f28-7314e0f48e28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407691519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3407691519
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/27.uart_stress_all.3006372832
Short name T228
Test name
Test status
Simulation time 257247448561 ps
CPU time 364.63 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:55:23 PM PST 24
Peak memory 215420 kb
Host smart-e8185bbf-f88a-4f96-be1c-188631bdb3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006372832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3006372832
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3773773902
Short name T31
Test name
Test status
Simulation time 38618541 ps
CPU time 0.77 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:43 PM PST 24
Peak memory 217036 kb
Host smart-f18e0d1f-3d46-48a4-b7f3-dd974a058cee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773773902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3773773902
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/40.uart_stress_all.3594719268
Short name T419
Test name
Test status
Simulation time 620579449407 ps
CPU time 155.42 seconds
Started Feb 21 03:50:33 PM PST 24
Finished Feb 21 03:53:09 PM PST 24
Peak memory 215672 kb
Host smart-4ccf83ae-14f7-4915-b10e-5d0e728dff83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594719268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3594719268
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all.2037548857
Short name T203
Test name
Test status
Simulation time 674375603053 ps
CPU time 552.87 seconds
Started Feb 21 03:49:54 PM PST 24
Finished Feb 21 03:59:07 PM PST 24
Peak memory 208044 kb
Host smart-e59ab4f2-a692-42a6-a3ea-236b98f0f412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037548857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2037548857
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4129828123
Short name T49
Test name
Test status
Simulation time 179728604772 ps
CPU time 278.68 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:56:32 PM PST 24
Peak memory 216432 kb
Host smart-e86033be-ee64-4ed3-86fb-839710ffb3d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129828123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4129828123
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3554842926
Short name T18
Test name
Test status
Simulation time 309917647206 ps
CPU time 461.1 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:56:47 PM PST 24
Peak memory 199608 kb
Host smart-abd86fbe-90ba-48d7-9141-05252f39cdf9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554842926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3554842926
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1898870342
Short name T36
Test name
Test status
Simulation time 42002411482 ps
CPU time 538.14 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:59:43 PM PST 24
Peak memory 215952 kb
Host smart-b6f6b4a9-fe8d-4945-9d75-7b87ca3018a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898870342 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1898870342
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1162663973
Short name T82
Test name
Test status
Simulation time 156210574995 ps
CPU time 304.45 seconds
Started Feb 21 03:51:22 PM PST 24
Finished Feb 21 03:56:28 PM PST 24
Peak memory 199680 kb
Host smart-41573394-e1fc-4b39-91af-227ba0742232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162663973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1162663973
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.3251882377
Short name T267
Test name
Test status
Simulation time 2781432317706 ps
CPU time 1119.47 seconds
Started Feb 21 03:47:46 PM PST 24
Finished Feb 21 04:06:26 PM PST 24
Peak memory 199852 kb
Host smart-37f7fc74-db9b-47fc-8a34-2835ff32a62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251882377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3251882377
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.3864213890
Short name T415
Test name
Test status
Simulation time 181668736716 ps
CPU time 83.9 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:50:06 PM PST 24
Peak memory 199648 kb
Host smart-8387e1bd-dce6-4068-b5d5-521801ace3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864213890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3864213890
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.604293434
Short name T90
Test name
Test status
Simulation time 69060126 ps
CPU time 1.32 seconds
Started Feb 21 12:35:00 PM PST 24
Finished Feb 21 12:35:04 PM PST 24
Peak memory 199452 kb
Host smart-cb8ca4a4-6177-4604-a534-3db857d0406d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604293434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.604293434
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.318889361
Short name T351
Test name
Test status
Simulation time 80949496357 ps
CPU time 24.71 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:49:03 PM PST 24
Peak memory 198868 kb
Host smart-991a3cf1-5e7d-452e-ac41-9fb96472dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318889361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.318889361
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.323681681
Short name T473
Test name
Test status
Simulation time 11386434 ps
CPU time 0.56 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:01 PM PST 24
Peak memory 194096 kb
Host smart-66fae5c2-10f0-49f6-acf1-b8de29e596cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323681681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.323681681
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.166540552
Short name T62
Test name
Test status
Simulation time 13930137 ps
CPU time 0.56 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 195440 kb
Host smart-bac0c016-8fef-427d-9f21-005dc7835623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166540552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.166540552
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3008863898
Short name T313
Test name
Test status
Simulation time 221006468892 ps
CPU time 335.18 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:54:40 PM PST 24
Peak memory 199660 kb
Host smart-53c08906-121e-460a-84a3-c535eb398b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008863898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3008863898
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1199667806
Short name T331
Test name
Test status
Simulation time 24262548763 ps
CPU time 24.29 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:49:18 PM PST 24
Peak memory 199492 kb
Host smart-d4c7c760-b14b-4369-9858-202073fc3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199667806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1199667806
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2819036350
Short name T138
Test name
Test status
Simulation time 104464173241 ps
CPU time 44.07 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:52:37 PM PST 24
Peak memory 199644 kb
Host smart-b3702f28-023b-4189-864d-fd39cd104a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819036350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2819036350
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1609019435
Short name T35
Test name
Test status
Simulation time 100214791782 ps
CPU time 500.39 seconds
Started Feb 21 03:51:37 PM PST 24
Finished Feb 21 03:59:58 PM PST 24
Peak memory 216328 kb
Host smart-82f8268f-85c2-4d97-8b2d-05b735d90afe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609019435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1609019435
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.250887589
Short name T196
Test name
Test status
Simulation time 360672537754 ps
CPU time 272.46 seconds
Started Feb 21 03:51:51 PM PST 24
Finished Feb 21 03:56:25 PM PST 24
Peak memory 199640 kb
Host smart-14c468fd-b64c-45e8-a214-44196805770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250887589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.250887589
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1528191686
Short name T10
Test name
Test status
Simulation time 133255695131 ps
CPU time 194.9 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:55:26 PM PST 24
Peak memory 199608 kb
Host smart-27200a79-0c18-4fe3-9aa9-a0148b94c6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528191686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1528191686
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4289421430
Short name T96
Test name
Test status
Simulation time 143736530 ps
CPU time 1.18 seconds
Started Feb 21 12:36:44 PM PST 24
Finished Feb 21 12:36:47 PM PST 24
Peak memory 198864 kb
Host smart-c6129f57-1b68-44da-8e05-2ea38326bae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289421430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4289421430
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3633927195
Short name T1
Test name
Test status
Simulation time 123930543831 ps
CPU time 509.51 seconds
Started Feb 21 03:53:21 PM PST 24
Finished Feb 21 04:01:51 PM PST 24
Peak memory 199604 kb
Host smart-b38ec372-0182-4fc1-a26b-ec36815f9cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633927195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3633927195
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.427549680
Short name T2
Test name
Test status
Simulation time 194898016368 ps
CPU time 44.74 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:46 PM PST 24
Peak memory 199680 kb
Host smart-508bdaf3-c681-470f-bd7d-87602ba210db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427549680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.427549680
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3406127033
Short name T123
Test name
Test status
Simulation time 15799847141 ps
CPU time 28.91 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:53:49 PM PST 24
Peak memory 199708 kb
Host smart-3bef5d2b-d637-4072-b758-37456f76cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406127033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3406127033
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.730073864
Short name T141
Test name
Test status
Simulation time 140974985089 ps
CPU time 212.14 seconds
Started Feb 21 03:49:46 PM PST 24
Finished Feb 21 03:53:19 PM PST 24
Peak memory 199628 kb
Host smart-008b58f8-f3a3-426e-8b00-262c1b7091c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730073864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.730073864
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_perf.3413318647
Short name T9
Test name
Test status
Simulation time 17819662554 ps
CPU time 224.68 seconds
Started Feb 21 03:50:30 PM PST 24
Finished Feb 21 03:54:15 PM PST 24
Peak memory 199660 kb
Host smart-cd6f1b9a-c339-4499-9683-1a0bf23f82e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413318647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3413318647
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/25.uart_stress_all.339453875
Short name T114
Test name
Test status
Simulation time 288790447462 ps
CPU time 344.22 seconds
Started Feb 21 03:49:07 PM PST 24
Finished Feb 21 03:54:52 PM PST 24
Peak memory 199644 kb
Host smart-a30649dd-6a3b-41e8-918b-d25d113dd824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339453875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.339453875
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4040983414
Short name T189
Test name
Test status
Simulation time 931308649993 ps
CPU time 566.06 seconds
Started Feb 21 03:51:44 PM PST 24
Finished Feb 21 04:01:11 PM PST 24
Peak memory 212824 kb
Host smart-a7bf8937-3243-4225-b2c1-6d463ecd9668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040983414 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4040983414
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.445686959
Short name T157
Test name
Test status
Simulation time 221030049652 ps
CPU time 29.77 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 03:54:09 PM PST 24
Peak memory 199704 kb
Host smart-73c0592e-52f5-45d6-8acb-11be1720e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445686959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.445686959
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1566746294
Short name T165
Test name
Test status
Simulation time 43780450188 ps
CPU time 93.29 seconds
Started Feb 21 03:52:08 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 199620 kb
Host smart-0598bf9a-4b08-4044-8906-f42b072953a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566746294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1566746294
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3629278572
Short name T299
Test name
Test status
Simulation time 65337222366 ps
CPU time 251.81 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:52:48 PM PST 24
Peak memory 216244 kb
Host smart-04cbffb2-3d09-476d-929c-6ec7483504c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629278572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3629278572
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.615492194
Short name T231
Test name
Test status
Simulation time 85462503660 ps
CPU time 143.11 seconds
Started Feb 21 03:52:51 PM PST 24
Finished Feb 21 03:55:14 PM PST 24
Peak memory 199712 kb
Host smart-f7d9d93c-0755-4973-9ad9-a3c04cda79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615492194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.615492194
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1608374293
Short name T135
Test name
Test status
Simulation time 100741308187 ps
CPU time 166.1 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:56:24 PM PST 24
Peak memory 199460 kb
Host smart-7b6b6684-03e4-4441-95d6-d6c50cec3ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608374293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1608374293
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.4003413153
Short name T104
Test name
Test status
Simulation time 300451554346 ps
CPU time 245.13 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:53:55 PM PST 24
Peak memory 208148 kb
Host smart-e2fb7305-1e04-4e97-8f0a-6aa0e1e60dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003413153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4003413153
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2229831626
Short name T195
Test name
Test status
Simulation time 104458554132 ps
CPU time 45.39 seconds
Started Feb 21 03:51:44 PM PST 24
Finished Feb 21 03:52:30 PM PST 24
Peak memory 199544 kb
Host smart-8a3a083e-6ebe-4a2c-bd90-0708c443933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229831626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2229831626
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3463587935
Short name T41
Test name
Test status
Simulation time 199882316198 ps
CPU time 1025.41 seconds
Started Feb 21 03:48:20 PM PST 24
Finished Feb 21 04:05:26 PM PST 24
Peak memory 216140 kb
Host smart-20577a71-03b8-41b1-854d-49acebf7b7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463587935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3463587935
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3854929451
Short name T188
Test name
Test status
Simulation time 110533346078 ps
CPU time 124.87 seconds
Started Feb 21 03:52:35 PM PST 24
Finished Feb 21 03:54:40 PM PST 24
Peak memory 199720 kb
Host smart-69aecbfe-50fa-4098-bee6-17ef5c2c2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854929451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3854929451
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1852683616
Short name T320
Test name
Test status
Simulation time 1226063710835 ps
CPU time 1142.5 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 04:07:59 PM PST 24
Peak memory 224620 kb
Host smart-ac8ffd26-68f6-40b2-9944-eb092987dee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852683616 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1852683616
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.3059989187
Short name T152
Test name
Test status
Simulation time 340102635211 ps
CPU time 550.56 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:57:15 PM PST 24
Peak memory 199616 kb
Host smart-328b4ff1-7c80-43cc-8633-9b99214655d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059989187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3059989187
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1254644969
Short name T290
Test name
Test status
Simulation time 248020949954 ps
CPU time 44.14 seconds
Started Feb 21 03:52:06 PM PST 24
Finished Feb 21 03:52:50 PM PST 24
Peak memory 199664 kb
Host smart-7dcdacc6-71f8-42e7-8a08-274c27c6074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254644969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1254644969
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.271294051
Short name T308
Test name
Test status
Simulation time 89140029936 ps
CPU time 36.45 seconds
Started Feb 21 03:52:13 PM PST 24
Finished Feb 21 03:52:50 PM PST 24
Peak memory 199584 kb
Host smart-5ba0b6e9-32c2-40be-a74b-8b2571705bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271294051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.271294051
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2361565151
Short name T268
Test name
Test status
Simulation time 15309579941 ps
CPU time 28.13 seconds
Started Feb 21 03:52:25 PM PST 24
Finished Feb 21 03:52:53 PM PST 24
Peak memory 199700 kb
Host smart-be5284b0-e3ce-4b22-8a31-d1d01ec3cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361565151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2361565151
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2992805723
Short name T353
Test name
Test status
Simulation time 237116226342 ps
CPU time 47.84 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:35 PM PST 24
Peak memory 199692 kb
Host smart-bb8dc5e4-aead-4152-90d5-cf13f142d902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992805723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2992805723
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1631107757
Short name T396
Test name
Test status
Simulation time 32157493347 ps
CPU time 13.36 seconds
Started Feb 21 03:51:51 PM PST 24
Finished Feb 21 03:52:05 PM PST 24
Peak memory 199644 kb
Host smart-de3c5513-789f-4bd6-aee2-6d19b4cd4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631107757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1631107757
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1054176590
Short name T252
Test name
Test status
Simulation time 19487595693 ps
CPU time 12.3 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 199660 kb
Host smart-e28e57cd-aef5-4c2d-b74f-a4983ab15d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054176590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1054176590
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3436247545
Short name T884
Test name
Test status
Simulation time 48611508379 ps
CPU time 42.03 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:53 PM PST 24
Peak memory 199636 kb
Host smart-ee51c84a-f43e-4690-b837-d9c0aa04d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436247545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3436247545
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2401422200
Short name T385
Test name
Test status
Simulation time 19516749018 ps
CPU time 14.37 seconds
Started Feb 21 03:52:25 PM PST 24
Finished Feb 21 03:52:40 PM PST 24
Peak memory 199356 kb
Host smart-9dacfea8-8ea4-48b5-85f2-1bc12047da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401422200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2401422200
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3323523447
Short name T266
Test name
Test status
Simulation time 29620769310 ps
CPU time 14.75 seconds
Started Feb 21 03:52:50 PM PST 24
Finished Feb 21 03:53:05 PM PST 24
Peak memory 199596 kb
Host smart-b893580d-dfba-424f-b3a7-b980a3f8c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323523447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3323523447
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2847991116
Short name T225
Test name
Test status
Simulation time 44383232916 ps
CPU time 115.79 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:54:45 PM PST 24
Peak memory 199708 kb
Host smart-55df0a10-a44a-4086-bc9a-a7c10a2830b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847991116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2847991116
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2899961446
Short name T263
Test name
Test status
Simulation time 83369829708 ps
CPU time 71.67 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:54:01 PM PST 24
Peak memory 199628 kb
Host smart-4d85bd4d-b7dd-4690-96dc-f71e5545888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899961446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2899961446
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3404593676
Short name T158
Test name
Test status
Simulation time 176254610482 ps
CPU time 20.86 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:49:17 PM PST 24
Peak memory 199692 kb
Host smart-9807bd49-55d6-4193-a230-7c468399bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404593676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3404593676
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.488824958
Short name T318
Test name
Test status
Simulation time 274772829205 ps
CPU time 36.36 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:53:57 PM PST 24
Peak memory 199732 kb
Host smart-a2c0a2b2-34f7-4215-86fb-990c0c05ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488824958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.488824958
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.20719404
Short name T220
Test name
Test status
Simulation time 132788074150 ps
CPU time 48.27 seconds
Started Feb 21 03:53:03 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199732 kb
Host smart-f79f832e-ddfd-49bb-a40c-e5822d558fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20719404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.20719404
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2977410931
Short name T371
Test name
Test status
Simulation time 75609242382 ps
CPU time 40.8 seconds
Started Feb 21 03:53:15 PM PST 24
Finished Feb 21 03:53:56 PM PST 24
Peak memory 199656 kb
Host smart-d967a2bd-3205-45a0-968d-4455a5eb9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977410931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2977410931
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1695030870
Short name T270
Test name
Test status
Simulation time 45928589879 ps
CPU time 19.15 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:07 PM PST 24
Peak memory 199320 kb
Host smart-28bfcd45-3316-4a6e-bb1f-b6c073625621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695030870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1695030870
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.377647210
Short name T171
Test name
Test status
Simulation time 169890266700 ps
CPU time 67.45 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:52:32 PM PST 24
Peak memory 199712 kb
Host smart-a73a1afc-a50d-4fbd-ae9e-45b1884ff4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377647210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.377647210
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3292577739
Short name T59
Test name
Test status
Simulation time 471926653623 ps
CPU time 1507.35 seconds
Started Feb 21 03:48:19 PM PST 24
Finished Feb 21 04:13:27 PM PST 24
Peak memory 224448 kb
Host smart-70871098-719e-498e-b53f-b019ed846898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292577739 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3292577739
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.962869794
Short name T378
Test name
Test status
Simulation time 265660100399 ps
CPU time 27.02 seconds
Started Feb 21 03:51:57 PM PST 24
Finished Feb 21 03:52:25 PM PST 24
Peak memory 199608 kb
Host smart-1759f9d4-ea50-4581-983e-cc9bbfb98bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962869794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.962869794
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3758397169
Short name T335
Test name
Test status
Simulation time 125205385981 ps
CPU time 93.27 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:53:40 PM PST 24
Peak memory 199656 kb
Host smart-7f5b7caf-53f0-4b3d-ad4e-8eedb2858353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758397169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3758397169
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.867482248
Short name T209
Test name
Test status
Simulation time 205075206664 ps
CPU time 51.33 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199548 kb
Host smart-fe8836b4-07a6-482b-9b4e-e5395aef1373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867482248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.867482248
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.552216017
Short name T142
Test name
Test status
Simulation time 224240545723 ps
CPU time 135.53 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:54:25 PM PST 24
Peak memory 199632 kb
Host smart-8786541d-e75a-483d-a808-524e8726f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552216017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.552216017
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2359339700
Short name T296
Test name
Test status
Simulation time 45196510871 ps
CPU time 71.4 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:50:15 PM PST 24
Peak memory 199672 kb
Host smart-87e0aeb0-3743-4d41-9c1d-f45619857d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359339700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2359339700
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3494974132
Short name T55
Test name
Test status
Simulation time 47620070852 ps
CPU time 40.18 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199116 kb
Host smart-8001374a-425a-4ab1-965d-a09b737f28d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494974132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3494974132
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2371633436
Short name T337
Test name
Test status
Simulation time 18971465373 ps
CPU time 16.88 seconds
Started Feb 21 03:52:37 PM PST 24
Finished Feb 21 03:52:54 PM PST 24
Peak memory 199628 kb
Host smart-12d3096e-a691-42c1-a25b-0c296a318fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371633436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2371633436
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3407045467
Short name T387
Test name
Test status
Simulation time 138280775271 ps
CPU time 24.46 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:14 PM PST 24
Peak memory 199624 kb
Host smart-8577cdac-c392-47a6-8d53-9d6ad416706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407045467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3407045467
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.766524302
Short name T216
Test name
Test status
Simulation time 67402207875 ps
CPU time 108.06 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:50:54 PM PST 24
Peak memory 199644 kb
Host smart-aa0b6b21-4860-41b2-ae4a-f7232bbaefd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766524302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.766524302
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.563404325
Short name T226
Test name
Test status
Simulation time 40197581527 ps
CPU time 56.54 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:35 PM PST 24
Peak memory 199712 kb
Host smart-24ddf180-2b38-4ead-b600-fdb7bdcd62aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563404325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.563404325
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3661467236
Short name T379
Test name
Test status
Simulation time 123652228613 ps
CPU time 783.73 seconds
Started Feb 21 03:50:50 PM PST 24
Finished Feb 21 04:03:55 PM PST 24
Peak memory 216392 kb
Host smart-5639c888-2789-4a85-b83f-56990f08c11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661467236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3661467236
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3123265088
Short name T276
Test name
Test status
Simulation time 227353790216 ps
CPU time 352.9 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:53:59 PM PST 24
Peak memory 199644 kb
Host smart-31cdfd99-1e4a-4ca0-9a24-9145c7178b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123265088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3123265088
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2221624410
Short name T906
Test name
Test status
Simulation time 89070867750 ps
CPU time 124.61 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:53:58 PM PST 24
Peak memory 199584 kb
Host smart-276fa6b4-456a-4685-b414-e397c55617e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221624410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2221624410
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3737062757
Short name T376
Test name
Test status
Simulation time 106220548793 ps
CPU time 99.17 seconds
Started Feb 21 03:51:54 PM PST 24
Finished Feb 21 03:53:34 PM PST 24
Peak memory 199684 kb
Host smart-16b3510b-aedb-4efb-ab23-8102c05b3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737062757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3737062757
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2094992447
Short name T394
Test name
Test status
Simulation time 65164067155 ps
CPU time 45.22 seconds
Started Feb 21 03:47:44 PM PST 24
Finished Feb 21 03:48:29 PM PST 24
Peak memory 199628 kb
Host smart-442c5166-6935-4a0e-bcd4-e090d426781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094992447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2094992447
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_perf.168475150
Short name T301
Test name
Test status
Simulation time 13779920986 ps
CPU time 689.81 seconds
Started Feb 21 03:47:39 PM PST 24
Finished Feb 21 03:59:10 PM PST 24
Peak memory 199596 kb
Host smart-e18d863e-7580-49a7-b2ae-aca05272f045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168475150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.168475150
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1697737683
Short name T850
Test name
Test status
Simulation time 11988003246 ps
CPU time 19.11 seconds
Started Feb 21 03:52:05 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 199812 kb
Host smart-47597216-f6d2-4d89-91c3-eafd8282e18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697737683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1697737683
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1328324509
Short name T40
Test name
Test status
Simulation time 116473704466 ps
CPU time 635.91 seconds
Started Feb 21 03:48:23 PM PST 24
Finished Feb 21 03:58:59 PM PST 24
Peak memory 224556 kb
Host smart-846ec5cb-e56c-494f-8322-aee65da6109c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328324509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1328324509
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4266836478
Short name T129
Test name
Test status
Simulation time 210513307426 ps
CPU time 224.11 seconds
Started Feb 21 03:52:06 PM PST 24
Finished Feb 21 03:55:51 PM PST 24
Peak memory 199696 kb
Host smart-80060606-06fc-4017-838e-5c3a7d242eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266836478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4266836478
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.918557837
Short name T259
Test name
Test status
Simulation time 229017012103 ps
CPU time 352.45 seconds
Started Feb 21 03:52:08 PM PST 24
Finished Feb 21 03:58:01 PM PST 24
Peak memory 199680 kb
Host smart-063e196a-e27d-4c93-8169-64b35aad498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918557837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.918557837
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.261681903
Short name T380
Test name
Test status
Simulation time 62769769746 ps
CPU time 32.29 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:52:43 PM PST 24
Peak memory 199652 kb
Host smart-8976e1ad-687c-452a-92ca-82ec61f41761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261681903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.261681903
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1861648190
Short name T280
Test name
Test status
Simulation time 114510461799 ps
CPU time 181.74 seconds
Started Feb 21 03:48:33 PM PST 24
Finished Feb 21 03:51:36 PM PST 24
Peak memory 199576 kb
Host smart-723c1d0e-9e29-416f-9d6b-45420ae0fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861648190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1861648190
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.343824573
Short name T343
Test name
Test status
Simulation time 108525606547 ps
CPU time 41.97 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:52:55 PM PST 24
Peak memory 199500 kb
Host smart-24175559-7c97-4daa-aa0f-30ffde15e2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343824573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.343824573
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.588734741
Short name T342
Test name
Test status
Simulation time 127478217435 ps
CPU time 50.18 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:53:00 PM PST 24
Peak memory 199368 kb
Host smart-ad0e61c9-87ee-4ef8-a2b4-99d038f035e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588734741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.588734741
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.159715943
Short name T969
Test name
Test status
Simulation time 35403727362 ps
CPU time 30.25 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:42 PM PST 24
Peak memory 199680 kb
Host smart-1eb692a3-7bcc-4ef9-a56b-d1468df3e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159715943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.159715943
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1224183899
Short name T1064
Test name
Test status
Simulation time 386686073175 ps
CPU time 709.68 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 04:00:25 PM PST 24
Peak memory 199848 kb
Host smart-cc599b4b-abf6-4e8d-95ae-70bd9779633c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224183899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1224183899
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2471543125
Short name T180
Test name
Test status
Simulation time 106414877439 ps
CPU time 95.87 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:54:02 PM PST 24
Peak memory 199708 kb
Host smart-41c842c3-2059-4966-b424-f5caa0a03368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471543125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2471543125
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3933398643
Short name T310
Test name
Test status
Simulation time 229393115480 ps
CPU time 207.08 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 199588 kb
Host smart-3748616e-5385-44d4-8cbf-26925190a460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933398643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3933398643
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1902879756
Short name T295
Test name
Test status
Simulation time 29059303725 ps
CPU time 16.36 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:49:11 PM PST 24
Peak memory 198972 kb
Host smart-eec9db90-eed8-4224-9bd6-1c790748caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902879756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1902879756
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.718628607
Short name T181
Test name
Test status
Simulation time 120384520954 ps
CPU time 109.65 seconds
Started Feb 21 03:52:27 PM PST 24
Finished Feb 21 03:54:17 PM PST 24
Peak memory 199712 kb
Host smart-58ac82c8-7d96-4377-8ad6-5e03aa0b704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718628607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.718628607
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1613097955
Short name T332
Test name
Test status
Simulation time 44787347345 ps
CPU time 15.97 seconds
Started Feb 21 03:52:38 PM PST 24
Finished Feb 21 03:52:55 PM PST 24
Peak memory 199708 kb
Host smart-b9903bf4-17e0-4797-a6a8-b7a66844888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613097955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1613097955
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1473428113
Short name T340
Test name
Test status
Simulation time 44387971398 ps
CPU time 35.18 seconds
Started Feb 21 03:52:34 PM PST 24
Finished Feb 21 03:53:09 PM PST 24
Peak memory 199628 kb
Host smart-8b9a7fa1-48cf-449d-97f6-2c4f69656c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473428113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1473428113
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2440388794
Short name T370
Test name
Test status
Simulation time 108457020363 ps
CPU time 267.87 seconds
Started Feb 21 03:52:34 PM PST 24
Finished Feb 21 03:57:02 PM PST 24
Peak memory 199672 kb
Host smart-6e3387f8-fe04-4c81-83fe-15ef170341a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440388794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2440388794
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2000232577
Short name T307
Test name
Test status
Simulation time 45357868356 ps
CPU time 73.59 seconds
Started Feb 21 03:47:40 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 199400 kb
Host smart-c1bc908a-d334-4165-a1fa-a783d09dc2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000232577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2000232577
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4260031867
Short name T160
Test name
Test status
Simulation time 29040351265 ps
CPU time 13.09 seconds
Started Feb 21 03:52:50 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199604 kb
Host smart-e7f6916a-f196-46e4-90c0-314e83276817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260031867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4260031867
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.526782200
Short name T361
Test name
Test status
Simulation time 93621785945 ps
CPU time 173.09 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:51:56 PM PST 24
Peak memory 199600 kb
Host smart-f60eeca0-77c4-4948-b75e-f1c75c8571d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526782200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.526782200
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2809406908
Short name T323
Test name
Test status
Simulation time 34655293747 ps
CPU time 14.59 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:49:09 PM PST 24
Peak memory 199660 kb
Host smart-050db6ab-c45e-4af8-9889-9ae301b0e964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809406908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2809406908
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.4279658568
Short name T294
Test name
Test status
Simulation time 293218770517 ps
CPU time 885.81 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 04:03:35 PM PST 24
Peak memory 199852 kb
Host smart-7402e577-c80d-485c-89f3-647baf2d174d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279658568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4279658568
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1951451516
Short name T235
Test name
Test status
Simulation time 150285791540 ps
CPU time 54.96 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 199652 kb
Host smart-61bf7622-bde5-4dfa-98a1-c927438fadaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951451516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1951451516
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4216534930
Short name T364
Test name
Test status
Simulation time 27416471151 ps
CPU time 9.8 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:53:35 PM PST 24
Peak memory 198764 kb
Host smart-a330c400-5dcd-4221-be9e-b33165787894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216534930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4216534930
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1736184329
Short name T126
Test name
Test status
Simulation time 57465087238 ps
CPU time 56.57 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:54:34 PM PST 24
Peak memory 199188 kb
Host smart-4d0c1775-9b48-4111-9e4f-9366c9b6b025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736184329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1736184329
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2506843933
Short name T293
Test name
Test status
Simulation time 207878853884 ps
CPU time 65.03 seconds
Started Feb 21 03:49:32 PM PST 24
Finished Feb 21 03:50:37 PM PST 24
Peak memory 199384 kb
Host smart-df9cb725-4a61-45d9-a78b-e3a9288f85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506843933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2506843933
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3444838007
Short name T399
Test name
Test status
Simulation time 144119964966 ps
CPU time 244.66 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:51:47 PM PST 24
Peak memory 199756 kb
Host smart-8935f185-3e76-4158-b4e9-7c954d18d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444838007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3444838007
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3966068823
Short name T383
Test name
Test status
Simulation time 21452103955 ps
CPU time 10.15 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:49:54 PM PST 24
Peak memory 199664 kb
Host smart-9086ed2d-1ff4-451f-992e-37ff91271283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966068823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3966068823
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_perf.124356192
Short name T287
Test name
Test status
Simulation time 19293815786 ps
CPU time 1025.47 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 04:06:53 PM PST 24
Peak memory 199452 kb
Host smart-d59a3eff-6998-4408-96a8-a045e305e905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124356192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.124356192
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2315743672
Short name T282
Test name
Test status
Simulation time 21220161879 ps
CPU time 34.38 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:22 PM PST 24
Peak memory 199652 kb
Host smart-6a53b4ef-79e1-4cfc-ad34-f903bd04cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315743672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2315743672
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2418975425
Short name T292
Test name
Test status
Simulation time 118610150204 ps
CPU time 817.37 seconds
Started Feb 21 03:50:35 PM PST 24
Finished Feb 21 04:04:13 PM PST 24
Peak memory 199680 kb
Host smart-c8542fde-c9b1-4be2-8698-39a124083527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418975425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2418975425
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_stress_all.81444808
Short name T103
Test name
Test status
Simulation time 699731607642 ps
CPU time 153.64 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:53:25 PM PST 24
Peak memory 208680 kb
Host smart-823abec4-c6fd-43a1-ba82-eab2a76c89ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81444808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.81444808
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all.84356019
Short name T324
Test name
Test status
Simulation time 217296314160 ps
CPU time 1236.28 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 04:11:36 PM PST 24
Peak memory 199756 kb
Host smart-635863af-53c5-4029-bfc0-f788008ef4aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84356019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.84356019
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all.1885118380
Short name T972
Test name
Test status
Simulation time 515283084036 ps
CPU time 471.18 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:58:50 PM PST 24
Peak memory 199740 kb
Host smart-2fe65550-e107-4e50-934b-209967307698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885118380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1885118380
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_perf.221462431
Short name T297
Test name
Test status
Simulation time 24964240792 ps
CPU time 123.52 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:50:09 PM PST 24
Peak memory 199708 kb
Host smart-4feef14a-8988-446b-8dc4-6bf69f0848f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221462431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.221462431
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1891318110
Short name T26
Test name
Test status
Simulation time 43545267312 ps
CPU time 549.12 seconds
Started Feb 21 03:51:19 PM PST 24
Finished Feb 21 04:00:29 PM PST 24
Peak memory 216384 kb
Host smart-515de796-4ca1-4abd-943a-449c0d0065f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891318110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1891318110
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3114325023
Short name T246
Test name
Test status
Simulation time 154095833017 ps
CPU time 308.56 seconds
Started Feb 21 03:51:37 PM PST 24
Finished Feb 21 03:56:46 PM PST 24
Peak memory 199596 kb
Host smart-eec661f6-5b62-4950-8288-976112a5d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114325023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3114325023
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3851023974
Short name T355
Test name
Test status
Simulation time 6818368177 ps
CPU time 11.47 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:52:04 PM PST 24
Peak memory 199624 kb
Host smart-b4199939-9559-4bc1-8c16-807f47a86df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851023974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3851023974
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2245057712
Short name T1118
Test name
Test status
Simulation time 16126467 ps
CPU time 0.65 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 194260 kb
Host smart-d4fe4891-ae99-41ce-ba70-231d5b9b13e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245057712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2245057712
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3773233471
Short name T1146
Test name
Test status
Simulation time 59845811 ps
CPU time 2.11 seconds
Started Feb 21 12:34:32 PM PST 24
Finished Feb 21 12:34:35 PM PST 24
Peak memory 197672 kb
Host smart-48e24b7e-ae67-4fa4-af03-f1e836f6ba99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773233471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3773233471
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2244633307
Short name T1210
Test name
Test status
Simulation time 17225372 ps
CPU time 0.57 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 195340 kb
Host smart-6cf2e7d5-3542-4bc4-94e7-828d6e0f24bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244633307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2244633307
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.257207950
Short name T1234
Test name
Test status
Simulation time 104356243 ps
CPU time 0.68 seconds
Started Feb 21 12:34:31 PM PST 24
Finished Feb 21 12:34:32 PM PST 24
Peak memory 197908 kb
Host smart-be1497eb-591e-4826-ac10-900703ff3f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257207950 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.257207950
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1815521222
Short name T80
Test name
Test status
Simulation time 45161354 ps
CPU time 0.6 seconds
Started Feb 21 12:34:40 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 195424 kb
Host smart-60ca6714-42a8-4793-80e5-7396825f9547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815521222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1815521222
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3150482655
Short name T1201
Test name
Test status
Simulation time 32476096 ps
CPU time 0.56 seconds
Started Feb 21 12:34:29 PM PST 24
Finished Feb 21 12:34:30 PM PST 24
Peak memory 194552 kb
Host smart-a108e09d-6156-483c-a830-e18b91e5c927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150482655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3150482655
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1052004908
Short name T1140
Test name
Test status
Simulation time 81368861 ps
CPU time 0.72 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:48 PM PST 24
Peak memory 194892 kb
Host smart-a16bd199-9967-49de-9742-aa77748d9737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052004908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1052004908
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.808093567
Short name T1170
Test name
Test status
Simulation time 68085568 ps
CPU time 1.76 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:48 PM PST 24
Peak memory 200244 kb
Host smart-0dbe581a-a773-4854-bb98-8173451f8c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808093567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.808093567
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3423945553
Short name T87
Test name
Test status
Simulation time 245917823 ps
CPU time 1.28 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 199248 kb
Host smart-989e1235-8ce8-4334-975f-4807e16534a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423945553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3423945553
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2047633640
Short name T1179
Test name
Test status
Simulation time 211406423 ps
CPU time 0.75 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 196332 kb
Host smart-beccf880-547d-41f7-a664-b97cd2882ec6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047633640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2047633640
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2780698821
Short name T1111
Test name
Test status
Simulation time 227696407 ps
CPU time 2.2 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:51 PM PST 24
Peak memory 197804 kb
Host smart-32a27738-a1bb-4c64-9739-762916a40e38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780698821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2780698821
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3488463438
Short name T61
Test name
Test status
Simulation time 38751396 ps
CPU time 0.64 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 195788 kb
Host smart-890e275b-3c52-41ca-8e77-e11a36a50081
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488463438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3488463438
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3936916630
Short name T1235
Test name
Test status
Simulation time 18197907 ps
CPU time 0.74 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 197672 kb
Host smart-c5cbfb0c-ac63-4ad3-944c-824dff4a150e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936916630 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3936916630
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2242644238
Short name T1165
Test name
Test status
Simulation time 13112995 ps
CPU time 0.59 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 195568 kb
Host smart-8c58ee18-721d-413f-b921-5d506da19a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242644238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2242644238
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1451611625
Short name T1144
Test name
Test status
Simulation time 14879159 ps
CPU time 0.62 seconds
Started Feb 21 12:35:34 PM PST 24
Finished Feb 21 12:35:35 PM PST 24
Peak memory 185168 kb
Host smart-c3aa405f-1cfe-4e96-bbd6-13cf0be02bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451611625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1451611625
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2813568251
Short name T1221
Test name
Test status
Simulation time 51811851 ps
CPU time 0.72 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 197016 kb
Host smart-2b06d038-157b-4740-8223-2dd096076c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813568251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2813568251
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1997805542
Short name T1207
Test name
Test status
Simulation time 374875189 ps
CPU time 1.61 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 200068 kb
Host smart-048502aa-8afa-4de2-9b6b-e19d6b89b498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997805542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1997805542
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.992012371
Short name T1216
Test name
Test status
Simulation time 155241462 ps
CPU time 0.86 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 198536 kb
Host smart-172e987d-a41e-454e-8596-9713b3dece11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992012371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.992012371
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2777766851
Short name T1163
Test name
Test status
Simulation time 65474040 ps
CPU time 0.94 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 199940 kb
Host smart-fc848362-d90c-4f0f-bdee-c030a75bd7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777766851 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2777766851
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1705381610
Short name T68
Test name
Test status
Simulation time 13964556 ps
CPU time 0.62 seconds
Started Feb 21 12:34:56 PM PST 24
Finished Feb 21 12:35:04 PM PST 24
Peak memory 195860 kb
Host smart-a4a6cadf-b968-4e07-9cbf-54492795882c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705381610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1705381610
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.53492688
Short name T1135
Test name
Test status
Simulation time 11401296 ps
CPU time 0.58 seconds
Started Feb 21 12:34:58 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 185124 kb
Host smart-5caff0e9-c5ff-4332-bc95-1530d4c356be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53492688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.53492688
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2908741727
Short name T1220
Test name
Test status
Simulation time 47041707 ps
CPU time 0.68 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195444 kb
Host smart-b5b73eae-be0d-45d0-8266-0f9854993f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908741727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2908741727
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4070132983
Short name T1115
Test name
Test status
Simulation time 22740295 ps
CPU time 1.01 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 199944 kb
Host smart-dda79acb-89f2-4766-842b-41e3eda3d081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070132983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4070132983
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2012190596
Short name T400
Test name
Test status
Simulation time 131898352 ps
CPU time 1.26 seconds
Started Feb 21 12:36:15 PM PST 24
Finished Feb 21 12:36:17 PM PST 24
Peak memory 199368 kb
Host smart-93d368d4-23dd-4449-8b41-03db61c25e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012190596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2012190596
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1617108927
Short name T1130
Test name
Test status
Simulation time 364362089 ps
CPU time 0.88 seconds
Started Feb 21 12:35:58 PM PST 24
Finished Feb 21 12:36:00 PM PST 24
Peak memory 199860 kb
Host smart-2055266d-59dd-4abd-ba9c-d9eff991cb17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617108927 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1617108927
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1402575912
Short name T1150
Test name
Test status
Simulation time 33408907 ps
CPU time 0.54 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:13 PM PST 24
Peak memory 195400 kb
Host smart-fb1d90e1-0b95-41ad-ba07-eee3b1033d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402575912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1402575912
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2023197553
Short name T1198
Test name
Test status
Simulation time 35871179 ps
CPU time 0.55 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 185160 kb
Host smart-5f903a3c-68df-41c4-8277-f0ee1a89cc3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023197553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2023197553
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2836039179
Short name T77
Test name
Test status
Simulation time 30914015 ps
CPU time 0.62 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195628 kb
Host smart-a0451beb-d625-4045-892c-b3f02a8b022a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836039179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2836039179
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2219121315
Short name T1214
Test name
Test status
Simulation time 56515205 ps
CPU time 1.36 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 200236 kb
Host smart-62bbfa7b-4a88-48c4-8bc4-5fa8e4c44c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219121315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2219121315
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2810805726
Short name T1236
Test name
Test status
Simulation time 57684916 ps
CPU time 0.9 seconds
Started Feb 21 12:36:24 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 197216 kb
Host smart-37267e48-6e7a-4410-8ee3-f470845979ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810805726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2810805726
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3522772281
Short name T1184
Test name
Test status
Simulation time 43214480 ps
CPU time 0.75 seconds
Started Feb 21 12:35:16 PM PST 24
Finished Feb 21 12:35:17 PM PST 24
Peak memory 198572 kb
Host smart-c5d90d82-73f3-46d2-8381-bcb26dafe1c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522772281 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3522772281
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2906854305
Short name T67
Test name
Test status
Simulation time 41229887 ps
CPU time 0.6 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:55 PM PST 24
Peak memory 195440 kb
Host smart-ad6e4b34-efa0-4202-9681-b089a3f6f0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906854305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2906854305
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2401161349
Short name T1227
Test name
Test status
Simulation time 87700248 ps
CPU time 0.58 seconds
Started Feb 21 12:35:44 PM PST 24
Finished Feb 21 12:35:45 PM PST 24
Peak memory 194188 kb
Host smart-1cdc9f86-2428-4322-ae50-a5208b843cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401161349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2401161349
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3014972207
Short name T1189
Test name
Test status
Simulation time 26712185 ps
CPU time 0.68 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 195876 kb
Host smart-89319467-1b46-4002-b976-8672c936c0d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014972207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3014972207
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2828363901
Short name T1232
Test name
Test status
Simulation time 108335553 ps
CPU time 2.04 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:07 PM PST 24
Peak memory 200084 kb
Host smart-35002ba5-3e7d-4cd5-a7ff-761a6ac395df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828363901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2828363901
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2911700274
Short name T94
Test name
Test status
Simulation time 178757305 ps
CPU time 1.22 seconds
Started Feb 21 12:35:12 PM PST 24
Finished Feb 21 12:35:14 PM PST 24
Peak memory 199264 kb
Host smart-7d98d0ee-6174-4f70-8c9c-a29ac8ac810c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911700274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2911700274
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3912452391
Short name T1173
Test name
Test status
Simulation time 49581865 ps
CPU time 1.21 seconds
Started Feb 21 12:35:44 PM PST 24
Finished Feb 21 12:35:46 PM PST 24
Peak memory 199928 kb
Host smart-3f5f0331-a037-4921-9271-56bb445b5bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912452391 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3912452391
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2531123219
Short name T1217
Test name
Test status
Simulation time 36387266 ps
CPU time 0.57 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195172 kb
Host smart-f7373827-f106-47dd-8655-4223a277d504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531123219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2531123219
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3022768039
Short name T1113
Test name
Test status
Simulation time 23480396 ps
CPU time 0.59 seconds
Started Feb 21 12:34:57 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 194404 kb
Host smart-e49668a7-bfc4-4a7d-8a1e-af9c01b643eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022768039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3022768039
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1163898129
Short name T1231
Test name
Test status
Simulation time 130548271 ps
CPU time 0.61 seconds
Started Feb 21 12:35:44 PM PST 24
Finished Feb 21 12:35:45 PM PST 24
Peak memory 195152 kb
Host smart-d044c217-3614-4807-93f8-e8e7009df6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163898129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1163898129
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1721859925
Short name T1147
Test name
Test status
Simulation time 44752829 ps
CPU time 1.94 seconds
Started Feb 21 12:35:44 PM PST 24
Finished Feb 21 12:35:46 PM PST 24
Peak memory 199796 kb
Host smart-e4a21c96-d510-4c7c-a240-0491f8758784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721859925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1721859925
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1992738326
Short name T1133
Test name
Test status
Simulation time 169815168 ps
CPU time 0.93 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 199120 kb
Host smart-74665649-1724-44ed-bd94-c84c8a757453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992738326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1992738326
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3936662018
Short name T1123
Test name
Test status
Simulation time 144714473 ps
CPU time 1.38 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 200160 kb
Host smart-b6cf8d86-3431-4916-948d-a2bd7b795224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936662018 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3936662018
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4052656716
Short name T1204
Test name
Test status
Simulation time 16911781 ps
CPU time 0.65 seconds
Started Feb 21 12:35:12 PM PST 24
Finished Feb 21 12:35:13 PM PST 24
Peak memory 195500 kb
Host smart-ace2e366-f57f-46d3-9870-549c88df53ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052656716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4052656716
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.791337355
Short name T1157
Test name
Test status
Simulation time 48587006 ps
CPU time 0.55 seconds
Started Feb 21 12:35:05 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 185136 kb
Host smart-aeba8fc8-81a8-4130-9509-b680a79ec0e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791337355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.791337355
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1392622215
Short name T1197
Test name
Test status
Simulation time 19543737 ps
CPU time 0.74 seconds
Started Feb 21 12:36:23 PM PST 24
Finished Feb 21 12:36:25 PM PST 24
Peak memory 194888 kb
Host smart-352410c6-a633-4eeb-85cd-f7709b1dcee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392622215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1392622215
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2393847162
Short name T1120
Test name
Test status
Simulation time 282341741 ps
CPU time 1.8 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:35:00 PM PST 24
Peak memory 200204 kb
Host smart-8163d62a-3581-401c-9806-4ac9eeb746b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393847162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2393847162
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1829053296
Short name T1230
Test name
Test status
Simulation time 68322587 ps
CPU time 1.22 seconds
Started Feb 21 12:36:45 PM PST 24
Finished Feb 21 12:36:47 PM PST 24
Peak memory 199092 kb
Host smart-c1a51ebb-db89-4baf-a2f8-4441ce7ff589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829053296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1829053296
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3074621639
Short name T1172
Test name
Test status
Simulation time 291957232 ps
CPU time 0.86 seconds
Started Feb 21 12:36:23 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 197916 kb
Host smart-c86d958e-6dee-4418-abe6-29edac3c8d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074621639 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3074621639
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2588248325
Short name T79
Test name
Test status
Simulation time 16789190 ps
CPU time 0.6 seconds
Started Feb 21 12:36:43 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 195284 kb
Host smart-a2383f3c-fe95-4421-b24a-e1a7a307f5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588248325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2588248325
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4007162703
Short name T1205
Test name
Test status
Simulation time 18663864 ps
CPU time 0.61 seconds
Started Feb 21 12:35:12 PM PST 24
Finished Feb 21 12:35:13 PM PST 24
Peak memory 185244 kb
Host smart-0fc15b05-fdd4-4176-8b76-f6578e7b3534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007162703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4007162703
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2623382816
Short name T1181
Test name
Test status
Simulation time 57295431 ps
CPU time 0.65 seconds
Started Feb 21 12:36:44 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 194608 kb
Host smart-e05d2a3a-d46b-4133-bc57-37d330baa7ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623382816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2623382816
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.805239738
Short name T1149
Test name
Test status
Simulation time 22808657 ps
CPU time 1.01 seconds
Started Feb 21 12:34:57 PM PST 24
Finished Feb 21 12:35:02 PM PST 24
Peak memory 199844 kb
Host smart-8c7cbe54-be3e-4d78-9e63-ff06374cf527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805239738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.805239738
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2239552445
Short name T401
Test name
Test status
Simulation time 244853721 ps
CPU time 1.27 seconds
Started Feb 21 12:35:45 PM PST 24
Finished Feb 21 12:35:46 PM PST 24
Peak memory 199048 kb
Host smart-d525b170-47a2-4a45-85bc-7a694f346c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239552445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2239552445
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1105355344
Short name T1182
Test name
Test status
Simulation time 66778465 ps
CPU time 0.75 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 198400 kb
Host smart-e22ffb37-d68a-45e6-9586-db1e7e3eec8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105355344 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1105355344
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2514734992
Short name T70
Test name
Test status
Simulation time 30467774 ps
CPU time 0.55 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195500 kb
Host smart-6c06c3c3-654b-446a-ada0-283b6ece9835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514734992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2514734992
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1453144262
Short name T1112
Test name
Test status
Simulation time 17252332 ps
CPU time 0.59 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 185216 kb
Host smart-475cfc0f-eedd-4291-a5f5-06bf9d017ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453144262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1453144262
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2689798897
Short name T1160
Test name
Test status
Simulation time 44953216 ps
CPU time 0.62 seconds
Started Feb 21 12:34:58 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 195560 kb
Host smart-534a8d5a-f2c3-41e0-bc05-77a5b887075d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689798897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2689798897
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4012304350
Short name T1159
Test name
Test status
Simulation time 103433000 ps
CPU time 1.76 seconds
Started Feb 21 12:35:08 PM PST 24
Finished Feb 21 12:35:16 PM PST 24
Peak memory 200160 kb
Host smart-0fe890b7-fd99-4417-aea7-8b9983c1b15b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012304350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4012304350
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.818696996
Short name T88
Test name
Test status
Simulation time 45964738 ps
CPU time 0.93 seconds
Started Feb 21 12:34:56 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 198872 kb
Host smart-ef1d9e00-c01e-4846-9913-0be7ca22ef9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818696996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.818696996
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2776609991
Short name T1139
Test name
Test status
Simulation time 22401042 ps
CPU time 1.09 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 200496 kb
Host smart-1eb7b674-9278-4b69-8b1e-db2d58953c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776609991 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2776609991
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3812547737
Short name T1233
Test name
Test status
Simulation time 16686386 ps
CPU time 0.62 seconds
Started Feb 21 12:35:06 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 195480 kb
Host smart-46a28ce6-a37d-41e2-9d7e-b7eeeb2b7f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812547737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3812547737
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.256413987
Short name T1116
Test name
Test status
Simulation time 13696675 ps
CPU time 0.54 seconds
Started Feb 21 12:36:45 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 185060 kb
Host smart-6eb7997c-69f6-44d7-9581-913468387a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256413987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.256413987
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3494327342
Short name T81
Test name
Test status
Simulation time 22466042 ps
CPU time 0.64 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 194660 kb
Host smart-b27de76c-09c6-4ec2-947d-7514c7c3df12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494327342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3494327342
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2362461116
Short name T1187
Test name
Test status
Simulation time 307000706 ps
CPU time 1.52 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 200132 kb
Host smart-f3eea5b6-f3e1-4fb2-8089-6ffc39dc9d54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362461116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2362461116
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3497917576
Short name T1188
Test name
Test status
Simulation time 183884890 ps
CPU time 0.96 seconds
Started Feb 21 12:36:43 PM PST 24
Finished Feb 21 12:36:47 PM PST 24
Peak memory 198788 kb
Host smart-10ff3df4-f5ab-4816-b785-eeba43ef6021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497917576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3497917576
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3450053680
Short name T1137
Test name
Test status
Simulation time 62045803 ps
CPU time 0.79 seconds
Started Feb 21 12:35:13 PM PST 24
Finished Feb 21 12:35:15 PM PST 24
Peak memory 199912 kb
Host smart-75286ba2-a693-43b9-8c4d-288035016771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450053680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3450053680
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3131167752
Short name T76
Test name
Test status
Simulation time 18727305 ps
CPU time 0.63 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195524 kb
Host smart-90d26ccc-fafa-4d41-a3b7-2723018e6937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131167752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3131167752
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3311153505
Short name T1107
Test name
Test status
Simulation time 14815023 ps
CPU time 0.58 seconds
Started Feb 21 12:35:25 PM PST 24
Finished Feb 21 12:35:26 PM PST 24
Peak memory 194448 kb
Host smart-0114d599-e8bf-4d60-aba4-fc8420d96171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311153505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3311153505
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.251184673
Short name T1202
Test name
Test status
Simulation time 68522282 ps
CPU time 0.63 seconds
Started Feb 21 12:35:05 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 195520 kb
Host smart-0aaba7d9-d0cd-424a-9d06-d7eeeec74fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251184673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.251184673
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1086971798
Short name T1212
Test name
Test status
Simulation time 103298396 ps
CPU time 1.58 seconds
Started Feb 21 12:35:08 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 200120 kb
Host smart-387309d3-a88e-4874-87b1-162a9c312c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086971798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1086971798
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.985350788
Short name T91
Test name
Test status
Simulation time 321833795 ps
CPU time 0.93 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:35:00 PM PST 24
Peak memory 198848 kb
Host smart-3126feb8-b449-4800-b073-075b8dbff4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985350788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.985350788
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3206940836
Short name T1213
Test name
Test status
Simulation time 75099292 ps
CPU time 1.21 seconds
Started Feb 21 12:34:49 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 200148 kb
Host smart-b1ad79b8-6923-4858-8aa8-e201c3609367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206940836 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3206940836
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3260122838
Short name T1222
Test name
Test status
Simulation time 15752562 ps
CPU time 0.64 seconds
Started Feb 21 12:35:02 PM PST 24
Finished Feb 21 12:35:08 PM PST 24
Peak memory 195424 kb
Host smart-c1ba6ea1-ca54-46d7-808c-b8d4f7d39002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260122838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3260122838
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.697056630
Short name T1211
Test name
Test status
Simulation time 40002630 ps
CPU time 0.62 seconds
Started Feb 21 12:36:23 PM PST 24
Finished Feb 21 12:36:25 PM PST 24
Peak memory 183260 kb
Host smart-b7a49dee-5944-46e7-955f-3652d82f85b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697056630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.697056630
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2141675280
Short name T73
Test name
Test status
Simulation time 86720962 ps
CPU time 0.75 seconds
Started Feb 21 12:35:13 PM PST 24
Finished Feb 21 12:35:15 PM PST 24
Peak memory 196092 kb
Host smart-acee246b-b829-41a4-8449-183bc09df659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141675280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2141675280
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2553897833
Short name T1141
Test name
Test status
Simulation time 186798537 ps
CPU time 2.06 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 200196 kb
Host smart-a4b29215-d637-44bb-9096-c4a3fa1646da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553897833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2553897833
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1141528982
Short name T93
Test name
Test status
Simulation time 191948590 ps
CPU time 1.32 seconds
Started Feb 21 12:35:07 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 199232 kb
Host smart-aa5acf29-c210-4c81-89db-b54ec772053e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141528982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1141528982
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.190464302
Short name T63
Test name
Test status
Simulation time 31175671 ps
CPU time 0.75 seconds
Started Feb 21 12:35:51 PM PST 24
Finished Feb 21 12:35:52 PM PST 24
Peak memory 196272 kb
Host smart-e0b8ed03-697e-44e9-99b7-f0595030a112
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190464302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.190464302
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3466515481
Short name T1176
Test name
Test status
Simulation time 1015787750 ps
CPU time 2.19 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:48 PM PST 24
Peak memory 197888 kb
Host smart-da146c4a-0cf3-407f-b96b-5bf13928f903
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466515481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3466515481
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2693562855
Short name T1131
Test name
Test status
Simulation time 25314811 ps
CPU time 0.59 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 195444 kb
Host smart-acf5691d-833e-433e-9ff2-540b015a4e83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693562855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2693562855
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1756841009
Short name T1167
Test name
Test status
Simulation time 69474872 ps
CPU time 0.97 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 199940 kb
Host smart-e8a93ff0-76b8-4904-88c2-a1cad323e38a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756841009 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1756841009
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2088372749
Short name T72
Test name
Test status
Simulation time 61405439 ps
CPU time 0.6 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 195432 kb
Host smart-c7e0fce1-249c-4b50-af9d-7cae2307d8da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088372749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2088372749
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3267450819
Short name T1190
Test name
Test status
Simulation time 30698428 ps
CPU time 0.55 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 194444 kb
Host smart-126e1ecd-eaf6-4b5e-b25b-3ddb371bd1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267450819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3267450819
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2021197912
Short name T1209
Test name
Test status
Simulation time 20761190 ps
CPU time 0.65 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 195652 kb
Host smart-504ab884-1120-4684-a2e7-a8807f676c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021197912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2021197912
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3790694815
Short name T1114
Test name
Test status
Simulation time 495471578 ps
CPU time 2.04 seconds
Started Feb 21 12:35:36 PM PST 24
Finished Feb 21 12:35:39 PM PST 24
Peak memory 200092 kb
Host smart-5c18d6b5-8734-478e-9f11-86ba6b33241f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790694815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3790694815
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2317126691
Short name T89
Test name
Test status
Simulation time 58391247 ps
CPU time 1 seconds
Started Feb 21 12:35:34 PM PST 24
Finished Feb 21 12:35:36 PM PST 24
Peak memory 198848 kb
Host smart-e1300416-82db-4c6a-b092-7db9c3567bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317126691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2317126691
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3784236113
Short name T1162
Test name
Test status
Simulation time 16574023 ps
CPU time 0.59 seconds
Started Feb 21 12:35:08 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 194456 kb
Host smart-d9c55ede-61f8-4b87-902f-8b26676d139c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784236113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3784236113
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2411430032
Short name T1199
Test name
Test status
Simulation time 12371614 ps
CPU time 0.57 seconds
Started Feb 21 12:35:05 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 185308 kb
Host smart-f60a8df8-97b2-4268-b834-fd1d11f0aa39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411430032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2411430032
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2826482231
Short name T1134
Test name
Test status
Simulation time 75845410 ps
CPU time 0.57 seconds
Started Feb 21 12:35:08 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 185220 kb
Host smart-7afff128-778f-4ded-8669-03e0c266439e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826482231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2826482231
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1168410247
Short name T1215
Test name
Test status
Simulation time 38051638 ps
CPU time 0.54 seconds
Started Feb 21 12:35:20 PM PST 24
Finished Feb 21 12:35:21 PM PST 24
Peak memory 185160 kb
Host smart-378dcc03-5b71-4d9e-8e30-905a8220fecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168410247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1168410247
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1313735581
Short name T1154
Test name
Test status
Simulation time 18541669 ps
CPU time 0.57 seconds
Started Feb 21 12:35:09 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 194436 kb
Host smart-1b81ac00-c5fa-4827-8f84-fcfca269b1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313735581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1313735581
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2910060841
Short name T1175
Test name
Test status
Simulation time 11148886 ps
CPU time 0.56 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 185228 kb
Host smart-c91618b4-c50c-4b3a-944d-7a8977551c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910060841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2910060841
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.888678097
Short name T1177
Test name
Test status
Simulation time 36443358 ps
CPU time 0.59 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 185212 kb
Host smart-519f532d-1a3b-4eb5-87a2-16e0c6cd9539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888678097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.888678097
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1808066170
Short name T1166
Test name
Test status
Simulation time 13802056 ps
CPU time 0.57 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 194420 kb
Host smart-26cab17c-f3a6-4e45-b466-065eb44457e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808066170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1808066170
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3613785306
Short name T1168
Test name
Test status
Simulation time 140873779 ps
CPU time 0.58 seconds
Started Feb 21 12:35:02 PM PST 24
Finished Feb 21 12:35:08 PM PST 24
Peak memory 185216 kb
Host smart-a1d9f16a-44a0-4b1c-b523-ca66bb049a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613785306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3613785306
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3149799475
Short name T1224
Test name
Test status
Simulation time 48888189 ps
CPU time 0.59 seconds
Started Feb 21 12:35:01 PM PST 24
Finished Feb 21 12:35:07 PM PST 24
Peak memory 194420 kb
Host smart-93fb7045-e5b4-4815-9416-1c2ab61d6987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149799475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3149799475
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2754449019
Short name T64
Test name
Test status
Simulation time 29942603 ps
CPU time 0.73 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 196228 kb
Host smart-ddf4b40a-ecd2-4c13-b5c0-edaf82189686
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754449019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2754449019
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.681058777
Short name T1152
Test name
Test status
Simulation time 452875980 ps
CPU time 2.18 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:51 PM PST 24
Peak memory 197904 kb
Host smart-6cd4b157-0929-4303-82fa-c0a807e3704e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681058777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.681058777
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1253815561
Short name T66
Test name
Test status
Simulation time 142780787 ps
CPU time 0.57 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 195436 kb
Host smart-3cc7096e-2f00-4086-a68a-2d899d9e2566
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253815561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1253815561
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2652839373
Short name T1164
Test name
Test status
Simulation time 74531829 ps
CPU time 1.1 seconds
Started Feb 21 12:34:56 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 199852 kb
Host smart-f6ac832b-e611-4439-9cfd-bbc6468c1db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652839373 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2652839373
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2391241745
Short name T1151
Test name
Test status
Simulation time 15771713 ps
CPU time 0.56 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 195464 kb
Host smart-6a07a98d-f421-49bb-9eae-c52acdcf8afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391241745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2391241745
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2935403605
Short name T1110
Test name
Test status
Simulation time 22672024 ps
CPU time 0.55 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 185172 kb
Host smart-c73d44d5-cf1d-4882-bde3-e8d6852f3318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935403605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2935403605
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.977959689
Short name T1155
Test name
Test status
Simulation time 55513741 ps
CPU time 0.61 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 195584 kb
Host smart-eb578347-6642-4668-ad66-b8afd7412194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977959689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.977959689
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2281888350
Short name T1143
Test name
Test status
Simulation time 60227841 ps
CPU time 1.83 seconds
Started Feb 21 12:35:01 PM PST 24
Finished Feb 21 12:35:05 PM PST 24
Peak memory 200276 kb
Host smart-b2c6df85-7422-472d-ab51-e210d632aac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281888350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2281888350
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1424624459
Short name T92
Test name
Test status
Simulation time 69273919 ps
CPU time 1.22 seconds
Started Feb 21 12:35:58 PM PST 24
Finished Feb 21 12:36:10 PM PST 24
Peak memory 199128 kb
Host smart-319e85a4-3400-4e8e-96a1-e79f893497c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424624459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1424624459
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4166861713
Short name T1218
Test name
Test status
Simulation time 14802459 ps
CPU time 0.58 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 185216 kb
Host smart-f40b12ad-63c4-46bb-8ba9-0ad04f2b5083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166861713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4166861713
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4131162299
Short name T1136
Test name
Test status
Simulation time 15401380 ps
CPU time 0.54 seconds
Started Feb 21 12:35:05 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 185160 kb
Host smart-73f06286-f213-4a5b-b054-4c8a6cd11cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131162299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4131162299
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3233044449
Short name T1171
Test name
Test status
Simulation time 12383038 ps
CPU time 0.55 seconds
Started Feb 21 12:35:19 PM PST 24
Finished Feb 21 12:35:20 PM PST 24
Peak memory 194404 kb
Host smart-ada827d5-4e94-46b6-861d-ac6828afbc10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233044449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3233044449
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1407267149
Short name T1183
Test name
Test status
Simulation time 95437292 ps
CPU time 0.59 seconds
Started Feb 21 12:35:01 PM PST 24
Finished Feb 21 12:35:05 PM PST 24
Peak memory 185304 kb
Host smart-478b8b1b-43ad-46ad-8755-8edc203b630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407267149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1407267149
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2362123358
Short name T1195
Test name
Test status
Simulation time 12530042 ps
CPU time 0.57 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 185160 kb
Host smart-3dcb99b4-e510-407f-9bd7-416681e36e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362123358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2362123358
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.531298249
Short name T1129
Test name
Test status
Simulation time 15995994 ps
CPU time 0.55 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 185200 kb
Host smart-9a9ec1f9-7574-4490-a0d6-0b5facafd484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531298249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.531298249
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.342148910
Short name T1174
Test name
Test status
Simulation time 13092291 ps
CPU time 0.58 seconds
Started Feb 21 12:35:45 PM PST 24
Finished Feb 21 12:35:46 PM PST 24
Peak memory 184992 kb
Host smart-944b1e65-e586-4d86-bc3a-74439c85a1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342148910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.342148910
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2286439556
Short name T1106
Test name
Test status
Simulation time 61265303 ps
CPU time 0.56 seconds
Started Feb 21 12:35:09 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 194456 kb
Host smart-fdc8c3e1-763f-4b92-8f97-54efe96195b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286439556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2286439556
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.848090503
Short name T1158
Test name
Test status
Simulation time 46442204 ps
CPU time 0.54 seconds
Started Feb 21 12:34:59 PM PST 24
Finished Feb 21 12:35:02 PM PST 24
Peak memory 185532 kb
Host smart-525afc89-94f6-4fa3-a2d3-41a04a87aabe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848090503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.848090503
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1717528082
Short name T1156
Test name
Test status
Simulation time 13912254 ps
CPU time 0.54 seconds
Started Feb 21 12:35:25 PM PST 24
Finished Feb 21 12:35:26 PM PST 24
Peak memory 185216 kb
Host smart-46ce78db-9126-4319-a539-fc9e97379410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717528082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1717528082
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2639159696
Short name T69
Test name
Test status
Simulation time 74769753 ps
CPU time 0.63 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 194708 kb
Host smart-bd56a751-7393-469f-b1bb-91c281c84d89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639159696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2639159696
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.758247232
Short name T1161
Test name
Test status
Simulation time 95763782 ps
CPU time 1.49 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 197676 kb
Host smart-ce905269-e6a9-4bde-8252-cd6a564eb3ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758247232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.758247232
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4086068250
Short name T71
Test name
Test status
Simulation time 25123306 ps
CPU time 0.57 seconds
Started Feb 21 12:34:49 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 195452 kb
Host smart-4469e660-2f78-4f21-b654-74c18cbe6ec8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086068250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4086068250
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3792631834
Short name T1138
Test name
Test status
Simulation time 82554802 ps
CPU time 0.73 seconds
Started Feb 21 12:34:56 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 198164 kb
Host smart-c6bf706c-ef90-4799-a7bb-d779f8958342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792631834 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3792631834
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1417066891
Short name T65
Test name
Test status
Simulation time 16472355 ps
CPU time 0.65 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 195408 kb
Host smart-ee45505f-cfaf-47a2-be01-04f416f938b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417066891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1417066891
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.288447857
Short name T1193
Test name
Test status
Simulation time 44361068 ps
CPU time 0.56 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:55 PM PST 24
Peak memory 194424 kb
Host smart-9a2fa4f5-306d-485c-89bf-e65f07b8d9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288447857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.288447857
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2693271213
Short name T75
Test name
Test status
Simulation time 36040906 ps
CPU time 0.78 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 197000 kb
Host smart-0458f5a7-9293-491e-b490-f0f06d273a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693271213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2693271213
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.546129288
Short name T1122
Test name
Test status
Simulation time 130102203 ps
CPU time 0.92 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 199800 kb
Host smart-f79a4254-f1ea-46f0-aa7b-a03a57532400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546129288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.546129288
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.560757755
Short name T1186
Test name
Test status
Simulation time 148972245 ps
CPU time 1.28 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 199292 kb
Host smart-6744e83f-3a51-42b3-8ed7-70249c60b10d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560757755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.560757755
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.732880795
Short name T1117
Test name
Test status
Simulation time 15851714 ps
CPU time 0.58 seconds
Started Feb 21 12:35:06 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 194420 kb
Host smart-b29d0699-366c-4a04-bdbc-3effc62ddebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732880795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.732880795
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1667352595
Short name T1226
Test name
Test status
Simulation time 59683154 ps
CPU time 0.59 seconds
Started Feb 21 12:35:07 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 185212 kb
Host smart-4299bf84-24a2-4146-9f91-a19f70f19ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667352595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1667352595
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.157752795
Short name T1180
Test name
Test status
Simulation time 22621524 ps
CPU time 0.61 seconds
Started Feb 21 12:35:34 PM PST 24
Finished Feb 21 12:35:35 PM PST 24
Peak memory 194756 kb
Host smart-2e2eb38a-897f-4341-beae-544c2b8f5fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157752795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.157752795
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1699119388
Short name T1125
Test name
Test status
Simulation time 13559209 ps
CPU time 0.59 seconds
Started Feb 21 12:34:59 PM PST 24
Finished Feb 21 12:35:02 PM PST 24
Peak memory 185160 kb
Host smart-a619d08e-66b8-4639-a92f-e3de32766737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699119388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1699119388
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4038900897
Short name T1127
Test name
Test status
Simulation time 44049941 ps
CPU time 0.58 seconds
Started Feb 21 12:34:58 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 185340 kb
Host smart-e95d7795-23d5-48fe-9b3f-a35af5cface2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038900897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4038900897
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2975467714
Short name T1228
Test name
Test status
Simulation time 13885682 ps
CPU time 0.57 seconds
Started Feb 21 12:35:25 PM PST 24
Finished Feb 21 12:35:26 PM PST 24
Peak memory 194768 kb
Host smart-f91b1d4e-512c-4ee9-99cf-31c2fd02f1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975467714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2975467714
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.732272221
Short name T1225
Test name
Test status
Simulation time 45715569 ps
CPU time 0.59 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 185172 kb
Host smart-73031279-3566-4181-a438-9817c41635dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732272221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.732272221
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4136942215
Short name T1203
Test name
Test status
Simulation time 73705068 ps
CPU time 0.61 seconds
Started Feb 21 12:35:02 PM PST 24
Finished Feb 21 12:35:08 PM PST 24
Peak memory 185196 kb
Host smart-0c9f79d6-d756-4a54-b28f-025bdd8635a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136942215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4136942215
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2374252197
Short name T1126
Test name
Test status
Simulation time 14596268 ps
CPU time 0.57 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 194452 kb
Host smart-57a3c876-1a31-4444-91f4-5745c0186f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374252197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2374252197
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.734730978
Short name T1124
Test name
Test status
Simulation time 13068973 ps
CPU time 0.57 seconds
Started Feb 21 12:35:00 PM PST 24
Finished Feb 21 12:35:03 PM PST 24
Peak memory 185176 kb
Host smart-c7371807-1f1a-41a9-b6bf-d28068e1e039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734730978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.734730978
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1386904778
Short name T1132
Test name
Test status
Simulation time 356093224 ps
CPU time 0.77 seconds
Started Feb 21 12:34:57 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 199596 kb
Host smart-8af703c4-02b1-4109-b065-b22e1cc7c3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386904778 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1386904778
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3175414891
Short name T1128
Test name
Test status
Simulation time 25330299 ps
CPU time 0.7 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:55 PM PST 24
Peak memory 185204 kb
Host smart-5136de2a-4169-4277-95bd-69a6f130f9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175414891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3175414891
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3626058560
Short name T1219
Test name
Test status
Simulation time 15553645 ps
CPU time 0.72 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 196944 kb
Host smart-dfa71a11-185c-43a7-b71c-0581e83a059c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626058560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3626058560
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1319774418
Short name T1121
Test name
Test status
Simulation time 147954505 ps
CPU time 2.07 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:40 PM PST 24
Peak memory 200128 kb
Host smart-a48ecdd5-476a-46ec-8339-68f038ab6b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319774418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1319774418
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2485735843
Short name T1148
Test name
Test status
Simulation time 147716767 ps
CPU time 1.33 seconds
Started Feb 21 12:34:42 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 199272 kb
Host smart-255cb0d6-a734-45ba-9e42-42b210fb9473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485735843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2485735843
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2473550536
Short name T1192
Test name
Test status
Simulation time 90863949 ps
CPU time 0.69 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 198920 kb
Host smart-7a2b9ec3-41ed-477e-9841-a42cb277d68d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473550536 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2473550536
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.643050913
Short name T1206
Test name
Test status
Simulation time 29247677 ps
CPU time 0.58 seconds
Started Feb 21 12:34:57 PM PST 24
Finished Feb 21 12:35:01 PM PST 24
Peak memory 195416 kb
Host smart-0bc8cda5-0bee-4264-8c37-35507a48dd04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643050913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.643050913
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3547621995
Short name T1108
Test name
Test status
Simulation time 36388598 ps
CPU time 0.53 seconds
Started Feb 21 12:36:13 PM PST 24
Finished Feb 21 12:36:15 PM PST 24
Peak memory 185172 kb
Host smart-bedeae1e-a470-42f3-af04-e487ff41983f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547621995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3547621995
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3213063192
Short name T74
Test name
Test status
Simulation time 27457986 ps
CPU time 0.75 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 197020 kb
Host smart-192528a1-aaf5-408c-a842-d0c420585f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213063192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3213063192
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1327693169
Short name T1185
Test name
Test status
Simulation time 59434512 ps
CPU time 1.4 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 200168 kb
Host smart-a5ac1201-465c-49f6-8c12-a8c65991a7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327693169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1327693169
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1005485696
Short name T1191
Test name
Test status
Simulation time 19426917 ps
CPU time 0.89 seconds
Started Feb 21 12:34:54 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 199460 kb
Host smart-d71c7dbb-1c7e-4eb5-8388-6664eef61a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005485696 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1005485696
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.53243878
Short name T78
Test name
Test status
Simulation time 22870866 ps
CPU time 0.57 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 195544 kb
Host smart-5b5a8ae5-d875-44ed-acd1-6e433cadcedb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53243878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.53243878
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2376622697
Short name T1200
Test name
Test status
Simulation time 21570793 ps
CPU time 0.55 seconds
Started Feb 21 12:36:24 PM PST 24
Finished Feb 21 12:36:25 PM PST 24
Peak memory 183728 kb
Host smart-15e2f80f-a96d-4f83-9b99-bd142f3e3e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376622697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2376622697
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1034775938
Short name T1196
Test name
Test status
Simulation time 48161088 ps
CPU time 0.72 seconds
Started Feb 21 12:35:16 PM PST 24
Finished Feb 21 12:35:17 PM PST 24
Peak memory 196688 kb
Host smart-eb74232b-bdd3-422e-8e3e-7ec63114f0c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034775938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1034775938
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3086293114
Short name T1229
Test name
Test status
Simulation time 101686008 ps
CPU time 2.42 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:10 PM PST 24
Peak memory 200128 kb
Host smart-486eed0f-4eec-4906-a902-a360d87de629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086293114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3086293114
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1692831714
Short name T95
Test name
Test status
Simulation time 93243973 ps
CPU time 0.97 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:35:00 PM PST 24
Peak memory 198936 kb
Host smart-e46e8099-7b66-430c-b514-d3655346fcb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692831714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1692831714
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.230973362
Short name T1237
Test name
Test status
Simulation time 25040792 ps
CPU time 0.73 seconds
Started Feb 21 12:35:45 PM PST 24
Finished Feb 21 12:35:46 PM PST 24
Peak memory 197868 kb
Host smart-308dffcd-8fc1-44a8-b820-2fd6c900d2dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230973362 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.230973362
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.537633416
Short name T1119
Test name
Test status
Simulation time 26380057 ps
CPU time 0.59 seconds
Started Feb 21 12:34:49 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 195408 kb
Host smart-51e6c85f-145f-4097-b95c-cba5a97d92f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537633416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.537633416
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3625736725
Short name T1153
Test name
Test status
Simulation time 25069811 ps
CPU time 0.61 seconds
Started Feb 21 12:35:01 PM PST 24
Finished Feb 21 12:35:05 PM PST 24
Peak memory 185304 kb
Host smart-075c1979-4e19-4475-81de-237d5b30d090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625736725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3625736725
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3760451497
Short name T1142
Test name
Test status
Simulation time 19254323 ps
CPU time 0.72 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 196884 kb
Host smart-ab5efbec-c718-41dc-8eff-87f16a882ada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760451497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3760451497
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2857814802
Short name T1169
Test name
Test status
Simulation time 33855292 ps
CPU time 1.76 seconds
Started Feb 21 12:34:55 PM PST 24
Finished Feb 21 12:35:00 PM PST 24
Peak memory 200064 kb
Host smart-9f92c43e-7045-4cb3-81f7-12294634790d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857814802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2857814802
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1272614399
Short name T1178
Test name
Test status
Simulation time 71999094 ps
CPU time 1.28 seconds
Started Feb 21 12:35:00 PM PST 24
Finished Feb 21 12:35:04 PM PST 24
Peak memory 199276 kb
Host smart-288ac9f7-91bd-4a50-bdb2-d89e1af6f321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272614399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1272614399
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.686041340
Short name T1194
Test name
Test status
Simulation time 18223008 ps
CPU time 0.74 seconds
Started Feb 21 12:35:44 PM PST 24
Finished Feb 21 12:35:45 PM PST 24
Peak memory 198576 kb
Host smart-1e6c97fa-0168-473a-96aa-0aff8e7d44f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686041340 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.686041340
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4103455668
Short name T1208
Test name
Test status
Simulation time 17406787 ps
CPU time 0.6 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 195540 kb
Host smart-bd16c28a-a62a-4b43-a7bc-ea00f687a34a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103455668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4103455668
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.844584398
Short name T1145
Test name
Test status
Simulation time 22146777 ps
CPU time 0.58 seconds
Started Feb 21 12:34:59 PM PST 24
Finished Feb 21 12:35:02 PM PST 24
Peak memory 185192 kb
Host smart-63675ccd-411b-4c24-a158-e1e6cc25920f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844584398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.844584398
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2161806343
Short name T1223
Test name
Test status
Simulation time 92634671 ps
CPU time 0.73 seconds
Started Feb 21 12:35:01 PM PST 24
Finished Feb 21 12:35:06 PM PST 24
Peak memory 196232 kb
Host smart-788e65b8-5a83-48c0-a300-8291b9839052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161806343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2161806343
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3029927043
Short name T1109
Test name
Test status
Simulation time 233429072 ps
CPU time 1.36 seconds
Started Feb 21 12:35:04 PM PST 24
Finished Feb 21 12:35:09 PM PST 24
Peak memory 200160 kb
Host smart-09af596b-3b5d-42f6-bdd9-c050a4cd7fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029927043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3029927043
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4072904845
Short name T786
Test name
Test status
Simulation time 52631766620 ps
CPU time 37.89 seconds
Started Feb 21 03:47:31 PM PST 24
Finished Feb 21 03:48:09 PM PST 24
Peak memory 198780 kb
Host smart-79acad71-5eaa-4a14-866f-e17a3652dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072904845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4072904845
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3100712617
Short name T1076
Test name
Test status
Simulation time 81454563230 ps
CPU time 136.49 seconds
Started Feb 21 03:47:47 PM PST 24
Finished Feb 21 03:50:04 PM PST 24
Peak memory 199660 kb
Host smart-6705bf1a-d88a-470f-90d1-88c091991a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100712617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3100712617
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2029360413
Short name T678
Test name
Test status
Simulation time 43694680550 ps
CPU time 23.62 seconds
Started Feb 21 03:47:47 PM PST 24
Finished Feb 21 03:48:11 PM PST 24
Peak memory 199636 kb
Host smart-dcd20c18-eadd-45e4-a3c3-be64a3ea9eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029360413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2029360413
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3090579191
Short name T721
Test name
Test status
Simulation time 1585890360516 ps
CPU time 729.7 seconds
Started Feb 21 03:47:31 PM PST 24
Finished Feb 21 03:59:41 PM PST 24
Peak memory 199500 kb
Host smart-7de25831-a207-4f71-b9e5-e81160fe2b4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090579191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3090579191
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3470852183
Short name T600
Test name
Test status
Simulation time 180591719444 ps
CPU time 881.16 seconds
Started Feb 21 03:47:49 PM PST 24
Finished Feb 21 04:02:31 PM PST 24
Peak memory 199616 kb
Host smart-b58cc037-03d2-4ac2-9c9f-5207a75db826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470852183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3470852183
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.703991399
Short name T1001
Test name
Test status
Simulation time 4566609538 ps
CPU time 11.93 seconds
Started Feb 21 03:47:33 PM PST 24
Finished Feb 21 03:47:45 PM PST 24
Peak memory 198768 kb
Host smart-7ae32eaa-aa79-47e5-b46c-0266a4bbf8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703991399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.703991399
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.331148476
Short name T531
Test name
Test status
Simulation time 12570981582 ps
CPU time 6.11 seconds
Started Feb 21 03:47:49 PM PST 24
Finished Feb 21 03:47:55 PM PST 24
Peak memory 197340 kb
Host smart-be942229-ee09-4af2-b066-3d88a6940b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331148476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.331148476
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3565051228
Short name T1075
Test name
Test status
Simulation time 12218129378 ps
CPU time 678.38 seconds
Started Feb 21 03:47:36 PM PST 24
Finished Feb 21 03:58:55 PM PST 24
Peak memory 199760 kb
Host smart-ba48a5cc-9933-41e5-9917-c40395329547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565051228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3565051228
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3377724756
Short name T1093
Test name
Test status
Simulation time 102957144586 ps
CPU time 17.73 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:13 PM PST 24
Peak memory 199336 kb
Host smart-81fbee49-fe21-401e-b272-d465df85d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377724756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3377724756
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3809212551
Short name T801
Test name
Test status
Simulation time 5871827603 ps
CPU time 3.04 seconds
Started Feb 21 03:47:31 PM PST 24
Finished Feb 21 03:47:34 PM PST 24
Peak memory 194708 kb
Host smart-603e67c2-ff8d-4840-be4e-048f03ac049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809212551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3809212551
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3117580441
Short name T596
Test name
Test status
Simulation time 284302060 ps
CPU time 1.44 seconds
Started Feb 21 03:47:39 PM PST 24
Finished Feb 21 03:47:41 PM PST 24
Peak memory 197648 kb
Host smart-9edffa17-35b1-4382-adc1-23a5b4a28889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117580441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3117580441
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1839396049
Short name T457
Test name
Test status
Simulation time 147563872565 ps
CPU time 484.98 seconds
Started Feb 21 03:47:44 PM PST 24
Finished Feb 21 03:55:49 PM PST 24
Peak memory 199624 kb
Host smart-ceb25db9-c228-4d28-925e-96fab84bbbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839396049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1839396049
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2118383641
Short name T1088
Test name
Test status
Simulation time 13558490889 ps
CPU time 15.2 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:58 PM PST 24
Peak memory 199532 kb
Host smart-efbe57ca-a768-4229-a60b-08de61a1f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118383641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2118383641
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.882962964
Short name T515
Test name
Test status
Simulation time 519430020 ps
CPU time 0.97 seconds
Started Feb 21 03:47:31 PM PST 24
Finished Feb 21 03:47:32 PM PST 24
Peak memory 195988 kb
Host smart-1798b734-2237-48a3-9774-b34e0bae3b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882962964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.882962964
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.405593933
Short name T582
Test name
Test status
Simulation time 89217275 ps
CPU time 0.55 seconds
Started Feb 21 03:47:48 PM PST 24
Finished Feb 21 03:47:48 PM PST 24
Peak memory 195104 kb
Host smart-f103d35f-de26-437f-bd66-ff57a41d8cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405593933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.405593933
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2181814095
Short name T1028
Test name
Test status
Simulation time 181070093248 ps
CPU time 77.46 seconds
Started Feb 21 03:47:46 PM PST 24
Finished Feb 21 03:49:04 PM PST 24
Peak memory 199648 kb
Host smart-a0ccb377-b926-4251-ac63-73465aaab0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181814095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2181814095
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2127933114
Short name T1094
Test name
Test status
Simulation time 125744089837 ps
CPU time 54.09 seconds
Started Feb 21 03:47:48 PM PST 24
Finished Feb 21 03:48:42 PM PST 24
Peak memory 199700 kb
Host smart-90a373a8-de00-4a6f-b782-003b66dd060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127933114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2127933114
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.2985122354
Short name T524
Test name
Test status
Simulation time 106974659653 ps
CPU time 40.52 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:36 PM PST 24
Peak memory 198824 kb
Host smart-bec4fdf2-e50e-45f3-9d55-13981325cb1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985122354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2985122354
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.37674039
Short name T878
Test name
Test status
Simulation time 99351030344 ps
CPU time 225.96 seconds
Started Feb 21 03:47:38 PM PST 24
Finished Feb 21 03:51:25 PM PST 24
Peak memory 199588 kb
Host smart-26b90234-329f-4bbf-a2ce-7bb4b1535a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37674039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.37674039
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1838034201
Short name T928
Test name
Test status
Simulation time 4360896943 ps
CPU time 2.97 seconds
Started Feb 21 03:47:33 PM PST 24
Finished Feb 21 03:47:36 PM PST 24
Peak memory 196860 kb
Host smart-4f465955-a1ba-45ab-96aa-29109228f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838034201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1838034201
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3376895902
Short name T51
Test name
Test status
Simulation time 7932046074 ps
CPU time 13.25 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:09 PM PST 24
Peak memory 193456 kb
Host smart-2f5c7d20-aedf-41ab-8d6c-26c0363e89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376895902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3376895902
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2254461620
Short name T594
Test name
Test status
Simulation time 1869540094 ps
CPU time 17.21 seconds
Started Feb 21 03:47:32 PM PST 24
Finished Feb 21 03:47:49 PM PST 24
Peak memory 197812 kb
Host smart-52b71bab-f6b4-45d6-828a-516ceba5a783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254461620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2254461620
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.939822491
Short name T554
Test name
Test status
Simulation time 110851002551 ps
CPU time 35.08 seconds
Started Feb 21 03:47:40 PM PST 24
Finished Feb 21 03:48:15 PM PST 24
Peak memory 199548 kb
Host smart-afd7fc51-fe81-40a5-969f-a2f98aefb1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939822491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.939822491
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2584440214
Short name T780
Test name
Test status
Simulation time 4147464792 ps
CPU time 2.21 seconds
Started Feb 21 03:47:40 PM PST 24
Finished Feb 21 03:47:42 PM PST 24
Peak memory 195304 kb
Host smart-fb537de4-b128-4630-9539-201ffe77d0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584440214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2584440214
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3137828940
Short name T97
Test name
Test status
Simulation time 34967762 ps
CPU time 0.78 seconds
Started Feb 21 03:47:33 PM PST 24
Finished Feb 21 03:47:34 PM PST 24
Peak memory 217188 kb
Host smart-3bc77779-647b-4dd8-994d-00c92a2c39d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137828940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3137828940
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1907028683
Short name T1016
Test name
Test status
Simulation time 496692554 ps
CPU time 1.8 seconds
Started Feb 21 03:47:30 PM PST 24
Finished Feb 21 03:47:32 PM PST 24
Peak memory 197924 kb
Host smart-2cc9ce2a-5ce0-481f-aa21-99c41e8af6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907028683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1907028683
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3795124305
Short name T325
Test name
Test status
Simulation time 40090744525 ps
CPU time 362.19 seconds
Started Feb 21 03:47:31 PM PST 24
Finished Feb 21 03:53:34 PM PST 24
Peak memory 213188 kb
Host smart-e4cd4374-94ac-448c-a397-6877c960e4de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795124305 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3795124305
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1487665363
Short name T441
Test name
Test status
Simulation time 2597776824 ps
CPU time 2.61 seconds
Started Feb 21 03:47:36 PM PST 24
Finished Feb 21 03:47:39 PM PST 24
Peak memory 197952 kb
Host smart-6cfe8dfa-d80e-4af0-8405-ecbfefe3932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487665363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1487665363
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3240010117
Short name T957
Test name
Test status
Simulation time 38218984989 ps
CPU time 12.07 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:07 PM PST 24
Peak memory 199712 kb
Host smart-7a630df8-f63d-44c3-aead-75853387cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240010117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3240010117
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2328840869
Short name T630
Test name
Test status
Simulation time 68034351 ps
CPU time 0.54 seconds
Started Feb 21 03:48:47 PM PST 24
Finished Feb 21 03:48:48 PM PST 24
Peak memory 195076 kb
Host smart-932e5584-b858-4bab-acfd-52ff6fe4e653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328840869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2328840869
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1015033476
Short name T848
Test name
Test status
Simulation time 61833130919 ps
CPU time 87.29 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 03:50:00 PM PST 24
Peak memory 199616 kb
Host smart-63d63cc4-b9e3-493e-b17d-bbc8ebbd3678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015033476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1015033476
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.736991799
Short name T513
Test name
Test status
Simulation time 93670724376 ps
CPU time 63.53 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:49:25 PM PST 24
Peak memory 199540 kb
Host smart-fa4a068b-4dc5-44da-8800-f0451a7c5d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736991799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.736991799
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.872974226
Short name T393
Test name
Test status
Simulation time 57365433252 ps
CPU time 34.69 seconds
Started Feb 21 03:48:39 PM PST 24
Finished Feb 21 03:49:16 PM PST 24
Peak memory 199364 kb
Host smart-ae792c4c-ad60-43bd-9b5c-aa7850b14f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872974226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.872974226
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.648350170
Short name T661
Test name
Test status
Simulation time 513502232417 ps
CPU time 312.03 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 03:53:45 PM PST 24
Peak memory 199212 kb
Host smart-3ebd97f0-6339-4676-ab54-8f7e78a8e0ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648350170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.648350170
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2181975553
Short name T1065
Test name
Test status
Simulation time 77028522686 ps
CPU time 211.65 seconds
Started Feb 21 03:48:22 PM PST 24
Finished Feb 21 03:51:54 PM PST 24
Peak memory 199720 kb
Host smart-d17b6f94-9903-4b20-a0c6-e85c38ada593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181975553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2181975553
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.776969620
Short name T13
Test name
Test status
Simulation time 8685166781 ps
CPU time 6.22 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:49:00 PM PST 24
Peak memory 198324 kb
Host smart-5f8856b1-eb2c-4647-8ac0-58bb7d076732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776969620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.776969620
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1007049614
Short name T407
Test name
Test status
Simulation time 222889228196 ps
CPU time 91.63 seconds
Started Feb 21 03:48:28 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 200044 kb
Host smart-6f0b36bb-71b9-4ff7-9aab-40f8a8b44444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007049614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1007049614
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.985243850
Short name T626
Test name
Test status
Simulation time 13031576944 ps
CPU time 179.32 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:51:35 PM PST 24
Peak memory 199648 kb
Host smart-3eeeb48b-31a0-462a-b4d1-984a0d49f260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985243850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.985243850
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2103887119
Short name T334
Test name
Test status
Simulation time 72078783662 ps
CPU time 12.98 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:48:45 PM PST 24
Peak memory 199120 kb
Host smart-1e98f0b1-3d8c-4f3e-913f-f05279db5d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103887119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2103887119
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2912140455
Short name T470
Test name
Test status
Simulation time 4872207126 ps
CPU time 2.82 seconds
Started Feb 21 03:48:28 PM PST 24
Finished Feb 21 03:48:31 PM PST 24
Peak memory 195384 kb
Host smart-96bccccb-9e8f-4551-97ef-22dd72401341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912140455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2912140455
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2216976939
Short name T543
Test name
Test status
Simulation time 576810458 ps
CPU time 1.72 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 03:48:37 PM PST 24
Peak memory 198520 kb
Host smart-dcdf505b-43cf-4ff9-8bc5-eb8f39c2982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216976939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2216976939
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3057395957
Short name T609
Test name
Test status
Simulation time 2019201495 ps
CPU time 2.77 seconds
Started Feb 21 03:48:22 PM PST 24
Finished Feb 21 03:48:25 PM PST 24
Peak memory 198276 kb
Host smart-b252fe70-f1e0-4169-984a-eba6bc0b5f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057395957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3057395957
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3433425831
Short name T100
Test name
Test status
Simulation time 72988216395 ps
CPU time 25.37 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 03:49:00 PM PST 24
Peak memory 199628 kb
Host smart-85062e1e-7690-428f-8133-c765d29e89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433425831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3433425831
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1795517099
Short name T190
Test name
Test status
Simulation time 48824704350 ps
CPU time 75.15 seconds
Started Feb 21 03:51:57 PM PST 24
Finished Feb 21 03:53:13 PM PST 24
Peak memory 199600 kb
Host smart-b0c2249c-4290-400a-b9ce-e5bbc12b2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795517099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1795517099
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3903660893
Short name T1069
Test name
Test status
Simulation time 21405843339 ps
CPU time 15.96 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:52:23 PM PST 24
Peak memory 199592 kb
Host smart-5d755199-3942-45b2-85ec-adbac88e706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903660893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3903660893
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.381307163
Short name T783
Test name
Test status
Simulation time 34235577199 ps
CPU time 22.93 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:34 PM PST 24
Peak memory 199312 kb
Host smart-f0c61edd-1d06-4456-83ef-b5430feb0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381307163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.381307163
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3408648814
Short name T497
Test name
Test status
Simulation time 83259399032 ps
CPU time 32.13 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:52:39 PM PST 24
Peak memory 199628 kb
Host smart-ad8e6ab4-cfde-4741-a4b7-b44dde1e7c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408648814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3408648814
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2305182133
Short name T346
Test name
Test status
Simulation time 35552189507 ps
CPU time 58.49 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:53:06 PM PST 24
Peak memory 199692 kb
Host smart-88a674dc-c6a5-42b4-be8d-b8ed7275c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305182133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2305182133
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2404015308
Short name T544
Test name
Test status
Simulation time 50869405161 ps
CPU time 31.24 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:42 PM PST 24
Peak memory 198728 kb
Host smart-044e872f-27e9-4fa0-a6e0-a87ce872d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404015308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2404015308
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.169846825
Short name T151
Test name
Test status
Simulation time 22854666790 ps
CPU time 37.25 seconds
Started Feb 21 03:52:06 PM PST 24
Finished Feb 21 03:52:44 PM PST 24
Peak memory 199596 kb
Host smart-6d24d3bd-0146-4eb1-809f-ced2384835cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169846825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.169846825
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.571794979
Short name T593
Test name
Test status
Simulation time 15142407149 ps
CPU time 21.05 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:52:29 PM PST 24
Peak memory 199636 kb
Host smart-b106fa3e-261e-4096-917c-c1054edd79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571794979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.571794979
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2320550301
Short name T951
Test name
Test status
Simulation time 23940695 ps
CPU time 0.54 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:48:55 PM PST 24
Peak memory 195104 kb
Host smart-ea517b82-069f-47d9-bd65-294e19d9552d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320550301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2320550301
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.143368599
Short name T239
Test name
Test status
Simulation time 212151484853 ps
CPU time 292.64 seconds
Started Feb 21 03:48:22 PM PST 24
Finished Feb 21 03:53:15 PM PST 24
Peak memory 199708 kb
Host smart-2e4007d3-e0a7-4e77-b461-3d6913449453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143368599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.143368599
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1546803404
Short name T492
Test name
Test status
Simulation time 80466684929 ps
CPU time 141.62 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:51:16 PM PST 24
Peak memory 199628 kb
Host smart-9f20058f-f04a-4278-ae5e-09b3f4e3b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546803404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1546803404
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.41092597
Short name T254
Test name
Test status
Simulation time 18559262162 ps
CPU time 24.63 seconds
Started Feb 21 03:48:28 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 199828 kb
Host smart-6fdc94dc-8e74-4661-a446-b8a13fde4596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41092597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.41092597
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4202402985
Short name T568
Test name
Test status
Simulation time 68387349558 ps
CPU time 538.22 seconds
Started Feb 21 03:48:18 PM PST 24
Finished Feb 21 03:57:17 PM PST 24
Peak memory 199688 kb
Host smart-49ba2989-5dd6-4130-a7e5-7f7387019160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202402985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4202402985
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_noise_filter.687954863
Short name T162
Test name
Test status
Simulation time 159538178969 ps
CPU time 67.87 seconds
Started Feb 21 03:48:29 PM PST 24
Finished Feb 21 03:49:38 PM PST 24
Peak memory 199852 kb
Host smart-578a707d-04fc-4f3b-92ca-0c649e9deeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687954863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.687954863
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.806702703
Short name T592
Test name
Test status
Simulation time 23823227423 ps
CPU time 1195.07 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 04:08:17 PM PST 24
Peak memory 199672 kb
Host smart-250e6749-0f22-4490-b6b4-b2266572b2e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806702703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.806702703
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1160901674
Short name T85
Test name
Test status
Simulation time 2686412452 ps
CPU time 31.33 seconds
Started Feb 21 03:48:22 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 198096 kb
Host smart-0d7f2b8c-39de-4bd0-a2e4-0da332922e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160901674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1160901674
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3343537104
Short name T274
Test name
Test status
Simulation time 55712024578 ps
CPU time 11.29 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:38 PM PST 24
Peak memory 197364 kb
Host smart-50d56d92-4874-4336-8b54-9105fa21f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343537104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3343537104
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2345285317
Short name T549
Test name
Test status
Simulation time 1715263425 ps
CPU time 3.47 seconds
Started Feb 21 03:48:29 PM PST 24
Finished Feb 21 03:48:33 PM PST 24
Peak memory 195144 kb
Host smart-9e41b174-beb8-41d8-a643-57b36d8a0d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345285317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2345285317
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4219326520
Short name T1054
Test name
Test status
Simulation time 523836554 ps
CPU time 1.21 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 03:48:36 PM PST 24
Peak memory 197592 kb
Host smart-da702b81-0884-4374-a2e1-7e22de840bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219326520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4219326520
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2706512964
Short name T615
Test name
Test status
Simulation time 49863817598 ps
CPU time 139.24 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:51:24 PM PST 24
Peak memory 199672 kb
Host smart-98648cb7-5f55-4123-80fa-311b9f125b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706512964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2706512964
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2499147035
Short name T692
Test name
Test status
Simulation time 1576060580 ps
CPU time 2.61 seconds
Started Feb 21 03:48:27 PM PST 24
Finished Feb 21 03:48:30 PM PST 24
Peak memory 197976 kb
Host smart-331d49ba-2e21-44de-97eb-189d67e75e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499147035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2499147035
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2536838600
Short name T698
Test name
Test status
Simulation time 47360049003 ps
CPU time 20.95 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 03:48:53 PM PST 24
Peak memory 199660 kb
Host smart-5e116472-ccd7-4012-bfcd-93738fcf4ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536838600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2536838600
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3379609369
Short name T1090
Test name
Test status
Simulation time 107532307393 ps
CPU time 142.37 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:54:30 PM PST 24
Peak memory 199628 kb
Host smart-cb20a824-f7e5-4ba6-a339-a24658a6d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379609369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3379609369
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3032858969
Short name T154
Test name
Test status
Simulation time 28444189566 ps
CPU time 69.34 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:53:16 PM PST 24
Peak memory 199652 kb
Host smart-89bcf63f-03c9-4c36-a521-a97f49424b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032858969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3032858969
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2487983532
Short name T277
Test name
Test status
Simulation time 32745313587 ps
CPU time 54.29 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:53:07 PM PST 24
Peak memory 199640 kb
Host smart-b91c8f46-2ca5-44dd-a200-77e35c0cc2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487983532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2487983532
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1954929668
Short name T321
Test name
Test status
Simulation time 191981029381 ps
CPU time 34.86 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:52:44 PM PST 24
Peak memory 199700 kb
Host smart-69c6de58-3d0c-4bc5-a422-df305f3a28dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954929668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1954929668
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2983155975
Short name T704
Test name
Test status
Simulation time 36243734 ps
CPU time 0.56 seconds
Started Feb 21 03:48:18 PM PST 24
Finished Feb 21 03:48:19 PM PST 24
Peak memory 194052 kb
Host smart-6cedaf29-15d5-47c0-8812-5e3b80093fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983155975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2983155975
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3641463181
Short name T1027
Test name
Test status
Simulation time 70223841873 ps
CPU time 59.37 seconds
Started Feb 21 03:48:29 PM PST 24
Finished Feb 21 03:49:29 PM PST 24
Peak memory 199812 kb
Host smart-778fbb69-5c89-4100-bb45-0c44b7993ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641463181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3641463181
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1300739952
Short name T799
Test name
Test status
Simulation time 53694988774 ps
CPU time 14.46 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:41 PM PST 24
Peak memory 197180 kb
Host smart-4919d1e7-b09f-4e75-a65a-09381a686151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300739952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1300739952
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.2428438311
Short name T785
Test name
Test status
Simulation time 870720134089 ps
CPU time 607.36 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:58:34 PM PST 24
Peak memory 199628 kb
Host smart-b14a4d8e-4432-4057-8bbd-dc93365d6a3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428438311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2428438311
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2955102197
Short name T421
Test name
Test status
Simulation time 122348606384 ps
CPU time 135.08 seconds
Started Feb 21 03:48:32 PM PST 24
Finished Feb 21 03:50:48 PM PST 24
Peak memory 199612 kb
Host smart-4b3b63f6-fa61-4830-9af6-8d1331da0661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955102197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2955102197
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.363107590
Short name T21
Test name
Test status
Simulation time 9504682844 ps
CPU time 21.31 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:48 PM PST 24
Peak memory 198808 kb
Host smart-704e35f3-6d43-4635-8ded-5107a85940a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363107590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.363107590
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.261353569
Short name T614
Test name
Test status
Simulation time 159752237659 ps
CPU time 98.08 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:50:14 PM PST 24
Peak memory 199956 kb
Host smart-adb542c6-ef95-4593-9d4b-3889a34328e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261353569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.261353569
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4125716212
Short name T559
Test name
Test status
Simulation time 24126731287 ps
CPU time 315.62 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:53:48 PM PST 24
Peak memory 199908 kb
Host smart-16c48233-8d7e-4e2a-ac2b-f65cef2cbc5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125716212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4125716212
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4187945102
Short name T833
Test name
Test status
Simulation time 2467287351 ps
CPU time 8.46 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:48:30 PM PST 24
Peak memory 198116 kb
Host smart-177c3091-448f-42c3-a637-9501651e988a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187945102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4187945102
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.486092446
Short name T975
Test name
Test status
Simulation time 196279689780 ps
CPU time 149.76 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:50:51 PM PST 24
Peak memory 199612 kb
Host smart-e1727bf6-04b1-4d7f-b8e6-f86041420a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486092446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.486092446
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3534524925
Short name T437
Test name
Test status
Simulation time 5240782573 ps
CPU time 4.3 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:48:36 PM PST 24
Peak memory 195408 kb
Host smart-43fa97b8-5973-4260-926f-4bbb3d46961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534524925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3534524925
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2592828454
Short name T597
Test name
Test status
Simulation time 5985179103 ps
CPU time 16.09 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:48:37 PM PST 24
Peak memory 199024 kb
Host smart-79e2862b-e1c5-4bf0-94c0-2fb589fab4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592828454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2592828454
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.396364538
Short name T107
Test name
Test status
Simulation time 220697868179 ps
CPU time 1271.21 seconds
Started Feb 21 03:48:32 PM PST 24
Finished Feb 21 04:09:45 PM PST 24
Peak memory 199664 kb
Host smart-e3788ed3-854a-43c3-ac0a-ff4416cea3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396364538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.396364538
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1987212977
Short name T434
Test name
Test status
Simulation time 5016772465 ps
CPU time 1.21 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:48:49 PM PST 24
Peak memory 198636 kb
Host smart-dea40174-2cd9-4930-a699-909fdf6b4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987212977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1987212977
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1678926250
Short name T1022
Test name
Test status
Simulation time 43676666992 ps
CPU time 18.41 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:45 PM PST 24
Peak memory 199624 kb
Host smart-6fc8ffe4-1b50-4186-9c3c-1cee8d65666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678926250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1678926250
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.647079679
Short name T893
Test name
Test status
Simulation time 37190929823 ps
CPU time 16.61 seconds
Started Feb 21 03:52:08 PM PST 24
Finished Feb 21 03:52:25 PM PST 24
Peak memory 199492 kb
Host smart-b5fc366b-7807-4c1d-b04f-bed5b5438fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647079679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.647079679
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1345289591
Short name T372
Test name
Test status
Simulation time 126316604289 ps
CPU time 19.35 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:52:27 PM PST 24
Peak memory 199564 kb
Host smart-6f1751f9-7c88-4840-9209-949ab6dafb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345289591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1345289591
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3842926278
Short name T839
Test name
Test status
Simulation time 202681148930 ps
CPU time 594.11 seconds
Started Feb 21 03:52:08 PM PST 24
Finished Feb 21 04:02:03 PM PST 24
Peak memory 199160 kb
Host smart-76b633ee-867e-41ea-b0a0-04f2d83dc90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842926278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3842926278
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.797334011
Short name T187
Test name
Test status
Simulation time 65215033794 ps
CPU time 29.08 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:41 PM PST 24
Peak memory 199392 kb
Host smart-16fef39f-4c3c-46a2-98fc-0551fd7d3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797334011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.797334011
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3709690965
Short name T120
Test name
Test status
Simulation time 76241852955 ps
CPU time 8.09 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:52:18 PM PST 24
Peak memory 199216 kb
Host smart-cafa09a9-c778-4fa5-8bb8-09e60c85598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709690965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3709690965
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.477519113
Short name T248
Test name
Test status
Simulation time 65083558319 ps
CPU time 108.2 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:53:56 PM PST 24
Peak memory 199552 kb
Host smart-e1c1dbf3-cffc-483b-9c28-7ddcc37c34ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477519113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.477519113
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2747919634
Short name T210
Test name
Test status
Simulation time 105494699182 ps
CPU time 172.73 seconds
Started Feb 21 03:52:09 PM PST 24
Finished Feb 21 03:55:03 PM PST 24
Peak memory 199472 kb
Host smart-79ad72fd-de09-4b56-a787-971061191b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747919634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2747919634
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3477113778
Short name T862
Test name
Test status
Simulation time 11059123380 ps
CPU time 18.48 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:30 PM PST 24
Peak memory 199572 kb
Host smart-66d4bdbd-53a2-4a94-8dfa-6b7d3d6b983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477113778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3477113778
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.169280316
Short name T522
Test name
Test status
Simulation time 55307211 ps
CPU time 0.54 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 195172 kb
Host smart-9c3e06f5-daed-47f9-bb25-c24f5f6fa268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169280316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.169280316
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.4142162316
Short name T1102
Test name
Test status
Simulation time 47695502947 ps
CPU time 92.54 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:50:11 PM PST 24
Peak memory 199656 kb
Host smart-bb2767ae-b279-49c4-bd22-f0a8b89f5a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142162316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4142162316
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2162635409
Short name T941
Test name
Test status
Simulation time 118301193446 ps
CPU time 188.49 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:52:03 PM PST 24
Peak memory 198416 kb
Host smart-7daf5564-3784-464d-9c91-1402cf8517df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162635409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2162635409
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.34859220
Short name T821
Test name
Test status
Simulation time 114358120791 ps
CPU time 48.22 seconds
Started Feb 21 03:48:39 PM PST 24
Finished Feb 21 03:49:29 PM PST 24
Peak memory 199612 kb
Host smart-b106ddcb-f25f-4134-891c-5718757df696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34859220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.34859220
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2035203052
Short name T735
Test name
Test status
Simulation time 198881971141 ps
CPU time 337.25 seconds
Started Feb 21 03:48:37 PM PST 24
Finished Feb 21 03:54:15 PM PST 24
Peak memory 199560 kb
Host smart-b0b1da7b-64ee-48e5-b5ab-3441e2f53d1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035203052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2035203052
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1729701196
Short name T413
Test name
Test status
Simulation time 62253796413 ps
CPU time 43.73 seconds
Started Feb 21 03:48:33 PM PST 24
Finished Feb 21 03:49:18 PM PST 24
Peak memory 199468 kb
Host smart-4b131ea3-d256-440f-8933-df432c9b943d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729701196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1729701196
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.600035604
Short name T685
Test name
Test status
Simulation time 9679588652 ps
CPU time 17.2 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 03:48:52 PM PST 24
Peak memory 198064 kb
Host smart-637afac4-b12d-4d07-8d91-a7b80f34d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600035604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.600035604
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1126183880
Short name T475
Test name
Test status
Simulation time 17742939513 ps
CPU time 13.1 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:40 PM PST 24
Peak memory 195484 kb
Host smart-f7a7b817-ec4a-44c2-bf56-df37a75faf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126183880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1126183880
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3082164916
Short name T852
Test name
Test status
Simulation time 7578926200 ps
CPU time 398.52 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:55:34 PM PST 24
Peak memory 199628 kb
Host smart-cbb84369-bffd-4700-a22d-60d5caf511b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082164916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3082164916
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3939837464
Short name T701
Test name
Test status
Simulation time 4335124562 ps
CPU time 9.32 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:48:59 PM PST 24
Peak memory 197988 kb
Host smart-64168855-6752-429c-93ca-e965385b1173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939837464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3939837464
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2235465029
Short name T298
Test name
Test status
Simulation time 20209788962 ps
CPU time 17.4 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:48:59 PM PST 24
Peak memory 198464 kb
Host smart-0e298a84-7cf0-4778-acca-53e1da2b28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235465029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2235465029
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1489545566
Short name T501
Test name
Test status
Simulation time 4253413112 ps
CPU time 7.55 seconds
Started Feb 21 03:48:37 PM PST 24
Finished Feb 21 03:48:46 PM PST 24
Peak memory 195380 kb
Host smart-238d65f9-9642-4086-90d2-1bfa07a5fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489545566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1489545566
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.735974869
Short name T651
Test name
Test status
Simulation time 914609825 ps
CPU time 1.65 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:48:38 PM PST 24
Peak memory 198928 kb
Host smart-4133c437-173a-4769-b16c-e1b977c74652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735974869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.735974869
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2812116832
Short name T575
Test name
Test status
Simulation time 192534281583 ps
CPU time 268.28 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199676 kb
Host smart-49ff7e8b-78c7-466f-8a9c-d3e60436a8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812116832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2812116832
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.280479341
Short name T989
Test name
Test status
Simulation time 633977920 ps
CPU time 1.93 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 03:48:37 PM PST 24
Peak memory 197152 kb
Host smart-897b5691-f860-4fdf-b26e-92f92053771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280479341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.280479341
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3420868263
Short name T570
Test name
Test status
Simulation time 17402488764 ps
CPU time 24.31 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:49:17 PM PST 24
Peak memory 198016 kb
Host smart-a1ca8599-1fdb-4ebf-966c-f8f9fa5f61bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420868263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3420868263
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1275830532
Short name T1055
Test name
Test status
Simulation time 33270603925 ps
CPU time 16.03 seconds
Started Feb 21 03:52:06 PM PST 24
Finished Feb 21 03:52:22 PM PST 24
Peak memory 199484 kb
Host smart-17ff6d39-ad0f-432f-9b12-1bcd66a97475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275830532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1275830532
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1257894589
Short name T363
Test name
Test status
Simulation time 30633882811 ps
CPU time 32.8 seconds
Started Feb 21 03:52:07 PM PST 24
Finished Feb 21 03:52:40 PM PST 24
Peak memory 199720 kb
Host smart-1bd6c07f-d77b-4a97-827b-a82522929fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257894589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1257894589
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2372590204
Short name T1059
Test name
Test status
Simulation time 21176224351 ps
CPU time 32.8 seconds
Started Feb 21 03:52:08 PM PST 24
Finished Feb 21 03:52:41 PM PST 24
Peak memory 199548 kb
Host smart-eb2f1531-c28c-4e44-ad84-0fe755573491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372590204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2372590204
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1982945597
Short name T211
Test name
Test status
Simulation time 92180653301 ps
CPU time 8.2 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:20 PM PST 24
Peak memory 199684 kb
Host smart-446be6cc-85a5-4ced-a2c2-bcb378cd608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982945597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1982945597
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2773138801
Short name T167
Test name
Test status
Simulation time 152347759316 ps
CPU time 75.25 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:53:28 PM PST 24
Peak memory 199612 kb
Host smart-47708709-1073-42c7-b00c-9706ea39996d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773138801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2773138801
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1356347591
Short name T397
Test name
Test status
Simulation time 66400596212 ps
CPU time 114.95 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:54:07 PM PST 24
Peak memory 199480 kb
Host smart-f46849ef-871b-4060-abe0-0a19ab680bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356347591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1356347591
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2834493488
Short name T714
Test name
Test status
Simulation time 18686190 ps
CPU time 0.58 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:48:42 PM PST 24
Peak memory 195116 kb
Host smart-850ac9f7-00a8-46e9-a48f-0a2a93e45cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834493488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2834493488
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2839909168
Short name T374
Test name
Test status
Simulation time 35603088681 ps
CPU time 16.04 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:49:05 PM PST 24
Peak memory 199652 kb
Host smart-09839d6e-23e5-434b-a8c7-8d99533202a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839909168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2839909168
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2339119485
Short name T58
Test name
Test status
Simulation time 35392933513 ps
CPU time 48.99 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:49:10 PM PST 24
Peak memory 199580 kb
Host smart-58457c8b-d506-43ec-9158-d71e7a9a129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339119485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2339119485
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1259723679
Short name T794
Test name
Test status
Simulation time 102768529173 ps
CPU time 45.45 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:49:21 PM PST 24
Peak memory 199660 kb
Host smart-8ac662d2-106c-415c-a3cc-64bdd2c7eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259723679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1259723679
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1038289694
Short name T620
Test name
Test status
Simulation time 18311848376 ps
CPU time 7.63 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:48:48 PM PST 24
Peak memory 197088 kb
Host smart-dee364e6-e248-413b-af6d-9b82f0ce6cb9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038289694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1038289694
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1275024698
Short name T410
Test name
Test status
Simulation time 163145906454 ps
CPU time 305.06 seconds
Started Feb 21 03:48:47 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199656 kb
Host smart-72375c26-52d1-4aad-8424-3205c96ce0e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275024698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1275024698
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1141160111
Short name T710
Test name
Test status
Simulation time 6209679375 ps
CPU time 4.29 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 03:48:37 PM PST 24
Peak memory 197920 kb
Host smart-e4c52d6c-eb3e-451a-a9ab-a6046ae45941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141160111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1141160111
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2563282966
Short name T528
Test name
Test status
Simulation time 22826791291 ps
CPU time 41.32 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:49:36 PM PST 24
Peak memory 198024 kb
Host smart-303d02b8-f991-4af0-abcc-726e489ec575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563282966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2563282966
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.170911379
Short name T633
Test name
Test status
Simulation time 28795817812 ps
CPU time 91.57 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:50:12 PM PST 24
Peak memory 199728 kb
Host smart-39894091-051f-466f-bbe9-00892a9abebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170911379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.170911379
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3570195960
Short name T1074
Test name
Test status
Simulation time 1764170063 ps
CPU time 7.05 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:49:00 PM PST 24
Peak memory 197360 kb
Host smart-8f08d956-3d9f-4eca-9c95-2bcfbe1979f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570195960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3570195960
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1359889347
Short name T462
Test name
Test status
Simulation time 806877886 ps
CPU time 1.21 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:48:37 PM PST 24
Peak memory 195052 kb
Host smart-800759bd-8f23-47a7-9d24-fb359015c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359889347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1359889347
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4231679856
Short name T761
Test name
Test status
Simulation time 5912667664 ps
CPU time 8.3 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:35 PM PST 24
Peak memory 198800 kb
Host smart-fbad94c3-90cf-4990-974f-2031a3137563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231679856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4231679856
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2432061172
Short name T612
Test name
Test status
Simulation time 153667460053 ps
CPU time 972.7 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 04:04:48 PM PST 24
Peak memory 199708 kb
Host smart-6a64cb36-5caf-47d9-bf11-91f441d59da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432061172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2432061172
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.658612326
Short name T284
Test name
Test status
Simulation time 28808721920 ps
CPU time 560.08 seconds
Started Feb 21 03:48:42 PM PST 24
Finished Feb 21 03:58:02 PM PST 24
Peak memory 212456 kb
Host smart-db051a15-f73d-49e8-bdd3-a7c3f2785a25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658612326 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.658612326
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3069544416
Short name T979
Test name
Test status
Simulation time 1000443547 ps
CPU time 3.3 seconds
Started Feb 21 03:48:28 PM PST 24
Finished Feb 21 03:48:33 PM PST 24
Peak memory 197556 kb
Host smart-b9bc7300-2647-4446-be3d-2ee32d91c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069544416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3069544416
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.770792400
Short name T824
Test name
Test status
Simulation time 152425433309 ps
CPU time 258.62 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:53:13 PM PST 24
Peak memory 199648 kb
Host smart-2cab9c84-5416-49c7-8b81-5235ee052ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770792400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.770792400
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1594124505
Short name T145
Test name
Test status
Simulation time 7567278741 ps
CPU time 9.25 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:21 PM PST 24
Peak memory 199732 kb
Host smart-d691c49a-e690-46e5-867c-10fa131ea304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594124505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1594124505
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2689308004
Short name T314
Test name
Test status
Simulation time 31782993090 ps
CPU time 136.21 seconds
Started Feb 21 03:52:13 PM PST 24
Finished Feb 21 03:54:30 PM PST 24
Peak memory 199672 kb
Host smart-a7bcdd2b-6170-40f2-9ddf-7d5bbca4cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689308004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2689308004
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3575849317
Short name T386
Test name
Test status
Simulation time 37054250532 ps
CPU time 16.06 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:27 PM PST 24
Peak memory 199736 kb
Host smart-29b32f58-23e1-4e1b-98b7-c096f3e2c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575849317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3575849317
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2401906707
Short name T57
Test name
Test status
Simulation time 83578257980 ps
CPU time 121.25 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:54:14 PM PST 24
Peak memory 199588 kb
Host smart-eef43f6d-2dcb-4f33-936c-525b3f61a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401906707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2401906707
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1241172759
Short name T146
Test name
Test status
Simulation time 33312620600 ps
CPU time 50.43 seconds
Started Feb 21 03:52:13 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199704 kb
Host smart-bf22d993-21a0-4b62-b183-529a6082f627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241172759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1241172759
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1396353149
Short name T237
Test name
Test status
Simulation time 26792650333 ps
CPU time 39.59 seconds
Started Feb 21 03:52:11 PM PST 24
Finished Feb 21 03:52:51 PM PST 24
Peak memory 199660 kb
Host smart-10f4932c-d057-4700-be2c-808ae2149dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396353149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1396353149
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3687391243
Short name T834
Test name
Test status
Simulation time 131807975418 ps
CPU time 88.55 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:53:41 PM PST 24
Peak memory 199656 kb
Host smart-535287fe-f609-4601-97f8-18a4934b3304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687391243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3687391243
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.544723854
Short name T305
Test name
Test status
Simulation time 31306613948 ps
CPU time 49.36 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:53:01 PM PST 24
Peak memory 199672 kb
Host smart-0d1b2adb-289f-4aa4-b7b5-b9a960d78112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544723854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.544723854
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2280672121
Short name T829
Test name
Test status
Simulation time 10031633 ps
CPU time 0.53 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 194080 kb
Host smart-1634a895-f2ac-43f2-b75e-1ddb0a5aaa18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280672121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2280672121
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3328177887
Short name T787
Test name
Test status
Simulation time 358310775288 ps
CPU time 214.92 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 03:52:18 PM PST 24
Peak memory 199480 kb
Host smart-cafba278-13aa-4b90-a2d5-401af1996d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328177887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3328177887
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.120257352
Short name T482
Test name
Test status
Simulation time 338391433539 ps
CPU time 534.84 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:57:33 PM PST 24
Peak memory 198720 kb
Host smart-6090b948-8c9f-44f6-a76f-f919812953fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120257352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.120257352
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3223826898
Short name T622
Test name
Test status
Simulation time 190597027911 ps
CPU time 375.74 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:54:54 PM PST 24
Peak memory 198644 kb
Host smart-55b834e4-c9aa-45db-9419-1a81ae3af99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223826898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3223826898
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1216390346
Short name T1031
Test name
Test status
Simulation time 2825441871 ps
CPU time 1.96 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:48:52 PM PST 24
Peak memory 197748 kb
Host smart-1301406a-9427-4d75-b128-81d2335f32ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216390346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1216390346
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1444372330
Short name T456
Test name
Test status
Simulation time 81214616666 ps
CPU time 72.01 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:49:54 PM PST 24
Peak memory 199908 kb
Host smart-f34364cb-7cb7-4fbe-bbe9-345125fd7f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444372330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1444372330
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1820631591
Short name T176
Test name
Test status
Simulation time 12488238054 ps
CPU time 239.35 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:52:41 PM PST 24
Peak memory 199636 kb
Host smart-2aa16f1a-53c7-4430-9bd0-1822a1fb2e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820631591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1820631591
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.805897371
Short name T625
Test name
Test status
Simulation time 1111282465 ps
CPU time 9.32 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:48:58 PM PST 24
Peak memory 197768 kb
Host smart-ac891b9d-09b8-4fc1-9c55-efd10ba8d8d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805897371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.805897371
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1124462256
Short name T1040
Test name
Test status
Simulation time 121456724631 ps
CPU time 189.95 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:52:02 PM PST 24
Peak memory 199668 kb
Host smart-1fb35685-e7d0-4b20-9b90-0134eda933b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124462256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1124462256
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.109707728
Short name T525
Test name
Test status
Simulation time 75604853321 ps
CPU time 123.98 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:50:59 PM PST 24
Peak memory 195176 kb
Host smart-422a1e6a-7cca-4e61-ad99-66bfc443fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109707728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.109707728
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1845990964
Short name T422
Test name
Test status
Simulation time 491137823 ps
CPU time 1.3 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 197908 kb
Host smart-d2d75d01-3f1e-45b3-8975-764d762117e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845990964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1845990964
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.149739741
Short name T529
Test name
Test status
Simulation time 1357231659 ps
CPU time 4.66 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:49:00 PM PST 24
Peak memory 198080 kb
Host smart-d1b0c1ad-83a1-43c8-b226-3e6d5d8655ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149739741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.149739741
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.200890584
Short name T101
Test name
Test status
Simulation time 104619711465 ps
CPU time 252.71 seconds
Started Feb 21 03:48:46 PM PST 24
Finished Feb 21 03:52:59 PM PST 24
Peak memory 199592 kb
Host smart-342bedab-5d21-44e0-8e66-2a2ca375c1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200890584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.200890584
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2824664210
Short name T243
Test name
Test status
Simulation time 43100967672 ps
CPU time 36.3 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:52:47 PM PST 24
Peak memory 199676 kb
Host smart-7273ab5e-ee78-4785-b83e-98ab45531de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824664210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2824664210
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1728809370
Short name T315
Test name
Test status
Simulation time 33946107002 ps
CPU time 19.58 seconds
Started Feb 21 03:52:12 PM PST 24
Finished Feb 21 03:52:32 PM PST 24
Peak memory 199372 kb
Host smart-3304edf9-0be4-429b-acb5-2306736fdc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728809370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1728809370
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.365043033
Short name T338
Test name
Test status
Simulation time 102423196079 ps
CPU time 81.42 seconds
Started Feb 21 03:52:10 PM PST 24
Finished Feb 21 03:53:33 PM PST 24
Peak memory 199628 kb
Host smart-d0506e9c-eca8-47a4-b710-d92dc5cd25b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365043033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.365043033
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4088671981
Short name T907
Test name
Test status
Simulation time 142172678721 ps
CPU time 60.1 seconds
Started Feb 21 03:52:23 PM PST 24
Finished Feb 21 03:53:24 PM PST 24
Peak memory 199564 kb
Host smart-d0228ac9-22d0-41ac-a71f-7b413081f624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088671981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4088671981
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3049384855
Short name T124
Test name
Test status
Simulation time 115928182376 ps
CPU time 184.42 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:55:29 PM PST 24
Peak memory 199736 kb
Host smart-b00dd059-d7df-4403-8841-738ffc701201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049384855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3049384855
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2614224633
Short name T194
Test name
Test status
Simulation time 336956071136 ps
CPU time 92.71 seconds
Started Feb 21 03:52:27 PM PST 24
Finished Feb 21 03:54:00 PM PST 24
Peak memory 199660 kb
Host smart-54ad4c6d-b55a-4a36-abbc-c753bc72b8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614224633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2614224633
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3347372922
Short name T879
Test name
Test status
Simulation time 9676401185 ps
CPU time 16.42 seconds
Started Feb 21 03:52:23 PM PST 24
Finished Feb 21 03:52:40 PM PST 24
Peak memory 198852 kb
Host smart-a06b202e-177e-4cbd-8f3f-086012d58215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347372922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3347372922
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2699130876
Short name T948
Test name
Test status
Simulation time 122122141987 ps
CPU time 195.87 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:55:42 PM PST 24
Peak memory 199728 kb
Host smart-5ccb3378-458e-4e7f-b448-604d7e37cc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699130876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2699130876
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4062845675
Short name T781
Test name
Test status
Simulation time 92065097 ps
CPU time 0.59 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:04 PM PST 24
Peak memory 195104 kb
Host smart-76970308-8238-4ab5-a2e5-0edfa792e105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062845675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4062845675
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4219836195
Short name T309
Test name
Test status
Simulation time 118620522780 ps
CPU time 48.62 seconds
Started Feb 21 03:48:39 PM PST 24
Finished Feb 21 03:49:30 PM PST 24
Peak memory 199608 kb
Host smart-d94c2457-6750-4c00-a833-58897053108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219836195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4219836195
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1632167593
Short name T671
Test name
Test status
Simulation time 101836182391 ps
CPU time 32.42 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:49:27 PM PST 24
Peak memory 199584 kb
Host smart-bd424106-78f7-4548-93f5-796a883a5da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632167593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1632167593
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1726045958
Short name T164
Test name
Test status
Simulation time 53897030402 ps
CPU time 23.04 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:49:14 PM PST 24
Peak memory 199020 kb
Host smart-0c785531-baa8-401f-94cb-656449d042eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726045958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1726045958
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.486443905
Short name T894
Test name
Test status
Simulation time 118445058098 ps
CPU time 220.12 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:52:35 PM PST 24
Peak memory 199636 kb
Host smart-fd02b6f7-4cfd-4533-b5ee-f402e93393f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486443905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.486443905
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.536845400
Short name T820
Test name
Test status
Simulation time 165362679660 ps
CPU time 1452.45 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 04:13:03 PM PST 24
Peak memory 199660 kb
Host smart-bd7ca099-b83e-4077-93e3-25d47b2beffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536845400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.536845400
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2467420417
Short name T844
Test name
Test status
Simulation time 1063960304 ps
CPU time 2.28 seconds
Started Feb 21 03:48:42 PM PST 24
Finished Feb 21 03:48:45 PM PST 24
Peak memory 197984 kb
Host smart-24cc759d-3bae-4fb8-9a3e-e152df523baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467420417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2467420417
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3148655434
Short name T645
Test name
Test status
Simulation time 128035816667 ps
CPU time 114.9 seconds
Started Feb 21 03:48:58 PM PST 24
Finished Feb 21 03:50:54 PM PST 24
Peak memory 199852 kb
Host smart-7207d7b8-b48e-4800-9dd8-5e3bf2e886a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148655434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3148655434
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2229525487
Short name T418
Test name
Test status
Simulation time 17485764719 ps
CPU time 995.3 seconds
Started Feb 21 03:49:01 PM PST 24
Finished Feb 21 04:05:37 PM PST 24
Peak memory 199628 kb
Host smart-12c0480c-a402-467f-ba41-d387f6e86c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229525487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2229525487
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1701762208
Short name T985
Test name
Test status
Simulation time 5970448441 ps
CPU time 3.64 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 195476 kb
Host smart-48a6b45c-0adf-4691-b9f8-895ee88710c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701762208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1701762208
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3833244292
Short name T47
Test name
Test status
Simulation time 641220238 ps
CPU time 3.03 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:48:53 PM PST 24
Peak memory 198148 kb
Host smart-0a9e1f18-7d0c-4f86-af33-965d98b23431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833244292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3833244292
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2478394319
Short name T1019
Test name
Test status
Simulation time 255844796982 ps
CPU time 924.65 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 04:04:08 PM PST 24
Peak memory 199552 kb
Host smart-ea854f92-5ab1-4d92-8f63-bbe75822fe84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478394319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2478394319
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1335851848
Short name T509
Test name
Test status
Simulation time 766070928 ps
CPU time 2.3 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:48:43 PM PST 24
Peak memory 197712 kb
Host smart-6984b272-31c6-4820-9867-6f2b551577ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335851848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1335851848
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1645287159
Short name T782
Test name
Test status
Simulation time 23090788631 ps
CPU time 40.47 seconds
Started Feb 21 03:48:42 PM PST 24
Finished Feb 21 03:49:23 PM PST 24
Peak memory 199640 kb
Host smart-62aca888-8a9e-4229-8e2c-3b2532a9b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645287159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1645287159
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.694496207
Short name T409
Test name
Test status
Simulation time 106059852449 ps
CPU time 21.56 seconds
Started Feb 21 03:52:27 PM PST 24
Finished Feb 21 03:52:48 PM PST 24
Peak memory 199684 kb
Host smart-a5fd1349-abd1-4888-9674-d1fe5214fbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694496207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.694496207
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2086220881
Short name T961
Test name
Test status
Simulation time 116819392647 ps
CPU time 198.52 seconds
Started Feb 21 03:52:25 PM PST 24
Finished Feb 21 03:55:43 PM PST 24
Peak memory 199528 kb
Host smart-9c2ceef0-00d5-4fa7-b7d5-aa3241d95527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086220881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2086220881
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1414654144
Short name T300
Test name
Test status
Simulation time 109581617465 ps
CPU time 158.9 seconds
Started Feb 21 03:52:23 PM PST 24
Finished Feb 21 03:55:02 PM PST 24
Peak memory 199656 kb
Host smart-ceb2aed1-d2db-45e2-992a-ad1bcb16f673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414654144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1414654144
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.523920123
Short name T916
Test name
Test status
Simulation time 25507641582 ps
CPU time 12 seconds
Started Feb 21 03:52:25 PM PST 24
Finished Feb 21 03:52:38 PM PST 24
Peak memory 199604 kb
Host smart-2ba31fa4-0185-4549-926b-235d11b74a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523920123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.523920123
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1044839965
Short name T281
Test name
Test status
Simulation time 22632162978 ps
CPU time 21.62 seconds
Started Feb 21 03:52:23 PM PST 24
Finished Feb 21 03:52:45 PM PST 24
Peak memory 199676 kb
Host smart-069afb64-deaa-458f-aad7-3f8406893991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044839965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1044839965
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.106807641
Short name T693
Test name
Test status
Simulation time 30299766613 ps
CPU time 63.3 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:53:27 PM PST 24
Peak memory 199660 kb
Host smart-115eae06-23f2-41d3-afa4-2a2c8be7570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106807641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.106807641
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1679048901
Short name T230
Test name
Test status
Simulation time 86354145426 ps
CPU time 13.47 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:52:38 PM PST 24
Peak memory 199724 kb
Host smart-76ed09d7-585e-407f-9fe6-ae2ed020b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679048901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1679048901
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2368053349
Short name T719
Test name
Test status
Simulation time 38403541 ps
CPU time 0.56 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 195132 kb
Host smart-0fab8294-f740-480a-8b01-60981ea8e6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368053349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2368053349
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.24443115
Short name T429
Test name
Test status
Simulation time 34378435366 ps
CPU time 78.83 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:50:22 PM PST 24
Peak memory 199748 kb
Host smart-9bad2bd6-aa68-4059-8712-bc817ae3472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24443115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.24443115
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.728445751
Short name T398
Test name
Test status
Simulation time 129045556310 ps
CPU time 14.25 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:14 PM PST 24
Peak memory 199092 kb
Host smart-f04e448e-3167-4abb-907f-72d25c3c73bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728445751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.728445751
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1246247344
Short name T933
Test name
Test status
Simulation time 20741386160 ps
CPU time 7.12 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:12 PM PST 24
Peak memory 199732 kb
Host smart-23b644c5-a04c-4ed3-835a-d97abbb506aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246247344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1246247344
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3319489845
Short name T915
Test name
Test status
Simulation time 102038608315 ps
CPU time 46.99 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:51 PM PST 24
Peak memory 197788 kb
Host smart-c52025c4-1998-4e14-9db9-dbe437687ea9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319489845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3319489845
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3807936799
Short name T663
Test name
Test status
Simulation time 147095993417 ps
CPU time 241.92 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:53:07 PM PST 24
Peak memory 199648 kb
Host smart-6c04aae8-be5b-42e4-b254-22d646464f61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807936799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3807936799
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.161681168
Short name T668
Test name
Test status
Simulation time 1803085665 ps
CPU time 1.93 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 198036 kb
Host smart-cf14ac3a-416b-438a-8b89-3602e2f3482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161681168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.161681168
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2613157236
Short name T558
Test name
Test status
Simulation time 12376343174 ps
CPU time 23.32 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:49:20 PM PST 24
Peak memory 198016 kb
Host smart-fa4d100f-25b2-40df-9f1d-8c07b8ae45f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613157236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2613157236
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3328234798
Short name T644
Test name
Test status
Simulation time 24958913511 ps
CPU time 204.67 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:52:29 PM PST 24
Peak memory 199560 kb
Host smart-6b85f27d-41a3-4920-aa7b-cc915e346c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328234798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3328234798
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3678101178
Short name T563
Test name
Test status
Simulation time 3877998688 ps
CPU time 35.55 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:49:31 PM PST 24
Peak memory 198120 kb
Host smart-74ca6d04-ba2f-4d87-8f33-c8ed038b52cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678101178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3678101178
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3212997865
Short name T808
Test name
Test status
Simulation time 2565470966 ps
CPU time 1.64 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 195120 kb
Host smart-0c1055c9-a933-4580-aa9c-5b7de0416d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212997865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3212997865
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1212644638
Short name T42
Test name
Test status
Simulation time 551425878 ps
CPU time 2.1 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:05 PM PST 24
Peak memory 197832 kb
Host smart-6ca69075-d2f0-495f-8676-3fc677a00415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212644638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1212644638
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.4291593127
Short name T934
Test name
Test status
Simulation time 1091434686652 ps
CPU time 2853.94 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 04:36:39 PM PST 24
Peak memory 199664 kb
Host smart-cbb26a41-ad6a-4592-be18-6cb5a9597557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291593127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4291593127
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.67795268
Short name T737
Test name
Test status
Simulation time 758719808 ps
CPU time 1.29 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 198584 kb
Host smart-ed553497-1487-40cf-a392-c883dd73bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67795268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.67795268
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1055999113
Short name T730
Test name
Test status
Simulation time 12390738636 ps
CPU time 5.7 seconds
Started Feb 21 03:49:00 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 197200 kb
Host smart-6c3a26fd-1901-4ba4-8fc3-54c5a1af1606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055999113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1055999113
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.528614468
Short name T250
Test name
Test status
Simulation time 23112949712 ps
CPU time 13.83 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:52:38 PM PST 24
Peak memory 199868 kb
Host smart-dab03afe-6d4b-46ef-97a7-a8c07d707aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528614468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.528614468
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.284479805
Short name T686
Test name
Test status
Simulation time 19215511499 ps
CPU time 37.42 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:53:03 PM PST 24
Peak memory 199640 kb
Host smart-7fbaadcf-b9db-4977-aee0-44d3ed6949be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284479805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.284479805
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2103185702
Short name T373
Test name
Test status
Simulation time 163576917122 ps
CPU time 78.38 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:53:45 PM PST 24
Peak memory 199632 kb
Host smart-c6d6c3d4-ee3a-43c7-881c-f84ad837b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103185702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2103185702
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.4272055843
Short name T223
Test name
Test status
Simulation time 68958606302 ps
CPU time 54.31 seconds
Started Feb 21 03:52:28 PM PST 24
Finished Feb 21 03:53:23 PM PST 24
Peak memory 199772 kb
Host smart-22e33bb4-f10d-4d78-933c-cfc304de0c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272055843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.4272055843
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2782997084
Short name T729
Test name
Test status
Simulation time 34133205933 ps
CPU time 10.83 seconds
Started Feb 21 03:52:22 PM PST 24
Finished Feb 21 03:52:33 PM PST 24
Peak memory 198968 kb
Host smart-2e8cb1d3-9a40-451f-a88e-c0abcd08ccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782997084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2782997084
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.401007227
Short name T199
Test name
Test status
Simulation time 175530708308 ps
CPU time 42.1 seconds
Started Feb 21 03:52:27 PM PST 24
Finished Feb 21 03:53:09 PM PST 24
Peak memory 199344 kb
Host smart-334134a3-a51d-409d-9044-138f788cdd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401007227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.401007227
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.4259741451
Short name T679
Test name
Test status
Simulation time 141690159142 ps
CPU time 213.67 seconds
Started Feb 21 03:52:26 PM PST 24
Finished Feb 21 03:56:00 PM PST 24
Peak memory 199292 kb
Host smart-f6b79ddb-f9ba-4b91-89ce-3a2b78335fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259741451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.4259741451
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2009020105
Short name T339
Test name
Test status
Simulation time 24691291485 ps
CPU time 21.17 seconds
Started Feb 21 03:52:24 PM PST 24
Finished Feb 21 03:52:45 PM PST 24
Peak memory 199488 kb
Host smart-acb0bd34-33b7-45a1-91bd-96eb6791b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009020105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2009020105
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2476818189
Short name T222
Test name
Test status
Simulation time 150312166919 ps
CPU time 226.2 seconds
Started Feb 21 03:52:35 PM PST 24
Finished Feb 21 03:56:22 PM PST 24
Peak memory 199660 kb
Host smart-bac4c0f3-3158-4753-88b3-e65ea7cdb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476818189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2476818189
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2924803997
Short name T982
Test name
Test status
Simulation time 73515771 ps
CPU time 0.54 seconds
Started Feb 21 03:48:35 PM PST 24
Finished Feb 21 03:48:36 PM PST 24
Peak memory 195088 kb
Host smart-990b17ea-bc59-4c05-ab7c-221aec8b3767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924803997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2924803997
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.673992427
Short name T1104
Test name
Test status
Simulation time 50795640205 ps
CPU time 28.58 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 03:49:12 PM PST 24
Peak memory 199640 kb
Host smart-278f8ece-caf5-4fde-b367-de423714ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673992427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.673992427
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.405981769
Short name T813
Test name
Test status
Simulation time 177194759978 ps
CPU time 64.41 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 198880 kb
Host smart-bf9de50f-f79a-4a11-9577-cc9b4b74e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405981769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.405981769
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.820669549
Short name T251
Test name
Test status
Simulation time 32124125826 ps
CPU time 12.95 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 199624 kb
Host smart-9b35ed80-27a0-4d5f-b115-00630fe76231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820669549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.820669549
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2650188509
Short name T602
Test name
Test status
Simulation time 1248128248566 ps
CPU time 136.03 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:51:09 PM PST 24
Peak memory 199624 kb
Host smart-4c66b642-c8cc-400a-85a7-f0c992055f6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650188509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2650188509
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1305283572
Short name T478
Test name
Test status
Simulation time 79437990178 ps
CPU time 125.74 seconds
Started Feb 21 03:48:44 PM PST 24
Finished Feb 21 03:50:50 PM PST 24
Peak memory 199660 kb
Host smart-27154d8f-9095-4241-9f80-f0e797395f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305283572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1305283572
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1847802429
Short name T650
Test name
Test status
Simulation time 4909088372 ps
CPU time 3.64 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:48:58 PM PST 24
Peak memory 198980 kb
Host smart-1b1781d3-1435-42c1-b60f-b1132103e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847802429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1847802429
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.350327122
Short name T1095
Test name
Test status
Simulation time 122128393227 ps
CPU time 58.01 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 03:49:41 PM PST 24
Peak memory 199840 kb
Host smart-91da2a39-629a-4b63-863f-f7fabdecba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350327122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.350327122
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4021033318
Short name T959
Test name
Test status
Simulation time 7503798400 ps
CPU time 89.34 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:50:24 PM PST 24
Peak memory 199648 kb
Host smart-4c486333-1dea-4bba-921d-b49573a50519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021033318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4021033318
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3725254402
Short name T19
Test name
Test status
Simulation time 3640868797 ps
CPU time 32.69 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:49:27 PM PST 24
Peak memory 197856 kb
Host smart-bb0bc19b-9fd8-4614-aec0-bd3576ec185d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725254402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3725254402
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2226497329
Short name T695
Test name
Test status
Simulation time 52806278117 ps
CPU time 42.88 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:49:32 PM PST 24
Peak memory 199748 kb
Host smart-78cea6f6-4be5-486f-8030-0c72f0086e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226497329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2226497329
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1601517614
Short name T503
Test name
Test status
Simulation time 3719211453 ps
CPU time 1.09 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:48:56 PM PST 24
Peak memory 195400 kb
Host smart-1841ceb7-5014-4676-91ef-d42c4e8290b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601517614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1601517614
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.274789342
Short name T798
Test name
Test status
Simulation time 625745032 ps
CPU time 2.66 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 198052 kb
Host smart-f941fdd2-0eb0-4671-8980-9d5dc3795b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274789342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.274789342
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.92818342
Short name T1078
Test name
Test status
Simulation time 254714822483 ps
CPU time 350.82 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:54:43 PM PST 24
Peak memory 208196 kb
Host smart-9ff208a5-05d8-447f-94c0-3884d8d311fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92818342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.92818342
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2311078449
Short name T706
Test name
Test status
Simulation time 1702952745 ps
CPU time 1.5 seconds
Started Feb 21 03:48:39 PM PST 24
Finished Feb 21 03:48:42 PM PST 24
Peak memory 197720 kb
Host smart-d86d2fe7-b33a-494d-995a-a5506e64d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311078449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2311078449
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3139340390
Short name T777
Test name
Test status
Simulation time 245898615282 ps
CPU time 47.84 seconds
Started Feb 21 03:48:44 PM PST 24
Finished Feb 21 03:49:32 PM PST 24
Peak memory 199660 kb
Host smart-14b71d71-c2fc-45ca-9a72-eb86c86ccc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139340390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3139340390
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2620628027
Short name T1013
Test name
Test status
Simulation time 54729268043 ps
CPU time 49.29 seconds
Started Feb 21 03:52:36 PM PST 24
Finished Feb 21 03:53:26 PM PST 24
Peak memory 199648 kb
Host smart-7d28d4a3-5687-47d8-bb6d-68ffc5227db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620628027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2620628027
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3700358655
Short name T1052
Test name
Test status
Simulation time 17870978731 ps
CPU time 4.82 seconds
Started Feb 21 03:52:36 PM PST 24
Finished Feb 21 03:52:41 PM PST 24
Peak memory 198956 kb
Host smart-23ae9206-d100-49f0-b458-7f5d122a4dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700358655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3700358655
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1035486120
Short name T150
Test name
Test status
Simulation time 146839681561 ps
CPU time 36.16 seconds
Started Feb 21 03:52:36 PM PST 24
Finished Feb 21 03:53:13 PM PST 24
Peak memory 199736 kb
Host smart-3dfb05cc-4a33-43d8-a81c-18892fe9678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035486120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1035486120
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2678923459
Short name T1057
Test name
Test status
Simulation time 91973268294 ps
CPU time 94.47 seconds
Started Feb 21 03:52:36 PM PST 24
Finished Feb 21 03:54:11 PM PST 24
Peak memory 199636 kb
Host smart-a0544d3c-5616-472b-9edd-1cef93696fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678923459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2678923459
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.116170622
Short name T1044
Test name
Test status
Simulation time 139548306381 ps
CPU time 54.42 seconds
Started Feb 21 03:52:38 PM PST 24
Finished Feb 21 03:53:32 PM PST 24
Peak memory 199708 kb
Host smart-3a9122db-5309-4b0a-9f92-6a2afefd68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116170622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.116170622
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1118959426
Short name T690
Test name
Test status
Simulation time 99625899078 ps
CPU time 47.92 seconds
Started Feb 21 03:52:37 PM PST 24
Finished Feb 21 03:53:25 PM PST 24
Peak memory 199528 kb
Host smart-68f73ffb-eb9b-4b19-9968-838b93e3e25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118959426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1118959426
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2668952748
Short name T750
Test name
Test status
Simulation time 40506724 ps
CPU time 0.53 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 195080 kb
Host smart-9974f871-2f12-4888-9417-6d4f62ee2cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668952748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2668952748
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.603954838
Short name T174
Test name
Test status
Simulation time 218610764605 ps
CPU time 195.12 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:52:10 PM PST 24
Peak memory 199704 kb
Host smart-e2c5753b-87ac-45a5-8111-11730a93335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603954838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.603954838
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.951294883
Short name T976
Test name
Test status
Simulation time 72253373089 ps
CPU time 108.09 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:50:48 PM PST 24
Peak memory 199412 kb
Host smart-2591d59d-3aac-4236-ab54-bfaf0fc34a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951294883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.951294883
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.672062257
Short name T689
Test name
Test status
Simulation time 10356472105 ps
CPU time 16.6 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:48:55 PM PST 24
Peak memory 198204 kb
Host smart-eb7e00f1-6288-4174-b75b-4c44dd190da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672062257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.672062257
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3561901950
Short name T662
Test name
Test status
Simulation time 629317399172 ps
CPU time 952.4 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 04:04:33 PM PST 24
Peak memory 199004 kb
Host smart-0b5201b3-74ce-450d-be04-7cd9f25cce90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561901950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3561901950
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3395111682
Short name T11
Test name
Test status
Simulation time 217194036303 ps
CPU time 88.77 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:50:25 PM PST 24
Peak memory 199688 kb
Host smart-17dcf24a-eb71-4c95-a176-ed08273b360c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395111682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3395111682
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.271799585
Short name T3
Test name
Test status
Simulation time 3973627694 ps
CPU time 3.64 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 195116 kb
Host smart-bba0165a-5700-4a23-8dd7-5307db5fa2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271799585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.271799585
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3789794416
Short name T755
Test name
Test status
Simulation time 85429650368 ps
CPU time 68.86 seconds
Started Feb 21 03:48:38 PM PST 24
Finished Feb 21 03:49:49 PM PST 24
Peak memory 198908 kb
Host smart-4692ac9a-457b-436b-ab16-90885b642b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789794416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3789794416
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3900443016
Short name T830
Test name
Test status
Simulation time 18416157427 ps
CPU time 138.91 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:51:11 PM PST 24
Peak memory 199672 kb
Host smart-68b472a4-635a-452d-9212-5799c1e527cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900443016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3900443016
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1626250881
Short name T535
Test name
Test status
Simulation time 1486467265 ps
CPU time 3.28 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:03 PM PST 24
Peak memory 197440 kb
Host smart-a8181240-c0f4-4ac8-9ad8-a3073278820c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626250881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1626250881
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1389900078
Short name T929
Test name
Test status
Simulation time 10988126481 ps
CPU time 22.67 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:49:13 PM PST 24
Peak memory 199708 kb
Host smart-16140c19-515c-4c9a-be62-a0e8be8dbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389900078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1389900078
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1590958658
Short name T425
Test name
Test status
Simulation time 3834471765 ps
CPU time 6.75 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 195380 kb
Host smart-ac1249ed-c1cf-4d81-b7e6-786ee61f5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590958658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1590958658
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1387188371
Short name T973
Test name
Test status
Simulation time 522504592 ps
CPU time 1.63 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:48:38 PM PST 24
Peak memory 197964 kb
Host smart-c18326b0-3203-4e60-b2da-69225e9c98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387188371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1387188371
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1495168403
Short name T944
Test name
Test status
Simulation time 860938087663 ps
CPU time 1195.76 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 04:08:50 PM PST 24
Peak memory 199664 kb
Host smart-f393f0ef-3769-4083-9f61-8f3ce99731a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495168403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1495168403
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3237633664
Short name T108
Test name
Test status
Simulation time 1569450285352 ps
CPU time 818.65 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 04:02:35 PM PST 24
Peak memory 229704 kb
Host smart-912db3bc-511c-45f2-956f-2154f0432943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237633664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3237633664
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.509887484
Short name T22
Test name
Test status
Simulation time 856611504 ps
CPU time 3.71 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:48:53 PM PST 24
Peak memory 198264 kb
Host smart-b5ad8e7d-f629-426f-9b6a-e530dd34e86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509887484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.509887484
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.182363132
Short name T1029
Test name
Test status
Simulation time 64948406861 ps
CPU time 156.07 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:51:35 PM PST 24
Peak memory 199712 kb
Host smart-7b5cbaab-0a37-4319-8123-8f1acff2c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182363132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.182363132
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2365513706
Short name T213
Test name
Test status
Simulation time 174354651443 ps
CPU time 146.78 seconds
Started Feb 21 03:52:41 PM PST 24
Finished Feb 21 03:55:08 PM PST 24
Peak memory 199732 kb
Host smart-46c8af33-3e60-4764-9423-8cff7cfaa2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365513706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2365513706
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3363201445
Short name T221
Test name
Test status
Simulation time 15536294348 ps
CPU time 13.92 seconds
Started Feb 21 03:52:41 PM PST 24
Finished Feb 21 03:52:55 PM PST 24
Peak memory 199060 kb
Host smart-789c2bd1-6fa9-4b6d-87b6-f3647767a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363201445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3363201445
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2599528755
Short name T655
Test name
Test status
Simulation time 25525646285 ps
CPU time 42.38 seconds
Started Feb 21 03:52:37 PM PST 24
Finished Feb 21 03:53:19 PM PST 24
Peak memory 199732 kb
Host smart-0f642f0a-802f-4854-a820-7ba95f3a5898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599528755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2599528755
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3376706827
Short name T257
Test name
Test status
Simulation time 71076800654 ps
CPU time 84.69 seconds
Started Feb 21 03:52:38 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 199720 kb
Host smart-330cdb6e-db84-4e48-bb57-ccc7cda00607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376706827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3376706827
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.286210041
Short name T1089
Test name
Test status
Simulation time 43846286945 ps
CPU time 72.98 seconds
Started Feb 21 03:52:41 PM PST 24
Finished Feb 21 03:53:54 PM PST 24
Peak memory 199556 kb
Host smart-020d2387-20f6-495c-87f6-b116c1ee1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286210041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.286210041
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.689671253
Short name T316
Test name
Test status
Simulation time 141450586441 ps
CPU time 50.96 seconds
Started Feb 21 03:52:34 PM PST 24
Finished Feb 21 03:53:25 PM PST 24
Peak memory 199648 kb
Host smart-8dbfb7fb-9e1f-4a9c-8791-575f5385b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689671253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.689671253
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1929269757
Short name T424
Test name
Test status
Simulation time 76866537390 ps
CPU time 59.29 seconds
Started Feb 21 03:52:37 PM PST 24
Finished Feb 21 03:53:37 PM PST 24
Peak memory 199164 kb
Host smart-b5b0b523-90ee-4e24-8f73-e6b6a711b273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929269757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1929269757
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.932474125
Short name T1032
Test name
Test status
Simulation time 34544712 ps
CPU time 0.53 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:43 PM PST 24
Peak memory 195164 kb
Host smart-bfb7a138-6632-451e-bdc7-4f3069fb5ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932474125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.932474125
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1188222301
Short name T288
Test name
Test status
Simulation time 17986131876 ps
CPU time 28.97 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:24 PM PST 24
Peak memory 199640 kb
Host smart-ca490f64-9173-4232-85d3-d74ff5b6fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188222301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1188222301
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.603231108
Short name T591
Test name
Test status
Simulation time 86460945600 ps
CPU time 137.08 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 03:50:00 PM PST 24
Peak memory 199620 kb
Host smart-93e3352b-6ae6-45e0-9c75-93ee9ec21b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603231108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.603231108
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.117732030
Short name T902
Test name
Test status
Simulation time 82330154080 ps
CPU time 15.69 seconds
Started Feb 21 03:47:33 PM PST 24
Finished Feb 21 03:47:49 PM PST 24
Peak memory 199620 kb
Host smart-8c1238f9-e49c-4cce-abcd-07992ac349e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117732030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.117732030
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.265500126
Short name T1105
Test name
Test status
Simulation time 128961208877 ps
CPU time 878.09 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 04:02:21 PM PST 24
Peak memory 199692 kb
Host smart-23cfa05f-ad68-4e3f-93e2-eb99ebe9d6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265500126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.265500126
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1788147046
Short name T541
Test name
Test status
Simulation time 5170425801 ps
CPU time 9.19 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 03:47:52 PM PST 24
Peak memory 197624 kb
Host smart-57805e3b-5380-474d-bef6-c5a084290984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788147046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1788147046
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3912392610
Short name T426
Test name
Test status
Simulation time 23036158849 ps
CPU time 35.52 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:31 PM PST 24
Peak memory 196136 kb
Host smart-d56701dd-b1f1-4ea3-bc3d-19769fa209b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912392610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3912392610
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3297352792
Short name T1086
Test name
Test status
Simulation time 17482145786 ps
CPU time 249.13 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:52:05 PM PST 24
Peak memory 199620 kb
Host smart-c401e6ef-dfef-43b3-89de-fb08119a2afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297352792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3297352792
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.419287609
Short name T486
Test name
Test status
Simulation time 3897739364 ps
CPU time 16.84 seconds
Started Feb 21 03:47:57 PM PST 24
Finished Feb 21 03:48:14 PM PST 24
Peak memory 198220 kb
Host smart-20888508-3952-40f2-9e2d-5880e735006a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419287609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.419287609
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.535314888
Short name T749
Test name
Test status
Simulation time 137627854946 ps
CPU time 233.38 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:51:36 PM PST 24
Peak memory 199656 kb
Host smart-8265b616-3614-4803-8793-0bb97e157662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535314888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.535314888
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2791633286
Short name T468
Test name
Test status
Simulation time 662317994 ps
CPU time 0.89 seconds
Started Feb 21 03:47:56 PM PST 24
Finished Feb 21 03:47:57 PM PST 24
Peak memory 195032 kb
Host smart-d0b66796-7b32-42a2-9c8c-a8e97ae77160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791633286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2791633286
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.50414261
Short name T33
Test name
Test status
Simulation time 176695320 ps
CPU time 0.85 seconds
Started Feb 21 03:47:57 PM PST 24
Finished Feb 21 03:47:58 PM PST 24
Peak memory 217204 kb
Host smart-aba9b70d-72a4-401b-9bcc-481694c34002
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50414261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.50414261
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4290843652
Short name T771
Test name
Test status
Simulation time 285538632 ps
CPU time 1.81 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:44 PM PST 24
Peak memory 199412 kb
Host smart-ed4267d9-3113-4a05-b7af-280785226560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290843652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4290843652
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3203051660
Short name T447
Test name
Test status
Simulation time 1027480273573 ps
CPU time 2315.59 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 04:26:19 PM PST 24
Peak memory 199628 kb
Host smart-fc74e2f4-4bd9-4235-8286-0715ad83ec1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203051660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3203051660
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4220711476
Short name T333
Test name
Test status
Simulation time 66425424345 ps
CPU time 413.74 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 03:54:37 PM PST 24
Peak memory 216204 kb
Host smart-8daf53e8-0274-4993-8f11-1b47fc8e4ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220711476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4220711476
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1080565825
Short name T442
Test name
Test status
Simulation time 648672647 ps
CPU time 2.41 seconds
Started Feb 21 03:47:57 PM PST 24
Finished Feb 21 03:47:59 PM PST 24
Peak memory 198116 kb
Host smart-4a68eb9c-e2d0-43db-8d31-c42ba6cb0647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080565825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1080565825
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1260146856
Short name T666
Test name
Test status
Simulation time 18527228690 ps
CPU time 31.03 seconds
Started Feb 21 03:47:55 PM PST 24
Finished Feb 21 03:48:26 PM PST 24
Peak memory 199636 kb
Host smart-66c2259e-9ec0-41fa-a4b7-a6d7d60aa3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260146856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1260146856
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2700128746
Short name T674
Test name
Test status
Simulation time 12847451 ps
CPU time 0.55 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:48:56 PM PST 24
Peak memory 194192 kb
Host smart-95c36bca-2302-4353-8468-cfe42418c9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700128746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2700128746
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2959147359
Short name T247
Test name
Test status
Simulation time 245342887156 ps
CPU time 29.1 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:49:22 PM PST 24
Peak memory 199608 kb
Host smart-89c72197-68ab-4130-b43a-2994a69edb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959147359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2959147359
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2040958938
Short name T629
Test name
Test status
Simulation time 223023478545 ps
CPU time 94.39 seconds
Started Feb 21 03:48:42 PM PST 24
Finished Feb 21 03:50:17 PM PST 24
Peak memory 199692 kb
Host smart-8660d90b-da75-4bb8-b931-32ab5aa0832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040958938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2040958938
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1016081103
Short name T258
Test name
Test status
Simulation time 13174625741 ps
CPU time 21.49 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:49:03 PM PST 24
Peak memory 199588 kb
Host smart-97f28410-45c3-4baa-8824-8d1cb49cb525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016081103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1016081103
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1998077102
Short name T826
Test name
Test status
Simulation time 256142715307 ps
CPU time 109.57 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:50:45 PM PST 24
Peak memory 199600 kb
Host smart-7308149f-ba4f-40b6-8b4b-2d5cffea0b62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998077102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1998077102
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_loopback.1592787209
Short name T636
Test name
Test status
Simulation time 5996430740 ps
CPU time 9.73 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:09 PM PST 24
Peak memory 197160 kb
Host smart-4fd443d3-f724-46e1-bb36-aa568828f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592787209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1592787209
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3325987921
Short name T143
Test name
Test status
Simulation time 84311864980 ps
CPU time 16.68 seconds
Started Feb 21 03:49:01 PM PST 24
Finished Feb 21 03:49:19 PM PST 24
Peak memory 195480 kb
Host smart-3f014891-4ef1-4a9f-9abe-57cebe618e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325987921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3325987921
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3959856379
Short name T574
Test name
Test status
Simulation time 11898337731 ps
CPU time 680.73 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 04:00:25 PM PST 24
Peak memory 199744 kb
Host smart-003791bd-56ee-4d3f-b5d9-c0762b8bf230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959856379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3959856379
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2809431860
Short name T898
Test name
Test status
Simulation time 1597984803 ps
CPU time 15.41 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:49:10 PM PST 24
Peak memory 197844 kb
Host smart-d71b9970-6335-407c-9695-a43be05aa3b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809431860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2809431860
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2560805318
Short name T846
Test name
Test status
Simulation time 68255661063 ps
CPU time 49.15 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:49 PM PST 24
Peak memory 198848 kb
Host smart-f9a4f1ea-3563-4eed-bace-b99095298e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560805318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2560805318
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.991902712
Short name T1000
Test name
Test status
Simulation time 530463201 ps
CPU time 1.4 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:04 PM PST 24
Peak memory 195148 kb
Host smart-8a67e1cd-48c6-451a-8c75-5a012d847898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991902712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.991902712
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1425487734
Short name T545
Test name
Test status
Simulation time 274055183 ps
CPU time 1.14 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:48:56 PM PST 24
Peak memory 197668 kb
Host smart-c9f52d06-3834-4aad-998b-c8e8c52cbed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425487734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1425487734
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1416811971
Short name T882
Test name
Test status
Simulation time 204968758080 ps
CPU time 411.67 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:55:56 PM PST 24
Peak memory 199672 kb
Host smart-6b4f65a7-797c-4877-a031-ae0843c6269a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416811971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1416811971
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3328315186
Short name T653
Test name
Test status
Simulation time 1229676609 ps
CPU time 3.09 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 198532 kb
Host smart-1b2a5299-8b2f-4946-b65b-c195f8db7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328315186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3328315186
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4201928364
Short name T404
Test name
Test status
Simulation time 56280694151 ps
CPU time 28.43 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:49:25 PM PST 24
Peak memory 199728 kb
Host smart-3840db6a-4736-4d55-8988-62e43aa16c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201928364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4201928364
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3793805298
Short name T392
Test name
Test status
Simulation time 176100021505 ps
CPU time 51.48 seconds
Started Feb 21 03:52:50 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 199636 kb
Host smart-b3d22a57-f781-460a-8e10-d0dd5f0f2981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793805298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3793805298
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1652549987
Short name T278
Test name
Test status
Simulation time 144890739623 ps
CPU time 48.68 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:38 PM PST 24
Peak memory 199216 kb
Host smart-58501635-2e51-4bae-b240-6b8de024746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652549987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1652549987
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1597161784
Short name T877
Test name
Test status
Simulation time 124074080117 ps
CPU time 266.48 seconds
Started Feb 21 03:52:47 PM PST 24
Finished Feb 21 03:57:14 PM PST 24
Peak memory 199688 kb
Host smart-08821c8c-a503-4e47-b19f-e58fc1d2f758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597161784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1597161784
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2810950372
Short name T170
Test name
Test status
Simulation time 132938123309 ps
CPU time 62.06 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:51 PM PST 24
Peak memory 199720 kb
Host smart-a390465e-02f8-482a-a33d-5f4025e73643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810950372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2810950372
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.833787544
Short name T229
Test name
Test status
Simulation time 38940760602 ps
CPU time 17.44 seconds
Started Feb 21 03:52:51 PM PST 24
Finished Feb 21 03:53:08 PM PST 24
Peak memory 199584 kb
Host smart-7aa8e4f7-98a9-4e1d-b0dc-6ebff388ba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833787544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.833787544
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1483393120
Short name T148
Test name
Test status
Simulation time 29039672550 ps
CPU time 16.3 seconds
Started Feb 21 03:52:47 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199480 kb
Host smart-0eff9ca4-dc98-41fe-b395-920cc2510c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483393120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1483393120
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1872192431
Short name T262
Test name
Test status
Simulation time 36889668910 ps
CPU time 81.5 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:54:11 PM PST 24
Peak memory 199648 kb
Host smart-15ccd667-944f-445f-be33-9872113a628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872192431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1872192431
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1677331225
Short name T987
Test name
Test status
Simulation time 21470725 ps
CPU time 0.57 seconds
Started Feb 21 03:48:41 PM PST 24
Finished Feb 21 03:48:43 PM PST 24
Peak memory 194108 kb
Host smart-24cf4049-ce52-4a62-b9f2-e497a3dc7f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677331225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1677331225
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4293145239
Short name T161
Test name
Test status
Simulation time 65133452228 ps
CPU time 95.84 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:50:31 PM PST 24
Peak memory 199712 kb
Host smart-fa7745d0-9567-481e-9b8d-8d2c956b5947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293145239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4293145239
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.44121943
Short name T155
Test name
Test status
Simulation time 25278240773 ps
CPU time 38.56 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 198956 kb
Host smart-ef246d3c-9e28-4838-bb01-f398ccd77ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44121943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.44121943
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1429679536
Short name T754
Test name
Test status
Simulation time 50077232744 ps
CPU time 72.46 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:50:18 PM PST 24
Peak memory 199676 kb
Host smart-17d7b30e-a3a0-434f-bcca-47603ea8aae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429679536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1429679536
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4121638803
Short name T759
Test name
Test status
Simulation time 658567465061 ps
CPU time 302.89 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:53:58 PM PST 24
Peak memory 198444 kb
Host smart-d66c937b-39ff-4475-bdeb-cc193efb6a8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121638803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4121638803
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2074758276
Short name T506
Test name
Test status
Simulation time 23450155531 ps
CPU time 145.97 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:51:16 PM PST 24
Peak memory 199596 kb
Host smart-522be1dd-79a1-478b-b4fd-3bae3b2273c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074758276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2074758276
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2662719839
Short name T927
Test name
Test status
Simulation time 9744739160 ps
CPU time 14.54 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 03:48:58 PM PST 24
Peak memory 197540 kb
Host smart-48abf4a8-3e55-4980-a344-5138791404f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662719839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2662719839
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.912111026
Short name T604
Test name
Test status
Simulation time 72572536896 ps
CPU time 156.59 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:51:36 PM PST 24
Peak memory 199272 kb
Host smart-402defcc-457b-4a7b-acdb-a9469a9856d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912111026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.912111026
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.28186539
Short name T899
Test name
Test status
Simulation time 48638545818 ps
CPU time 1224.26 seconds
Started Feb 21 03:49:00 PM PST 24
Finished Feb 21 04:09:26 PM PST 24
Peak memory 199680 kb
Host smart-181466f7-d8d4-4b9a-93c4-f54670406ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28186539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.28186539
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2810498786
Short name T835
Test name
Test status
Simulation time 3537411947 ps
CPU time 16.09 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:16 PM PST 24
Peak memory 197580 kb
Host smart-fb500081-2567-4066-b000-521ac3b54f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810498786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2810498786
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.811781534
Short name T1049
Test name
Test status
Simulation time 6774159272 ps
CPU time 2.38 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:48:52 PM PST 24
Peak memory 195364 kb
Host smart-11c2ffd7-9138-4e42-914b-ad2ec2f196f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811781534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.811781534
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.198119379
Short name T861
Test name
Test status
Simulation time 467942911 ps
CPU time 1.44 seconds
Started Feb 21 03:48:55 PM PST 24
Finished Feb 21 03:48:57 PM PST 24
Peak memory 197572 kb
Host smart-41075ac8-deda-471a-9030-17842277e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198119379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.198119379
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2972795464
Short name T743
Test name
Test status
Simulation time 517553338 ps
CPU time 1.98 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:48:54 PM PST 24
Peak memory 197948 kb
Host smart-24445269-202d-498e-81a5-c992b7553f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972795464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2972795464
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.621927245
Short name T54
Test name
Test status
Simulation time 65714773147 ps
CPU time 28.65 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:33 PM PST 24
Peak memory 199652 kb
Host smart-c9b8ca37-dcff-4c39-9a24-2af4fcff1478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621927245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.621927245
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1747298647
Short name T930
Test name
Test status
Simulation time 49827130714 ps
CPU time 22.52 seconds
Started Feb 21 03:52:51 PM PST 24
Finished Feb 21 03:53:14 PM PST 24
Peak memory 199424 kb
Host smart-55c196e6-0959-4cff-8761-3402203bfe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747298647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1747298647
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2295765754
Short name T212
Test name
Test status
Simulation time 94694923240 ps
CPU time 149.95 seconds
Started Feb 21 03:52:50 PM PST 24
Finished Feb 21 03:55:20 PM PST 24
Peak memory 199656 kb
Host smart-7c3d518c-0431-4c38-9f31-a9a9e665b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295765754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2295765754
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1537472497
Short name T381
Test name
Test status
Simulation time 17827216442 ps
CPU time 8.86 seconds
Started Feb 21 03:52:47 PM PST 24
Finished Feb 21 03:52:56 PM PST 24
Peak memory 199628 kb
Host smart-10a957af-275c-4a00-bccb-653251f1621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537472497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1537472497
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1083297917
Short name T240
Test name
Test status
Simulation time 99908985626 ps
CPU time 36.4 seconds
Started Feb 21 03:52:48 PM PST 24
Finished Feb 21 03:53:25 PM PST 24
Peak memory 199636 kb
Host smart-feae7698-19e7-4afd-85f2-9f7b195f4149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083297917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1083297917
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2024110642
Short name T810
Test name
Test status
Simulation time 77753206485 ps
CPU time 30.51 seconds
Started Feb 21 03:52:53 PM PST 24
Finished Feb 21 03:53:24 PM PST 24
Peak memory 199448 kb
Host smart-703e05e8-cff2-4def-ae2e-c6f59449329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024110642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2024110642
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2632683130
Short name T937
Test name
Test status
Simulation time 126484844145 ps
CPU time 17.81 seconds
Started Feb 21 03:52:50 PM PST 24
Finished Feb 21 03:53:08 PM PST 24
Peak memory 199192 kb
Host smart-ee476543-3b41-4135-97a1-9b91acad463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632683130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2632683130
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3872403199
Short name T960
Test name
Test status
Simulation time 52461891367 ps
CPU time 20.5 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:10 PM PST 24
Peak memory 199540 kb
Host smart-9e07814b-5c88-47c5-8504-01e28f229c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872403199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3872403199
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2048311481
Short name T144
Test name
Test status
Simulation time 28614135882 ps
CPU time 37.93 seconds
Started Feb 21 03:52:48 PM PST 24
Finished Feb 21 03:53:26 PM PST 24
Peak memory 199628 kb
Host smart-53097cec-c009-4afb-88aa-31a360711c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048311481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2048311481
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4077465445
Short name T654
Test name
Test status
Simulation time 14610799 ps
CPU time 0.57 seconds
Started Feb 21 03:48:50 PM PST 24
Finished Feb 21 03:48:51 PM PST 24
Peak memory 195132 kb
Host smart-62de4e30-d1e6-47d6-b184-1f1ca0e93c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077465445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4077465445
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2030134344
Short name T807
Test name
Test status
Simulation time 78657514766 ps
CPU time 55.47 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:49:45 PM PST 24
Peak memory 199716 kb
Host smart-80d31eae-3dd4-44af-bd66-88600b400802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030134344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2030134344
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2165888876
Short name T414
Test name
Test status
Simulation time 54622338969 ps
CPU time 80.15 seconds
Started Feb 21 03:48:45 PM PST 24
Finished Feb 21 03:50:06 PM PST 24
Peak memory 199680 kb
Host smart-1573f867-5839-4a56-95ea-c384ec0aaf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165888876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2165888876
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.1338225489
Short name T709
Test name
Test status
Simulation time 58742877434 ps
CPU time 13.39 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:17 PM PST 24
Peak memory 199432 kb
Host smart-e4a256d1-2531-42d5-8d43-da3b3a4c6cc0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338225489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1338225489
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1453936500
Short name T980
Test name
Test status
Simulation time 41889894812 ps
CPU time 176.17 seconds
Started Feb 21 03:48:52 PM PST 24
Finished Feb 21 03:51:49 PM PST 24
Peak memory 199636 kb
Host smart-0f86e4d2-17a8-4c88-8b97-4d47c9469468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453936500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1453936500
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2441649322
Short name T947
Test name
Test status
Simulation time 7172936221 ps
CPU time 2.43 seconds
Started Feb 21 03:48:51 PM PST 24
Finished Feb 21 03:48:53 PM PST 24
Peak memory 198312 kb
Host smart-4fcef94d-c73c-4d85-8d43-0ae22c739217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441649322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2441649322
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.85739285
Short name T557
Test name
Test status
Simulation time 30434006755 ps
CPU time 49.02 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:49:38 PM PST 24
Peak memory 197556 kb
Host smart-6621ba74-6ec1-4c48-8ca0-a418f31604cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85739285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.85739285
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3979811187
Short name T1038
Test name
Test status
Simulation time 21841538466 ps
CPU time 1027.48 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 04:05:57 PM PST 24
Peak memory 199656 kb
Host smart-19298588-8527-407e-8b2d-3c59c72bb8c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979811187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3979811187
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3575028967
Short name T875
Test name
Test status
Simulation time 112395258814 ps
CPU time 49.14 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:53 PM PST 24
Peak memory 199716 kb
Host smart-d05aede8-c8e0-4ca7-b3a4-5ff8ed19d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575028967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3575028967
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2097692757
Short name T494
Test name
Test status
Simulation time 4533727011 ps
CPU time 7.67 seconds
Started Feb 21 03:48:43 PM PST 24
Finished Feb 21 03:48:51 PM PST 24
Peak memory 195384 kb
Host smart-82a28cbd-c557-42a1-9778-f4be04251bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097692757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2097692757
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3521602201
Short name T566
Test name
Test status
Simulation time 498418554 ps
CPU time 1.83 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:48:51 PM PST 24
Peak memory 197488 kb
Host smart-552183b4-f17d-4ef5-8aee-e86cd1cbcc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521602201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3521602201
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2644078775
Short name T149
Test name
Test status
Simulation time 130105809201 ps
CPU time 227.94 seconds
Started Feb 21 03:49:01 PM PST 24
Finished Feb 21 03:52:50 PM PST 24
Peak memory 199760 kb
Host smart-b6f7b8f6-cceb-4c1c-a1ef-ee07bd48610a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644078775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2644078775
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.408586848
Short name T8
Test name
Test status
Simulation time 1064354106 ps
CPU time 2.3 seconds
Started Feb 21 03:48:58 PM PST 24
Finished Feb 21 03:49:01 PM PST 24
Peak memory 198168 kb
Host smart-55721152-39ae-43df-8130-b17154d27686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408586848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.408586848
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3884335373
Short name T1033
Test name
Test status
Simulation time 54230604715 ps
CPU time 13.74 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:48:55 PM PST 24
Peak memory 199156 kb
Host smart-b85604bc-088e-4f61-bbe0-30524187caa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884335373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3884335373
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.247233237
Short name T1018
Test name
Test status
Simulation time 25375712776 ps
CPU time 12.19 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:53:01 PM PST 24
Peak memory 199160 kb
Host smart-5a70217b-0b90-40e4-acdc-95cc3794e066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247233237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.247233237
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2940299637
Short name T606
Test name
Test status
Simulation time 52047409661 ps
CPU time 39.79 seconds
Started Feb 21 03:52:51 PM PST 24
Finished Feb 21 03:53:31 PM PST 24
Peak memory 199536 kb
Host smart-643cc066-45e4-4f25-a62e-31e5d193da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940299637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2940299637
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2233068180
Short name T232
Test name
Test status
Simulation time 137882955195 ps
CPU time 204.33 seconds
Started Feb 21 03:52:49 PM PST 24
Finished Feb 21 03:56:14 PM PST 24
Peak memory 199724 kb
Host smart-9aac3862-bf11-45a9-a923-d237a70d1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233068180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2233068180
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2968863334
Short name T322
Test name
Test status
Simulation time 88330358502 ps
CPU time 95.6 seconds
Started Feb 21 03:53:23 PM PST 24
Finished Feb 21 03:55:00 PM PST 24
Peak memory 199720 kb
Host smart-0608566a-2f22-4f97-a61f-357d162912e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968863334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2968863334
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1222201959
Short name T198
Test name
Test status
Simulation time 26239857464 ps
CPU time 19.62 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:53:34 PM PST 24
Peak memory 199368 kb
Host smart-6ebe333b-b4d6-4233-8822-167bcf21446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222201959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1222201959
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1568467331
Short name T776
Test name
Test status
Simulation time 47571423692 ps
CPU time 23.96 seconds
Started Feb 21 03:53:23 PM PST 24
Finished Feb 21 03:53:47 PM PST 24
Peak memory 199192 kb
Host smart-fbbce721-12e3-4d5a-8515-0700d9edf97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568467331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1568467331
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4006433553
Short name T272
Test name
Test status
Simulation time 31507604119 ps
CPU time 13.63 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:30 PM PST 24
Peak memory 198980 kb
Host smart-dfbe3809-3bd1-4d84-8d72-e2e35b61db18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006433553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4006433553
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2774574088
Short name T354
Test name
Test status
Simulation time 97135716644 ps
CPU time 102.61 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:55:03 PM PST 24
Peak memory 199696 kb
Host smart-a9f90911-85bb-487f-b7fb-625c3f11b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774574088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2774574088
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3329634730
Short name T870
Test name
Test status
Simulation time 18467454953 ps
CPU time 32.02 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:53:46 PM PST 24
Peak memory 199680 kb
Host smart-505935ce-5b07-4d6b-bfd7-374227785a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329634730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3329634730
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.743575648
Short name T883
Test name
Test status
Simulation time 14774838 ps
CPU time 0.57 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:05 PM PST 24
Peak memory 195100 kb
Host smart-74128b7d-0469-40bf-baf2-779b6ea384c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743575648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.743575648
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2350115605
Short name T727
Test name
Test status
Simulation time 63127972861 ps
CPU time 50.26 seconds
Started Feb 21 03:49:05 PM PST 24
Finished Feb 21 03:49:57 PM PST 24
Peak memory 199716 kb
Host smart-c2e01f6c-48f2-4b1a-b874-8b5eb129e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350115605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2350115605
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4152264138
Short name T955
Test name
Test status
Simulation time 59812256219 ps
CPU time 18.81 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:49:13 PM PST 24
Peak memory 199656 kb
Host smart-e21ea471-ae6f-468c-ac01-119cafc49819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152264138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4152264138
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.3532681640
Short name T968
Test name
Test status
Simulation time 75339799325 ps
CPU time 168.32 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 199632 kb
Host smart-9a3e7185-6dd2-4d07-94b6-bb61ee03cfb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532681640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3532681640
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.535576812
Short name T530
Test name
Test status
Simulation time 94367075270 ps
CPU time 241.89 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:53:02 PM PST 24
Peak memory 199232 kb
Host smart-06080906-e3d0-4bbd-9249-40e301a779b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535576812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.535576812
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_noise_filter.981108336
Short name T784
Test name
Test status
Simulation time 56607505765 ps
CPU time 75.94 seconds
Started Feb 21 03:49:00 PM PST 24
Finished Feb 21 03:50:16 PM PST 24
Peak memory 198724 kb
Host smart-5d3457d5-6808-4873-ad50-8e0fce53e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981108336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.981108336
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1901727228
Short name T768
Test name
Test status
Simulation time 24813179432 ps
CPU time 225.9 seconds
Started Feb 21 03:49:00 PM PST 24
Finished Feb 21 03:52:46 PM PST 24
Peak memory 199696 kb
Host smart-69f957a8-aef9-4f15-92fe-b27e7b31df4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901727228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1901727228
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3855360264
Short name T366
Test name
Test status
Simulation time 14606923821 ps
CPU time 21.87 seconds
Started Feb 21 03:48:58 PM PST 24
Finished Feb 21 03:49:21 PM PST 24
Peak memory 199632 kb
Host smart-ac0dae3b-f01f-496a-af07-5d1459ccae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855360264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3855360264
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.221555
Short name T440
Test name
Test status
Simulation time 39295207607 ps
CPU time 62.65 seconds
Started Feb 21 03:48:53 PM PST 24
Finished Feb 21 03:49:57 PM PST 24
Peak memory 195464 kb
Host smart-8cb329f1-256c-4107-af16-bd15d01bd965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.221555
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3181091148
Short name T670
Test name
Test status
Simulation time 927117862 ps
CPU time 3.47 seconds
Started Feb 21 03:48:59 PM PST 24
Finished Feb 21 03:49:03 PM PST 24
Peak memory 197920 kb
Host smart-e050437e-2517-4847-929b-2694f39251ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181091148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3181091148
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2342877923
Short name T24
Test name
Test status
Simulation time 21080028405 ps
CPU time 173.04 seconds
Started Feb 21 03:48:49 PM PST 24
Finished Feb 21 03:51:43 PM PST 24
Peak memory 216244 kb
Host smart-fb0a866e-ba76-402f-b615-d18edc4d75d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342877923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2342877923
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1627349397
Short name T984
Test name
Test status
Simulation time 667319897 ps
CPU time 1.43 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:48:58 PM PST 24
Peak memory 197156 kb
Host smart-9673cd59-0636-4592-b2c0-dce80171b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627349397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1627349397
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.44053564
Short name T578
Test name
Test status
Simulation time 95114726880 ps
CPU time 49.51 seconds
Started Feb 21 03:48:48 PM PST 24
Finished Feb 21 03:49:37 PM PST 24
Peak memory 199696 kb
Host smart-1c0f3e19-607c-402a-9969-df684f865035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44053564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.44053564
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2899646406
Short name T184
Test name
Test status
Simulation time 124537422220 ps
CPU time 109.38 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:55:03 PM PST 24
Peak memory 198928 kb
Host smart-fc5226e1-61d3-41f0-b05d-2eb02304f490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899646406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2899646406
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.872512923
Short name T360
Test name
Test status
Simulation time 61480749238 ps
CPU time 23.81 seconds
Started Feb 21 03:53:23 PM PST 24
Finished Feb 21 03:53:47 PM PST 24
Peak memory 199580 kb
Host smart-92a86293-9ce0-4b7b-a73b-6d3bda0ee853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872512923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.872512923
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.774980150
Short name T260
Test name
Test status
Simulation time 124712757161 ps
CPU time 50.43 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:54:07 PM PST 24
Peak memory 199604 kb
Host smart-57fb713c-e4e3-4e9e-a97d-f639248b086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774980150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.774980150
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2940546220
Short name T238
Test name
Test status
Simulation time 72169477585 ps
CPU time 107.71 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:55:12 PM PST 24
Peak memory 199716 kb
Host smart-063446e1-9cdb-4d15-b8d4-a0665cceb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940546220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2940546220
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4142775479
Short name T218
Test name
Test status
Simulation time 87989019973 ps
CPU time 132.11 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:55:29 PM PST 24
Peak memory 199908 kb
Host smart-ce6b7731-0463-4695-805e-2c67c9ef2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142775479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4142775479
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2874013807
Short name T707
Test name
Test status
Simulation time 109173829359 ps
CPU time 74.56 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:54:39 PM PST 24
Peak memory 199480 kb
Host smart-8d1636a0-4679-49f3-899f-2aa9bdae37ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874013807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2874013807
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1953892576
Short name T326
Test name
Test status
Simulation time 98536464816 ps
CPU time 36 seconds
Started Feb 21 03:53:15 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199668 kb
Host smart-e9bec3f5-04ef-49e3-9ecb-3655668dbd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953892576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1953892576
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.564102825
Short name T5
Test name
Test status
Simulation time 173387514227 ps
CPU time 268.44 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:57:42 PM PST 24
Peak memory 199628 kb
Host smart-a0d05044-82e5-4f93-8356-44a5d24eff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564102825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.564102825
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2456546241
Short name T673
Test name
Test status
Simulation time 12682027 ps
CPU time 0.56 seconds
Started Feb 21 03:49:05 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 195124 kb
Host smart-ddbebf20-d977-4283-9718-467923cd7a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456546241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2456546241
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2420096634
Short name T411
Test name
Test status
Simulation time 37435772003 ps
CPU time 34.27 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:38 PM PST 24
Peak memory 199604 kb
Host smart-ce094ae2-2bd4-4941-b775-fd0a5a8af2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420096634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2420096634
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3331012353
Short name T700
Test name
Test status
Simulation time 146542861976 ps
CPU time 118.38 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:51:02 PM PST 24
Peak memory 199564 kb
Host smart-18eb02c9-58e6-408e-9026-335a3173cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331012353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3331012353
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1381422382
Short name T724
Test name
Test status
Simulation time 38078237440 ps
CPU time 20.22 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:25 PM PST 24
Peak memory 199604 kb
Host smart-7ead6419-c7f1-4939-b1e2-5312e78dd538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381422382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1381422382
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.885691427
Short name T1050
Test name
Test status
Simulation time 121432903607 ps
CPU time 384.8 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:55:31 PM PST 24
Peak memory 199656 kb
Host smart-790afa99-f213-408d-bdad-635c103254aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885691427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.885691427
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.896592283
Short name T502
Test name
Test status
Simulation time 216090547 ps
CPU time 0.79 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:06 PM PST 24
Peak memory 195136 kb
Host smart-00ecdfa1-2aeb-43dd-bb21-998b12f622b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896592283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.896592283
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2109498004
Short name T185
Test name
Test status
Simulation time 22714210409 ps
CPU time 29.89 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:35 PM PST 24
Peak memory 196536 kb
Host smart-7cc9cf63-ba55-4f77-aee2-e5cd11283e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109498004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2109498004
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1074941108
Short name T488
Test name
Test status
Simulation time 9353320705 ps
CPU time 565.01 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:58:30 PM PST 24
Peak memory 199660 kb
Host smart-e39b8ed5-aa97-468f-932d-733462caa43c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074941108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1074941108
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.302599134
Short name T556
Test name
Test status
Simulation time 2951179776 ps
CPU time 10.52 seconds
Started Feb 21 03:49:05 PM PST 24
Finished Feb 21 03:49:17 PM PST 24
Peak memory 198064 kb
Host smart-6ed63d9c-c02e-41e4-9b28-89824d66b9f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302599134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.302599134
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1436072520
Short name T99
Test name
Test status
Simulation time 1700477006 ps
CPU time 1.98 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 195132 kb
Host smart-681b5a06-f868-4d6c-b833-c6abb9df0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436072520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1436072520
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.736909577
Short name T922
Test name
Test status
Simulation time 281991812 ps
CPU time 2.1 seconds
Started Feb 21 03:48:57 PM PST 24
Finished Feb 21 03:48:59 PM PST 24
Peak memory 198132 kb
Host smart-7c37880e-f707-4e05-afdb-e6c0c131a2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736909577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.736909577
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2424883532
Short name T388
Test name
Test status
Simulation time 348663428227 ps
CPU time 60.37 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:50:06 PM PST 24
Peak memory 208100 kb
Host smart-60f51a88-1587-4511-b226-373b0a2d6da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424883532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2424883532
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3085467337
Short name T694
Test name
Test status
Simulation time 1537801715 ps
CPU time 2.7 seconds
Started Feb 21 03:48:56 PM PST 24
Finished Feb 21 03:48:59 PM PST 24
Peak memory 197956 kb
Host smart-602ca742-fa3b-46b2-ab17-607a071b7335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085467337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3085467337
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2828824734
Short name T745
Test name
Test status
Simulation time 93687020149 ps
CPU time 158.77 seconds
Started Feb 21 03:49:05 PM PST 24
Finished Feb 21 03:51:45 PM PST 24
Peak memory 199700 kb
Host smart-d360db5e-8ec9-4629-9700-290a42ac279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828824734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2828824734
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1089032809
Short name T224
Test name
Test status
Simulation time 32093459749 ps
CPU time 16.55 seconds
Started Feb 21 03:53:21 PM PST 24
Finished Feb 21 03:53:37 PM PST 24
Peak memory 199728 kb
Host smart-4555aaa8-a83d-4112-b4ae-fdb6e408e10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089032809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1089032809
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3910933481
Short name T253
Test name
Test status
Simulation time 112647239334 ps
CPU time 198.3 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:56:39 PM PST 24
Peak memory 199664 kb
Host smart-44f922de-4043-4e3f-9ea5-ff81efd85fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910933481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3910933481
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1016730447
Short name T369
Test name
Test status
Simulation time 31662514406 ps
CPU time 49.24 seconds
Started Feb 21 03:53:19 PM PST 24
Finished Feb 21 03:54:09 PM PST 24
Peak memory 199424 kb
Host smart-6e43a842-cbbd-433c-8ab8-777b0e5603f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016730447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1016730447
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3431552434
Short name T762
Test name
Test status
Simulation time 37753257202 ps
CPU time 31.61 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199432 kb
Host smart-b3858c61-24c6-466b-86f8-02bc72a0283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431552434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3431552434
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.146487473
Short name T923
Test name
Test status
Simulation time 43895237477 ps
CPU time 33.38 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:50 PM PST 24
Peak memory 199248 kb
Host smart-038e2587-1b70-4702-9239-9e34aa536e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146487473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.146487473
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2906084466
Short name T872
Test name
Test status
Simulation time 32502781158 ps
CPU time 27.28 seconds
Started Feb 21 03:53:17 PM PST 24
Finished Feb 21 03:53:45 PM PST 24
Peak memory 199644 kb
Host smart-f4bde502-4a24-49cc-a7a5-df5f5a4b6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906084466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2906084466
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3926422974
Short name T864
Test name
Test status
Simulation time 16993975668 ps
CPU time 26.71 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:43 PM PST 24
Peak memory 199020 kb
Host smart-d08dc0b5-bf63-4d07-9656-5d6d902d44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926422974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3926422974
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1995890861
Short name T589
Test name
Test status
Simulation time 74073423495 ps
CPU time 26.21 seconds
Started Feb 21 03:53:25 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 198824 kb
Host smart-06d5397b-18cb-4e6e-95b0-e9488870e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995890861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1995890861
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.635871211
Short name T539
Test name
Test status
Simulation time 69596643044 ps
CPU time 78.69 seconds
Started Feb 21 03:53:17 PM PST 24
Finished Feb 21 03:54:36 PM PST 24
Peak memory 199652 kb
Host smart-b5e3ada8-2d70-46fe-a05a-b18f7872f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635871211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.635871211
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3928560958
Short name T1073
Test name
Test status
Simulation time 17923820 ps
CPU time 0.58 seconds
Started Feb 21 03:49:06 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 194976 kb
Host smart-3d05c2fa-9ab1-447b-bbc1-7eca65a7ccdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928560958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3928560958
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2873422044
Short name T349
Test name
Test status
Simulation time 94224377130 ps
CPU time 32.65 seconds
Started Feb 21 03:49:09 PM PST 24
Finished Feb 21 03:49:42 PM PST 24
Peak memory 199644 kb
Host smart-43bbfe5f-78e1-4478-9cf4-1cf1c9eea389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873422044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2873422044
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3846213921
Short name T499
Test name
Test status
Simulation time 65795786781 ps
CPU time 121.22 seconds
Started Feb 21 03:49:08 PM PST 24
Finished Feb 21 03:51:10 PM PST 24
Peak memory 199200 kb
Host smart-cca6dd6e-3e43-4ac2-aece-b3be306c68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846213921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3846213921
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.1011004131
Short name T935
Test name
Test status
Simulation time 314972084746 ps
CPU time 337.88 seconds
Started Feb 21 03:49:10 PM PST 24
Finished Feb 21 03:54:48 PM PST 24
Peak memory 199704 kb
Host smart-d4673506-9dc5-4052-a1c4-db19f7130483
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011004131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1011004131
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1016643482
Short name T573
Test name
Test status
Simulation time 106224885997 ps
CPU time 839.34 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 04:03:06 PM PST 24
Peak memory 199604 kb
Host smart-de4e2349-f455-4a12-b7ff-f3ffd72a9071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016643482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1016643482
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3272758521
Short name T1081
Test name
Test status
Simulation time 5210895557 ps
CPU time 4.05 seconds
Started Feb 21 03:49:02 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 198172 kb
Host smart-3dd8e4de-c0d6-4ecb-b43e-ec144ad874d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272758521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3272758521
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3136609646
Short name T17
Test name
Test status
Simulation time 92457042439 ps
CPU time 93.68 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:50:39 PM PST 24
Peak memory 209080 kb
Host smart-f495a3ff-249d-4f7c-8a1d-594357fb6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136609646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3136609646
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1021870289
Short name T1077
Test name
Test status
Simulation time 10963323287 ps
CPU time 606 seconds
Started Feb 21 03:49:10 PM PST 24
Finished Feb 21 03:59:17 PM PST 24
Peak memory 199680 kb
Host smart-c65aa884-97c9-4f6f-9b50-6046599abc11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021870289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1021870289
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1169400422
Short name T599
Test name
Test status
Simulation time 682633007 ps
CPU time 8.99 seconds
Started Feb 21 03:49:10 PM PST 24
Finished Feb 21 03:49:19 PM PST 24
Peak memory 197260 kb
Host smart-20bbfe59-443c-4d30-8d7a-35f3af06da68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169400422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1169400422
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4158444394
Short name T1097
Test name
Test status
Simulation time 21294550638 ps
CPU time 30.18 seconds
Started Feb 21 03:49:09 PM PST 24
Finished Feb 21 03:49:39 PM PST 24
Peak memory 199636 kb
Host smart-4912611a-fff6-42c0-98d8-c8272b55bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158444394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4158444394
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.773892506
Short name T1100
Test name
Test status
Simulation time 30912418243 ps
CPU time 16.82 seconds
Started Feb 21 03:49:09 PM PST 24
Finished Feb 21 03:49:26 PM PST 24
Peak memory 195496 kb
Host smart-d1e5eff6-475f-4b5e-86d5-af45743a6ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773892506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.773892506
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2425700145
Short name T687
Test name
Test status
Simulation time 650392062 ps
CPU time 1.68 seconds
Started Feb 21 03:49:03 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 197556 kb
Host smart-44dea3a8-4c55-4a88-afbd-2ac237397657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425700145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2425700145
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.172614539
Short name T669
Test name
Test status
Simulation time 1100998798 ps
CPU time 4.2 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:49:10 PM PST 24
Peak memory 198760 kb
Host smart-afc7f551-ba04-453c-b380-6d64bfb944d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172614539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.172614539
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2704424960
Short name T946
Test name
Test status
Simulation time 74749054734 ps
CPU time 32.49 seconds
Started Feb 21 03:49:10 PM PST 24
Finished Feb 21 03:49:43 PM PST 24
Peak memory 199132 kb
Host smart-eb203607-2228-4179-b025-2a8170257de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704424960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2704424960
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.624203258
Short name T116
Test name
Test status
Simulation time 17764340202 ps
CPU time 15.6 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:53:30 PM PST 24
Peak memory 199492 kb
Host smart-f698d56f-542a-4b20-b3ce-a9a35c3691a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624203258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.624203258
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4006046302
Short name T876
Test name
Test status
Simulation time 24244944172 ps
CPU time 41.68 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:58 PM PST 24
Peak memory 199652 kb
Host smart-38dab1aa-bd23-4289-91f8-8633842957a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006046302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4006046302
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2196887910
Short name T823
Test name
Test status
Simulation time 261888468936 ps
CPU time 132.8 seconds
Started Feb 21 03:53:17 PM PST 24
Finished Feb 21 03:55:30 PM PST 24
Peak memory 199832 kb
Host smart-8f9448ad-3cbd-4e2e-b640-46ce29082793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196887910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2196887910
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2825221808
Short name T256
Test name
Test status
Simulation time 106893570558 ps
CPU time 23.55 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:53:38 PM PST 24
Peak memory 199064 kb
Host smart-ff776978-5e30-464e-a6ce-36dd7929999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825221808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2825221808
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2249283319
Short name T265
Test name
Test status
Simulation time 18483231280 ps
CPU time 29.42 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:46 PM PST 24
Peak memory 199908 kb
Host smart-82f8b22d-f0a6-47b7-83ae-c1951b0f70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249283319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2249283319
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.611511768
Short name T273
Test name
Test status
Simulation time 191936180524 ps
CPU time 26 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:54:02 PM PST 24
Peak memory 199632 kb
Host smart-574d5a8f-caee-4b1e-9aa3-06238c940690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611511768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.611511768
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1519512892
Short name T173
Test name
Test status
Simulation time 14078232031 ps
CPU time 24.52 seconds
Started Feb 21 03:53:20 PM PST 24
Finished Feb 21 03:53:45 PM PST 24
Peak memory 199592 kb
Host smart-10f1f531-1c31-4bbf-81f7-10546dcfcd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519512892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1519512892
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.489954940
Short name T137
Test name
Test status
Simulation time 19457991917 ps
CPU time 7.89 seconds
Started Feb 21 03:53:04 PM PST 24
Finished Feb 21 03:53:12 PM PST 24
Peak memory 198868 kb
Host smart-fae0e672-72d8-45d5-89fe-e9f518c4d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489954940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.489954940
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2472310624
Short name T236
Test name
Test status
Simulation time 98290948898 ps
CPU time 34.28 seconds
Started Feb 21 03:53:05 PM PST 24
Finished Feb 21 03:53:40 PM PST 24
Peak memory 199644 kb
Host smart-15a83a63-4637-4449-8af5-b0e4611d8775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472310624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2472310624
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4075809872
Short name T511
Test name
Test status
Simulation time 13133635 ps
CPU time 0.58 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:49:19 PM PST 24
Peak memory 195132 kb
Host smart-0884abba-c791-44e6-8b18-78b968c57030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075809872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4075809872
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.966246131
Short name T703
Test name
Test status
Simulation time 56943789385 ps
CPU time 24.25 seconds
Started Feb 21 03:49:19 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 199580 kb
Host smart-d95fd7e4-1b61-4f18-89b6-d0c22693864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966246131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.966246131
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2998475446
Short name T903
Test name
Test status
Simulation time 54805694909 ps
CPU time 73.84 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:50:30 PM PST 24
Peak memory 199632 kb
Host smart-5cee139e-dbe0-41bb-ad27-b001681d04e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998475446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2998475446
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.643691353
Short name T319
Test name
Test status
Simulation time 62154486585 ps
CPU time 89.33 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:50:46 PM PST 24
Peak memory 199628 kb
Host smart-88eca2ca-e14b-4d97-a221-d64cfc31827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643691353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.643691353
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3324862910
Short name T1085
Test name
Test status
Simulation time 13393360422 ps
CPU time 11.69 seconds
Started Feb 21 03:49:06 PM PST 24
Finished Feb 21 03:49:19 PM PST 24
Peak memory 198684 kb
Host smart-ae019f32-cb8e-4f24-ac55-a1f1a6d8c986
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324862910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3324862910
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1226285222
Short name T624
Test name
Test status
Simulation time 87865366501 ps
CPU time 629.45 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:59:46 PM PST 24
Peak memory 199632 kb
Host smart-3fe529ca-eff2-4cdd-bc93-3a4714db2ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226285222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1226285222
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.649065791
Short name T742
Test name
Test status
Simulation time 1161972545 ps
CPU time 4.14 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:49:23 PM PST 24
Peak memory 197236 kb
Host smart-8f4f0cec-5d95-4610-a26e-e45b9d9fdd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649065791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.649065791
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1390922020
Short name T569
Test name
Test status
Simulation time 85626390412 ps
CPU time 101.03 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:50:57 PM PST 24
Peak memory 199804 kb
Host smart-36ef5670-802a-42d0-afd8-99d69badd46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390922020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1390922020
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2460420502
Short name T1002
Test name
Test status
Simulation time 43910803686 ps
CPU time 533.93 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:58:11 PM PST 24
Peak memory 199628 kb
Host smart-1c5b673c-2b20-42ca-b7e7-514565af4d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460420502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2460420502
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3418593562
Short name T1045
Test name
Test status
Simulation time 659362891 ps
CPU time 5.68 seconds
Started Feb 21 03:49:17 PM PST 24
Finished Feb 21 03:49:23 PM PST 24
Peak memory 197948 kb
Host smart-c8565acb-87eb-4614-b55e-d340120ef5a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418593562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3418593562
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1312454486
Short name T1030
Test name
Test status
Simulation time 119648676507 ps
CPU time 49.72 seconds
Started Feb 21 03:49:15 PM PST 24
Finished Feb 21 03:50:06 PM PST 24
Peak memory 198652 kb
Host smart-f578d8e3-1893-44ef-939c-a4a88d7e2cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312454486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1312454486
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1717576341
Short name T567
Test name
Test status
Simulation time 4773267057 ps
CPU time 2.13 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:49:21 PM PST 24
Peak memory 195412 kb
Host smart-0377d17c-f059-4530-9926-4ffa800715d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717576341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1717576341
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2156123720
Short name T733
Test name
Test status
Simulation time 5528525251 ps
CPU time 6.92 seconds
Started Feb 21 03:49:04 PM PST 24
Finished Feb 21 03:49:13 PM PST 24
Peak memory 198696 kb
Host smart-a0b1f70f-a9fb-42a9-a83d-a673ab03f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156123720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2156123720
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3746637918
Short name T950
Test name
Test status
Simulation time 3186115060577 ps
CPU time 1521.29 seconds
Started Feb 21 03:49:17 PM PST 24
Finished Feb 21 04:14:39 PM PST 24
Peak memory 199676 kb
Host smart-d9e6c259-78b7-45bc-97a6-3e122ff66796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746637918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3746637918
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2946070088
Short name T521
Test name
Test status
Simulation time 1165901092 ps
CPU time 3.73 seconds
Started Feb 21 03:49:22 PM PST 24
Finished Feb 21 03:49:26 PM PST 24
Peak memory 198320 kb
Host smart-64959ca7-2b4b-451e-a847-15f8459ebf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946070088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2946070088
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1903579304
Short name T1079
Test name
Test status
Simulation time 21483109878 ps
CPU time 71.16 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:50:41 PM PST 24
Peak memory 199660 kb
Host smart-9ade28a6-1d26-48d4-8f5a-a03fad1ca823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903579304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1903579304
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3724224213
Short name T352
Test name
Test status
Simulation time 161550503666 ps
CPU time 47.91 seconds
Started Feb 21 03:53:15 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 199640 kb
Host smart-b802663b-b95d-4ae4-8a1c-daff8afb17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724224213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3724224213
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4119828387
Short name T139
Test name
Test status
Simulation time 21001890258 ps
CPU time 17.82 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:53:54 PM PST 24
Peak memory 199320 kb
Host smart-0d476dd9-42c3-444f-9e21-df80e8f68f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119828387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4119828387
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.935068099
Short name T205
Test name
Test status
Simulation time 115311614279 ps
CPU time 181.44 seconds
Started Feb 21 03:53:13 PM PST 24
Finished Feb 21 03:56:16 PM PST 24
Peak memory 199740 kb
Host smart-c5dd4d39-5a5b-4d70-84aa-dc2fdd86920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935068099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.935068099
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1461319158
Short name T514
Test name
Test status
Simulation time 7082660076 ps
CPU time 12.65 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 03:53:51 PM PST 24
Peak memory 199524 kb
Host smart-89dea782-7006-48f8-95b3-95b720d5005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461319158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1461319158
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3012618552
Short name T330
Test name
Test status
Simulation time 15276025132 ps
CPU time 26.64 seconds
Started Feb 21 03:53:23 PM PST 24
Finished Feb 21 03:53:50 PM PST 24
Peak memory 199612 kb
Host smart-f76041d5-a036-4add-9a1c-3e05f0c3b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012618552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3012618552
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1162629512
Short name T357
Test name
Test status
Simulation time 35416876569 ps
CPU time 15.19 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199668 kb
Host smart-8c3db6ce-1982-4116-8e68-ede1e13ec92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162629512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1162629512
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1573596081
Short name T837
Test name
Test status
Simulation time 17934608243 ps
CPU time 15.42 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 198540 kb
Host smart-f7e458ec-03d0-4a4a-a862-018b1326ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573596081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1573596081
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3610188243
Short name T132
Test name
Test status
Simulation time 43227466853 ps
CPU time 19.8 seconds
Started Feb 21 03:53:21 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 199652 kb
Host smart-aad175e4-1ac3-4d05-8389-cc048116eba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610188243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3610188243
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.174183149
Short name T732
Test name
Test status
Simulation time 30366969916 ps
CPU time 26.78 seconds
Started Feb 21 03:53:22 PM PST 24
Finished Feb 21 03:53:49 PM PST 24
Peak memory 199360 kb
Host smart-e1296d1f-639b-4ccf-b7e1-d88d549046ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174183149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.174183149
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3898774909
Short name T311
Test name
Test status
Simulation time 112299891185 ps
CPU time 32.01 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:48 PM PST 24
Peak memory 199712 kb
Host smart-913b5cc0-eb98-4144-8766-ca8be4ca925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898774909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3898774909
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3076562014
Short name T1015
Test name
Test status
Simulation time 29612879 ps
CPU time 0.53 seconds
Started Feb 21 03:49:20 PM PST 24
Finished Feb 21 03:49:20 PM PST 24
Peak memory 195104 kb
Host smart-7d754a18-9445-4d82-905e-a18c3ff8fe5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076562014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3076562014
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1127744177
Short name T974
Test name
Test status
Simulation time 36322637091 ps
CPU time 144.08 seconds
Started Feb 21 03:49:13 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 199624 kb
Host smart-82d6ccd4-3b93-4016-a3c7-5f3a700e0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127744177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1127744177
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1670764585
Short name T317
Test name
Test status
Simulation time 27645741841 ps
CPU time 45.48 seconds
Started Feb 21 03:49:27 PM PST 24
Finished Feb 21 03:50:13 PM PST 24
Peak memory 198800 kb
Host smart-72a47446-ed3d-4601-b685-ca1ec36680c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670764585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1670764585
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1143047065
Short name T269
Test name
Test status
Simulation time 13559910187 ps
CPU time 7.42 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:49:24 PM PST 24
Peak memory 199544 kb
Host smart-e222ab2e-f74a-4dcc-94a9-6f1de3893fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143047065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1143047065
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3009637542
Short name T748
Test name
Test status
Simulation time 32194207507 ps
CPU time 19.36 seconds
Started Feb 21 03:49:24 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 199528 kb
Host smart-4e30e11e-24ff-4ccb-8f6b-23d3337afa42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009637542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3009637542
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3893567483
Short name T571
Test name
Test status
Simulation time 63152074242 ps
CPU time 490.36 seconds
Started Feb 21 03:49:24 PM PST 24
Finished Feb 21 03:57:34 PM PST 24
Peak memory 199656 kb
Host smart-85431481-f43d-4df1-afe8-11bc1ee62e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893567483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3893567483
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2055288357
Short name T994
Test name
Test status
Simulation time 1227682227 ps
CPU time 2.45 seconds
Started Feb 21 03:49:17 PM PST 24
Finished Feb 21 03:49:20 PM PST 24
Peak memory 195176 kb
Host smart-2195fae6-31c7-4124-a094-c0cca1aec72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055288357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2055288357
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3840740797
Short name T646
Test name
Test status
Simulation time 4436769646 ps
CPU time 7.16 seconds
Started Feb 21 03:49:16 PM PST 24
Finished Feb 21 03:49:23 PM PST 24
Peak memory 195308 kb
Host smart-258065b7-c298-461d-a8f0-620f94cb90a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840740797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3840740797
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.4174824340
Short name T1103
Test name
Test status
Simulation time 13152084051 ps
CPU time 355.57 seconds
Started Feb 21 03:49:17 PM PST 24
Finished Feb 21 03:55:14 PM PST 24
Peak memory 199708 kb
Host smart-051708a6-6f35-4dac-95a7-21b6efad56dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174824340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4174824340
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2258918353
Short name T992
Test name
Test status
Simulation time 1549260982 ps
CPU time 6.83 seconds
Started Feb 21 03:49:20 PM PST 24
Finished Feb 21 03:49:27 PM PST 24
Peak memory 197720 kb
Host smart-6aeabb9e-8cc1-439b-b8e9-add64553b2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258918353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2258918353
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.4159510797
Short name T193
Test name
Test status
Simulation time 321200127262 ps
CPU time 91.13 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:51:00 PM PST 24
Peak memory 199464 kb
Host smart-37464f77-3876-4e1e-b266-4a1bd51d5a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159510797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4159510797
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.644999476
Short name T868
Test name
Test status
Simulation time 4308763589 ps
CPU time 2.73 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:49:22 PM PST 24
Peak memory 195484 kb
Host smart-1e54d9a2-5cd1-43b0-937d-c9ad5fe595dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644999476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.644999476
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1095062185
Short name T881
Test name
Test status
Simulation time 470153109 ps
CPU time 1.42 seconds
Started Feb 21 03:49:20 PM PST 24
Finished Feb 21 03:49:22 PM PST 24
Peak memory 198548 kb
Host smart-62186cb5-7074-402b-a211-f87e58226296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095062185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1095062185
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3236245039
Short name T377
Test name
Test status
Simulation time 60930467914 ps
CPU time 181.67 seconds
Started Feb 21 03:49:24 PM PST 24
Finished Feb 21 03:52:26 PM PST 24
Peak memory 216324 kb
Host smart-15b39007-7882-48f3-9d1a-5fc520ff1109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236245039 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3236245039
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2911553237
Short name T504
Test name
Test status
Simulation time 7141786413 ps
CPU time 8.67 seconds
Started Feb 21 03:49:19 PM PST 24
Finished Feb 21 03:49:28 PM PST 24
Peak memory 199496 kb
Host smart-d1a4cfcf-fda7-4e1b-a84e-ad2d017d2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911553237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2911553237
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3755770354
Short name T153
Test name
Test status
Simulation time 23557351457 ps
CPU time 33.77 seconds
Started Feb 21 03:49:14 PM PST 24
Finished Feb 21 03:49:49 PM PST 24
Peak memory 197452 kb
Host smart-7c908c00-c4cc-4105-a81a-fbaecc5ceadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755770354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3755770354
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2885375932
Short name T261
Test name
Test status
Simulation time 48063332897 ps
CPU time 58.11 seconds
Started Feb 21 03:53:40 PM PST 24
Finished Feb 21 03:54:38 PM PST 24
Peak memory 199036 kb
Host smart-15c4f01b-9d0d-486f-aae6-d57d27b25544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885375932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2885375932
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4215718184
Short name T156
Test name
Test status
Simulation time 127823408268 ps
CPU time 64.59 seconds
Started Feb 21 03:53:22 PM PST 24
Finished Feb 21 03:54:28 PM PST 24
Peak memory 199720 kb
Host smart-5dbef0ad-a952-424e-85e2-2b2b839afc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215718184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4215718184
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1613663987
Short name T192
Test name
Test status
Simulation time 78063863403 ps
CPU time 133.36 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:55:38 PM PST 24
Peak memory 199692 kb
Host smart-d4f0b76f-99a8-4b0b-bd2e-968e9be75cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613663987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1613663987
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1161144055
Short name T312
Test name
Test status
Simulation time 68336638769 ps
CPU time 14.55 seconds
Started Feb 21 03:53:22 PM PST 24
Finished Feb 21 03:53:37 PM PST 24
Peak memory 199616 kb
Host smart-5551b7e3-b964-4063-802f-38926c070aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161144055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1161144055
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3575252931
Short name T118
Test name
Test status
Simulation time 27385261045 ps
CPU time 46.17 seconds
Started Feb 21 03:53:40 PM PST 24
Finished Feb 21 03:54:26 PM PST 24
Peak memory 199652 kb
Host smart-00aa9867-b2d1-49b3-b408-649685fde3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575252931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3575252931
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1945226578
Short name T547
Test name
Test status
Simulation time 41116019967 ps
CPU time 27.23 seconds
Started Feb 21 03:53:16 PM PST 24
Finished Feb 21 03:53:44 PM PST 24
Peak memory 199660 kb
Host smart-8de2cbb2-e207-4946-b914-75010dc25469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945226578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1945226578
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.383482705
Short name T912
Test name
Test status
Simulation time 66426948752 ps
CPU time 28.8 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:54:05 PM PST 24
Peak memory 199592 kb
Host smart-62d44e23-9eac-430b-b47a-cef870042bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383482705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.383482705
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.844824854
Short name T197
Test name
Test status
Simulation time 65970632012 ps
CPU time 23.3 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:53:48 PM PST 24
Peak memory 199452 kb
Host smart-ca216c55-0f7c-4408-8870-490279326206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844824854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.844824854
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.511414499
Short name T741
Test name
Test status
Simulation time 38966243 ps
CPU time 0.54 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:49:41 PM PST 24
Peak memory 195084 kb
Host smart-79e1c42a-96f1-4311-bd65-13a19b2d05ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511414499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.511414499
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3644707072
Short name T271
Test name
Test status
Simulation time 20444491986 ps
CPU time 17.66 seconds
Started Feb 21 03:49:27 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 199584 kb
Host smart-e4ef9217-1d84-4e9a-aa03-c5ccfb04cab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644707072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3644707072
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3515006365
Short name T726
Test name
Test status
Simulation time 124824572618 ps
CPU time 189.99 seconds
Started Feb 21 03:49:31 PM PST 24
Finished Feb 21 03:52:41 PM PST 24
Peak memory 199416 kb
Host smart-58441919-5dad-44f9-94e0-aeb78e329e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515006365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3515006365
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.11889664
Short name T988
Test name
Test status
Simulation time 58017046724 ps
CPU time 27 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:49:56 PM PST 24
Peak memory 199632 kb
Host smart-e3ff6708-52b5-4ea8-b562-d31ad8644076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11889664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.11889664
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1994854300
Short name T715
Test name
Test status
Simulation time 375286743069 ps
CPU time 174.16 seconds
Started Feb 21 03:49:34 PM PST 24
Finished Feb 21 03:52:28 PM PST 24
Peak memory 199644 kb
Host smart-e6fd22ae-32f1-4f87-b8e7-d2002217bdc5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994854300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1994854300
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2410469280
Short name T406
Test name
Test status
Simulation time 75395662582 ps
CPU time 239.29 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:53:28 PM PST 24
Peak memory 199740 kb
Host smart-5f3096b4-24af-43b1-8724-9327c9a7e96f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410469280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2410469280
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1153572088
Short name T845
Test name
Test status
Simulation time 10934252976 ps
CPU time 7.7 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:49:38 PM PST 24
Peak memory 198848 kb
Host smart-9a99588e-5e69-493c-8c51-510aa119d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153572088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1153572088
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2392406877
Short name T179
Test name
Test status
Simulation time 60145367969 ps
CPU time 106.96 seconds
Started Feb 21 03:49:29 PM PST 24
Finished Feb 21 03:51:16 PM PST 24
Peak memory 199240 kb
Host smart-9ef9f6bb-535f-463f-a24c-08f7b441a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392406877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2392406877
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3423307016
Short name T416
Test name
Test status
Simulation time 13284961277 ps
CPU time 791.46 seconds
Started Feb 21 03:49:39 PM PST 24
Finished Feb 21 04:02:51 PM PST 24
Peak memory 199708 kb
Host smart-2e2033bd-5f57-4cd6-8fe1-f15b0a7b81ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423307016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3423307016
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2761663142
Short name T1046
Test name
Test status
Simulation time 1767181199 ps
CPU time 5.5 seconds
Started Feb 21 03:49:33 PM PST 24
Finished Feb 21 03:49:39 PM PST 24
Peak memory 197752 kb
Host smart-2a66ca89-b89d-42ca-b383-2ff328f53de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761663142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2761663142
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3452026323
Short name T356
Test name
Test status
Simulation time 127853043901 ps
CPU time 175.13 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 199588 kb
Host smart-61b4f2aa-4eee-4771-9580-e05aa26ea9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452026323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3452026323
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3064780029
Short name T508
Test name
Test status
Simulation time 3065034455 ps
CPU time 1.96 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:49:30 PM PST 24
Peak memory 195096 kb
Host smart-c2c57946-eb47-479c-9c84-394c9e69397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064780029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3064780029
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.28844696
Short name T800
Test name
Test status
Simulation time 270895136 ps
CPU time 1.43 seconds
Started Feb 21 03:49:20 PM PST 24
Finished Feb 21 03:49:22 PM PST 24
Peak memory 197768 kb
Host smart-684c994b-354c-484a-af2d-e32e8b37b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28844696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.28844696
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2727222693
Short name T113
Test name
Test status
Simulation time 192171315215 ps
CPU time 282.51 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:54:11 PM PST 24
Peak memory 199752 kb
Host smart-905c1631-8ddb-42c8-9420-9f02c888632f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727222693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2727222693
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2416918778
Short name T911
Test name
Test status
Simulation time 55346588421 ps
CPU time 280.79 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:54:26 PM PST 24
Peak memory 208008 kb
Host smart-dbe51684-e7fd-4a79-9385-4bc6987944bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416918778 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2416918778
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.695629919
Short name T562
Test name
Test status
Simulation time 511900600 ps
CPU time 2.28 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:49:46 PM PST 24
Peak memory 198000 kb
Host smart-c9f9403b-6c73-4f2f-abb9-13b1617e2d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695629919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.695629919
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2151596650
Short name T133
Test name
Test status
Simulation time 7039623112 ps
CPU time 12.33 seconds
Started Feb 21 03:49:18 PM PST 24
Finished Feb 21 03:49:31 PM PST 24
Peak memory 196036 kb
Host smart-b740ad60-7191-4147-812d-9b87f4d8f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151596650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2151596650
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3648658959
Short name T206
Test name
Test status
Simulation time 84994442641 ps
CPU time 39.24 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:18 PM PST 24
Peak memory 199660 kb
Host smart-4dedd121-f1ee-49bf-b296-beea1428f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648658959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3648658959
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4259996825
Short name T289
Test name
Test status
Simulation time 28842440261 ps
CPU time 72.15 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 03:54:51 PM PST 24
Peak memory 199724 kb
Host smart-656393fb-cbcf-46a3-99c5-46bcc43c54d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259996825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4259996825
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1990013084
Short name T362
Test name
Test status
Simulation time 17128552212 ps
CPU time 10.25 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:53:52 PM PST 24
Peak memory 199220 kb
Host smart-b535e81a-c98e-4e01-9711-2fa1c85363a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990013084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1990013084
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2392043299
Short name T1026
Test name
Test status
Simulation time 15554449628 ps
CPU time 13.37 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:53:38 PM PST 24
Peak memory 199136 kb
Host smart-4c74d7cf-1307-4b64-80a0-df2fab096b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392043299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2392043299
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1657033900
Short name T217
Test name
Test status
Simulation time 79689220594 ps
CPU time 74.13 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:54:56 PM PST 24
Peak memory 199648 kb
Host smart-0496257a-6476-42f9-941e-e321f3d8a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657033900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1657033900
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.897062314
Short name T204
Test name
Test status
Simulation time 105812396242 ps
CPU time 207.33 seconds
Started Feb 21 03:53:45 PM PST 24
Finished Feb 21 03:57:14 PM PST 24
Peak memory 199644 kb
Host smart-9a8d97d5-55e8-4a1f-9f88-181769a18777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897062314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.897062314
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2803785720
Short name T241
Test name
Test status
Simulation time 27219930911 ps
CPU time 52.4 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:54:29 PM PST 24
Peak memory 199656 kb
Host smart-aa2953ec-6cac-4334-9a3c-9cc82bed89c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803785720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2803785720
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3139620289
Short name T304
Test name
Test status
Simulation time 15016514989 ps
CPU time 9.45 seconds
Started Feb 21 03:53:23 PM PST 24
Finished Feb 21 03:53:33 PM PST 24
Peak memory 199180 kb
Host smart-217daadf-d50f-4d2c-b711-b33d2790ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139620289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3139620289
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1963915028
Short name T943
Test name
Test status
Simulation time 67377533901 ps
CPU time 100.02 seconds
Started Feb 21 03:53:24 PM PST 24
Finished Feb 21 03:55:05 PM PST 24
Peak memory 199628 kb
Host smart-f4ab2f9a-b807-4cdc-beaa-d3eb2dd8401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963915028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1963915028
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2034091870
Short name T788
Test name
Test status
Simulation time 219328686227 ps
CPU time 36.38 seconds
Started Feb 21 03:53:30 PM PST 24
Finished Feb 21 03:54:07 PM PST 24
Peak memory 199724 kb
Host smart-af3e270b-7641-4c52-ae70-a0b832ebf595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034091870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2034091870
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2775997771
Short name T789
Test name
Test status
Simulation time 24933489 ps
CPU time 0.57 seconds
Started Feb 21 03:49:41 PM PST 24
Finished Feb 21 03:49:42 PM PST 24
Peak memory 195104 kb
Host smart-ef92be42-db8d-4184-9587-a3636bf39bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775997771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2775997771
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3223072845
Short name T805
Test name
Test status
Simulation time 151968572758 ps
CPU time 65.46 seconds
Started Feb 21 03:49:28 PM PST 24
Finished Feb 21 03:50:33 PM PST 24
Peak memory 199616 kb
Host smart-d80936a0-e45e-4611-8e47-be043f33f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223072845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3223072845
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3843103490
Short name T637
Test name
Test status
Simulation time 23566484401 ps
CPU time 31.6 seconds
Started Feb 21 03:49:32 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 199100 kb
Host smart-d3be81ca-68ce-4f63-a5a5-118037eff956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843103490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3843103490
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.4251702974
Short name T1101
Test name
Test status
Simulation time 105997955682 ps
CPU time 178.63 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:52:43 PM PST 24
Peak memory 199484 kb
Host smart-ae5ec57d-747d-4d6a-868e-682d7c513368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251702974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4251702974
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.687217533
Short name T491
Test name
Test status
Simulation time 10889480310 ps
CPU time 21.75 seconds
Started Feb 21 03:49:32 PM PST 24
Finished Feb 21 03:49:54 PM PST 24
Peak memory 198096 kb
Host smart-e80a59fe-804a-421e-84b8-6e5ff146b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687217533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.687217533
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.137430289
Short name T897
Test name
Test status
Simulation time 64655444916 ps
CPU time 59.02 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:50:29 PM PST 24
Peak memory 198908 kb
Host smart-217d95eb-461c-43bc-8b6f-3e32004b7203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137430289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.137430289
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3450496961
Short name T993
Test name
Test status
Simulation time 21389965132 ps
CPU time 1228.13 seconds
Started Feb 21 03:49:33 PM PST 24
Finished Feb 21 04:10:02 PM PST 24
Peak memory 199496 kb
Host smart-85526921-6b91-4ad3-b28d-1836848907b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450496961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3450496961
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3160286969
Short name T538
Test name
Test status
Simulation time 466299217 ps
CPU time 4.73 seconds
Started Feb 21 03:49:41 PM PST 24
Finished Feb 21 03:49:46 PM PST 24
Peak memory 197836 kb
Host smart-2a81278b-2ab8-4269-b3fc-03323fff87da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160286969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3160286969
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.516182944
Short name T1042
Test name
Test status
Simulation time 191431182490 ps
CPU time 59.77 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:50:30 PM PST 24
Peak memory 199648 kb
Host smart-9072c273-ae5a-499b-9922-42439ada6813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516182944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.516182944
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.406168291
Short name T1062
Test name
Test status
Simulation time 37956631298 ps
CPU time 8.59 seconds
Started Feb 21 03:49:33 PM PST 24
Finished Feb 21 03:49:42 PM PST 24
Peak memory 194940 kb
Host smart-0e1c0387-1d02-4674-b035-c81a669a2c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406168291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.406168291
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.696990119
Short name T1060
Test name
Test status
Simulation time 6283059246 ps
CPU time 24.84 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:49:55 PM PST 24
Peak memory 198988 kb
Host smart-1c514393-788d-4ad9-8ebb-5d5d04627d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696990119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.696990119
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1862071833
Short name T555
Test name
Test status
Simulation time 193847487819 ps
CPU time 326.57 seconds
Started Feb 21 03:49:42 PM PST 24
Finished Feb 21 03:55:10 PM PST 24
Peak memory 199648 kb
Host smart-2b646b24-0a24-48b6-837d-8d84fe592171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862071833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1862071833
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3912302616
Short name T496
Test name
Test status
Simulation time 1695242761 ps
CPU time 1.79 seconds
Started Feb 21 03:49:32 PM PST 24
Finished Feb 21 03:49:34 PM PST 24
Peak memory 198036 kb
Host smart-2bfb061a-625f-46e4-962c-11f7170d53b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912302616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3912302616
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1548168683
Short name T962
Test name
Test status
Simulation time 75316059950 ps
CPU time 58.4 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:50:29 PM PST 24
Peak memory 199656 kb
Host smart-7860b810-1ebe-4a67-82d4-cb892ceba691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548168683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1548168683
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.450905551
Short name T255
Test name
Test status
Simulation time 49976322139 ps
CPU time 21.44 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 199588 kb
Host smart-5c757ad9-46f9-4365-9372-1ed222bb479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450905551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.450905551
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2014167018
Short name T303
Test name
Test status
Simulation time 77648421033 ps
CPU time 129.6 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:55:47 PM PST 24
Peak memory 199660 kb
Host smart-63442273-a194-42da-8b5a-098b49d9c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014167018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2014167018
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3406115729
Short name T215
Test name
Test status
Simulation time 102275691855 ps
CPU time 24.86 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 199468 kb
Host smart-c44fc793-29a0-465f-a1f3-ff536ee619d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406115729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3406115729
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3707607327
Short name T306
Test name
Test status
Simulation time 225203876575 ps
CPU time 195.2 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:56:53 PM PST 24
Peak memory 199628 kb
Host smart-be522114-1db1-4ff1-a61f-3e145663f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707607327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3707607327
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2958468178
Short name T1098
Test name
Test status
Simulation time 101995523013 ps
CPU time 153.86 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 03:56:13 PM PST 24
Peak memory 199656 kb
Host smart-51097246-149d-435f-8ac9-966c8666b5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958468178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2958468178
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3984183911
Short name T140
Test name
Test status
Simulation time 123842952516 ps
CPU time 192.63 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:56:50 PM PST 24
Peak memory 199572 kb
Host smart-1d8e3cd8-72ec-4f26-92c3-9ef926ea4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984183911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3984183911
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3934205311
Short name T949
Test name
Test status
Simulation time 47950766415 ps
CPU time 41.52 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:54:19 PM PST 24
Peak memory 199720 kb
Host smart-fd9023e0-b6c3-43e6-8bb2-098a72adb9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934205311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3934205311
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1024800907
Short name T595
Test name
Test status
Simulation time 39169613 ps
CPU time 0.61 seconds
Started Feb 21 03:47:54 PM PST 24
Finished Feb 21 03:47:55 PM PST 24
Peak memory 195108 kb
Host smart-2286725a-8429-4d47-962d-68ac74545097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024800907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1024800907
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1289889679
Short name T344
Test name
Test status
Simulation time 66229442031 ps
CPU time 38.12 seconds
Started Feb 21 03:47:56 PM PST 24
Finished Feb 21 03:48:34 PM PST 24
Peak memory 199692 kb
Host smart-4d1970dc-f5d7-4aa8-8cf1-41f87cde4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289889679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1289889679
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.33979283
Short name T117
Test name
Test status
Simulation time 21602565740 ps
CPU time 21.35 seconds
Started Feb 21 03:47:34 PM PST 24
Finished Feb 21 03:47:56 PM PST 24
Peak memory 199452 kb
Host smart-929f9057-6bc4-467d-bc16-3d0e8512dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33979283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.33979283
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2998852791
Short name T659
Test name
Test status
Simulation time 333830030186 ps
CPU time 595.4 seconds
Started Feb 21 03:47:56 PM PST 24
Finished Feb 21 03:57:51 PM PST 24
Peak memory 199256 kb
Host smart-4e36de81-e0a6-4ed8-ab36-cad889f387a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998852791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2998852791
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1071797322
Short name T1014
Test name
Test status
Simulation time 132282746672 ps
CPU time 390.62 seconds
Started Feb 21 03:48:00 PM PST 24
Finished Feb 21 03:54:32 PM PST 24
Peak memory 199684 kb
Host smart-9b1edca9-d12b-40e3-96f8-a5c87cba0343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071797322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1071797322
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1179864317
Short name T495
Test name
Test status
Simulation time 4225497313 ps
CPU time 2.8 seconds
Started Feb 21 03:47:49 PM PST 24
Finished Feb 21 03:47:52 PM PST 24
Peak memory 198248 kb
Host smart-63aa8c89-6fce-4bb1-bcc8-ac2b1363a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179864317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1179864317
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2395333177
Short name T736
Test name
Test status
Simulation time 89863908445 ps
CPU time 247.8 seconds
Started Feb 21 03:47:47 PM PST 24
Finished Feb 21 03:51:55 PM PST 24
Peak memory 199728 kb
Host smart-b6396cdf-8611-4d81-a410-d39fddf23f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395333177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2395333177
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1387251643
Short name T534
Test name
Test status
Simulation time 20094802884 ps
CPU time 1085.63 seconds
Started Feb 21 03:47:59 PM PST 24
Finished Feb 21 04:06:05 PM PST 24
Peak memory 199676 kb
Host smart-2948278a-9f5b-42ca-b8c5-797f6bb6a652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387251643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1387251643
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3769545488
Short name T1087
Test name
Test status
Simulation time 1165262122 ps
CPU time 4.47 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 03:47:47 PM PST 24
Peak memory 197864 kb
Host smart-a9a92b4c-5f65-4aa1-8b9c-37640b8add90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769545488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3769545488
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.239569937
Short name T327
Test name
Test status
Simulation time 305998688106 ps
CPU time 100.65 seconds
Started Feb 21 03:47:59 PM PST 24
Finished Feb 21 03:49:40 PM PST 24
Peak memory 199612 kb
Host smart-636e09c4-571c-4a1e-a373-7ddfa5e78605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239569937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.239569937
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1671552350
Short name T631
Test name
Test status
Simulation time 5920614037 ps
CPU time 10.84 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:53 PM PST 24
Peak memory 195416 kb
Host smart-55abef5f-ac53-4181-a2ec-af7397ef1ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671552350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1671552350
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1305797875
Short name T32
Test name
Test status
Simulation time 36720446 ps
CPU time 0.8 seconds
Started Feb 21 03:47:59 PM PST 24
Finished Feb 21 03:48:05 PM PST 24
Peak memory 217196 kb
Host smart-1a3553db-c9b8-41fe-8be0-4e8e505acf9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305797875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1305797875
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.287024930
Short name T1051
Test name
Test status
Simulation time 5482995537 ps
CPU time 17.33 seconds
Started Feb 21 03:47:43 PM PST 24
Finished Feb 21 03:48:00 PM PST 24
Peak memory 198356 kb
Host smart-098031b7-b783-45d8-84b0-df86e40e0b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287024930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.287024930
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1250636692
Short name T811
Test name
Test status
Simulation time 2674491557093 ps
CPU time 4637.85 seconds
Started Feb 21 03:47:50 PM PST 24
Finished Feb 21 05:05:08 PM PST 24
Peak memory 199660 kb
Host smart-e361346f-4879-40b0-b5a3-ae57ad9d3c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250636692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1250636692
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1787128162
Short name T510
Test name
Test status
Simulation time 2857730751 ps
CPU time 3.83 seconds
Started Feb 21 03:47:54 PM PST 24
Finished Feb 21 03:47:58 PM PST 24
Peak memory 197740 kb
Host smart-3158eb5d-c3eb-4b92-80e5-79572022114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787128162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1787128162
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2377228547
Short name T896
Test name
Test status
Simulation time 32746756087 ps
CPU time 14.58 seconds
Started Feb 21 03:47:42 PM PST 24
Finished Feb 21 03:47:57 PM PST 24
Peak memory 199748 kb
Host smart-1c0680b8-90ec-4476-8b99-51d94b9ee042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377228547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2377228547
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3344155764
Short name T613
Test name
Test status
Simulation time 13409966 ps
CPU time 0.56 seconds
Started Feb 21 03:49:42 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 194192 kb
Host smart-ce6bf633-57da-42e4-b68a-efef03368cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344155764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3344155764
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2139919991
Short name T812
Test name
Test status
Simulation time 93733607983 ps
CPU time 36.04 seconds
Started Feb 21 03:49:33 PM PST 24
Finished Feb 21 03:50:09 PM PST 24
Peak memory 199580 kb
Host smart-7b27cfaa-3642-4a30-9d97-27bdb3c567ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139919991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2139919991
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2767176982
Short name T526
Test name
Test status
Simulation time 14483305559 ps
CPU time 11.91 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:49:52 PM PST 24
Peak memory 197248 kb
Host smart-9c4ed682-9cd0-4191-9813-afe6467875b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767176982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2767176982
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1693222311
Short name T130
Test name
Test status
Simulation time 34263445567 ps
CPU time 54.54 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:50:38 PM PST 24
Peak memory 199700 kb
Host smart-c31603fc-9c41-4653-b04d-ddf063cf4847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693222311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1693222311
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3754653716
Short name T536
Test name
Test status
Simulation time 244386425330 ps
CPU time 355.28 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:55:40 PM PST 24
Peak memory 199720 kb
Host smart-dfb117ac-9109-41d3-af83-7afbf2083022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754653716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3754653716
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3162703391
Short name T867
Test name
Test status
Simulation time 8138934539 ps
CPU time 12.18 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:49:53 PM PST 24
Peak memory 198528 kb
Host smart-adba9db1-ac42-48c5-84c2-464c1d5d02c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162703391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3162703391
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2456263289
Short name T890
Test name
Test status
Simulation time 80625972021 ps
CPU time 179.63 seconds
Started Feb 21 03:49:42 PM PST 24
Finished Feb 21 03:52:43 PM PST 24
Peak memory 198984 kb
Host smart-14b59457-ccd7-4b5a-81f7-b2d2bafa8d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456263289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2456263289
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2318800364
Short name T163
Test name
Test status
Simulation time 20378458485 ps
CPU time 945.98 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 04:05:31 PM PST 24
Peak memory 199680 kb
Host smart-19308768-68c3-43d9-b8e9-c221e7693d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318800364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2318800364
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.715672485
Short name T389
Test name
Test status
Simulation time 33492731518 ps
CPU time 12.99 seconds
Started Feb 21 03:49:30 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 199068 kb
Host smart-df021dc6-70f8-4832-8adf-0220dd445922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715672485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.715672485
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1663638642
Short name T699
Test name
Test status
Simulation time 464800597 ps
CPU time 0.96 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:49:42 PM PST 24
Peak memory 195060 kb
Host smart-752c7727-f228-48de-ac79-1f3fc065806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663638642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1663638642
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4187607178
Short name T603
Test name
Test status
Simulation time 6262156484 ps
CPU time 16.56 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:50:06 PM PST 24
Peak memory 198688 kb
Host smart-0432429d-7973-4d3c-a645-1e341b95850c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187607178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4187607178
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.344184503
Short name T112
Test name
Test status
Simulation time 16653322479 ps
CPU time 213.97 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:53:19 PM PST 24
Peak memory 208960 kb
Host smart-f83eda10-20ff-4ea7-a955-e681b55e5baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344184503 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.344184503
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3810745611
Short name T579
Test name
Test status
Simulation time 532399897 ps
CPU time 2.13 seconds
Started Feb 21 03:49:34 PM PST 24
Finished Feb 21 03:49:36 PM PST 24
Peak memory 198116 kb
Host smart-607943cc-c443-4fe3-9adf-b4722fdef444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810745611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3810745611
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1007716027
Short name T1012
Test name
Test status
Simulation time 108189490378 ps
CPU time 157.89 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:52:23 PM PST 24
Peak memory 199728 kb
Host smart-20773342-c4ea-4cc8-9cc2-35c4cac5dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007716027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1007716027
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2021661840
Short name T997
Test name
Test status
Simulation time 62959008 ps
CPU time 0.54 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:49:45 PM PST 24
Peak memory 195112 kb
Host smart-cb12da65-5a4c-4b01-aee5-a5ff857f858b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021661840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2021661840
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3636500570
Short name T1053
Test name
Test status
Simulation time 104787189184 ps
CPU time 188.65 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:52:53 PM PST 24
Peak memory 199620 kb
Host smart-9a957a21-7e6b-446b-8e2e-440a20fd6820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636500570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3636500570
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3693976683
Short name T793
Test name
Test status
Simulation time 132913465473 ps
CPU time 108.77 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:51:29 PM PST 24
Peak memory 198920 kb
Host smart-f741cbaf-2338-4add-bf52-a3ca1bc7ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693976683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3693976683
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.3012305837
Short name T836
Test name
Test status
Simulation time 489981895461 ps
CPU time 274.91 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:54:21 PM PST 24
Peak memory 199616 kb
Host smart-2bc87977-f5f9-4d5c-8965-bbfd7ae59ac4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012305837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3012305837
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.77672946
Short name T550
Test name
Test status
Simulation time 136289179592 ps
CPU time 450.54 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:57:16 PM PST 24
Peak memory 199728 kb
Host smart-12da0c70-3c09-49b6-a06c-16f511dfb635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77672946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.77672946
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.54843024
Short name T1010
Test name
Test status
Simulation time 9074144018 ps
CPU time 24.55 seconds
Started Feb 21 03:49:49 PM PST 24
Finished Feb 21 03:50:14 PM PST 24
Peak memory 199140 kb
Host smart-e447b449-d955-4fb0-b007-95a1da4dd45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54843024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.54843024
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.73853367
Short name T921
Test name
Test status
Simulation time 184934439094 ps
CPU time 66.42 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:50:52 PM PST 24
Peak memory 208096 kb
Host smart-3acf5c2f-840b-4601-becf-3e5f28545cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73853367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.73853367
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3028702960
Short name T540
Test name
Test status
Simulation time 38962147579 ps
CPU time 555.84 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:59:05 PM PST 24
Peak memory 199472 kb
Host smart-f7603c2f-975d-4ee0-a517-0a2ec65a54e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028702960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3028702960
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2824849990
Short name T1080
Test name
Test status
Simulation time 90218798329 ps
CPU time 40.53 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:50:25 PM PST 24
Peak memory 198696 kb
Host smart-e0648965-ad04-419a-8e1a-fd3b34f258f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824849990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2824849990
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4091941331
Short name T643
Test name
Test status
Simulation time 39087161818 ps
CPU time 17.44 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 195376 kb
Host smart-9a683045-241f-4f86-a6e3-50003f75edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091941331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4091941331
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2472173814
Short name T940
Test name
Test status
Simulation time 670837573 ps
CPU time 3.14 seconds
Started Feb 21 03:49:34 PM PST 24
Finished Feb 21 03:49:38 PM PST 24
Peak memory 198072 kb
Host smart-9b4b8f53-21b5-42fb-a1ce-65bbe6fba11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472173814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2472173814
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1199222770
Short name T744
Test name
Test status
Simulation time 6787313900 ps
CPU time 9.27 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:49:59 PM PST 24
Peak memory 199276 kb
Host smart-1fe23e97-4fa0-4d6b-a6cf-01cb1c1f754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199222770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1199222770
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1484589762
Short name T914
Test name
Test status
Simulation time 53009674355 ps
CPU time 22.31 seconds
Started Feb 21 03:49:40 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 199712 kb
Host smart-763d6cf2-af44-4159-8054-9caff7aa949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484589762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1484589762
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1241757375
Short name T519
Test name
Test status
Simulation time 11742460 ps
CPU time 0.55 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:49:48 PM PST 24
Peak memory 195136 kb
Host smart-1cad35d0-9cfb-4e63-856d-7258f41d998e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241757375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1241757375
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1876513878
Short name T999
Test name
Test status
Simulation time 67124032940 ps
CPU time 100.97 seconds
Started Feb 21 03:49:49 PM PST 24
Finished Feb 21 03:51:31 PM PST 24
Peak memory 199628 kb
Host smart-897f6491-9020-4208-b30d-4656655d84a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876513878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1876513878
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3971429405
Short name T708
Test name
Test status
Simulation time 53071231684 ps
CPU time 33.71 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:50:22 PM PST 24
Peak memory 198560 kb
Host smart-6e341611-a19b-44e9-84b7-31d695644e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971429405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3971429405
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.1449314910
Short name T675
Test name
Test status
Simulation time 159409710591 ps
CPU time 130.48 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:51:55 PM PST 24
Peak memory 196436 kb
Host smart-f8664315-89ad-4766-a0e5-dbdb93867700
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449314910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1449314910
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1737218211
Short name T978
Test name
Test status
Simulation time 87845808709 ps
CPU time 948.04 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 04:05:33 PM PST 24
Peak memory 199656 kb
Host smart-df4ad62e-6ef1-4c43-aac0-a542149ff69e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737218211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1737218211
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1805309452
Short name T952
Test name
Test status
Simulation time 22647011782 ps
CPU time 15.36 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 195280 kb
Host smart-c8e845cd-7951-4a5f-8202-b5372bb19f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805309452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1805309452
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3350391028
Short name T464
Test name
Test status
Simulation time 142875655 ps
CPU time 0.6 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:49:46 PM PST 24
Peak memory 195036 kb
Host smart-9238e813-a7bf-4d73-b744-bfbcdb8110a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350391028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3350391028
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2477015272
Short name T382
Test name
Test status
Simulation time 216837043308 ps
CPU time 41.68 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:50:27 PM PST 24
Peak memory 199652 kb
Host smart-08e69467-5003-4922-b4bc-f0a1b8c80428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477015272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2477015272
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2601719479
Short name T747
Test name
Test status
Simulation time 4210126821 ps
CPU time 2.34 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:49:51 PM PST 24
Peak memory 195408 kb
Host smart-55ac98e6-b602-4d42-b2c2-3348144b79a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601719479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2601719479
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2795323208
Short name T664
Test name
Test status
Simulation time 447284252 ps
CPU time 2.87 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:49:52 PM PST 24
Peak memory 198760 kb
Host smart-a0f13fd4-3e0f-4086-b6b5-dd0b6c93a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795323208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2795323208
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1637550799
Short name T1017
Test name
Test status
Simulation time 45558582796 ps
CPU time 132.69 seconds
Started Feb 21 03:49:46 PM PST 24
Finished Feb 21 03:51:59 PM PST 24
Peak memory 208048 kb
Host smart-ca677f9a-8953-4713-b184-a2fddd3a474e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637550799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1637550799
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1330815436
Short name T111
Test name
Test status
Simulation time 201326133631 ps
CPU time 1062.54 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 04:07:28 PM PST 24
Peak memory 225112 kb
Host smart-615b55b5-9c27-4652-9669-5b1ad7b181af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330815436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1330815436
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3915597317
Short name T433
Test name
Test status
Simulation time 7672499095 ps
CPU time 13.27 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:49:59 PM PST 24
Peak memory 199680 kb
Host smart-ae4fe750-601f-455a-a764-6a2aaf326cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915597317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3915597317
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2160531695
Short name T722
Test name
Test status
Simulation time 78810226623 ps
CPU time 65.58 seconds
Started Feb 21 03:49:46 PM PST 24
Finished Feb 21 03:50:51 PM PST 24
Peak memory 199676 kb
Host smart-34ba47dc-7927-4390-8950-d32ef63d35d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160531695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2160531695
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.939040370
Short name T517
Test name
Test status
Simulation time 12559786 ps
CPU time 0.55 seconds
Started Feb 21 03:49:43 PM PST 24
Finished Feb 21 03:49:44 PM PST 24
Peak memory 195096 kb
Host smart-37a3cd82-84ac-4692-981f-ae0331a9dbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939040370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.939040370
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1215456317
Short name T648
Test name
Test status
Simulation time 237661420789 ps
CPU time 73.77 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:51:03 PM PST 24
Peak memory 199656 kb
Host smart-b5040099-b13a-44c0-a00a-1cf746832100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215456317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1215456317
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1651642957
Short name T1037
Test name
Test status
Simulation time 100241414809 ps
CPU time 153.67 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 198840 kb
Host smart-08f6e4e7-c9b9-4c43-9b1b-2ca334199f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651642957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1651642957
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.448301724
Short name T564
Test name
Test status
Simulation time 12808247253 ps
CPU time 9.89 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:49:55 PM PST 24
Peak memory 196304 kb
Host smart-4198e772-28d1-445e-8d52-04ea18addba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448301724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.448301724
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1474555353
Short name T986
Test name
Test status
Simulation time 127673212032 ps
CPU time 238.02 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:53:46 PM PST 24
Peak memory 199748 kb
Host smart-ea1b01d2-7eec-495a-b84b-9a758f6510dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474555353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1474555353
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2872793853
Short name T590
Test name
Test status
Simulation time 241774116094 ps
CPU time 308.11 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:54:53 PM PST 24
Peak memory 199660 kb
Host smart-7700ffa4-d211-4c5d-95de-9939765d7d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872793853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2872793853
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_noise_filter.903503486
Short name T408
Test name
Test status
Simulation time 142815095602 ps
CPU time 33.41 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:21 PM PST 24
Peak memory 199852 kb
Host smart-f52c3505-910c-4f74-8974-b478edb5bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903503486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.903503486
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.513784200
Short name T428
Test name
Test status
Simulation time 11680416444 ps
CPU time 302.87 seconds
Started Feb 21 03:49:41 PM PST 24
Finished Feb 21 03:54:44 PM PST 24
Peak memory 199720 kb
Host smart-4acb350a-dd8d-4e66-a585-2d6707a96850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513784200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.513784200
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2138159036
Short name T901
Test name
Test status
Simulation time 3892032616 ps
CPU time 24.21 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:50:09 PM PST 24
Peak memory 198324 kb
Host smart-3808197e-40e3-4fbd-87c7-fc881bbf651c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138159036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2138159036
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.477621053
Short name T942
Test name
Test status
Simulation time 1459257482 ps
CPU time 1.88 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:49:52 PM PST 24
Peak memory 195012 kb
Host smart-14876307-0ad8-4eac-81e4-c11f329f7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477621053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.477621053
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1015793416
Short name T892
Test name
Test status
Simulation time 6253426588 ps
CPU time 14.01 seconds
Started Feb 21 03:49:46 PM PST 24
Finished Feb 21 03:50:00 PM PST 24
Peak memory 198524 kb
Host smart-7a37561a-388d-4cf0-b5d6-6cb0647dee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015793416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1015793416
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3432726497
Short name T200
Test name
Test status
Simulation time 875562358288 ps
CPU time 157.34 seconds
Started Feb 21 03:49:44 PM PST 24
Finished Feb 21 03:52:23 PM PST 24
Peak memory 215296 kb
Host smart-0cee348a-e054-4f5f-8df4-30d10112922c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432726497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3432726497
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3144152131
Short name T427
Test name
Test status
Simulation time 8261526831 ps
CPU time 9.84 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:49:57 PM PST 24
Peak memory 199152 kb
Host smart-4eca514a-8980-4fed-b450-aa0dbed70ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144152131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3144152131
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.4290846834
Short name T683
Test name
Test status
Simulation time 20656953363 ps
CPU time 15.39 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 197144 kb
Host smart-6b7b26f7-ac10-43b7-85d8-ba5732320522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290846834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4290846834
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2924743217
Short name T30
Test name
Test status
Simulation time 42879966 ps
CPU time 0.56 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:49:50 PM PST 24
Peak memory 195148 kb
Host smart-8cfc219b-4962-4a5f-90f6-725bd77d719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924743217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2924743217
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2878137810
Short name T390
Test name
Test status
Simulation time 32136448608 ps
CPU time 17.91 seconds
Started Feb 21 03:49:49 PM PST 24
Finished Feb 21 03:50:08 PM PST 24
Peak memory 199580 kb
Host smart-40fe4b5f-ca39-40a3-9687-e593ed568d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878137810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2878137810
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1908985600
Short name T740
Test name
Test status
Simulation time 100032731002 ps
CPU time 41.21 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:50:27 PM PST 24
Peak memory 199396 kb
Host smart-6983e492-3a53-4979-a320-95c9a22a1baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908985600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1908985600
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.836153458
Short name T183
Test name
Test status
Simulation time 64441779712 ps
CPU time 112.55 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:51:41 PM PST 24
Peak memory 199632 kb
Host smart-85688380-0974-493a-8649-0e1462839c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836153458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.836153458
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1902778791
Short name T1025
Test name
Test status
Simulation time 705425109496 ps
CPU time 142.85 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:52:12 PM PST 24
Peak memory 199732 kb
Host smart-cb1ed1f7-099f-4481-9ea2-3d89fc2299dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902778791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1902778791
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2175607642
Short name T619
Test name
Test status
Simulation time 184915422175 ps
CPU time 877.2 seconds
Started Feb 21 03:49:51 PM PST 24
Finished Feb 21 04:04:28 PM PST 24
Peak memory 199624 kb
Host smart-e83dcd09-5f77-4d56-ba7f-4c7f11ee4c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175607642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2175607642
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2056526024
Short name T455
Test name
Test status
Simulation time 4965674482 ps
CPU time 7.39 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:49:56 PM PST 24
Peak memory 198968 kb
Host smart-afffbead-31ee-42cc-b1f3-a2f6d58b1378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056526024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2056526024
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2072177287
Short name T552
Test name
Test status
Simulation time 24987478028 ps
CPU time 40.01 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:50:28 PM PST 24
Peak memory 197128 kb
Host smart-65fd51af-8909-4d69-958b-d01f01cf9f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072177287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2072177287
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.561893068
Short name T105
Test name
Test status
Simulation time 12088169949 ps
CPU time 149.54 seconds
Started Feb 21 03:49:51 PM PST 24
Finished Feb 21 03:52:21 PM PST 24
Peak memory 199628 kb
Host smart-b8e9c4a5-8f11-42ae-8b78-671839d48a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561893068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.561893068
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2577616532
Short name T423
Test name
Test status
Simulation time 3115957953 ps
CPU time 5.7 seconds
Started Feb 21 03:49:51 PM PST 24
Finished Feb 21 03:49:57 PM PST 24
Peak memory 195396 kb
Host smart-1f9dd30c-eaba-43b7-a1ab-a694a7158d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577616532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2577616532
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1102331922
Short name T439
Test name
Test status
Simulation time 294671129 ps
CPU time 1.31 seconds
Started Feb 21 03:49:45 PM PST 24
Finished Feb 21 03:49:47 PM PST 24
Peak memory 198000 kb
Host smart-0ca2a3cf-b15d-4e32-a2cf-1da0b2e691cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102331922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1102331922
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4059054690
Short name T186
Test name
Test status
Simulation time 630438254514 ps
CPU time 670.95 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 04:00:59 PM PST 24
Peak memory 199724 kb
Host smart-9c79f87a-82a8-4152-947f-9793facb1e0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059054690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4059054690
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3681605673
Short name T731
Test name
Test status
Simulation time 1062000326 ps
CPU time 3.4 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:49:54 PM PST 24
Peak memory 198128 kb
Host smart-f69ced36-e050-45a5-bcb2-c451c79cd5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681605673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3681605673
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3694167389
Short name T1084
Test name
Test status
Simulation time 26683807719 ps
CPU time 11.25 seconds
Started Feb 21 03:49:46 PM PST 24
Finished Feb 21 03:49:58 PM PST 24
Peak memory 198144 kb
Host smart-7fcbb831-adbb-44a5-81d3-f0805acba7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694167389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3694167389
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1078572438
Short name T641
Test name
Test status
Simulation time 41464795 ps
CPU time 0.53 seconds
Started Feb 21 03:49:56 PM PST 24
Finished Feb 21 03:49:57 PM PST 24
Peak memory 194100 kb
Host smart-e9260762-3d46-46d8-88a5-92a43bb554f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078572438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1078572438
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1198292480
Short name T886
Test name
Test status
Simulation time 278423340462 ps
CPU time 105.91 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:51:33 PM PST 24
Peak memory 199576 kb
Host smart-62ff71c1-9360-4564-8b05-cca11f138091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198292480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1198292480
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1411464461
Short name T1021
Test name
Test status
Simulation time 7597325701 ps
CPU time 5.59 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:49:55 PM PST 24
Peak memory 198312 kb
Host smart-c2b2b122-c2e2-4830-99d3-dbe05bc1acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411464461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1411464461
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.745397885
Short name T14
Test name
Test status
Simulation time 80760188473 ps
CPU time 44.06 seconds
Started Feb 21 03:49:49 PM PST 24
Finished Feb 21 03:50:34 PM PST 24
Peak memory 199284 kb
Host smart-e74508a4-a738-4d44-b590-545278d59c29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745397885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.745397885
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.917654343
Short name T516
Test name
Test status
Simulation time 109257771307 ps
CPU time 610.61 seconds
Started Feb 21 03:49:48 PM PST 24
Finished Feb 21 03:59:59 PM PST 24
Peak memory 199660 kb
Host smart-16bbf230-eb43-46ef-8ff7-143468a5f40e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917654343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.917654343
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3289185664
Short name T527
Test name
Test status
Simulation time 2327670879 ps
CPU time 5.61 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:49:56 PM PST 24
Peak memory 198512 kb
Host smart-b904625b-2b88-4be6-887a-76ad7fe16dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289185664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3289185664
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.748915243
Short name T166
Test name
Test status
Simulation time 134841414197 ps
CPU time 58.58 seconds
Started Feb 21 03:49:51 PM PST 24
Finished Feb 21 03:50:50 PM PST 24
Peak memory 199724 kb
Host smart-8d1ad465-5885-4f3f-ad10-34e2afd2d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748915243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.748915243
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2413228411
Short name T580
Test name
Test status
Simulation time 27820773161 ps
CPU time 779.94 seconds
Started Feb 21 03:49:49 PM PST 24
Finished Feb 21 04:02:50 PM PST 24
Peak memory 199632 kb
Host smart-9955a80a-66cd-464f-a75b-f797b9d94e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413228411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2413228411
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4090121716
Short name T696
Test name
Test status
Simulation time 3275950556 ps
CPU time 9.55 seconds
Started Feb 21 03:49:51 PM PST 24
Finished Feb 21 03:50:02 PM PST 24
Peak memory 198096 kb
Host smart-1b378e3e-7cdd-433a-a104-040dc63c5315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090121716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4090121716
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2555393781
Short name T532
Test name
Test status
Simulation time 313989162477 ps
CPU time 233.88 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 198860 kb
Host smart-f2eab07f-2064-4fd8-bc5d-8e3cdecf2b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555393781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2555393781
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.480586060
Short name T476
Test name
Test status
Simulation time 1841703012 ps
CPU time 3.68 seconds
Started Feb 21 03:49:50 PM PST 24
Finished Feb 21 03:49:54 PM PST 24
Peak memory 195144 kb
Host smart-9175854f-8f37-4e17-9694-a77688460c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480586060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.480586060
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2666566560
Short name T640
Test name
Test status
Simulation time 326484191 ps
CPU time 1.21 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:49:49 PM PST 24
Peak memory 197552 kb
Host smart-ae4b7978-b8d5-4115-91c4-9c1775071de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666566560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2666566560
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.94775341
Short name T774
Test name
Test status
Simulation time 12410824877 ps
CPU time 25.88 seconds
Started Feb 21 03:49:47 PM PST 24
Finished Feb 21 03:50:13 PM PST 24
Peak memory 199492 kb
Host smart-b9c6700a-c2da-40f7-9546-22ad72446719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94775341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.94775341
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2903296115
Short name T967
Test name
Test status
Simulation time 17707911998 ps
CPU time 32.2 seconds
Started Feb 21 03:50:03 PM PST 24
Finished Feb 21 03:50:36 PM PST 24
Peak memory 199684 kb
Host smart-487f3908-994e-44c9-ae52-638236564422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903296115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2903296115
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3486989748
Short name T469
Test name
Test status
Simulation time 13247472 ps
CPU time 0.57 seconds
Started Feb 21 03:50:08 PM PST 24
Finished Feb 21 03:50:08 PM PST 24
Peak memory 195168 kb
Host smart-dea0d899-d55e-4be9-affa-72ccc4eb3b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486989748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3486989748
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1885506130
Short name T1067
Test name
Test status
Simulation time 274990943786 ps
CPU time 449.17 seconds
Started Feb 21 03:49:57 PM PST 24
Finished Feb 21 03:57:27 PM PST 24
Peak memory 199692 kb
Host smart-25a8b3b6-2974-44f2-9e15-aefbb1650ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885506130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1885506130
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1512832208
Short name T178
Test name
Test status
Simulation time 283967238824 ps
CPU time 401.96 seconds
Started Feb 21 03:49:55 PM PST 24
Finished Feb 21 03:56:37 PM PST 24
Peak memory 199720 kb
Host smart-8d61b5af-4678-47c1-a18f-510257e64d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512832208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1512832208
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4070380659
Short name T214
Test name
Test status
Simulation time 60015280547 ps
CPU time 107.28 seconds
Started Feb 21 03:49:56 PM PST 24
Finished Feb 21 03:51:44 PM PST 24
Peak memory 199648 kb
Host smart-bf6719a5-c792-4275-8ec0-c4783b0dcb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070380659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4070380659
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.897949441
Short name T676
Test name
Test status
Simulation time 11831648044 ps
CPU time 5.55 seconds
Started Feb 21 03:49:56 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 195216 kb
Host smart-a924f39f-0b25-42b5-8aa1-b2dbf608cbed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897949441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.897949441
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3974372608
Short name T1007
Test name
Test status
Simulation time 78541569795 ps
CPU time 228.97 seconds
Started Feb 21 03:50:04 PM PST 24
Finished Feb 21 03:53:54 PM PST 24
Peak memory 199728 kb
Host smart-3362c55b-b665-4b1f-b2da-35e09637abbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974372608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3974372608
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2119281429
Short name T477
Test name
Test status
Simulation time 2293323190 ps
CPU time 2.68 seconds
Started Feb 21 03:49:55 PM PST 24
Finished Feb 21 03:49:58 PM PST 24
Peak memory 195528 kb
Host smart-3724574b-2887-4d67-8029-be2640af2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119281429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2119281429
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3090035673
Short name T767
Test name
Test status
Simulation time 139122800869 ps
CPU time 49.83 seconds
Started Feb 21 03:49:52 PM PST 24
Finished Feb 21 03:50:42 PM PST 24
Peak memory 197252 kb
Host smart-098eeebd-481d-44db-8a28-ee2db1d6d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090035673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3090035673
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1859485286
Short name T588
Test name
Test status
Simulation time 15371017308 ps
CPU time 685.27 seconds
Started Feb 21 03:49:53 PM PST 24
Finished Feb 21 04:01:19 PM PST 24
Peak memory 199648 kb
Host smart-71e02249-2048-4490-be49-d89d044005f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859485286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1859485286
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2588566018
Short name T672
Test name
Test status
Simulation time 2710147421 ps
CPU time 8.58 seconds
Started Feb 21 03:49:54 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 197552 kb
Host smart-45e6431e-cdc5-4ccb-89fd-d70d9d9dd6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588566018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2588566018
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1698783321
Short name T790
Test name
Test status
Simulation time 82709299435 ps
CPU time 131.73 seconds
Started Feb 21 03:49:56 PM PST 24
Finished Feb 21 03:52:08 PM PST 24
Peak memory 199660 kb
Host smart-256bcb89-fbea-4422-b77a-43d5c829f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698783321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1698783321
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2562913801
Short name T1039
Test name
Test status
Simulation time 1709067115 ps
CPU time 3.33 seconds
Started Feb 21 03:49:55 PM PST 24
Finished Feb 21 03:49:59 PM PST 24
Peak memory 195036 kb
Host smart-d1c30c15-0beb-45fc-95a2-c0cbf9ef68b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562913801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2562913801
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.259574783
Short name T792
Test name
Test status
Simulation time 5816470286 ps
CPU time 22.03 seconds
Started Feb 21 03:49:57 PM PST 24
Finished Feb 21 03:50:19 PM PST 24
Peak memory 199016 kb
Host smart-0f7bb19d-cba0-4a3a-ad05-bff6dfb1fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259574783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.259574783
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1462835697
Short name T15
Test name
Test status
Simulation time 364359738241 ps
CPU time 146.37 seconds
Started Feb 21 03:50:00 PM PST 24
Finished Feb 21 03:52:26 PM PST 24
Peak memory 199672 kb
Host smart-ad62812a-d057-4ffa-8217-1d3b4d01d9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462835697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1462835697
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1797945957
Short name T453
Test name
Test status
Simulation time 73730461359 ps
CPU time 592.17 seconds
Started Feb 21 03:49:59 PM PST 24
Finished Feb 21 03:59:51 PM PST 24
Peak memory 216296 kb
Host smart-b76c609b-49ee-4ce3-afaa-183969bb36b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797945957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1797945957
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1369748558
Short name T23
Test name
Test status
Simulation time 1198790704 ps
CPU time 2.06 seconds
Started Feb 21 03:49:54 PM PST 24
Finished Feb 21 03:49:56 PM PST 24
Peak memory 197620 kb
Host smart-ac264238-2b93-405c-b696-24830fcd8096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369748558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1369748558
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2910740452
Short name T577
Test name
Test status
Simulation time 76396984675 ps
CPU time 80.02 seconds
Started Feb 21 03:49:56 PM PST 24
Finished Feb 21 03:51:17 PM PST 24
Peak memory 199528 kb
Host smart-2cd37b05-cb57-4974-bc0d-15ea4e0af140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910740452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2910740452
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.701148916
Short name T639
Test name
Test status
Simulation time 16921801 ps
CPU time 0.56 seconds
Started Feb 21 03:50:00 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 195124 kb
Host smart-1ab5d139-d2de-4c3c-b1ec-2326a1d9360d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701148916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.701148916
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2131950160
Short name T917
Test name
Test status
Simulation time 308669838104 ps
CPU time 181.61 seconds
Started Feb 21 03:50:01 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199612 kb
Host smart-35a4532a-3e6f-49f2-8d6e-3f2c38252aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131950160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2131950160
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.474285691
Short name T283
Test name
Test status
Simulation time 39189934299 ps
CPU time 31.21 seconds
Started Feb 21 03:50:02 PM PST 24
Finished Feb 21 03:50:34 PM PST 24
Peak memory 199640 kb
Host smart-20c56c12-17a3-478b-a87e-e8262ce2e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474285691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.474285691
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4268504274
Short name T443
Test name
Test status
Simulation time 125142284043 ps
CPU time 238.29 seconds
Started Feb 21 03:50:00 PM PST 24
Finished Feb 21 03:53:59 PM PST 24
Peak memory 199736 kb
Host smart-89eb7038-4d26-4f69-a658-11c32d210294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268504274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4268504274
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1347383714
Short name T84
Test name
Test status
Simulation time 2910758456906 ps
CPU time 1121.31 seconds
Started Feb 21 03:50:08 PM PST 24
Finished Feb 21 04:08:49 PM PST 24
Peak memory 198248 kb
Host smart-31597c60-f56a-434a-b12b-916e3f0f5b3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347383714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1347383714
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4128835164
Short name T432
Test name
Test status
Simulation time 103020438791 ps
CPU time 466.03 seconds
Started Feb 21 03:50:00 PM PST 24
Finished Feb 21 03:57:46 PM PST 24
Peak memory 199660 kb
Host smart-5ac734fe-706d-4569-8820-4cdb34e82991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128835164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4128835164
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3770715672
Short name T459
Test name
Test status
Simulation time 6500530175 ps
CPU time 4.92 seconds
Started Feb 21 03:50:03 PM PST 24
Finished Feb 21 03:50:09 PM PST 24
Peak memory 198460 kb
Host smart-9b5c0b8f-db42-43c0-834d-edfc4593a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770715672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3770715672
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3866116134
Short name T444
Test name
Test status
Simulation time 41311928879 ps
CPU time 70.9 seconds
Started Feb 21 03:50:03 PM PST 24
Finished Feb 21 03:51:15 PM PST 24
Peak memory 199276 kb
Host smart-fb8c1ef3-d279-4ca6-89cc-9ff72b2c98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866116134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3866116134
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1511836036
Short name T546
Test name
Test status
Simulation time 20957010921 ps
CPU time 284.71 seconds
Started Feb 21 03:50:02 PM PST 24
Finished Feb 21 03:54:48 PM PST 24
Peak memory 199648 kb
Host smart-03965f9e-a551-4fb6-9d34-2eb066ad3317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511836036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1511836036
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2386917070
Short name T717
Test name
Test status
Simulation time 27810099342 ps
CPU time 44.39 seconds
Started Feb 21 03:50:04 PM PST 24
Finished Feb 21 03:50:49 PM PST 24
Peak memory 199252 kb
Host smart-14802666-4805-429e-b44b-38fc3ce41668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386917070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2386917070
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.196363562
Short name T576
Test name
Test status
Simulation time 37838920137 ps
CPU time 56.94 seconds
Started Feb 21 03:49:59 PM PST 24
Finished Feb 21 03:50:57 PM PST 24
Peak memory 195296 kb
Host smart-90d1f1dd-50c5-4e94-bc7d-e3ef960e0092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196363562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.196363562
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2650411858
Short name T718
Test name
Test status
Simulation time 5806603703 ps
CPU time 22.48 seconds
Started Feb 21 03:50:03 PM PST 24
Finished Feb 21 03:50:26 PM PST 24
Peak memory 199064 kb
Host smart-ae5b8e43-d1bc-4cba-b6bd-54074dd5d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650411858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2650411858
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3806747730
Short name T191
Test name
Test status
Simulation time 191647039819 ps
CPU time 99.32 seconds
Started Feb 21 03:50:04 PM PST 24
Finished Feb 21 03:51:44 PM PST 24
Peak memory 199672 kb
Host smart-73b36f69-2ff2-4e85-95fa-7c836d7ab924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806747730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3806747730
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3943563468
Short name T838
Test name
Test status
Simulation time 1669385033 ps
CPU time 1.42 seconds
Started Feb 21 03:49:59 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 197048 kb
Host smart-0be4d844-6c9c-44c9-bb8a-360855482c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943563468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3943563468
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4158534051
Short name T431
Test name
Test status
Simulation time 48888765197 ps
CPU time 84.29 seconds
Started Feb 21 03:50:01 PM PST 24
Finished Feb 21 03:51:26 PM PST 24
Peak memory 199616 kb
Host smart-190ed9e4-fae6-4609-adea-0386e9ec6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158534051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4158534051
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2891721755
Short name T1099
Test name
Test status
Simulation time 14955099 ps
CPU time 0.56 seconds
Started Feb 21 03:50:26 PM PST 24
Finished Feb 21 03:50:27 PM PST 24
Peak memory 195148 kb
Host smart-9d227f41-8853-4f0c-af9c-7622e581ce0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891721755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2891721755
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1894387148
Short name T50
Test name
Test status
Simulation time 78788303430 ps
CPU time 270.89 seconds
Started Feb 21 03:50:07 PM PST 24
Finished Feb 21 03:54:38 PM PST 24
Peak memory 199656 kb
Host smart-cecbda3a-f1af-4602-a855-c136a5f1321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894387148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1894387148
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3659280664
Short name T763
Test name
Test status
Simulation time 259499392475 ps
CPU time 108.93 seconds
Started Feb 21 03:50:07 PM PST 24
Finished Feb 21 03:51:56 PM PST 24
Peak memory 198840 kb
Host smart-c6766d40-ad61-4523-9552-96c3eb7a121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659280664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3659280664
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3434661127
Short name T234
Test name
Test status
Simulation time 23285016200 ps
CPU time 33.47 seconds
Started Feb 21 03:50:06 PM PST 24
Finished Feb 21 03:50:40 PM PST 24
Peak memory 199268 kb
Host smart-ff7e3afc-d83a-4efb-98b9-cb7c86e23943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434661127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3434661127
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3841618755
Short name T561
Test name
Test status
Simulation time 11200185684 ps
CPU time 4.82 seconds
Started Feb 21 03:50:10 PM PST 24
Finished Feb 21 03:50:16 PM PST 24
Peak memory 196336 kb
Host smart-af22d21c-a240-4e38-a5e2-047b91e4f87f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841618755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3841618755
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2353720891
Short name T627
Test name
Test status
Simulation time 186992935083 ps
CPU time 468.74 seconds
Started Feb 21 03:50:07 PM PST 24
Finished Feb 21 03:57:57 PM PST 24
Peak memory 199720 kb
Host smart-713e5482-9871-4119-9c4d-88f84b411988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353720891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2353720891
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3651323834
Short name T1061
Test name
Test status
Simulation time 8978619501 ps
CPU time 13.62 seconds
Started Feb 21 03:50:05 PM PST 24
Finished Feb 21 03:50:19 PM PST 24
Peak memory 198656 kb
Host smart-f889a586-dab2-4b85-92e1-83b01a46b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651323834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3651323834
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.712505272
Short name T854
Test name
Test status
Simulation time 115411350353 ps
CPU time 83.83 seconds
Started Feb 21 03:50:05 PM PST 24
Finished Feb 21 03:51:29 PM PST 24
Peak memory 198904 kb
Host smart-5cb6cbe2-e2bf-455b-98d1-dc920f199382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712505272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.712505272
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4116286225
Short name T435
Test name
Test status
Simulation time 9312628696 ps
CPU time 574.31 seconds
Started Feb 21 03:50:08 PM PST 24
Finished Feb 21 03:59:42 PM PST 24
Peak memory 199540 kb
Host smart-4e2bdc4e-20f4-4600-8540-a31a876921b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116286225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4116286225
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2029489542
Short name T681
Test name
Test status
Simulation time 1384881114 ps
CPU time 2.93 seconds
Started Feb 21 03:50:06 PM PST 24
Finished Feb 21 03:50:09 PM PST 24
Peak memory 197828 kb
Host smart-b281e513-cab8-4aab-b425-305561780136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029489542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2029489542
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.625290715
Short name T365
Test name
Test status
Simulation time 114834354743 ps
CPU time 40.41 seconds
Started Feb 21 03:50:08 PM PST 24
Finished Feb 21 03:50:48 PM PST 24
Peak memory 199712 kb
Host smart-970231e7-3adb-4d53-8a42-82dc2c7911e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625290715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.625290715
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1105100996
Short name T638
Test name
Test status
Simulation time 42338354331 ps
CPU time 7.01 seconds
Started Feb 21 03:50:09 PM PST 24
Finished Feb 21 03:50:17 PM PST 24
Peak memory 195152 kb
Host smart-03ee7c93-bb23-4a88-8bba-e84f03f8ff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105100996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1105100996
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.556337320
Short name T512
Test name
Test status
Simulation time 521348118 ps
CPU time 1.65 seconds
Started Feb 21 03:50:05 PM PST 24
Finished Feb 21 03:50:07 PM PST 24
Peak memory 198052 kb
Host smart-1aee2dda-9d51-455a-bb7c-4623e0053500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556337320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.556337320
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3446215012
Short name T109
Test name
Test status
Simulation time 190512805904 ps
CPU time 499.2 seconds
Started Feb 21 03:50:20 PM PST 24
Finished Feb 21 03:58:40 PM PST 24
Peak memory 216356 kb
Host smart-717c08d3-acec-4f0d-bfd2-55bac6e6eb9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446215012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3446215012
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2331280529
Short name T485
Test name
Test status
Simulation time 6286749145 ps
CPU time 22.72 seconds
Started Feb 21 03:50:05 PM PST 24
Finished Feb 21 03:50:28 PM PST 24
Peak memory 198528 kb
Host smart-d42d1086-e8e5-4d8b-8926-e648921513a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331280529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2331280529
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2779789079
Short name T954
Test name
Test status
Simulation time 268603459682 ps
CPU time 161.12 seconds
Started Feb 21 03:50:05 PM PST 24
Finished Feb 21 03:52:47 PM PST 24
Peak memory 199592 kb
Host smart-4409a4c2-33d2-4bdf-92ab-2ff351d8d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779789079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2779789079
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3901201318
Short name T28
Test name
Test status
Simulation time 41094356 ps
CPU time 0.55 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:50:46 PM PST 24
Peak memory 195116 kb
Host smart-67c2521b-82e4-4b96-bdd9-5d6fb15cf8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901201318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3901201318
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.833945153
Short name T616
Test name
Test status
Simulation time 28395003624 ps
CPU time 23.15 seconds
Started Feb 21 03:50:34 PM PST 24
Finished Feb 21 03:50:58 PM PST 24
Peak memory 199728 kb
Host smart-31b8084c-484e-48df-962b-372f2e8cc53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833945153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.833945153
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2735826917
Short name T618
Test name
Test status
Simulation time 31059947539 ps
CPU time 43.7 seconds
Started Feb 21 03:50:21 PM PST 24
Finished Feb 21 03:51:05 PM PST 24
Peak memory 199040 kb
Host smart-b0a830c2-5f31-4a4f-be91-7587a86bfb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735826917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2735826917
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.4076716993
Short name T375
Test name
Test status
Simulation time 50750413091 ps
CPU time 45.16 seconds
Started Feb 21 03:50:32 PM PST 24
Finished Feb 21 03:51:17 PM PST 24
Peak memory 199600 kb
Host smart-7dc973fc-c0a1-4d91-b160-69421621f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076716993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.4076716993
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.430679336
Short name T1006
Test name
Test status
Simulation time 168414419004 ps
CPU time 205.48 seconds
Started Feb 21 03:50:24 PM PST 24
Finished Feb 21 03:53:50 PM PST 24
Peak memory 199660 kb
Host smart-eb149b5a-6b1f-4157-88a7-47d7b1ca629d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430679336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.430679336
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_loopback.725162919
Short name T1068
Test name
Test status
Simulation time 7771416014 ps
CPU time 7.31 seconds
Started Feb 21 03:50:26 PM PST 24
Finished Feb 21 03:50:33 PM PST 24
Peak memory 197048 kb
Host smart-73917274-2bdc-47f8-9f6e-2414b4969492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725162919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.725162919
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3917708759
Short name T617
Test name
Test status
Simulation time 242825390117 ps
CPU time 71.19 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:51:37 PM PST 24
Peak memory 199848 kb
Host smart-19cfb6e7-24f3-4804-a45c-c0d55a2b4a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917708759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3917708759
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1597837751
Short name T919
Test name
Test status
Simulation time 2675795481 ps
CPU time 5.51 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:50:30 PM PST 24
Peak memory 198276 kb
Host smart-6cfc22a9-3233-4e5b-a7ef-0a8c201ee62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597837751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1597837751
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4132582073
Short name T395
Test name
Test status
Simulation time 159582750205 ps
CPU time 53.72 seconds
Started Feb 21 03:50:33 PM PST 24
Finished Feb 21 03:51:27 PM PST 24
Peak memory 198884 kb
Host smart-52ec6cb9-6535-43ba-ab58-e44e7aef6a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132582073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4132582073
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.160620597
Short name T43
Test name
Test status
Simulation time 4576337124 ps
CPU time 4.25 seconds
Started Feb 21 03:50:24 PM PST 24
Finished Feb 21 03:50:29 PM PST 24
Peak memory 195468 kb
Host smart-662f7ccb-4427-47ee-9f04-28ab30fbd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160620597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.160620597
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1161211633
Short name T533
Test name
Test status
Simulation time 314724626 ps
CPU time 1.33 seconds
Started Feb 21 03:50:32 PM PST 24
Finished Feb 21 03:50:33 PM PST 24
Peak memory 197384 kb
Host smart-2628182d-aac4-4f6a-b51f-bdbadeb3ea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161211633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1161211633
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3233120504
Short name T887
Test name
Test status
Simulation time 1523741829 ps
CPU time 3.26 seconds
Started Feb 21 03:50:35 PM PST 24
Finished Feb 21 03:50:39 PM PST 24
Peak memory 198120 kb
Host smart-dcac5be4-bdca-4b3e-8692-9db8e598a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233120504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3233120504
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1679635876
Short name T122
Test name
Test status
Simulation time 17468544539 ps
CPU time 6.6 seconds
Started Feb 21 03:50:27 PM PST 24
Finished Feb 21 03:50:34 PM PST 24
Peak memory 196656 kb
Host smart-83138e54-98a4-473f-9247-9b636cf9b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679635876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1679635876
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1772101348
Short name T880
Test name
Test status
Simulation time 22943156 ps
CPU time 0.58 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:48:09 PM PST 24
Peak memory 195132 kb
Host smart-a96fe0d9-d45d-46cd-b100-2ed64adadc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772101348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1772101348
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2040430568
Short name T548
Test name
Test status
Simulation time 37737065741 ps
CPU time 67.69 seconds
Started Feb 21 03:47:49 PM PST 24
Finished Feb 21 03:48:57 PM PST 24
Peak memory 199640 kb
Host smart-16449123-7f88-4d48-8b6c-47dccbab9df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040430568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2040430568
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.100259764
Short name T368
Test name
Test status
Simulation time 70592780935 ps
CPU time 31.64 seconds
Started Feb 21 03:47:59 PM PST 24
Finished Feb 21 03:48:31 PM PST 24
Peak memory 199228 kb
Host smart-6bdb4f76-c12c-47fa-8b56-8f3fd3e49e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100259764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.100259764
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.900604946
Short name T168
Test name
Test status
Simulation time 29601635887 ps
CPU time 56.83 seconds
Started Feb 21 03:47:54 PM PST 24
Finished Feb 21 03:48:51 PM PST 24
Peak memory 199580 kb
Host smart-bd6a76af-40a2-4424-890a-d2474b62533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900604946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.900604946
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3797304600
Short name T498
Test name
Test status
Simulation time 10857744214 ps
CPU time 17.68 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:48:21 PM PST 24
Peak memory 195408 kb
Host smart-1f5127a2-1140-416c-8e66-c78c4dd1a86b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797304600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3797304600
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2588913665
Short name T753
Test name
Test status
Simulation time 145800323277 ps
CPU time 666.02 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:59:15 PM PST 24
Peak memory 199256 kb
Host smart-045379ca-d905-47e3-9d83-9987e4ee53b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588913665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2588913665
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1563054207
Short name T471
Test name
Test status
Simulation time 3146193710 ps
CPU time 2.2 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:48:05 PM PST 24
Peak memory 198116 kb
Host smart-d7bae4b4-172a-41b2-a12f-ccfdc57a20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563054207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1563054207
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3575487828
Short name T500
Test name
Test status
Simulation time 34855343060 ps
CPU time 34.59 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:41 PM PST 24
Peak memory 199924 kb
Host smart-c27a4bc0-f4d4-4ed8-8595-9d0ee4351b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575487828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3575487828
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3572498923
Short name T702
Test name
Test status
Simulation time 33612912278 ps
CPU time 500.88 seconds
Started Feb 21 03:48:09 PM PST 24
Finished Feb 21 03:56:31 PM PST 24
Peak memory 199608 kb
Host smart-78d7af23-961c-4def-8e04-89de37fd95bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572498923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3572498923
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2591521558
Short name T860
Test name
Test status
Simulation time 605404309 ps
CPU time 4.98 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:48:15 PM PST 24
Peak memory 197432 kb
Host smart-c07c1193-a340-4e1f-8d2f-dc419a91283a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591521558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2591521558
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2316585984
Short name T842
Test name
Test status
Simulation time 17907424655 ps
CPU time 16.69 seconds
Started Feb 21 03:48:12 PM PST 24
Finished Feb 21 03:48:29 PM PST 24
Peak memory 199188 kb
Host smart-0fd36552-3f8c-4c64-a786-a0ad754abde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316585984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2316585984
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.224303712
Short name T998
Test name
Test status
Simulation time 82915301783 ps
CPU time 57.96 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:49:34 PM PST 24
Peak memory 195392 kb
Host smart-21fa9f38-5e76-4e73-aea8-9ce7adcde372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224303712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.224303712
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.4185534650
Short name T98
Test name
Test status
Simulation time 152950599 ps
CPU time 0.77 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:07 PM PST 24
Peak memory 217164 kb
Host smart-49765505-7db7-4754-89dc-e15ea5da76d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185534650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4185534650
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2555468360
Short name T480
Test name
Test status
Simulation time 672673524 ps
CPU time 2.29 seconds
Started Feb 21 03:48:00 PM PST 24
Finished Feb 21 03:48:04 PM PST 24
Peak memory 198484 kb
Host smart-12b4f730-6863-4451-9eeb-72919b873b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555468360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2555468360
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1250780994
Short name T682
Test name
Test status
Simulation time 248626393513 ps
CPU time 674.96 seconds
Started Feb 21 03:48:17 PM PST 24
Finished Feb 21 03:59:33 PM PST 24
Peak memory 208360 kb
Host smart-3b64b970-2e47-4a60-a154-62c03e69523c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250780994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1250780994
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2964265495
Short name T856
Test name
Test status
Simulation time 171271251216 ps
CPU time 672.44 seconds
Started Feb 21 03:48:04 PM PST 24
Finished Feb 21 03:59:16 PM PST 24
Peak memory 216204 kb
Host smart-23af62d0-83aa-430e-8bce-246b9ae8d554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964265495 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2964265495
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3662041496
Short name T53
Test name
Test status
Simulation time 3220437399 ps
CPU time 1.45 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 03:48:33 PM PST 24
Peak memory 198652 kb
Host smart-31d8b661-4034-4dbd-a492-6807f5b6fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662041496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3662041496
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1007656622
Short name T1058
Test name
Test status
Simulation time 57650977770 ps
CPU time 61.24 seconds
Started Feb 21 03:47:54 PM PST 24
Finished Feb 21 03:48:55 PM PST 24
Peak memory 199636 kb
Host smart-745cd246-c5ed-4e4d-a339-62ada1873c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007656622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1007656622
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.414194860
Short name T1036
Test name
Test status
Simulation time 52085506 ps
CPU time 0.56 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:50:47 PM PST 24
Peak memory 195128 kb
Host smart-84275e1e-311f-4397-a9bb-6846abc8eeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414194860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.414194860
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3028578975
Short name T926
Test name
Test status
Simulation time 60495136173 ps
CPU time 27.79 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:50:53 PM PST 24
Peak memory 199596 kb
Host smart-5ce5aaf0-5019-4073-89a2-fee90cbf6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028578975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3028578975
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.111902539
Short name T48
Test name
Test status
Simulation time 193704914303 ps
CPU time 290.43 seconds
Started Feb 21 03:50:35 PM PST 24
Finished Feb 21 03:55:27 PM PST 24
Peak memory 199620 kb
Host smart-cb5d15dd-6ebe-4c41-b835-9169daf6ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111902539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.111902539
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3632277935
Short name T131
Test name
Test status
Simulation time 36749598307 ps
CPU time 52.27 seconds
Started Feb 21 03:50:33 PM PST 24
Finished Feb 21 03:51:25 PM PST 24
Peak memory 199620 kb
Host smart-0a26ec4f-0754-48c7-b1c6-bca6590a4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632277935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3632277935
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2659401680
Short name T825
Test name
Test status
Simulation time 92774675691 ps
CPU time 255.04 seconds
Started Feb 21 03:50:32 PM PST 24
Finished Feb 21 03:54:47 PM PST 24
Peak memory 199672 kb
Host smart-2c205b66-9ad2-43bc-b2f2-c979cd33ab28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659401680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2659401680
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2312961259
Short name T461
Test name
Test status
Simulation time 995973444 ps
CPU time 1.2 seconds
Started Feb 21 03:50:35 PM PST 24
Finished Feb 21 03:50:37 PM PST 24
Peak memory 196520 kb
Host smart-8a236dbd-e89b-42ce-8c3a-b01c788021cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312961259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2312961259
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3256578982
Short name T642
Test name
Test status
Simulation time 42859291502 ps
CPU time 22.26 seconds
Started Feb 21 03:50:31 PM PST 24
Finished Feb 21 03:50:53 PM PST 24
Peak memory 195920 kb
Host smart-dd4abdf9-a821-4d9c-982b-6b4068ec422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256578982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3256578982
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1244449795
Short name T487
Test name
Test status
Simulation time 17334386626 ps
CPU time 93.05 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:52:30 PM PST 24
Peak memory 199748 kb
Host smart-e4a55cbd-9b2b-4715-8a94-cc8c2c463595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244449795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1244449795
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.524358410
Short name T286
Test name
Test status
Simulation time 42883018396 ps
CPU time 80.49 seconds
Started Feb 21 03:50:33 PM PST 24
Finished Feb 21 03:51:54 PM PST 24
Peak memory 199628 kb
Host smart-43d53dd2-404e-42b0-8e95-bc4e05d5a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524358410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.524358410
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4225860683
Short name T908
Test name
Test status
Simulation time 4711751324 ps
CPU time 2.42 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:50:28 PM PST 24
Peak memory 195476 kb
Host smart-936ecdbb-54a6-4003-996f-1d00b8f673bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225860683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4225860683
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1684449065
Short name T1011
Test name
Test status
Simulation time 5334401243 ps
CPU time 10.4 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:50:36 PM PST 24
Peak memory 198420 kb
Host smart-810d07d4-49ef-421d-ab46-b2f9b7f55269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684449065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1684449065
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3330324587
Short name T752
Test name
Test status
Simulation time 708335092 ps
CPU time 3.55 seconds
Started Feb 21 03:50:25 PM PST 24
Finished Feb 21 03:50:29 PM PST 24
Peak memory 198432 kb
Host smart-36ae9c24-278f-4f41-a098-bcf1d7d0a646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330324587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3330324587
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4172427943
Short name T403
Test name
Test status
Simulation time 133589529679 ps
CPU time 37.91 seconds
Started Feb 21 03:50:31 PM PST 24
Finished Feb 21 03:51:09 PM PST 24
Peak memory 199736 kb
Host smart-db0da784-2219-49ca-baab-dbcde33a9bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172427943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4172427943
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2018800922
Short name T977
Test name
Test status
Simulation time 50888759 ps
CPU time 0.55 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:50:48 PM PST 24
Peak memory 195124 kb
Host smart-e73856a9-1c56-4045-ab6c-995dc7f86197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018800922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2018800922
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.260277729
Short name T227
Test name
Test status
Simulation time 132168025198 ps
CPU time 218.06 seconds
Started Feb 21 03:50:50 PM PST 24
Finished Feb 21 03:54:29 PM PST 24
Peak memory 199636 kb
Host smart-4ce2a97d-2ba3-4515-8054-ae72cafc6517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260277729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.260277729
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.787847708
Short name T106
Test name
Test status
Simulation time 132156346358 ps
CPU time 46.62 seconds
Started Feb 21 03:51:00 PM PST 24
Finished Feb 21 03:51:47 PM PST 24
Peak memory 198720 kb
Host smart-50351d23-6282-4407-98dd-75b09b3f7317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787847708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.787847708
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.883508006
Short name T523
Test name
Test status
Simulation time 27463243099 ps
CPU time 14.6 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:51:12 PM PST 24
Peak memory 199444 kb
Host smart-68157f06-d088-498d-a708-8d58f11885d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883508006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.883508006
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.710199501
Short name T172
Test name
Test status
Simulation time 52646628815 ps
CPU time 39.81 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:51:26 PM PST 24
Peak memory 199680 kb
Host smart-161a84e2-a264-48f8-bee5-378de99dbc90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710199501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.710199501
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.36906629
Short name T849
Test name
Test status
Simulation time 48079481279 ps
CPU time 343.15 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:56:27 PM PST 24
Peak memory 199636 kb
Host smart-0c1c0190-2d72-45b6-85e2-300bacd185be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36906629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.36906629
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.506116968
Short name T628
Test name
Test status
Simulation time 4598100026 ps
CPU time 8.12 seconds
Started Feb 21 03:50:36 PM PST 24
Finished Feb 21 03:50:45 PM PST 24
Peak memory 196700 kb
Host smart-9cf86235-a0c6-4930-b9a5-fbd7a51a6bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506116968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.506116968
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2721367250
Short name T797
Test name
Test status
Simulation time 156608228127 ps
CPU time 84.31 seconds
Started Feb 21 03:50:50 PM PST 24
Finished Feb 21 03:52:16 PM PST 24
Peak memory 207872 kb
Host smart-75aef330-5deb-49c8-b94d-e7be142ebd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721367250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2721367250
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3971487381
Short name T125
Test name
Test status
Simulation time 5853181570 ps
CPU time 61.16 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:51:58 PM PST 24
Peak memory 199648 kb
Host smart-5a679abd-85c5-48cc-9f88-f44d254199e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971487381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3971487381
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1045197413
Short name T795
Test name
Test status
Simulation time 367740998 ps
CPU time 4.72 seconds
Started Feb 21 03:50:35 PM PST 24
Finished Feb 21 03:50:40 PM PST 24
Peak memory 197944 kb
Host smart-03e9b56b-a4b4-4e59-8a33-985c14492156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045197413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1045197413
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1838071449
Short name T705
Test name
Test status
Simulation time 314341505171 ps
CPU time 225.21 seconds
Started Feb 21 03:50:56 PM PST 24
Finished Feb 21 03:54:41 PM PST 24
Peak memory 199624 kb
Host smart-0ca5b473-7b79-43cf-8fd9-091052e49073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838071449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1838071449
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.700048473
Short name T970
Test name
Test status
Simulation time 3463364292 ps
CPU time 3.12 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:50:46 PM PST 24
Peak memory 195364 kb
Host smart-3727b194-be9e-4d96-ad8d-5409d295a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700048473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.700048473
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.740681436
Short name T436
Test name
Test status
Simulation time 864947822 ps
CPU time 2.04 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:50:54 PM PST 24
Peak memory 199024 kb
Host smart-3698f25a-eb4b-448c-bfa7-68e8a04ec414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740681436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.740681436
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1394595157
Short name T859
Test name
Test status
Simulation time 118234416387 ps
CPU time 1233.91 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 04:11:18 PM PST 24
Peak memory 199748 kb
Host smart-73b8bf03-c38a-4735-8a93-80645d7762a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394595157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1394595157
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.700791370
Short name T658
Test name
Test status
Simulation time 6743970894 ps
CPU time 8.38 seconds
Started Feb 21 03:51:00 PM PST 24
Finished Feb 21 03:51:09 PM PST 24
Peak memory 198892 kb
Host smart-bfe9518e-5566-4417-9ad6-21542c38ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700791370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.700791370
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2385679442
Short name T611
Test name
Test status
Simulation time 98595161283 ps
CPU time 163.46 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:53:28 PM PST 24
Peak memory 199688 kb
Host smart-ec6f689b-c8f3-4652-bac9-9975547a9f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385679442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2385679442
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.945110380
Short name T647
Test name
Test status
Simulation time 16247919 ps
CPU time 0.54 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:50:46 PM PST 24
Peak memory 194164 kb
Host smart-089193a4-6b6a-4ac9-9d5a-fa3d57877b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945110380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.945110380
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2710501075
Short name T831
Test name
Test status
Simulation time 110165016816 ps
CPU time 234.36 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:54:41 PM PST 24
Peak memory 199748 kb
Host smart-fdeda5dc-3f21-4c0a-a00d-9b1d1a474b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710501075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2710501075
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.365215622
Short name T621
Test name
Test status
Simulation time 90688987597 ps
CPU time 128.13 seconds
Started Feb 21 03:50:49 PM PST 24
Finished Feb 21 03:52:57 PM PST 24
Peak memory 199384 kb
Host smart-79c00489-e9b7-4a96-a7c0-326c71a5fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365215622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.365215622
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.729709707
Short name T1048
Test name
Test status
Simulation time 197876229496 ps
CPU time 302.03 seconds
Started Feb 21 03:50:50 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 198848 kb
Host smart-633428cc-c319-4026-86d6-2520b5360ea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729709707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.729709707
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.615959478
Short name T677
Test name
Test status
Simulation time 121259749466 ps
CPU time 531.2 seconds
Started Feb 21 03:50:42 PM PST 24
Finished Feb 21 03:59:34 PM PST 24
Peak memory 199664 kb
Host smart-66966336-3a20-4adf-ab74-5571051d7e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615959478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.615959478
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1125769547
Short name T806
Test name
Test status
Simulation time 9477506104 ps
CPU time 20.27 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:21 PM PST 24
Peak memory 199080 kb
Host smart-51819d86-68c7-453d-bd1a-0ad6c81c4836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125769547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1125769547
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.266140529
Short name T712
Test name
Test status
Simulation time 174656807135 ps
CPU time 147.92 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:53:11 PM PST 24
Peak memory 207924 kb
Host smart-18db7b9f-e82c-4460-831a-e1199cc4a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266140529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.266140529
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4233057738
Short name T44
Test name
Test status
Simulation time 19419253055 ps
CPU time 808.06 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 04:04:15 PM PST 24
Peak memory 199624 kb
Host smart-2552ef43-80ec-414d-afd0-6c625b2b1517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233057738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4233057738
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3461617296
Short name T560
Test name
Test status
Simulation time 1464086373 ps
CPU time 14.61 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:50:58 PM PST 24
Peak memory 197368 kb
Host smart-320caa33-7650-4198-8bf7-d9493a64474f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461617296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3461617296
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.379863136
Short name T716
Test name
Test status
Simulation time 132607570749 ps
CPU time 60.61 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:51:47 PM PST 24
Peak memory 199608 kb
Host smart-323ba13a-e9be-4365-a5e1-0df3b1e696ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379863136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.379863136
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.530579224
Short name T479
Test name
Test status
Simulation time 2895149819 ps
CPU time 3.1 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:50:55 PM PST 24
Peak memory 195120 kb
Host smart-3b802a38-1105-490e-812e-d4d7e8a96a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530579224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.530579224
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.296851881
Short name T888
Test name
Test status
Simulation time 715960044 ps
CPU time 2.82 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:50:48 PM PST 24
Peak memory 198060 kb
Host smart-a333efa6-3381-4e41-b60d-dae005a3a190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296851881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.296851881
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.63938485
Short name T939
Test name
Test status
Simulation time 533996517902 ps
CPU time 420.79 seconds
Started Feb 21 03:50:40 PM PST 24
Finished Feb 21 03:57:42 PM PST 24
Peak memory 200040 kb
Host smart-483ffb0b-52e8-4db6-9b5e-5017538f13f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63938485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.63938485
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.20430534
Short name T467
Test name
Test status
Simulation time 6998752997 ps
CPU time 20.11 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:51:06 PM PST 24
Peak memory 199108 kb
Host smart-33e474f9-93af-4a1b-8149-a61aa8459a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20430534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.20430534
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2226118462
Short name T1072
Test name
Test status
Simulation time 44005870254 ps
CPU time 56.92 seconds
Started Feb 21 03:50:50 PM PST 24
Finished Feb 21 03:51:48 PM PST 24
Peak memory 199664 kb
Host smart-7d797ecd-7115-4ea3-b3da-7448063ac15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226118462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2226118462
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3750339393
Short name T865
Test name
Test status
Simulation time 39542167 ps
CPU time 0.54 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:50:45 PM PST 24
Peak memory 195140 kb
Host smart-8f0a8d6b-537c-4657-9fd7-573eb0acaa3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750339393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3750339393
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.522906811
Short name T56
Test name
Test status
Simulation time 117929975623 ps
CPU time 51.19 seconds
Started Feb 21 03:50:39 PM PST 24
Finished Feb 21 03:51:30 PM PST 24
Peak memory 199640 kb
Host smart-a7d1ef71-e5f1-48c1-b723-94747cb3ec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522906811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.522906811
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.486913560
Short name T359
Test name
Test status
Simulation time 48759552819 ps
CPU time 33.24 seconds
Started Feb 21 03:50:56 PM PST 24
Finished Feb 21 03:51:29 PM PST 24
Peak memory 199640 kb
Host smart-8685cb6e-ddee-4961-8bbc-00cb6a9acca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486913560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.486913560
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2079197485
Short name T328
Test name
Test status
Simulation time 111348895924 ps
CPU time 44.35 seconds
Started Feb 21 03:50:41 PM PST 24
Finished Feb 21 03:51:26 PM PST 24
Peak memory 199688 kb
Host smart-7eda1b51-8a26-4623-95bf-af4e2042f394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079197485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2079197485
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1901202023
Short name T446
Test name
Test status
Simulation time 253404172657 ps
CPU time 41.36 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:51:25 PM PST 24
Peak memory 199492 kb
Host smart-96cd3e49-377b-466c-8dcc-b9a95caab786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901202023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1901202023
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1795691775
Short name T920
Test name
Test status
Simulation time 91161789818 ps
CPU time 676.91 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 04:02:00 PM PST 24
Peak memory 199624 kb
Host smart-12782cff-00ca-4165-9a75-98cead0c5d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795691775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1795691775
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2154451470
Short name T924
Test name
Test status
Simulation time 3083457265 ps
CPU time 6.7 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:50:52 PM PST 24
Peak memory 198864 kb
Host smart-51aae032-9b60-4660-9a88-efa9b6a555fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154451470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2154451470
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3756937824
Short name T1034
Test name
Test status
Simulation time 89159537984 ps
CPU time 43.26 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:51:28 PM PST 24
Peak memory 199720 kb
Host smart-57e8f152-582c-41cd-a42a-c9a8eedaf311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756937824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3756937824
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1885185997
Short name T46
Test name
Test status
Simulation time 11251806616 ps
CPU time 549.22 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:59:53 PM PST 24
Peak memory 199624 kb
Host smart-6de4ebda-f5ed-412f-9cb1-23587ad0fc93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885185997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1885185997
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.891354955
Short name T465
Test name
Test status
Simulation time 4173221598 ps
CPU time 8.82 seconds
Started Feb 21 03:50:49 PM PST 24
Finished Feb 21 03:50:58 PM PST 24
Peak memory 198252 kb
Host smart-d02ca21a-6990-4dfd-981b-0c6e4ceea630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891354955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.891354955
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3596271777
Short name T802
Test name
Test status
Simulation time 38583667733 ps
CPU time 112.81 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:52:36 PM PST 24
Peak memory 199652 kb
Host smart-35cf70c5-eece-4653-952b-05f614fb4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596271777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3596271777
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2756898380
Short name T766
Test name
Test status
Simulation time 36690650322 ps
CPU time 51.66 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 195120 kb
Host smart-9f58fe1e-f369-4648-ae3c-0d1f7a91ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756898380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2756898380
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1216758336
Short name T430
Test name
Test status
Simulation time 110387811 ps
CPU time 0.81 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:50:44 PM PST 24
Peak memory 196376 kb
Host smart-01dab39e-de4a-468e-8ad7-f5a0032f1487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216758336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1216758336
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3156533677
Short name T1035
Test name
Test status
Simulation time 438584888616 ps
CPU time 1054.79 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 04:08:18 PM PST 24
Peak memory 199660 kb
Host smart-77b48fe0-3856-433f-a997-2105b1bcfd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156533677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3156533677
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3727998729
Short name T843
Test name
Test status
Simulation time 7205889746 ps
CPU time 15.97 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:50:59 PM PST 24
Peak memory 199212 kb
Host smart-fa677cc0-7851-4989-a7a2-48d709d0523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727998729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3727998729
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1498620684
Short name T725
Test name
Test status
Simulation time 339731189301 ps
CPU time 34.72 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:51:19 PM PST 24
Peak memory 199660 kb
Host smart-0aad0dff-9b58-46b7-a17f-02d3dcc7ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498620684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1498620684
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1484611185
Short name T936
Test name
Test status
Simulation time 10935905 ps
CPU time 0.55 seconds
Started Feb 21 03:51:00 PM PST 24
Finished Feb 21 03:51:01 PM PST 24
Peak memory 194108 kb
Host smart-56e7e4f8-f9b5-496b-ab1a-b66b2f565c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484611185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1484611185
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3676001832
Short name T484
Test name
Test status
Simulation time 69841668737 ps
CPU time 108.24 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:52:35 PM PST 24
Peak memory 199656 kb
Host smart-8c5e1605-b175-41c3-a7e8-90e85111f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676001832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3676001832
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3315639639
Short name T757
Test name
Test status
Simulation time 39403731439 ps
CPU time 40.6 seconds
Started Feb 21 03:50:42 PM PST 24
Finished Feb 21 03:51:23 PM PST 24
Peak memory 199656 kb
Host smart-35ef6c6e-f25e-4d71-a685-b7b46c5c1983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315639639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3315639639
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2602661685
Short name T134
Test name
Test status
Simulation time 90388127586 ps
CPU time 89.8 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 03:52:15 PM PST 24
Peak memory 199752 kb
Host smart-edb9d8ee-6507-4f0e-9bad-6a2a17e98c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602661685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2602661685
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1107561567
Short name T863
Test name
Test status
Simulation time 265434607617 ps
CPU time 45.54 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:51:43 PM PST 24
Peak memory 198984 kb
Host smart-85542cad-987f-4a72-83d2-248224b7b518
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107561567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1107561567
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1509815887
Short name T857
Test name
Test status
Simulation time 168458158536 ps
CPU time 945.08 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 04:06:44 PM PST 24
Peak memory 199500 kb
Host smart-498d9a69-45ef-4d52-be0b-d17de7b838f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509815887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1509815887
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2788201662
Short name T858
Test name
Test status
Simulation time 3454225256 ps
CPU time 9.77 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:50:57 PM PST 24
Peak memory 198616 kb
Host smart-bbe360a8-47c1-413e-bf04-e6117e5df68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788201662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2788201662
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.502820675
Short name T518
Test name
Test status
Simulation time 184682504489 ps
CPU time 66.59 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:51:49 PM PST 24
Peak memory 199896 kb
Host smart-60f3507f-3a2a-456a-821c-6b2ed08dea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502820675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.502820675
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2199664940
Short name T665
Test name
Test status
Simulation time 14450185642 ps
CPU time 808.31 seconds
Started Feb 21 03:50:44 PM PST 24
Finished Feb 21 04:04:14 PM PST 24
Peak memory 199728 kb
Host smart-332d9c31-5378-4afe-aee8-eb1d0b7536f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199664940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2199664940
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2008937134
Short name T1008
Test name
Test status
Simulation time 5172273689 ps
CPU time 47.68 seconds
Started Feb 21 03:50:41 PM PST 24
Finished Feb 21 03:51:29 PM PST 24
Peak memory 198564 kb
Host smart-5a676171-9a95-4585-a205-e27d2198c83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008937134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2008937134
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3494918151
Short name T778
Test name
Test status
Simulation time 20803868125 ps
CPU time 37.19 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:51:37 PM PST 24
Peak memory 199084 kb
Host smart-b9cb5aee-8a60-4848-80da-e299a7e39781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494918151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3494918151
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.349233602
Short name T586
Test name
Test status
Simulation time 1594071683 ps
CPU time 1.82 seconds
Started Feb 21 03:50:49 PM PST 24
Finished Feb 21 03:50:51 PM PST 24
Peak memory 195012 kb
Host smart-dddfc943-a8c9-4a59-be90-5153be4b547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349233602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.349233602
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2952425629
Short name T583
Test name
Test status
Simulation time 5544686154 ps
CPU time 8.99 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:51:07 PM PST 24
Peak memory 199008 kb
Host smart-ebfc2991-bb99-4ab0-a5a9-08012e6694f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952425629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2952425629
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.721053090
Short name T38
Test name
Test status
Simulation time 27799481857 ps
CPU time 287.69 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:55:45 PM PST 24
Peak memory 216392 kb
Host smart-5e77b8b4-25d9-4ce7-95da-56ad51aae1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721053090 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.721053090
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1275951863
Short name T711
Test name
Test status
Simulation time 1985884347 ps
CPU time 2.61 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:04 PM PST 24
Peak memory 198088 kb
Host smart-7ac37d13-cf75-467d-a67d-60ad860a7492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275951863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1275951863
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1904763304
Short name T565
Test name
Test status
Simulation time 30814495270 ps
CPU time 49.7 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:51 PM PST 24
Peak memory 199656 kb
Host smart-0ed309af-3a65-4300-9353-2c41a15abff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904763304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1904763304
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2791482536
Short name T874
Test name
Test status
Simulation time 12443346 ps
CPU time 0.62 seconds
Started Feb 21 03:51:03 PM PST 24
Finished Feb 21 03:51:04 PM PST 24
Peak memory 195148 kb
Host smart-067b1560-9a24-4489-8ff6-d3eaa832f1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791482536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2791482536
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1180427810
Short name T1024
Test name
Test status
Simulation time 173880697456 ps
CPU time 66.54 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:51:59 PM PST 24
Peak memory 199464 kb
Host smart-c56ef34b-f76d-4bbe-a609-f36c97fe9876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180427810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1180427810
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.814616201
Short name T348
Test name
Test status
Simulation time 37464715720 ps
CPU time 61.69 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:51:54 PM PST 24
Peak memory 199580 kb
Host smart-9f50f53e-d184-4e72-adee-d42710da9b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814616201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.814616201
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1996200176
Short name T336
Test name
Test status
Simulation time 66124792959 ps
CPU time 41.46 seconds
Started Feb 21 03:50:57 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 199660 kb
Host smart-05c460bf-e0d2-4a67-9b89-f3c5614a3379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996200176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1996200176
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3148346822
Short name T905
Test name
Test status
Simulation time 27124562438 ps
CPU time 24.66 seconds
Started Feb 21 03:50:47 PM PST 24
Finished Feb 21 03:51:12 PM PST 24
Peak memory 199112 kb
Host smart-e4df8fe7-857b-4596-a65b-58022d4643b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148346822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3148346822
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3070183511
Short name T847
Test name
Test status
Simulation time 99926306083 ps
CPU time 251.1 seconds
Started Feb 21 03:50:43 PM PST 24
Finished Feb 21 03:54:55 PM PST 24
Peak memory 199724 kb
Host smart-8bd767d7-595e-49ab-a9b5-886c789740f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070183511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3070183511
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2650255002
Short name T964
Test name
Test status
Simulation time 4308421491 ps
CPU time 2.32 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:51:02 PM PST 24
Peak memory 196828 kb
Host smart-ac2c92c9-16dd-4595-8850-54b69409295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650255002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2650255002
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3849900027
Short name T635
Test name
Test status
Simulation time 32839224382 ps
CPU time 30.4 seconds
Started Feb 21 03:50:51 PM PST 24
Finished Feb 21 03:51:22 PM PST 24
Peak memory 197932 kb
Host smart-6d15b17b-78aa-46ff-b0a0-75f4571f89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849900027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3849900027
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1318806559
Short name T405
Test name
Test status
Simulation time 18434904847 ps
CPU time 486.56 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:59:06 PM PST 24
Peak memory 199404 kb
Host smart-0463ac32-05cf-480c-8791-faf33f9fa890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318806559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1318806559
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1983078527
Short name T995
Test name
Test status
Simulation time 4118478255 ps
CPU time 8.17 seconds
Started Feb 21 03:50:45 PM PST 24
Finished Feb 21 03:50:55 PM PST 24
Peak memory 198060 kb
Host smart-bcca9b55-c694-4e1f-9939-4c6c064eafa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983078527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1983078527
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3797047022
Short name T971
Test name
Test status
Simulation time 244385275647 ps
CPU time 106.32 seconds
Started Feb 21 03:50:42 PM PST 24
Finished Feb 21 03:52:28 PM PST 24
Peak memory 199636 kb
Host smart-0951d8ae-1911-4103-8503-60901b4158ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797047022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3797047022
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2960283512
Short name T656
Test name
Test status
Simulation time 4284138943 ps
CPU time 7.48 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:51:07 PM PST 24
Peak memory 195392 kb
Host smart-9356ce60-2b70-486b-b341-1323d062afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960283512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2960283512
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3068041660
Short name T904
Test name
Test status
Simulation time 5545324385 ps
CPU time 15.12 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:51:14 PM PST 24
Peak memory 198360 kb
Host smart-eab900e2-577e-4ca6-a05b-0fc18d50f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068041660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3068041660
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1052066658
Short name T765
Test name
Test status
Simulation time 975274118 ps
CPU time 3.44 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:50:51 PM PST 24
Peak memory 198064 kb
Host smart-59e3bb53-134e-4f90-bf91-bb75c9fc0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052066658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1052066658
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1822796063
Short name T553
Test name
Test status
Simulation time 8274921957 ps
CPU time 12.96 seconds
Started Feb 21 03:50:46 PM PST 24
Finished Feb 21 03:50:59 PM PST 24
Peak memory 195856 kb
Host smart-71f878df-53d3-427f-9222-bb6200aa2c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822796063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1822796063
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3447927284
Short name T634
Test name
Test status
Simulation time 17641894 ps
CPU time 0.59 seconds
Started Feb 21 03:51:03 PM PST 24
Finished Feb 21 03:51:04 PM PST 24
Peak memory 195144 kb
Host smart-e659ad35-c870-4287-a1b7-22ef13be15cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447927284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3447927284
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1824091661
Short name T610
Test name
Test status
Simulation time 155622138779 ps
CPU time 124.15 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:53:03 PM PST 24
Peak memory 199612 kb
Host smart-d6e4640e-5806-421f-b88b-ad62a4e2818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824091661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1824091661
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.87642595
Short name T932
Test name
Test status
Simulation time 131657698983 ps
CPU time 291.77 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:55:51 PM PST 24
Peak memory 199652 kb
Host smart-65065c87-c558-4728-ae3b-6b555b39f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87642595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.87642595
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.169498183
Short name T242
Test name
Test status
Simulation time 193957526276 ps
CPU time 36.67 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 199776 kb
Host smart-7b18e811-6053-41c1-a00c-bc38f3616e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169498183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.169498183
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1193394730
Short name T815
Test name
Test status
Simulation time 73075725022 ps
CPU time 130.87 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:53:12 PM PST 24
Peak memory 199716 kb
Host smart-a58fff43-c9d3-48e7-a510-c84bcfcb4910
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193394730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1193394730
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2713315420
Short name T891
Test name
Test status
Simulation time 104195165284 ps
CPU time 259.67 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:55:19 PM PST 24
Peak memory 199632 kb
Host smart-bdeac2b8-b401-45d1-aee8-39bae8d20930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713315420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2713315420
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4251990327
Short name T769
Test name
Test status
Simulation time 3649554732 ps
CPU time 2.38 seconds
Started Feb 21 03:50:59 PM PST 24
Finished Feb 21 03:51:02 PM PST 24
Peak memory 198368 kb
Host smart-be82514c-0c1c-4115-81cb-89a53d3de119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251990327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4251990327
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1404025128
Short name T841
Test name
Test status
Simulation time 121150988480 ps
CPU time 64.09 seconds
Started Feb 21 03:50:55 PM PST 24
Finished Feb 21 03:51:59 PM PST 24
Peak memory 199664 kb
Host smart-1d556218-aa3d-4aab-ac34-3af8ad3ecf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404025128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1404025128
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.720063530
Short name T1041
Test name
Test status
Simulation time 34003668460 ps
CPU time 387.34 seconds
Started Feb 21 03:51:03 PM PST 24
Finished Feb 21 03:57:31 PM PST 24
Peak memory 199660 kb
Host smart-b9d901cd-d138-4b11-830e-6543daf8737b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720063530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.720063530
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2838524775
Short name T1005
Test name
Test status
Simulation time 761351372 ps
CPU time 5.16 seconds
Started Feb 21 03:50:56 PM PST 24
Finished Feb 21 03:51:01 PM PST 24
Peak memory 197840 kb
Host smart-4e324dc5-f1c8-4cae-b8cb-310674d333ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838524775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2838524775
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1211324126
Short name T489
Test name
Test status
Simulation time 50131246400 ps
CPU time 22.12 seconds
Started Feb 21 03:51:00 PM PST 24
Finished Feb 21 03:51:22 PM PST 24
Peak memory 198228 kb
Host smart-942e1d47-15f4-4204-8fea-0e8aa4a53918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211324126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1211324126
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1867855107
Short name T493
Test name
Test status
Simulation time 7260615043 ps
CPU time 10.51 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:12 PM PST 24
Peak memory 195408 kb
Host smart-ee304a6e-692f-4ee9-8fd1-e906dc6984c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867855107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1867855107
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4218804095
Short name T632
Test name
Test status
Simulation time 271464681 ps
CPU time 1.17 seconds
Started Feb 21 03:51:01 PM PST 24
Finished Feb 21 03:51:03 PM PST 24
Peak memory 197820 kb
Host smart-4e46d89c-080c-43dc-a359-24b2ffdc0944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218804095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4218804095
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3713868159
Short name T598
Test name
Test status
Simulation time 7179470365 ps
CPU time 1.73 seconds
Started Feb 21 03:50:55 PM PST 24
Finished Feb 21 03:50:57 PM PST 24
Peak memory 198168 kb
Host smart-75281a70-8e3e-46ec-be79-66a271dfa567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713868159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3713868159
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1198818826
Short name T481
Test name
Test status
Simulation time 96753538361 ps
CPU time 188.85 seconds
Started Feb 21 03:51:00 PM PST 24
Finished Feb 21 03:54:09 PM PST 24
Peak memory 199624 kb
Host smart-4b3f4c98-d25e-466d-869e-ed074b7b4ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198818826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1198818826
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.578169252
Short name T29
Test name
Test status
Simulation time 10698478 ps
CPU time 0.6 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 03:51:11 PM PST 24
Peak memory 195108 kb
Host smart-5d8a02de-96ee-4f56-a7cd-91c8ba074645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578169252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.578169252
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2380365194
Short name T869
Test name
Test status
Simulation time 25712253291 ps
CPU time 39.77 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 199512 kb
Host smart-e71423c6-7d14-4e24-9afe-a07ac753ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380365194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2380365194
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2058824890
Short name T963
Test name
Test status
Simulation time 224633724211 ps
CPU time 91.55 seconds
Started Feb 21 03:51:04 PM PST 24
Finished Feb 21 03:52:36 PM PST 24
Peak memory 199540 kb
Host smart-d4f8263e-d8b9-4e27-a0ba-be46b89edbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058824890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2058824890
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3555650984
Short name T6
Test name
Test status
Simulation time 108568391918 ps
CPU time 161.3 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:53:39 PM PST 24
Peak memory 199696 kb
Host smart-a64518de-b9da-41b4-ac81-7fcbc6e07211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555650984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3555650984
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2532029730
Short name T412
Test name
Test status
Simulation time 157850807204 ps
CPU time 884.59 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 04:05:55 PM PST 24
Peak memory 199628 kb
Host smart-b288b6af-fcb0-4e66-90ca-eaa10842e390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532029730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2532029730
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2928896183
Short name T925
Test name
Test status
Simulation time 7321315709 ps
CPU time 10.78 seconds
Started Feb 21 03:51:11 PM PST 24
Finished Feb 21 03:51:22 PM PST 24
Peak memory 198932 kb
Host smart-46bfbb9f-31c9-463e-9bde-412f8abd3f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928896183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2928896183
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1310798402
Short name T420
Test name
Test status
Simulation time 128279641555 ps
CPU time 290.11 seconds
Started Feb 21 03:51:04 PM PST 24
Finished Feb 21 03:55:54 PM PST 24
Peak memory 208028 kb
Host smart-c363f86e-6ca2-412b-b7c4-541ffb6ce799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310798402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1310798402
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3101569020
Short name T175
Test name
Test status
Simulation time 19765801529 ps
CPU time 964.32 seconds
Started Feb 21 03:51:16 PM PST 24
Finished Feb 21 04:07:21 PM PST 24
Peak memory 199748 kb
Host smart-c0f51c56-d6a7-4e9b-85e0-d695b8ff2a1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101569020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3101569020
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3144951240
Short name T758
Test name
Test status
Simulation time 2493097775 ps
CPU time 7.27 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:51:05 PM PST 24
Peak memory 197772 kb
Host smart-bf817e8a-f643-4903-b1dd-d414b81cd4dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144951240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3144951240
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1585686637
Short name T827
Test name
Test status
Simulation time 75889039197 ps
CPU time 70.23 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:52:34 PM PST 24
Peak memory 199516 kb
Host smart-f00bb435-d5a4-4884-ace1-f321172eb5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585686637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1585686637
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4262982576
Short name T991
Test name
Test status
Simulation time 441957917 ps
CPU time 1.3 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:51:00 PM PST 24
Peak memory 195060 kb
Host smart-001262d5-2a21-4a8b-ab26-b37485442cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262982576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4262982576
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.307811407
Short name T483
Test name
Test status
Simulation time 570041848 ps
CPU time 1.23 seconds
Started Feb 21 03:51:04 PM PST 24
Finished Feb 21 03:51:05 PM PST 24
Peak memory 197764 kb
Host smart-cb9af210-5f39-4fc0-a051-c01e3a5c8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307811407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.307811407
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1097825527
Short name T739
Test name
Test status
Simulation time 90630306224 ps
CPU time 61.46 seconds
Started Feb 21 03:51:09 PM PST 24
Finished Feb 21 03:52:10 PM PST 24
Peak memory 199360 kb
Host smart-fa5550a1-2862-40b7-8236-ce370423e132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097825527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1097825527
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1479445248
Short name T384
Test name
Test status
Simulation time 55156588316 ps
CPU time 77.99 seconds
Started Feb 21 03:51:11 PM PST 24
Finished Feb 21 03:52:29 PM PST 24
Peak memory 210404 kb
Host smart-868ddfcc-7aa8-429c-b592-e7660d1f0b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479445248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1479445248
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1346066966
Short name T900
Test name
Test status
Simulation time 1119844725 ps
CPU time 2.22 seconds
Started Feb 21 03:51:09 PM PST 24
Finished Feb 21 03:51:12 PM PST 24
Peak memory 198072 kb
Host smart-b7350392-d176-413c-90f9-b2f659c30400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346066966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1346066966
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2469981028
Short name T182
Test name
Test status
Simulation time 46472286805 ps
CPU time 70.74 seconds
Started Feb 21 03:50:58 PM PST 24
Finished Feb 21 03:52:09 PM PST 24
Peak memory 199224 kb
Host smart-7641454b-aee7-410f-827b-97e3462d4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469981028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2469981028
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3760117238
Short name T537
Test name
Test status
Simulation time 14680574 ps
CPU time 0.56 seconds
Started Feb 21 03:51:09 PM PST 24
Finished Feb 21 03:51:09 PM PST 24
Peak memory 195132 kb
Host smart-aba7d4fb-94a6-410c-9b27-f97388441dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760117238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3760117238
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2424486508
Short name T367
Test name
Test status
Simulation time 83057882147 ps
CPU time 27.64 seconds
Started Feb 21 03:51:15 PM PST 24
Finished Feb 21 03:51:43 PM PST 24
Peak memory 199672 kb
Host smart-efd7f56d-e259-495d-8e27-84ecf39c210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424486508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2424486508
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.830041093
Short name T347
Test name
Test status
Simulation time 168423728627 ps
CPU time 67.88 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 03:52:18 PM PST 24
Peak memory 199652 kb
Host smart-f31318b6-c392-4297-8999-2953c6d69b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830041093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.830041093
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.436218190
Short name T285
Test name
Test status
Simulation time 18285747440 ps
CPU time 14.22 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:51:38 PM PST 24
Peak memory 198972 kb
Host smart-53c1241f-ec9b-46fc-a499-2abdc3ddbeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436218190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.436218190
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2037116839
Short name T660
Test name
Test status
Simulation time 416680543437 ps
CPU time 658.96 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 04:02:10 PM PST 24
Peak memory 199400 kb
Host smart-0c9db00f-4ebb-4f50-9c8d-fe97caf765c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037116839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2037116839
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1209142069
Short name T505
Test name
Test status
Simulation time 79196724882 ps
CPU time 350.88 seconds
Started Feb 21 03:51:15 PM PST 24
Finished Feb 21 03:57:06 PM PST 24
Peak memory 199504 kb
Host smart-62d5097f-a655-4a88-b95e-0aa6c6ba6d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1209142069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1209142069
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2452087546
Short name T542
Test name
Test status
Simulation time 8200536157 ps
CPU time 8.24 seconds
Started Feb 21 03:51:11 PM PST 24
Finished Feb 21 03:51:20 PM PST 24
Peak memory 196820 kb
Host smart-11e6e7cc-87e2-4370-8de8-a6aba000234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452087546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2452087546
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1065724456
Short name T953
Test name
Test status
Simulation time 11275044833 ps
CPU time 120.66 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 03:53:11 PM PST 24
Peak memory 199624 kb
Host smart-cc0bf4a2-da13-42c9-b987-3dafab9766ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065724456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1065724456
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2435406208
Short name T460
Test name
Test status
Simulation time 1790372611 ps
CPU time 15.5 seconds
Started Feb 21 03:51:19 PM PST 24
Finished Feb 21 03:51:35 PM PST 24
Peak memory 197872 kb
Host smart-e96741b0-4ff7-443f-bb08-e8fcb8b10ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435406208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2435406208
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.433382924
Short name T853
Test name
Test status
Simulation time 88771520325 ps
CPU time 141.78 seconds
Started Feb 21 03:51:20 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 198380 kb
Host smart-a68532d2-78ec-4f0c-936b-7f031900848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433382924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.433382924
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.4060483663
Short name T667
Test name
Test status
Simulation time 5810753126 ps
CPU time 4.74 seconds
Started Feb 21 03:51:18 PM PST 24
Finished Feb 21 03:51:23 PM PST 24
Peak memory 195512 kb
Host smart-31b29a41-589f-4f50-8ae1-297a08757245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060483663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.4060483663
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3861516980
Short name T463
Test name
Test status
Simulation time 444019728 ps
CPU time 1.45 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 03:51:24 PM PST 24
Peak memory 197828 kb
Host smart-5062f457-ccb9-4636-94bc-394385c1947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861516980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3861516980
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3509654652
Short name T490
Test name
Test status
Simulation time 864980276 ps
CPU time 1.61 seconds
Started Feb 21 03:51:20 PM PST 24
Finished Feb 21 03:51:22 PM PST 24
Peak memory 198180 kb
Host smart-0426e16f-51a3-40ef-988d-de359fad9240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509654652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3509654652
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3140868668
Short name T1009
Test name
Test status
Simulation time 37589000904 ps
CPU time 65.74 seconds
Started Feb 21 03:51:15 PM PST 24
Finished Feb 21 03:52:21 PM PST 24
Peak memory 199528 kb
Host smart-a3c4692f-ac03-4f9c-ada6-1c7549d23ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140868668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3140868668
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1237763066
Short name T1066
Test name
Test status
Simulation time 40700244 ps
CPU time 0.54 seconds
Started Feb 21 03:51:20 PM PST 24
Finished Feb 21 03:51:21 PM PST 24
Peak memory 195160 kb
Host smart-fd3a9521-6ca3-4d3d-bec5-1c37dea76d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237763066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1237763066
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2365827801
Short name T275
Test name
Test status
Simulation time 246813974359 ps
CPU time 253.14 seconds
Started Feb 21 03:51:19 PM PST 24
Finished Feb 21 03:55:32 PM PST 24
Peak memory 199708 kb
Host smart-047b7541-465e-465f-a9cd-a5f2763e8e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365827801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2365827801
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4128977821
Short name T102
Test name
Test status
Simulation time 159746912341 ps
CPU time 278 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 03:56:00 PM PST 24
Peak memory 199644 kb
Host smart-d034d1be-17b5-48b2-a4cf-158900069269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128977821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4128977821
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.903573956
Short name T958
Test name
Test status
Simulation time 115445320447 ps
CPU time 19 seconds
Started Feb 21 03:51:13 PM PST 24
Finished Feb 21 03:51:32 PM PST 24
Peak memory 199664 kb
Host smart-dd842f78-22a0-42f6-b6ba-2609b2e54fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903573956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.903573956
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2127647709
Short name T791
Test name
Test status
Simulation time 340666142072 ps
CPU time 147.88 seconds
Started Feb 21 03:51:10 PM PST 24
Finished Feb 21 03:53:38 PM PST 24
Peak memory 196384 kb
Host smart-d3eacceb-c3da-4b9d-b8f4-22803f71dac0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127647709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2127647709
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.122908081
Short name T302
Test name
Test status
Simulation time 210916910006 ps
CPU time 811.97 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 04:04:54 PM PST 24
Peak memory 199656 kb
Host smart-af97697e-ae2f-4003-9a22-27ceefc4c272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122908081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.122908081
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2097735025
Short name T723
Test name
Test status
Simulation time 1295809396 ps
CPU time 1.22 seconds
Started Feb 21 03:51:20 PM PST 24
Finished Feb 21 03:51:22 PM PST 24
Peak memory 195316 kb
Host smart-113203c7-9a56-4c7d-b349-6452ef9e9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097735025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2097735025
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.330003485
Short name T983
Test name
Test status
Simulation time 42713524475 ps
CPU time 174.57 seconds
Started Feb 21 03:51:15 PM PST 24
Finished Feb 21 03:54:10 PM PST 24
Peak memory 199016 kb
Host smart-70ffd6b4-6c7f-4f19-8480-c47f41b5be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330003485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.330003485
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2991545582
Short name T4
Test name
Test status
Simulation time 31604251640 ps
CPU time 427.04 seconds
Started Feb 21 03:51:26 PM PST 24
Finished Feb 21 03:58:33 PM PST 24
Peak memory 199704 kb
Host smart-c536002e-4eb5-487b-8b70-a0478d223b4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991545582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2991545582
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.128336221
Short name T760
Test name
Test status
Simulation time 346051020229 ps
CPU time 730.25 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 04:03:34 PM PST 24
Peak memory 199732 kb
Host smart-e5d5b646-e686-4eda-8040-0fb665712af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128336221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.128336221
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2971667492
Short name T803
Test name
Test status
Simulation time 3036964149 ps
CPU time 1.86 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:51:26 PM PST 24
Peak memory 195000 kb
Host smart-38c3a0fc-8705-4e15-bdf9-8667831f00e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971667492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2971667492
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.680840704
Short name T966
Test name
Test status
Simulation time 6340304266 ps
CPU time 31.04 seconds
Started Feb 21 03:51:11 PM PST 24
Finished Feb 21 03:51:42 PM PST 24
Peak memory 198408 kb
Host smart-ad901b21-5afd-4640-8cb1-5054e427ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680840704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.680840704
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.560182421
Short name T136
Test name
Test status
Simulation time 105787622700 ps
CPU time 164.97 seconds
Started Feb 21 03:51:25 PM PST 24
Finished Feb 21 03:54:10 PM PST 24
Peak memory 208028 kb
Host smart-72b36607-01c1-40bd-b102-702e899cad6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560182421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.560182421
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3569337668
Short name T913
Test name
Test status
Simulation time 1247456528 ps
CPU time 2.15 seconds
Started Feb 21 03:51:22 PM PST 24
Finished Feb 21 03:51:25 PM PST 24
Peak memory 197892 kb
Host smart-33bc6d62-4538-4e17-8adf-b52fee3e8e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569337668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3569337668
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2527884769
Short name T728
Test name
Test status
Simulation time 93135056052 ps
CPU time 78.3 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:52:42 PM PST 24
Peak memory 199536 kb
Host smart-cd01692b-9d9f-4c91-9695-3c39faef3785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527884769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2527884769
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3402582147
Short name T608
Test name
Test status
Simulation time 16594777 ps
CPU time 0.61 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:48:10 PM PST 24
Peak memory 194660 kb
Host smart-0b460cc7-7b4b-49b5-91bd-4be39b98d030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402582147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3402582147
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3960328703
Short name T345
Test name
Test status
Simulation time 77534690953 ps
CPU time 88 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:49:32 PM PST 24
Peak memory 199532 kb
Host smart-7da5f252-8ba7-4ce5-b803-a966a89f768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960328703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3960328703
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1263933221
Short name T1003
Test name
Test status
Simulation time 40071311876 ps
CPU time 16.51 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:22 PM PST 24
Peak memory 199016 kb
Host smart-03c825ca-a00a-4c34-ad5d-de1e9de7d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263933221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1263933221
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.151635992
Short name T177
Test name
Test status
Simulation time 45847838444 ps
CPU time 21.27 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:48:25 PM PST 24
Peak memory 199716 kb
Host smart-bae27bd6-aaf2-43cd-bbe2-474f46d51632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151635992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.151635992
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2993515205
Short name T233
Test name
Test status
Simulation time 457303912906 ps
CPU time 704.9 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:59:49 PM PST 24
Peak memory 199628 kb
Host smart-ebcace24-9cbd-4621-a786-230593bc5b1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993515205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2993515205
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2607484849
Short name T832
Test name
Test status
Simulation time 100308412494 ps
CPU time 552.05 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:57:19 PM PST 24
Peak memory 199676 kb
Host smart-0610d0f9-708b-4a3d-979e-48d4cf975bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607484849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2607484849
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2108360956
Short name T816
Test name
Test status
Simulation time 212909742594 ps
CPU time 115.18 seconds
Started Feb 21 03:48:07 PM PST 24
Finished Feb 21 03:50:03 PM PST 24
Peak memory 208060 kb
Host smart-30ecb917-a1f0-40da-b5ab-9d6d7ca77f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108360956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2108360956
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.4113642475
Short name T885
Test name
Test status
Simulation time 2763202281 ps
CPU time 14.68 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:21 PM PST 24
Peak memory 198084 kb
Host smart-9b634c33-2ad1-4953-974e-4fbf07d6542f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113642475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4113642475
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4176268265
Short name T818
Test name
Test status
Simulation time 64907342774 ps
CPU time 63.94 seconds
Started Feb 21 03:48:02 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 199584 kb
Host smart-ccb3eec6-9b75-4b48-bde3-c2688aa6d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176268265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4176268265
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1645901736
Short name T1071
Test name
Test status
Simulation time 24927606973 ps
CPU time 11 seconds
Started Feb 21 03:47:58 PM PST 24
Finished Feb 21 03:48:10 PM PST 24
Peak memory 195364 kb
Host smart-3a3bad96-75e0-45f8-9036-e3cab42f6e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645901736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1645901736
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2056636689
Short name T1096
Test name
Test status
Simulation time 277932578 ps
CPU time 1.46 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:48:33 PM PST 24
Peak memory 198068 kb
Host smart-bfbeffbe-5c3c-46e2-b0d8-b4de235f5aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056636689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2056636689
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3884106735
Short name T822
Test name
Test status
Simulation time 91800743249 ps
CPU time 678.66 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:59:40 PM PST 24
Peak memory 215556 kb
Host smart-eabc3a81-afb6-43fa-8ef8-fca4678d5b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884106735 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3884106735
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1153006513
Short name T931
Test name
Test status
Simulation time 1651802959 ps
CPU time 1.89 seconds
Started Feb 21 03:48:07 PM PST 24
Finished Feb 21 03:48:09 PM PST 24
Peak memory 198000 kb
Host smart-585d6f63-11a3-4a0f-aea5-14d4fbea94a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153006513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1153006513
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2963755356
Short name T52
Test name
Test status
Simulation time 105870275231 ps
CPU time 133.24 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:50:20 PM PST 24
Peak memory 199728 kb
Host smart-b693f690-604e-4b8f-ae03-e021af78f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963755356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2963755356
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2095128182
Short name T779
Test name
Test status
Simulation time 129200029008 ps
CPU time 49.44 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 03:52:12 PM PST 24
Peak memory 199564 kb
Host smart-5a77ffd7-03c1-4c65-9095-d30c96ecc59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095128182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2095128182
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2054083687
Short name T652
Test name
Test status
Simulation time 21156546071 ps
CPU time 34.09 seconds
Started Feb 21 03:51:24 PM PST 24
Finished Feb 21 03:51:59 PM PST 24
Peak memory 199676 kb
Host smart-32ad22b6-28f0-443f-b8dd-9a54ad53afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054083687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2054083687
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1175955185
Short name T938
Test name
Test status
Simulation time 22600049293 ps
CPU time 20.27 seconds
Started Feb 21 03:51:24 PM PST 24
Finished Feb 21 03:51:45 PM PST 24
Peak memory 199704 kb
Host smart-5ecff081-b2cf-4407-b71a-695210e0f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175955185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1175955185
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2465691420
Short name T60
Test name
Test status
Simulation time 515824642666 ps
CPU time 1337.55 seconds
Started Feb 21 03:51:25 PM PST 24
Finished Feb 21 04:13:43 PM PST 24
Peak memory 232708 kb
Host smart-90bc643e-ef8f-4d24-af6f-60ca8ad2d930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465691420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2465691420
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4224767743
Short name T128
Test name
Test status
Simulation time 71221970828 ps
CPU time 113.27 seconds
Started Feb 21 03:51:21 PM PST 24
Finished Feb 21 03:53:16 PM PST 24
Peak memory 199288 kb
Host smart-7f06bc1e-e254-4716-b41f-06778197b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224767743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4224767743
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1627487921
Short name T1020
Test name
Test status
Simulation time 56150406341 ps
CPU time 12.17 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:51:36 PM PST 24
Peak memory 199736 kb
Host smart-12be8204-c045-48c0-b7c7-e6ea697bf8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627487921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1627487921
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2081894754
Short name T110
Test name
Test status
Simulation time 100957175455 ps
CPU time 285.8 seconds
Started Feb 21 03:51:23 PM PST 24
Finished Feb 21 03:56:09 PM PST 24
Peak memory 216392 kb
Host smart-35faf489-a8bb-4dda-9f29-01b648ecf38a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081894754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2081894754
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1425318804
Short name T202
Test name
Test status
Simulation time 25209607044 ps
CPU time 44.1 seconds
Started Feb 21 03:51:24 PM PST 24
Finished Feb 21 03:52:09 PM PST 24
Peak memory 199556 kb
Host smart-593a8e99-9890-48fa-80b0-bcbc530b6dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425318804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1425318804
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2593807680
Short name T358
Test name
Test status
Simulation time 26711640602 ps
CPU time 34.19 seconds
Started Feb 21 03:51:32 PM PST 24
Finished Feb 21 03:52:07 PM PST 24
Peak memory 199648 kb
Host smart-45a6de5b-bbdc-42b5-86e8-c77f27aeb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593807680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2593807680
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2148806119
Short name T855
Test name
Test status
Simulation time 47538174341 ps
CPU time 31.44 seconds
Started Feb 21 03:51:26 PM PST 24
Finished Feb 21 03:51:58 PM PST 24
Peak memory 199672 kb
Host smart-0483b343-a547-4dea-90d1-d71b01c20a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148806119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2148806119
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.74517111
Short name T866
Test name
Test status
Simulation time 16588271 ps
CPU time 0.54 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:48:06 PM PST 24
Peak memory 194148 kb
Host smart-2254590e-acca-41a3-a988-b4cf35257c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74517111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.74517111
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1397260011
Short name T751
Test name
Test status
Simulation time 54169463043 ps
CPU time 41.78 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:48:52 PM PST 24
Peak memory 199700 kb
Host smart-b0e0e542-d84c-4241-b2e8-7c51dfe28619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397260011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1397260011
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.667018172
Short name T1092
Test name
Test status
Simulation time 76398891135 ps
CPU time 71.62 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:49:22 PM PST 24
Peak memory 199756 kb
Host smart-42ec423a-1e7a-41db-b045-81aadb928d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667018172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.667018172
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.4152964804
Short name T871
Test name
Test status
Simulation time 22690630958 ps
CPU time 39.24 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:48:48 PM PST 24
Peak memory 198624 kb
Host smart-1a29e446-6a9b-46b8-b69b-a13237a6d9de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152964804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4152964804
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2544180266
Short name T814
Test name
Test status
Simulation time 132673525550 ps
CPU time 253.32 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:52:45 PM PST 24
Peak memory 199664 kb
Host smart-a579a4f2-2deb-40a0-855a-11cbc46a7232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544180266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2544180266
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3461006654
Short name T20
Test name
Test status
Simulation time 13261035414 ps
CPU time 7.19 seconds
Started Feb 21 03:48:13 PM PST 24
Finished Feb 21 03:48:21 PM PST 24
Peak memory 198912 kb
Host smart-1b5352b3-9198-4d1f-a24e-43b0a5f23a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461006654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3461006654
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1627383989
Short name T828
Test name
Test status
Simulation time 69067369673 ps
CPU time 124.13 seconds
Started Feb 21 03:48:09 PM PST 24
Finished Feb 21 03:50:14 PM PST 24
Peak memory 199932 kb
Host smart-2dee56ec-7f9e-4251-8a8f-1beb0b436aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627383989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1627383989
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4087948031
Short name T623
Test name
Test status
Simulation time 12320938179 ps
CPU time 637.71 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:58:43 PM PST 24
Peak memory 199632 kb
Host smart-d2747028-5222-41b6-a733-75aa7e77ead8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087948031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4087948031
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1337516996
Short name T910
Test name
Test status
Simulation time 3030252465 ps
CPU time 3.45 seconds
Started Feb 21 03:48:03 PM PST 24
Finished Feb 21 03:48:07 PM PST 24
Peak memory 198248 kb
Host smart-9b4cbb99-15ce-4abd-a38e-a5e45c619c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337516996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1337516996
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1149646415
Short name T713
Test name
Test status
Simulation time 217339743739 ps
CPU time 150.71 seconds
Started Feb 21 03:48:11 PM PST 24
Finished Feb 21 03:50:42 PM PST 24
Peak memory 199740 kb
Host smart-3bcd41d6-02c4-4c8d-8227-b6b798360b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149646415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1149646415
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2786556044
Short name T691
Test name
Test status
Simulation time 2359621411 ps
CPU time 1.28 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:48:07 PM PST 24
Peak memory 195068 kb
Host smart-068c799d-cef2-4c72-98ad-24d496c7143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786556044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2786556044
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.967821847
Short name T649
Test name
Test status
Simulation time 5542916355 ps
CPU time 6.72 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:48:12 PM PST 24
Peak memory 198508 kb
Host smart-6ec26fb4-9790-4e20-a823-99953d7b66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967821847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.967821847
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.997988838
Short name T507
Test name
Test status
Simulation time 211960550366 ps
CPU time 2532.54 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 04:30:18 PM PST 24
Peak memory 199620 kb
Host smart-d441b7d2-4ac6-4691-8a7e-086bf4050e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997988838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.997988838
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2448200068
Short name T772
Test name
Test status
Simulation time 738296844 ps
CPU time 1.36 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:48:11 PM PST 24
Peak memory 196224 kb
Host smart-f4a62f1b-35d7-4a5e-8c69-cbb88f178083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448200068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2448200068
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.101074487
Short name T804
Test name
Test status
Simulation time 46904055861 ps
CPU time 25.41 seconds
Started Feb 21 03:48:02 PM PST 24
Finished Feb 21 03:48:28 PM PST 24
Peak memory 199656 kb
Host smart-e1e1708e-d207-4fa5-b763-1a41b6a1496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101074487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.101074487
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2334090601
Short name T291
Test name
Test status
Simulation time 46608381360 ps
CPU time 51.41 seconds
Started Feb 21 03:51:22 PM PST 24
Finished Feb 21 03:52:14 PM PST 24
Peak memory 198844 kb
Host smart-fc2b368e-8a22-45d5-b582-e0155b26096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334090601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2334090601
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.689185313
Short name T454
Test name
Test status
Simulation time 25691890371 ps
CPU time 484.78 seconds
Started Feb 21 03:51:34 PM PST 24
Finished Feb 21 03:59:39 PM PST 24
Peak memory 213648 kb
Host smart-3a25a807-f5d2-4807-a983-db09d63a3da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689185313 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.689185313
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3919698669
Short name T981
Test name
Test status
Simulation time 324155184702 ps
CPU time 30.44 seconds
Started Feb 21 03:51:27 PM PST 24
Finished Feb 21 03:51:57 PM PST 24
Peak memory 199664 kb
Host smart-4f6be282-7c18-401e-a6cc-6454d5895cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919698669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3919698669
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2453816769
Short name T249
Test name
Test status
Simulation time 16010796921 ps
CPU time 27.66 seconds
Started Feb 21 03:51:37 PM PST 24
Finished Feb 21 03:52:05 PM PST 24
Peak memory 198964 kb
Host smart-ca4dfaff-67d2-433c-a5b4-7c4105b8d88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453816769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2453816769
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2802861030
Short name T688
Test name
Test status
Simulation time 158296894268 ps
CPU time 538.15 seconds
Started Feb 21 03:51:34 PM PST 24
Finished Feb 21 04:00:34 PM PST 24
Peak memory 216244 kb
Host smart-a11f7a4c-b01d-427c-850c-526d1c4690b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802861030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2802861030
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3809440044
Short name T756
Test name
Test status
Simulation time 20836525486 ps
CPU time 32.28 seconds
Started Feb 21 03:51:36 PM PST 24
Finished Feb 21 03:52:09 PM PST 24
Peak memory 199424 kb
Host smart-a6a3eb3d-cc63-429b-a192-a972430f7cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809440044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3809440044
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3628385466
Short name T451
Test name
Test status
Simulation time 84054738548 ps
CPU time 1170.67 seconds
Started Feb 21 03:51:33 PM PST 24
Finished Feb 21 04:11:05 PM PST 24
Peak memory 214464 kb
Host smart-8ddc42ee-05ed-40eb-804b-30f01f6eb9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628385466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3628385466
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1873144643
Short name T159
Test name
Test status
Simulation time 89590395207 ps
CPU time 144.02 seconds
Started Feb 21 03:51:35 PM PST 24
Finished Feb 21 03:54:00 PM PST 24
Peak memory 199512 kb
Host smart-be6e6a20-6dfc-4246-8dbe-dd266174a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873144643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1873144643
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2465478977
Short name T34
Test name
Test status
Simulation time 92768275834 ps
CPU time 39.76 seconds
Started Feb 21 03:51:27 PM PST 24
Finished Feb 21 03:52:08 PM PST 24
Peak memory 199132 kb
Host smart-acd2473d-b917-4667-984d-a8b117eb6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465478977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2465478977
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2573522860
Short name T587
Test name
Test status
Simulation time 25234621083 ps
CPU time 36.5 seconds
Started Feb 21 03:51:34 PM PST 24
Finished Feb 21 03:52:12 PM PST 24
Peak memory 199656 kb
Host smart-70333168-5317-4b7c-af46-0c2f838ece5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573522860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2573522860
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2306487161
Short name T402
Test name
Test status
Simulation time 9333379998 ps
CPU time 107.51 seconds
Started Feb 21 03:51:37 PM PST 24
Finished Feb 21 03:53:25 PM PST 24
Peak memory 208172 kb
Host smart-aeefe3c1-d3d4-4fed-81cb-ac607892a31e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306487161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2306487161
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.326361974
Short name T773
Test name
Test status
Simulation time 303929054881 ps
CPU time 53.04 seconds
Started Feb 21 03:51:35 PM PST 24
Finished Feb 21 03:52:29 PM PST 24
Peak memory 199576 kb
Host smart-dd67e98d-3811-4f7b-919e-96e5f307edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326361974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.326361974
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1604650768
Short name T119
Test name
Test status
Simulation time 40292738207 ps
CPU time 107.8 seconds
Started Feb 21 03:51:28 PM PST 24
Finished Feb 21 03:53:16 PM PST 24
Peak memory 199644 kb
Host smart-9518ab86-b8a0-497f-8f87-42e5e848092a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604650768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1604650768
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1080758952
Short name T37
Test name
Test status
Simulation time 118017493090 ps
CPU time 385.21 seconds
Started Feb 21 03:51:35 PM PST 24
Finished Feb 21 03:58:01 PM PST 24
Peak memory 216400 kb
Host smart-bd0dcbb7-fe54-459c-83b0-8394e1db9404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080758952 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1080758952
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2534405010
Short name T244
Test name
Test status
Simulation time 69239562129 ps
CPU time 50.36 seconds
Started Feb 21 03:51:29 PM PST 24
Finished Feb 21 03:52:19 PM PST 24
Peak memory 199684 kb
Host smart-d5577051-06b9-44b4-be66-63cd17e3d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534405010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2534405010
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1266828375
Short name T945
Test name
Test status
Simulation time 52532295 ps
CPU time 0.54 seconds
Started Feb 21 03:48:01 PM PST 24
Finished Feb 21 03:48:03 PM PST 24
Peak memory 195132 kb
Host smart-041d4d50-1b8f-46f9-a9f6-e0a87d4b799d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266828375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1266828375
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1638174971
Short name T684
Test name
Test status
Simulation time 109649185766 ps
CPU time 49.5 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:56 PM PST 24
Peak memory 199632 kb
Host smart-0ac50792-0b8d-439a-bab9-a4517d1d4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638174971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1638174971
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3310961464
Short name T329
Test name
Test status
Simulation time 325613440370 ps
CPU time 55.12 seconds
Started Feb 21 03:48:09 PM PST 24
Finished Feb 21 03:49:04 PM PST 24
Peak memory 198956 kb
Host smart-47c2f2e4-697c-4ab5-a074-c13b14703046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310961464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3310961464
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1722059277
Short name T350
Test name
Test status
Simulation time 22556508913 ps
CPU time 17.17 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:23 PM PST 24
Peak memory 199416 kb
Host smart-983095bf-d72d-4c3d-9ea9-3779547e029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722059277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1722059277
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1023413974
Short name T417
Test name
Test status
Simulation time 13451960157 ps
CPU time 16.54 seconds
Started Feb 21 03:48:19 PM PST 24
Finished Feb 21 03:48:36 PM PST 24
Peak memory 198780 kb
Host smart-717699c1-5b58-4c73-b8ec-ec1d065997eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023413974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1023413974
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2980724530
Short name T990
Test name
Test status
Simulation time 62834882782 ps
CPU time 183.87 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:51:11 PM PST 24
Peak memory 199632 kb
Host smart-81681b8f-4d8d-4825-9d4e-21224289cd7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980724530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2980724530
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2797499456
Short name T572
Test name
Test status
Simulation time 7546547702 ps
CPU time 12.43 seconds
Started Feb 21 03:48:18 PM PST 24
Finished Feb 21 03:48:30 PM PST 24
Peak memory 199172 kb
Host smart-976b39d9-f9bd-4434-a8df-25b637494642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797499456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2797499456
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2026655296
Short name T965
Test name
Test status
Simulation time 157483059650 ps
CPU time 60.77 seconds
Started Feb 21 03:48:24 PM PST 24
Finished Feb 21 03:49:26 PM PST 24
Peak memory 199728 kb
Host smart-389804fe-8b95-491c-871d-2c0cd6160d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026655296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2026655296
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4050659739
Short name T1004
Test name
Test status
Simulation time 38235643674 ps
CPU time 2019.05 seconds
Started Feb 21 03:48:31 PM PST 24
Finished Feb 21 04:22:11 PM PST 24
Peak memory 199732 kb
Host smart-8be0026d-c663-4294-8720-baaed1a30ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050659739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4050659739
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2372816250
Short name T86
Test name
Test status
Simulation time 2310284859 ps
CPU time 22.63 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:48:31 PM PST 24
Peak memory 198524 kb
Host smart-f007d76f-2d04-45b8-ae59-a52b044bbfe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372816250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2372816250
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3494331464
Short name T207
Test name
Test status
Simulation time 76724181503 ps
CPU time 65.61 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:49:12 PM PST 24
Peak memory 199652 kb
Host smart-3547a386-63ee-43ce-a215-0c8d5f22e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494331464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3494331464
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2441549523
Short name T956
Test name
Test status
Simulation time 29989218959 ps
CPU time 13.21 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:48:19 PM PST 24
Peak memory 195316 kb
Host smart-44b2456b-cf9e-4593-8e6b-5602334d9f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441549523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2441549523
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.161608812
Short name T448
Test name
Test status
Simulation time 518837123 ps
CPU time 1.09 seconds
Started Feb 21 03:48:07 PM PST 24
Finished Feb 21 03:48:09 PM PST 24
Peak memory 197804 kb
Host smart-fdc96e98-85a4-4b1a-b208-61429528cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161608812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.161608812
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.271299860
Short name T1056
Test name
Test status
Simulation time 193657017464 ps
CPU time 358.29 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 216196 kb
Host smart-c08632cb-04cc-4bb4-9212-90112b547494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271299860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.271299860
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1514505631
Short name T39
Test name
Test status
Simulation time 129327959416 ps
CPU time 568.84 seconds
Started Feb 21 03:48:16 PM PST 24
Finished Feb 21 03:57:45 PM PST 24
Peak memory 216164 kb
Host smart-bf580b95-b4c5-4cc5-9b81-b96f0bddecfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514505631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1514505631
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3481081565
Short name T601
Test name
Test status
Simulation time 1092403734 ps
CPU time 3.05 seconds
Started Feb 21 03:48:09 PM PST 24
Finished Feb 21 03:48:12 PM PST 24
Peak memory 198040 kb
Host smart-fb202de6-f422-4f01-aea8-e878fe6f710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481081565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3481081565
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1733894494
Short name T1083
Test name
Test status
Simulation time 53722696685 ps
CPU time 80.77 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:49:30 PM PST 24
Peak memory 199656 kb
Host smart-ce6b13df-94cf-464e-a285-f43097b9db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733894494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1733894494
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1618399240
Short name T581
Test name
Test status
Simulation time 147487496624 ps
CPU time 56.36 seconds
Started Feb 21 03:51:35 PM PST 24
Finished Feb 21 03:52:33 PM PST 24
Peak memory 199620 kb
Host smart-3d316ef0-2ba2-4cfd-95d5-4f8e00146cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618399240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1618399240
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.626399792
Short name T219
Test name
Test status
Simulation time 158452436676 ps
CPU time 43.77 seconds
Started Feb 21 03:51:33 PM PST 24
Finished Feb 21 03:52:17 PM PST 24
Peak memory 199728 kb
Host smart-b2037ee0-a464-4677-8561-9ab384a6ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626399792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.626399792
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2562823536
Short name T873
Test name
Test status
Simulation time 235697300444 ps
CPU time 1462.07 seconds
Started Feb 21 03:51:34 PM PST 24
Finished Feb 21 04:15:58 PM PST 24
Peak memory 221716 kb
Host smart-4dcd1f33-4975-4949-82e0-03552b2fe314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562823536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2562823536
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.967860868
Short name T1063
Test name
Test status
Simulation time 140511987528 ps
CPU time 232.69 seconds
Started Feb 21 03:51:41 PM PST 24
Finished Feb 21 03:55:34 PM PST 24
Peak memory 199708 kb
Host smart-177f46cc-9c63-48ec-aa90-3d860647c61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967860868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.967860868
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2440459471
Short name T121
Test name
Test status
Simulation time 38414412604 ps
CPU time 36.71 seconds
Started Feb 21 03:51:39 PM PST 24
Finished Feb 21 03:52:16 PM PST 24
Peak memory 199712 kb
Host smart-ceb33784-bef4-4fba-98e7-eda914bc8912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440459471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2440459471
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2483718256
Short name T115
Test name
Test status
Simulation time 25053309699 ps
CPU time 42.07 seconds
Started Feb 21 03:51:41 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 199600 kb
Host smart-1075be87-8118-41b0-9ba9-b93771408d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483718256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2483718256
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1931515937
Short name T169
Test name
Test status
Simulation time 33026401559 ps
CPU time 46.79 seconds
Started Feb 21 03:51:34 PM PST 24
Finished Feb 21 03:52:21 PM PST 24
Peak memory 199520 kb
Host smart-ca5481f8-5e01-4dfe-9e1c-a35597c75431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931515937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1931515937
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1221369622
Short name T840
Test name
Test status
Simulation time 26797174299 ps
CPU time 16.27 seconds
Started Feb 21 03:51:40 PM PST 24
Finished Feb 21 03:51:57 PM PST 24
Peak memory 199632 kb
Host smart-e1abb801-a0bf-4837-9dd7-813c90af504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221369622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1221369622
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1215575800
Short name T1070
Test name
Test status
Simulation time 93265392484 ps
CPU time 70.13 seconds
Started Feb 21 03:51:36 PM PST 24
Finished Feb 21 03:52:47 PM PST 24
Peak memory 198900 kb
Host smart-c2a48adc-2e04-4b90-ac89-df498476d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215575800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1215575800
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1665549957
Short name T895
Test name
Test status
Simulation time 21437817 ps
CPU time 0.59 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:48:06 PM PST 24
Peak memory 195120 kb
Host smart-afce300d-58d5-44ac-bfb2-4eda8ba14262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665549957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1665549957
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2530593011
Short name T1023
Test name
Test status
Simulation time 116632392591 ps
CPU time 94.05 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:49:39 PM PST 24
Peak memory 199608 kb
Host smart-370e993e-4e26-4341-a47d-df22d0fe571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530593011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2530593011
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.487939687
Short name T584
Test name
Test status
Simulation time 136547436445 ps
CPU time 197.26 seconds
Started Feb 21 03:48:17 PM PST 24
Finished Feb 21 03:51:35 PM PST 24
Peak memory 199716 kb
Host smart-01df3b28-9cf7-4042-8e42-be0084dbbc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487939687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.487939687
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3227986637
Short name T341
Test name
Test status
Simulation time 151532508239 ps
CPU time 83.33 seconds
Started Feb 21 03:48:17 PM PST 24
Finished Feb 21 03:49:41 PM PST 24
Peak memory 199652 kb
Host smart-904be15a-708b-4325-b304-78c7336fa264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227986637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3227986637
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3855028232
Short name T458
Test name
Test status
Simulation time 1956233946922 ps
CPU time 713.5 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 04:00:04 PM PST 24
Peak memory 199068 kb
Host smart-552fae32-3442-46e2-9179-7bb9ee9b2f12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855028232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3855028232
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3119044285
Short name T851
Test name
Test status
Simulation time 114871266273 ps
CPU time 118.84 seconds
Started Feb 21 03:48:09 PM PST 24
Finished Feb 21 03:50:08 PM PST 24
Peak memory 199672 kb
Host smart-8c6b6bbf-77af-4080-9ca5-e60fe7217091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119044285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3119044285
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1226814312
Short name T466
Test name
Test status
Simulation time 2586647659 ps
CPU time 1.41 seconds
Started Feb 21 03:48:06 PM PST 24
Finished Feb 21 03:48:08 PM PST 24
Peak memory 196684 kb
Host smart-99ee1077-880f-4e2d-b64d-8b43889fbf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226814312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1226814312
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1147640308
Short name T438
Test name
Test status
Simulation time 90190892749 ps
CPU time 255.27 seconds
Started Feb 21 03:48:08 PM PST 24
Finished Feb 21 03:52:24 PM PST 24
Peak memory 199808 kb
Host smart-da758b9a-86cf-4cb1-b5bc-09a696f17b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147640308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1147640308
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2313079570
Short name T520
Test name
Test status
Simulation time 8178660019 ps
CPU time 293.66 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:53:04 PM PST 24
Peak memory 199616 kb
Host smart-eec0ae23-9dd1-4352-a5a7-43f813c006a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313079570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2313079570
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1052512781
Short name T472
Test name
Test status
Simulation time 1951670097 ps
CPU time 3.32 seconds
Started Feb 21 03:48:04 PM PST 24
Finished Feb 21 03:48:08 PM PST 24
Peak memory 197800 kb
Host smart-96bfdae1-ce5c-467a-955b-f34174a2e083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052512781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1052512781
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1259555148
Short name T770
Test name
Test status
Simulation time 19710806469 ps
CPU time 28.36 seconds
Started Feb 21 03:48:02 PM PST 24
Finished Feb 21 03:48:31 PM PST 24
Peak memory 199384 kb
Host smart-5eb73cd0-3515-4bb5-861f-022a66c07e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259555148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1259555148
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3868941898
Short name T657
Test name
Test status
Simulation time 4873314552 ps
CPU time 4.39 seconds
Started Feb 21 03:48:17 PM PST 24
Finished Feb 21 03:48:22 PM PST 24
Peak memory 195328 kb
Host smart-36d9a7f1-632d-4ea7-b8ef-7b573b31abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868941898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3868941898
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3690018583
Short name T474
Test name
Test status
Simulation time 636984104 ps
CPU time 1.23 seconds
Started Feb 21 03:48:18 PM PST 24
Finished Feb 21 03:48:20 PM PST 24
Peak memory 197556 kb
Host smart-b22b8ef1-fade-454b-ae03-c0baf2c9670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690018583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3690018583
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.129743249
Short name T279
Test name
Test status
Simulation time 498578136210 ps
CPU time 238.54 seconds
Started Feb 21 03:48:24 PM PST 24
Finished Feb 21 03:52:23 PM PST 24
Peak memory 199724 kb
Host smart-7d96b57e-ba5d-49f2-af34-9946a0bc86be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129743249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.129743249
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2161146122
Short name T1047
Test name
Test status
Simulation time 6203915735 ps
CPU time 17.21 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:48:53 PM PST 24
Peak memory 199140 kb
Host smart-f66ad237-d6b7-44c0-bab5-d96d5d5832dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161146122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2161146122
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2399311547
Short name T585
Test name
Test status
Simulation time 34171099964 ps
CPU time 58.66 seconds
Started Feb 21 03:48:12 PM PST 24
Finished Feb 21 03:49:11 PM PST 24
Peak memory 199656 kb
Host smart-8d5b3388-ed74-4199-b4af-8e22745bd51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399311547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2399311547
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4291120243
Short name T918
Test name
Test status
Simulation time 127322807944 ps
CPU time 113.81 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:53:47 PM PST 24
Peak memory 199700 kb
Host smart-96e57400-1b68-4a73-a146-ef55367ec2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291120243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4291120243
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.551680181
Short name T1043
Test name
Test status
Simulation time 111322150435 ps
CPU time 320.06 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:57:14 PM PST 24
Peak memory 216288 kb
Host smart-6b0cd4f9-36de-4d41-93d8-ee48454e0536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551680181 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.551680181
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3173960818
Short name T201
Test name
Test status
Simulation time 129584881269 ps
CPU time 93.99 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:53:28 PM PST 24
Peak memory 199648 kb
Host smart-2503b30d-af37-45cc-82a8-f0a406d964de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173960818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3173960818
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2208345017
Short name T147
Test name
Test status
Simulation time 15616098213 ps
CPU time 25.09 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:52:19 PM PST 24
Peak memory 199376 kb
Host smart-5fb77027-2f09-45a2-91c6-1d520d377660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208345017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2208345017
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4059135993
Short name T680
Test name
Test status
Simulation time 30028081513 ps
CPU time 344.24 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:57:38 PM PST 24
Peak memory 215660 kb
Host smart-5c14f323-c44e-49ce-ab71-06078e51465a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059135993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4059135993
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4027622019
Short name T605
Test name
Test status
Simulation time 22449701141 ps
CPU time 32.52 seconds
Started Feb 21 03:51:54 PM PST 24
Finished Feb 21 03:52:28 PM PST 24
Peak memory 198684 kb
Host smart-a7f56dbe-1b59-4ecd-a990-07d9f9e630e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027622019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4027622019
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3650068680
Short name T775
Test name
Test status
Simulation time 162131566869 ps
CPU time 265.03 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:56:17 PM PST 24
Peak memory 199664 kb
Host smart-41c2b48c-4b1c-4d10-828d-2b40f0f393dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650068680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3650068680
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2172382710
Short name T449
Test name
Test status
Simulation time 22414481184 ps
CPU time 387.74 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:58:21 PM PST 24
Peak memory 212796 kb
Host smart-671b026e-ebdb-4966-b700-c7737fdb91c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172382710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2172382710
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2235238171
Short name T208
Test name
Test status
Simulation time 20941448706 ps
CPU time 37.54 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:52:32 PM PST 24
Peak memory 199316 kb
Host smart-ac78cb76-ebc7-4cb7-89b3-fdf6668fbf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235238171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2235238171
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2960851933
Short name T720
Test name
Test status
Simulation time 129181604986 ps
CPU time 24.27 seconds
Started Feb 21 03:51:54 PM PST 24
Finished Feb 21 03:52:19 PM PST 24
Peak memory 199728 kb
Host smart-d1fc2f82-53fb-43ee-88b6-ba9e5561abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960851933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2960851933
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4022152184
Short name T734
Test name
Test status
Simulation time 26397868 ps
CPU time 0.54 seconds
Started Feb 21 03:48:26 PM PST 24
Finished Feb 21 03:48:27 PM PST 24
Peak memory 193876 kb
Host smart-2f6dfe1b-c8ce-482f-9a06-4a72d7e7c12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022152184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4022152184
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.498459962
Short name T764
Test name
Test status
Simulation time 59536432723 ps
CPU time 74.82 seconds
Started Feb 21 03:48:21 PM PST 24
Finished Feb 21 03:49:36 PM PST 24
Peak memory 199608 kb
Host smart-a3335745-97b4-4b45-b614-13289da68523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498459962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.498459962
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2188666376
Short name T889
Test name
Test status
Simulation time 98889050542 ps
CPU time 64.21 seconds
Started Feb 21 03:48:05 PM PST 24
Finished Feb 21 03:49:09 PM PST 24
Peak memory 199656 kb
Host smart-6a60c8b3-9605-4e31-b090-f9dd1d9abb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188666376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2188666376
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1309117035
Short name T996
Test name
Test status
Simulation time 41260217717 ps
CPU time 59.86 seconds
Started Feb 21 03:48:07 PM PST 24
Finished Feb 21 03:49:07 PM PST 24
Peak memory 199116 kb
Host smart-8e18cc13-f0ae-4ebb-8ba4-3a2fd9d0a4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309117035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1309117035
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.326562510
Short name T746
Test name
Test status
Simulation time 280027893995 ps
CPU time 151.06 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:51:12 PM PST 24
Peak memory 199576 kb
Host smart-01452fa5-4eeb-4d3e-96c8-4d3d35e604e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326562510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.326562510
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3749534140
Short name T796
Test name
Test status
Simulation time 170453306442 ps
CPU time 361 seconds
Started Feb 21 03:48:37 PM PST 24
Finished Feb 21 03:54:38 PM PST 24
Peak memory 199744 kb
Host smart-4873cbbd-8809-41e5-b4fc-e16828b21b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3749534140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3749534140
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2579398676
Short name T1091
Test name
Test status
Simulation time 2336650988 ps
CPU time 3.18 seconds
Started Feb 21 03:48:37 PM PST 24
Finished Feb 21 03:48:41 PM PST 24
Peak memory 198072 kb
Host smart-e2ea6054-c251-4b12-8219-85b68357ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579398676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2579398676
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1812140175
Short name T45
Test name
Test status
Simulation time 17701595777 ps
CPU time 29.86 seconds
Started Feb 21 03:48:40 PM PST 24
Finished Feb 21 03:49:11 PM PST 24
Peak memory 197408 kb
Host smart-dd6d6643-6d85-4d7a-b17b-bee38e66da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812140175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1812140175
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2413618222
Short name T697
Test name
Test status
Simulation time 15748485123 ps
CPU time 844.09 seconds
Started Feb 21 03:48:32 PM PST 24
Finished Feb 21 04:02:38 PM PST 24
Peak memory 199648 kb
Host smart-e74a6dcd-ce10-4f65-97ff-029560659a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413618222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2413618222
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2865065241
Short name T551
Test name
Test status
Simulation time 2749844241 ps
CPU time 7.35 seconds
Started Feb 21 03:48:30 PM PST 24
Finished Feb 21 03:48:39 PM PST 24
Peak memory 198216 kb
Host smart-dc91bfc6-e564-4989-afc9-eb2d5e0cc984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865065241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2865065241
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.572664834
Short name T817
Test name
Test status
Simulation time 45586607120 ps
CPU time 35.55 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:49:12 PM PST 24
Peak memory 199756 kb
Host smart-6e54914d-7cb3-4855-bec8-14b776708693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572664834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.572664834
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2081142185
Short name T738
Test name
Test status
Simulation time 43614005799 ps
CPU time 65.86 seconds
Started Feb 21 03:48:54 PM PST 24
Finished Feb 21 03:50:01 PM PST 24
Peak memory 195032 kb
Host smart-e7dad2df-89a0-44d9-a87e-31de1d9fc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081142185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2081142185
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.376732370
Short name T819
Test name
Test status
Simulation time 146153048 ps
CPU time 0.82 seconds
Started Feb 21 03:48:10 PM PST 24
Finished Feb 21 03:48:11 PM PST 24
Peak memory 196404 kb
Host smart-6a822d98-c441-4003-ab7c-da01a679cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376732370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.376732370
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2285933617
Short name T909
Test name
Test status
Simulation time 92933293841 ps
CPU time 1132.29 seconds
Started Feb 21 03:48:34 PM PST 24
Finished Feb 21 04:07:27 PM PST 24
Peak memory 199668 kb
Host smart-2d061ad0-d13d-47ab-a01a-c345c54188bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285933617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2285933617
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3815526471
Short name T445
Test name
Test status
Simulation time 1034568300 ps
CPU time 2.09 seconds
Started Feb 21 03:48:22 PM PST 24
Finished Feb 21 03:48:25 PM PST 24
Peak memory 197920 kb
Host smart-7aa23095-37fe-455a-9421-9e61b81d5314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815526471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3815526471
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2774596520
Short name T607
Test name
Test status
Simulation time 113635579504 ps
CPU time 58.5 seconds
Started Feb 21 03:48:36 PM PST 24
Finished Feb 21 03:49:35 PM PST 24
Peak memory 199656 kb
Host smart-108c1034-ba84-46f1-94ae-8f7ccc90d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774596520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2774596520
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2014539397
Short name T245
Test name
Test status
Simulation time 35816090391 ps
CPU time 16.8 seconds
Started Feb 21 03:51:54 PM PST 24
Finished Feb 21 03:52:12 PM PST 24
Peak memory 198936 kb
Host smart-f06776fc-6250-418b-9ff6-c0cdb0a8f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014539397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2014539397
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.170789174
Short name T452
Test name
Test status
Simulation time 16561559818 ps
CPU time 298.22 seconds
Started Feb 21 03:51:53 PM PST 24
Finished Feb 21 03:56:52 PM PST 24
Peak memory 216168 kb
Host smart-8acdc778-d8e9-4021-b38c-5379f94999c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170789174 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.170789174
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.761298313
Short name T809
Test name
Test status
Simulation time 178299204553 ps
CPU time 187.91 seconds
Started Feb 21 03:51:51 PM PST 24
Finished Feb 21 03:54:59 PM PST 24
Peak memory 199708 kb
Host smart-a52fc8a4-c798-4d9d-bec2-4d62e662eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761298313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.761298313
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.894546117
Short name T391
Test name
Test status
Simulation time 203838261042 ps
CPU time 38.67 seconds
Started Feb 21 03:51:52 PM PST 24
Finished Feb 21 03:52:32 PM PST 24
Peak memory 199608 kb
Host smart-d5da705c-28ab-45aa-b448-51ceb6b93030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894546117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.894546117
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2986891673
Short name T264
Test name
Test status
Simulation time 54808589112 ps
CPU time 24.55 seconds
Started Feb 21 03:51:54 PM PST 24
Finished Feb 21 03:52:20 PM PST 24
Peak memory 199332 kb
Host smart-0473bf77-6e0a-4acf-9754-79b38aca9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986891673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2986891673
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1839042905
Short name T450
Test name
Test status
Simulation time 15878605243 ps
CPU time 181.32 seconds
Started Feb 21 03:51:55 PM PST 24
Finished Feb 21 03:54:58 PM PST 24
Peak memory 199784 kb
Host smart-15a6451b-8084-43f0-a0d1-4d934a4b1ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839042905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1839042905
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2910467862
Short name T1082
Test name
Test status
Simulation time 12505090059 ps
CPU time 12.31 seconds
Started Feb 21 03:51:57 PM PST 24
Finished Feb 21 03:52:10 PM PST 24
Peak memory 199744 kb
Host smart-6eba60a3-6908-4bb6-bb56-e7b2824b3215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910467862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2910467862
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1880857019
Short name T127
Test name
Test status
Simulation time 141666275885 ps
CPU time 216.33 seconds
Started Feb 21 03:51:51 PM PST 24
Finished Feb 21 03:55:28 PM PST 24
Peak memory 199480 kb
Host smart-40858334-6cf9-4940-97dc-6813e47eb9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880857019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1880857019
Directory /workspace/99.uart_fifo_reset/latest
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