Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	114726	1			T1	2		T2	47		T4	30
all_values[1]	114726	1			T1	2		T2	47		T4	30
all_values[2]	114726	1			T1	2		T2	47		T4	30
all_values[3]	114726	1			T1	2		T2	47		T4	30
all_values[4]	114726	1			T1	2		T2	47		T4	30
all_values[5]	114726	1			T1	2		T2	47		T4	30
all_values[6]	114726	1			T1	2		T2	47		T4	30
all_values[7]	114726	1			T1	2		T2	47		T4	30

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

457466

1

T1

16

T2

145

T4

148

auto[1]

460342

1

T2

231

T4

92

T5

107

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

902006

1

T1

13

T2

357

T4

232

auto[1]

15802

1

T1

3

T2

19

T4

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	50448	1			T1	1		T2	13		T4	24
all_values[0]	auto[0]	auto[1]	2299	1			T1	1		T4	4		T5	4
all_values[0]	auto[1]	auto[0]	59839	1			T2	27		T4	2		T5	12
all_values[0]	auto[1]	auto[1]	2140	1			T2	7		T5	1		T10	3
all_values[1]	auto[0]	auto[0]	55021	1			T1	1		T2	21		T4	24
all_values[1]	auto[0]	auto[1]	2796	1			T1	1		T2	1		T5	1
all_values[1]	auto[1]	auto[0]	54712	1			T2	21		T4	6		T5	13
all_values[1]	auto[1]	auto[1]	2197	1			T2	4		T10	3		T14	5
all_values[2]	auto[0]	auto[0]	55428	1			T1	1		T2	28		T4	18
all_values[2]	auto[0]	auto[1]	2219	1			T1	1		T2	2		T4	1
all_values[2]	auto[1]	auto[0]	55097	1			T2	12		T4	8		T5	5
all_values[2]	auto[1]	auto[1]	1982	1			T2	5		T4	3		T5	1
all_values[3]	auto[0]	auto[0]	61196	1			T1	2		T2	13		T4	11
all_values[3]	auto[0]	auto[1]	160	1			T11	2		T16	1		T15	3
all_values[3]	auto[1]	auto[0]	53197	1			T2	34		T4	19		T5	16
all_values[3]	auto[1]	auto[1]	173	1			T11	3		T15	1		T17	1
all_values[4]	auto[0]	auto[0]	57600	1			T1	2		T2	15		T4	24
all_values[4]	auto[0]	auto[1]	485	1			T11	9		T16	19		T15	3
all_values[4]	auto[1]	auto[0]	56277	1			T2	32		T4	6		T5	19
all_values[4]	auto[1]	auto[1]	364	1			T15	5		T17	1		T22	5
all_values[5]	auto[0]	auto[0]	54415	1			T1	2		T2	31		T4	9
all_values[5]	auto[0]	auto[1]	116	1			T15	5		T30	2		T37	1
all_values[5]	auto[1]	auto[0]	60080	1			T2	16		T4	21		T5	20
all_values[5]	auto[1]	auto[1]	115	1			T15	1		T30	2		T37	2
all_values[6]	auto[0]	auto[0]	55789	1			T1	2		T2	8		T4	9
all_values[6]	auto[0]	auto[1]	125	1			T15	4		T30	2		T37	2
all_values[6]	auto[1]	auto[0]	58709	1			T2	39		T4	21		T5	9
all_values[6]	auto[1]	auto[1]	103	1			T15	3		T30	4		T37	2
all_values[7]	auto[0]	auto[0]	59107	1			T1	2		T2	13		T4	24
all_values[7]	auto[0]	auto[1]	262	1			T11	1		T15	3		T325	2
all_values[7]	auto[1]	auto[0]	55091	1			T2	34		T4	6		T5	11
all_values[7]	auto[1]	auto[1]	266	1			T11	2		T15	1		T325	7