Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1737	1			T1	1		T4	1		T7	1
auto[BaudRate115200]	1750	1			T1	1		T2	1		T4	1
auto[BaudRate230400]	1525	1			T4	1		T5	2		T8	1
auto[BaudRate128Kbps]	1529	1			T2	1		T4	3		T5	1
auto[BaudRate256Kbps]	1700	1			T4	2		T5	1		T7	1
auto[BaudRate1Mbps]	1340	1			T2	5		T4	1		T10	1
auto[BaudRate1p5Mbps]	965	1			T2	3		T4	1		T9	2

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1034	1			T28	16		T51	6		T320	5
freqs[25]	931	1			T8	2		T10	7		T13	5
freqs[48]	496	1			T12	9		T16	4		T200	6
freqs[50]	349	1			T1	2		T2	10		T27	5
freqs[100]	889	1			T46	16		T47	12		T154	7

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	177	1			T28	2		T51	1		T320	2
auto[BaudRate9600]	freqs[25]	146	1			T141	2		T428	1		T477	1
auto[BaudRate9600]	freqs[48]	92	1			T200	2		T235	2		T204	2
auto[BaudRate9600]	freqs[50]	61	1			T1	1		T54	1		T226	3
auto[BaudRate9600]	freqs[100]	141	1			T46	5		T47	2		T349	2
auto[BaudRate115200]	freqs[24]	155	1			T28	3		T51	1		T133	1
auto[BaudRate115200]	freqs[25]	161	1			T8	1		T10	3		T141	5
auto[BaudRate115200]	freqs[48]	80	1			T16	1		T200	1		T204	3
auto[BaudRate115200]	freqs[50]	43	1			T1	1		T2	1		T27	2
auto[BaudRate115200]	freqs[100]	170	1			T46	11		T47	2		T154	3
auto[BaudRate230400]	freqs[24]	163	1			T28	2		T51	1		T320	2
auto[BaudRate230400]	freqs[25]	128	1			T8	1		T10	2		T13	2
auto[BaudRate230400]	freqs[48]	55	1			T16	1		T200	1		T478	2
auto[BaudRate230400]	freqs[50]	41	1			T27	1		T54	2		T340	3
auto[BaudRate230400]	freqs[100]	120	1			T47	2		T154	2		T20	6
auto[BaudRate128Kbps]	freqs[24]	158	1			T28	4		T51	2		T320	1
auto[BaudRate128Kbps]	freqs[25]	112	1			T13	1		T141	3		T232	1
auto[BaudRate128Kbps]	freqs[48]	62	1			T16	2		T204	3		T354	1
auto[BaudRate128Kbps]	freqs[50]	46	1			T2	1		T27	1		T54	1
auto[BaudRate128Kbps]	freqs[100]	107	1			T154	1		T20	3		T21	6
auto[BaudRate256Kbps]	freqs[24]	122	1			T51	1		T133	2		T131	3
auto[BaudRate256Kbps]	freqs[25]	155	1			T10	1		T13	1		T159	3
auto[BaudRate256Kbps]	freqs[48]	71	1			T12	1		T235	1		T461	1
auto[BaudRate256Kbps]	freqs[50]	50	1			T54	1		T43	1		T226	3
auto[BaudRate256Kbps]	freqs[100]	127	1			T47	3		T154	1		T20	6
auto[BaudRate1Mbps]	freqs[24]	183	1			T28	4		T133	2		T131	1
auto[BaudRate1Mbps]	freqs[25]	151	1			T10	1		T13	1		T159	1
auto[BaudRate1Mbps]	freqs[48]	56	1			T12	4		T200	1		T235	1
auto[BaudRate1Mbps]	freqs[50]	51	1			T2	5		T226	1		T340	2
auto[BaudRate1Mbps]	freqs[100]	118	1			T47	2		T349	2		T21	6
auto[BaudRate1p5Mbps]	freqs[25]	78	1			T141	2		T419	1		T342	6
auto[BaudRate1p5Mbps]	freqs[48]	80	1			T12	4		T200	1		T235	1
auto[BaudRate1p5Mbps]	freqs[50]	57	1			T2	3		T27	1		T226	1
auto[BaudRate1p5Mbps]	freqs[100]	106	1			T47	1		T20	3		T349	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded