Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1978 1 T1 1 T2 2 T7 1
all_levels[1] 576 1 T2 2 T11 24 T136 2
all_levels[2] 353 1 T2 1 T5 1 T10 3
all_levels[3] 348 1 T14 4 T12 1 T16 24
all_levels[4] 370 1 T11 5 T48 2 T420 1
all_levels[5] 584 1 T132 1 T45 2 T49 2
all_levels[6] 628 1 T14 1 T28 1 T131 1
all_levels[7] 152 1 T54 1 T55 2 T239 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%