Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	114726	1			T1	2		T2	47		T4	30
all_pins[1]	114726	1			T1	2		T2	47		T4	30
all_pins[2]	114726	1			T1	2		T2	47		T4	30
all_pins[3]	114726	1			T1	2		T2	47		T4	30
all_pins[4]	114726	1			T1	2		T2	47		T4	30
all_pins[5]	114726	1			T1	2		T2	47		T4	30
all_pins[6]	114726	1			T1	2		T2	47		T4	30
all_pins[7]	114726	1			T1	2		T2	47		T4	30

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	909670	1			T1	16		T2	359		T4	235
values[0x1]	8138	1			T2	17		T4	5		T5	3
transitions[0x0=>0x1]	7465	1			T2	15		T4	5		T5	3
transitions[0x1=>0x0]	7483	1			T2	15		T4	5		T5	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	112541	1			T1	2		T2	40		T4	30
all_pins[0]	values[0x1]	2185	1			T2	7		T5	1		T10	3
all_pins[0]	transitions[0x0=>0x1]	1943	1			T2	5		T5	1		T10	3
all_pins[0]	transitions[0x1=>0x0]	1953	1			T2	2		T10	3		T14	4
all_pins[1]	values[0x0]	112531	1			T1	2		T2	43		T4	30
all_pins[1]	values[0x1]	2195	1			T2	4		T10	3		T14	5
all_pins[1]	transitions[0x0=>0x1]	1966	1			T2	4		T10	3		T14	3
all_pins[1]	transitions[0x1=>0x0]	1840	1			T2	5		T4	3		T5	1
all_pins[2]	values[0x0]	112657	1			T1	2		T2	42		T4	27
all_pins[2]	values[0x1]	2069	1			T2	5		T4	3		T5	1
all_pins[2]	transitions[0x0=>0x1]	2034	1			T2	5		T4	3		T5	1
all_pins[2]	transitions[0x1=>0x0]	138	1			T11	3		T17	1		T179	5
all_pins[3]	values[0x0]	114553	1			T1	2		T2	47		T4	30
all_pins[3]	values[0x1]	173	1			T11	3		T15	1		T17	1
all_pins[3]	transitions[0x0=>0x1]	150	1			T11	3		T17	1		T179	5
all_pins[3]	transitions[0x1=>0x0]	341	1			T15	4		T17	1		T22	5
all_pins[4]	values[0x0]	114362	1			T1	2		T2	47		T4	30
all_pins[4]	values[0x1]	364	1			T15	5		T17	1		T22	5
all_pins[4]	transitions[0x0=>0x1]	316	1			T15	4		T17	1		T22	4
all_pins[4]	transitions[0x1=>0x0]	124	1			T16	1		T17	2		T411	2
all_pins[5]	values[0x0]	114554	1			T1	2		T2	47		T4	30
all_pins[5]	values[0x1]	172	1			T16	1		T15	1		T17	2
all_pins[5]	transitions[0x0=>0x1]	147	1			T16	1		T15	1		T17	2
all_pins[5]	transitions[0x1=>0x0]	689	1			T2	1		T4	2		T5	1
all_pins[6]	values[0x0]	114012	1			T1	2		T2	46		T4	28
all_pins[6]	values[0x1]	714	1			T2	1		T4	2		T5	1
all_pins[6]	transitions[0x0=>0x1]	682	1			T2	1		T4	2		T5	1
all_pins[6]	transitions[0x1=>0x0]	234	1			T11	2		T15	1		T325	7
all_pins[7]	values[0x0]	114460	1			T1	2		T2	47		T4	30
all_pins[7]	values[0x1]	266	1			T11	2		T15	1		T325	7
all_pins[7]	transitions[0x0=>0x1]	227	1			T11	2		T15	1		T325	7
all_pins[7]	transitions[0x1=>0x0]	2164	1			T2	7		T5	1		T10	3