Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 0 7 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1241 1 T1 1 T7 1 T8 1
all_levels[1] 571 1 T4 1 T5 1 T28 3
all_levels[2] 623 1 T2 5 T5 3 T10 4
all_levels[3] 617 1 T14 3 T27 1 T28 5
all_levels[4] 545 1 T4 2 T5 1 T14 2
all_levels[5] 473 1 T2 2 T4 1 T28 2
all_levels[6] 473 1 T50 1 T12 2 T136 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%