Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	498	1			T15	14		T30	11		T37	7
all_values[1]	498	1			T15	14		T30	11		T37	7
all_values[2]	498	1			T15	14		T30	11		T37	7
all_values[3]	498	1			T15	14		T30	11		T37	7
all_values[4]	498	1			T15	14		T30	11		T37	7
all_values[5]	498	1			T15	14		T30	11		T37	7
all_values[6]	498	1			T15	14		T30	11		T37	7
all_values[7]	498	1			T15	14		T30	11		T37	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2186

1

T15

52

T30

57

T37

27

auto[1]

1798

1

T15

60

T30

31

T37

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1569

1

T15

41

T30

31

T37

17

auto[1]

2415

1

T15

71

T30

57

T37

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2338

1

T15

60

T30

49

T37

32

auto[1]

1646

1

T15

52

T30

39

T37

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	104	1			T15	3		T30	3		T37	4
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T15	2		T30	1		T37	1
all_values[0]	auto[0]	auto[1]	auto[0]	91	1			T15	3		T30	2		T236	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T30	1		T236	1		T40	4
all_values[0]	auto[1]	auto[0]	auto[1]	112	1			T15	2		T30	2		T37	1
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T15	4		T30	2		T37	1
all_values[1]	auto[0]	auto[0]	auto[0]	125	1			T15	6		T30	3		T236	4
all_values[1]	auto[0]	auto[0]	auto[1]	46	1			T15	1		T30	1		T37	1
all_values[1]	auto[0]	auto[1]	auto[0]	93	1			T15	3		T37	2		T38	2
all_values[1]	auto[0]	auto[1]	auto[1]	39	1			T30	2		T37	1		T39	3
all_values[1]	auto[1]	auto[0]	auto[1]	109	1			T30	3		T37	2		T39	2
all_values[1]	auto[1]	auto[1]	auto[1]	86	1			T15	4		T30	2		T37	1
all_values[2]	auto[0]	auto[0]	auto[0]	96	1			T15	4		T30	4		T37	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T30	1		T38	2		T40	2
all_values[2]	auto[0]	auto[1]	auto[0]	87	1			T15	1		T37	2		T236	2
all_values[2]	auto[0]	auto[1]	auto[1]	62	1			T15	4		T37	2		T38	1
all_values[2]	auto[1]	auto[0]	auto[1]	109	1			T15	2		T30	6		T37	1
all_values[2]	auto[1]	auto[1]	auto[1]	101	1			T15	3		T37	1		T236	1
all_values[3]	auto[0]	auto[0]	auto[0]	108	1			T15	1		T30	3		T39	4
all_values[3]	auto[0]	auto[0]	auto[1]	47	1			T15	2		T30	1		T236	1
all_values[3]	auto[0]	auto[1]	auto[0]	92	1			T15	5		T38	2		T39	1
all_values[3]	auto[0]	auto[1]	auto[1]	45	1			T30	2		T37	2		T39	1
all_values[3]	auto[1]	auto[0]	auto[1]	119	1			T15	2		T30	4		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	87	1			T15	4		T30	1		T37	4
all_values[4]	auto[0]	auto[0]	auto[0]	117	1			T15	4		T30	4		T37	1
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T15	1		T37	1		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	86	1			T15	1		T30	1		T37	2
all_values[4]	auto[0]	auto[1]	auto[1]	46	1			T15	1		T30	1		T40	3
all_values[4]	auto[1]	auto[0]	auto[1]	98	1			T15	1		T30	1		T37	1
all_values[4]	auto[1]	auto[1]	auto[1]	97	1			T15	6		T30	4		T37	2
all_values[5]	auto[0]	auto[0]	auto[0]	105	1			T15	1		T30	4		T37	2
all_values[5]	auto[0]	auto[0]	auto[1]	50	1			T15	2		T37	2		T236	1
all_values[5]	auto[0]	auto[1]	auto[0]	85	1			T15	2		T30	1		T236	2
all_values[5]	auto[0]	auto[1]	auto[1]	46	1			T30	1		T38	1		T40	1
all_values[5]	auto[1]	auto[0]	auto[1]	113	1			T15	7		T30	2		T37	1
all_values[5]	auto[1]	auto[1]	auto[1]	99	1			T15	2		T30	3		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	117	1			T30	4		T37	2		T236	1
all_values[6]	auto[0]	auto[0]	auto[1]	45	1			T15	3		T30	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	79	1			T15	3		T30	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[1]	39	1			T15	1		T30	2		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	129	1			T15	2		T30	1		T37	2
all_values[6]	auto[1]	auto[1]	auto[1]	89	1			T15	5		T30	2		T236	1
all_values[7]	auto[0]	auto[0]	auto[0]	110	1			T15	1		T236	1		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	51	1			T15	1		T30	3		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	74	1			T15	3		T30	1		T39	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T15	1		T30	1		T37	2
all_values[7]	auto[1]	auto[0]	auto[1]	130	1			T15	4		T30	5		T37	1
all_values[7]	auto[1]	auto[1]	auto[1]	78	1			T15	4		T30	1		T37	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal