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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.79 98.45 100.00 99.76 100.00 97.44


Total test records in report: 1240
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T1047 /workspace/coverage/default/92.uart_fifo_reset.3944696105 Feb 25 01:38:58 PM PST 24 Feb 25 01:41:08 PM PST 24 82887672057 ps
T1048 /workspace/coverage/default/18.uart_rx_parity_err.307107841 Feb 25 01:34:06 PM PST 24 Feb 25 01:34:51 PM PST 24 59072676774 ps
T1049 /workspace/coverage/default/140.uart_fifo_reset.1850578195 Feb 25 01:39:21 PM PST 24 Feb 25 01:39:58 PM PST 24 25466210735 ps
T1050 /workspace/coverage/default/43.uart_perf.4042470666 Feb 25 01:37:19 PM PST 24 Feb 25 01:42:03 PM PST 24 21940081521 ps
T1051 /workspace/coverage/default/99.uart_fifo_reset.3666654430 Feb 25 01:39:01 PM PST 24 Feb 25 01:39:16 PM PST 24 44533243550 ps
T1052 /workspace/coverage/default/1.uart_noise_filter.3529902086 Feb 25 01:32:32 PM PST 24 Feb 25 01:33:18 PM PST 24 25966011061 ps
T1053 /workspace/coverage/default/249.uart_fifo_reset.1597940850 Feb 25 01:40:20 PM PST 24 Feb 25 01:43:49 PM PST 24 109477620535 ps
T1054 /workspace/coverage/default/1.uart_tx_rx.3571919307 Feb 25 01:32:29 PM PST 24 Feb 25 01:33:00 PM PST 24 296170258983 ps
T1055 /workspace/coverage/default/2.uart_fifo_overflow.275979766 Feb 25 01:32:29 PM PST 24 Feb 25 01:33:06 PM PST 24 86495808837 ps
T476 /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3149254096 Feb 25 01:33:32 PM PST 24 Feb 25 01:42:56 PM PST 24 46151251358 ps
T1056 /workspace/coverage/default/42.uart_fifo_overflow.3476374518 Feb 25 01:37:23 PM PST 24 Feb 25 01:38:28 PM PST 24 151404185747 ps
T1057 /workspace/coverage/default/2.uart_long_xfer_wo_dly.732356994 Feb 25 01:32:39 PM PST 24 Feb 25 01:42:20 PM PST 24 205188499888 ps
T1058 /workspace/coverage/default/42.uart_noise_filter.3106637373 Feb 25 01:37:22 PM PST 24 Feb 25 01:38:54 PM PST 24 264090051069 ps
T1059 /workspace/coverage/default/147.uart_fifo_reset.4029457305 Feb 25 01:39:20 PM PST 24 Feb 25 01:39:39 PM PST 24 107817165671 ps
T1060 /workspace/coverage/default/21.uart_alert_test.3932332392 Feb 25 01:34:52 PM PST 24 Feb 25 01:34:54 PM PST 24 16890616 ps
T69 /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1768152599 Feb 25 01:39:00 PM PST 24 Feb 25 01:44:58 PM PST 24 122706144835 ps
T1061 /workspace/coverage/default/45.uart_fifo_full.3708542472 Feb 25 01:37:36 PM PST 24 Feb 25 01:38:01 PM PST 24 17219207987 ps
T1062 /workspace/coverage/default/171.uart_fifo_reset.3584583926 Feb 25 01:39:42 PM PST 24 Feb 25 01:40:56 PM PST 24 97194433135 ps
T1063 /workspace/coverage/default/149.uart_fifo_reset.251244785 Feb 25 01:39:21 PM PST 24 Feb 25 01:39:48 PM PST 24 30411601976 ps
T1064 /workspace/coverage/default/47.uart_stress_all.3221244213 Feb 25 01:38:03 PM PST 24 Feb 25 01:46:08 PM PST 24 325850249407 ps
T1065 /workspace/coverage/default/11.uart_loopback.434817932 Feb 25 01:33:18 PM PST 24 Feb 25 01:33:19 PM PST 24 44939555 ps
T1066 /workspace/coverage/default/15.uart_long_xfer_wo_dly.1668108133 Feb 25 01:34:04 PM PST 24 Feb 25 01:45:06 PM PST 24 130568783256 ps
T356 /workspace/coverage/default/225.uart_fifo_reset.1451666518 Feb 25 01:40:02 PM PST 24 Feb 25 01:45:19 PM PST 24 190111118916 ps
T1067 /workspace/coverage/default/35.uart_intr.3589532507 Feb 25 01:36:36 PM PST 24 Feb 25 01:36:55 PM PST 24 45856749061 ps
T1068 /workspace/coverage/default/21.uart_rx_oversample.3131782744 Feb 25 01:34:58 PM PST 24 Feb 25 01:35:08 PM PST 24 1841070662 ps
T1069 /workspace/coverage/default/18.uart_loopback.815035170 Feb 25 01:34:11 PM PST 24 Feb 25 01:34:34 PM PST 24 10269648846 ps
T1070 /workspace/coverage/default/48.uart_fifo_overflow.1585115100 Feb 25 01:38:08 PM PST 24 Feb 25 01:42:38 PM PST 24 188238036969 ps
T470 /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3719960770 Feb 25 01:37:20 PM PST 24 Feb 25 01:42:53 PM PST 24 28236911643 ps
T1071 /workspace/coverage/default/93.uart_fifo_reset.468145794 Feb 25 01:38:56 PM PST 24 Feb 25 01:40:08 PM PST 24 46178093918 ps
T1072 /workspace/coverage/default/37.uart_smoke.1669262543 Feb 25 01:36:38 PM PST 24 Feb 25 01:36:44 PM PST 24 6110941470 ps
T1073 /workspace/coverage/default/157.uart_fifo_reset.3336652054 Feb 25 01:39:35 PM PST 24 Feb 25 01:40:08 PM PST 24 77066381668 ps
T1074 /workspace/coverage/default/78.uart_stress_all_with_rand_reset.387737944 Feb 25 01:38:43 PM PST 24 Feb 25 01:44:08 PM PST 24 115469748092 ps
T1075 /workspace/coverage/default/10.uart_fifo_overflow.4247123390 Feb 25 01:33:12 PM PST 24 Feb 25 01:33:33 PM PST 24 24995917914 ps
T1076 /workspace/coverage/default/7.uart_tx_ovrd.2014257853 Feb 25 01:32:55 PM PST 24 Feb 25 01:32:58 PM PST 24 2531132988 ps
T1077 /workspace/coverage/default/25.uart_noise_filter.2606605035 Feb 25 01:35:07 PM PST 24 Feb 25 01:36:00 PM PST 24 48065844645 ps
T376 /workspace/coverage/default/11.uart_fifo_overflow.3082286786 Feb 25 01:33:25 PM PST 24 Feb 25 01:34:02 PM PST 24 45847353047 ps
T1078 /workspace/coverage/default/44.uart_loopback.521045647 Feb 25 01:37:31 PM PST 24 Feb 25 01:37:40 PM PST 24 6764971144 ps
T1079 /workspace/coverage/default/25.uart_fifo_overflow.2024471459 Feb 25 01:35:03 PM PST 24 Feb 25 01:36:19 PM PST 24 87466717959 ps
T1080 /workspace/coverage/default/26.uart_noise_filter.2611055771 Feb 25 01:35:04 PM PST 24 Feb 25 01:37:05 PM PST 24 180045715676 ps
T1081 /workspace/coverage/default/26.uart_tx_ovrd.3671848907 Feb 25 01:35:13 PM PST 24 Feb 25 01:35:15 PM PST 24 1431597633 ps
T1082 /workspace/coverage/default/28.uart_rx_oversample.3210997237 Feb 25 01:35:32 PM PST 24 Feb 25 01:35:54 PM PST 24 2150078518 ps
T1083 /workspace/coverage/default/49.uart_alert_test.735502639 Feb 25 01:38:15 PM PST 24 Feb 25 01:38:16 PM PST 24 44498065 ps
T1084 /workspace/coverage/default/18.uart_rx_start_bit_filter.2699821378 Feb 25 01:34:01 PM PST 24 Feb 25 01:34:03 PM PST 24 677305473 ps
T372 /workspace/coverage/default/190.uart_fifo_reset.1003686521 Feb 25 01:39:51 PM PST 24 Feb 25 01:40:19 PM PST 24 18259340603 ps
T1085 /workspace/coverage/default/154.uart_fifo_reset.1624566602 Feb 25 01:39:37 PM PST 24 Feb 25 01:40:11 PM PST 24 75273040869 ps
T70 /workspace/coverage/default/45.uart_stress_all_with_rand_reset.460891492 Feb 25 01:37:39 PM PST 24 Feb 25 01:56:39 PM PST 24 318252166852 ps
T388 /workspace/coverage/default/8.uart_fifo_full.3786752239 Feb 25 01:33:08 PM PST 24 Feb 25 01:34:00 PM PST 24 130472222247 ps
T1086 /workspace/coverage/default/21.uart_loopback.1128143598 Feb 25 01:34:57 PM PST 24 Feb 25 01:35:02 PM PST 24 5655528208 ps
T1087 /workspace/coverage/default/218.uart_fifo_reset.1364537137 Feb 25 01:40:01 PM PST 24 Feb 25 01:42:23 PM PST 24 97308180248 ps
T1088 /workspace/coverage/default/47.uart_long_xfer_wo_dly.334962481 Feb 25 01:38:02 PM PST 24 Feb 25 01:46:12 PM PST 24 131130858697 ps
T1089 /workspace/coverage/default/27.uart_stress_all.2490047052 Feb 25 01:35:18 PM PST 24 Feb 25 01:57:39 PM PST 24 57633530228 ps
T400 /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1604510866 Feb 25 01:34:11 PM PST 24 Feb 25 01:37:12 PM PST 24 201406912061 ps
T1090 /workspace/coverage/default/13.uart_tx_rx.2778926148 Feb 25 01:33:36 PM PST 24 Feb 25 01:33:56 PM PST 24 72164145077 ps
T1091 /workspace/coverage/default/158.uart_fifo_reset.2201487049 Feb 25 01:39:39 PM PST 24 Feb 25 01:40:32 PM PST 24 111418217476 ps
T1092 /workspace/coverage/default/106.uart_fifo_reset.3662959165 Feb 25 01:39:00 PM PST 24 Feb 25 01:39:26 PM PST 24 15684864060 ps
T1093 /workspace/coverage/default/15.uart_tx_ovrd.2328539528 Feb 25 01:33:50 PM PST 24 Feb 25 01:33:52 PM PST 24 2153960592 ps
T1094 /workspace/coverage/default/8.uart_intr.1328311549 Feb 25 01:33:04 PM PST 24 Feb 25 01:47:47 PM PST 24 1295208867188 ps
T1095 /workspace/coverage/default/4.uart_fifo_overflow.3377050879 Feb 25 01:32:34 PM PST 24 Feb 25 01:36:37 PM PST 24 151843730846 ps
T1096 /workspace/coverage/default/38.uart_long_xfer_wo_dly.201163976 Feb 25 01:36:47 PM PST 24 Feb 25 01:44:56 PM PST 24 227085006541 ps
T1097 /workspace/coverage/default/46.uart_noise_filter.3865548164 Feb 25 01:37:37 PM PST 24 Feb 25 01:40:28 PM PST 24 182644457910 ps
T1098 /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3375612711 Feb 25 01:38:07 PM PST 24 Feb 25 01:42:02 PM PST 24 49514844843 ps
T1099 /workspace/coverage/default/55.uart_fifo_reset.21128192 Feb 25 01:38:20 PM PST 24 Feb 25 01:39:20 PM PST 24 37694718202 ps
T1100 /workspace/coverage/default/18.uart_alert_test.4224244185 Feb 25 01:34:12 PM PST 24 Feb 25 01:34:12 PM PST 24 23842390 ps
T324 /workspace/coverage/default/148.uart_fifo_reset.944791843 Feb 25 01:39:23 PM PST 24 Feb 25 01:40:24 PM PST 24 101779915735 ps
T1101 /workspace/coverage/default/37.uart_alert_test.56787865 Feb 25 01:36:47 PM PST 24 Feb 25 01:36:50 PM PST 24 35408903 ps
T390 /workspace/coverage/default/14.uart_stress_all.3029831155 Feb 25 01:33:43 PM PST 24 Feb 25 01:39:10 PM PST 24 467057133261 ps
T329 /workspace/coverage/default/137.uart_fifo_reset.4164128337 Feb 25 01:39:21 PM PST 24 Feb 25 01:39:39 PM PST 24 20738543551 ps
T1102 /workspace/coverage/default/28.uart_long_xfer_wo_dly.2591675097 Feb 25 01:35:36 PM PST 24 Feb 25 01:41:41 PM PST 24 95688607324 ps
T1103 /workspace/coverage/default/196.uart_fifo_reset.90098118 Feb 25 01:39:51 PM PST 24 Feb 25 01:40:09 PM PST 24 8517809068 ps
T1104 /workspace/coverage/default/215.uart_fifo_reset.3361130678 Feb 25 01:40:02 PM PST 24 Feb 25 01:40:18 PM PST 24 38895221877 ps
T1105 /workspace/coverage/default/41.uart_tx_ovrd.3592402405 Feb 25 01:37:14 PM PST 24 Feb 25 01:37:16 PM PST 24 1853655891 ps
T1106 /workspace/coverage/default/9.uart_loopback.2746177994 Feb 25 01:33:12 PM PST 24 Feb 25 01:33:15 PM PST 24 4348961733 ps
T1107 /workspace/coverage/default/12.uart_fifo_full.3782716111 Feb 25 01:33:31 PM PST 24 Feb 25 01:35:36 PM PST 24 213887353392 ps
T1108 /workspace/coverage/default/22.uart_tx_ovrd.3893778540 Feb 25 01:35:06 PM PST 24 Feb 25 01:35:09 PM PST 24 2338044776 ps
T1109 /workspace/coverage/default/3.uart_tx_rx.923236431 Feb 25 01:32:50 PM PST 24 Feb 25 01:32:59 PM PST 24 42401411944 ps
T71 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3982092638 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 155762014 ps
T1110 /workspace/coverage/cover_reg_top/27.uart_intr_test.2846309355 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 14158392 ps
T1111 /workspace/coverage/cover_reg_top/5.uart_intr_test.709107968 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:53 PM PST 24 13780519 ps
T1112 /workspace/coverage/cover_reg_top/32.uart_intr_test.680107603 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:58 PM PST 24 49917751 ps
T72 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3857260051 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:03 PM PST 24 14474927 ps
T1113 /workspace/coverage/cover_reg_top/6.uart_tl_errors.409515191 Feb 25 12:30:20 PM PST 24 Feb 25 12:30:22 PM PST 24 773225684 ps
T1114 /workspace/coverage/cover_reg_top/47.uart_intr_test.552053382 Feb 25 12:31:00 PM PST 24 Feb 25 12:31:02 PM PST 24 53722676 ps
T1115 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2127234033 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:57 PM PST 24 12766010 ps
T82 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2439200124 Feb 25 12:31:07 PM PST 24 Feb 25 12:31:08 PM PST 24 15255382 ps
T83 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1661320813 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:50 PM PST 24 33228312 ps
T1116 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2923115958 Feb 25 12:30:58 PM PST 24 Feb 25 12:31:00 PM PST 24 166618891 ps
T84 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4016495522 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 84126996 ps
T1117 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3040212404 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:58 PM PST 24 63611099 ps
T1118 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3794717232 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:54 PM PST 24 40691181 ps
T1119 /workspace/coverage/cover_reg_top/21.uart_intr_test.4002095878 Feb 25 12:31:33 PM PST 24 Feb 25 12:31:35 PM PST 24 22128095 ps
T85 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3153487733 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:32 PM PST 24 46403794 ps
T86 /workspace/coverage/cover_reg_top/0.uart_csr_rw.150460693 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 13820266 ps
T91 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2771493776 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:45 PM PST 24 144041874 ps
T87 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2960042274 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 13801174 ps
T92 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4153109545 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 83866538 ps
T93 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2298661030 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 174765891 ps
T1120 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.102334876 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:50 PM PST 24 71052901 ps
T100 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4010184577 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 179351336 ps
T1121 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2374606090 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:45 PM PST 24 11797570 ps
T1122 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3879975927 Feb 25 12:30:48 PM PST 24 Feb 25 12:30:49 PM PST 24 46200971 ps
T88 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2645279619 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 12594984 ps
T73 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1291268635 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:54 PM PST 24 15316803 ps
T74 /workspace/coverage/cover_reg_top/7.uart_csr_rw.923373294 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 65031835 ps
T1123 /workspace/coverage/cover_reg_top/10.uart_intr_test.478835945 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:56 PM PST 24 20787577 ps
T1124 /workspace/coverage/cover_reg_top/18.uart_intr_test.601461207 Feb 25 12:30:48 PM PST 24 Feb 25 12:30:49 PM PST 24 12885866 ps
T1125 /workspace/coverage/cover_reg_top/41.uart_intr_test.1871868566 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:58 PM PST 24 137708961 ps
T89 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3415512114 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 12402799 ps
T1126 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1622194293 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 75610336 ps
T1127 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3868471353 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:54 PM PST 24 54759552 ps
T90 /workspace/coverage/cover_reg_top/1.uart_csr_rw.727150897 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:33 PM PST 24 12350277 ps
T1128 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2084213857 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:54 PM PST 24 598149228 ps
T1129 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.506217036 Feb 25 12:30:53 PM PST 24 Feb 25 12:30:54 PM PST 24 23303179 ps
T1130 /workspace/coverage/cover_reg_top/13.uart_intr_test.1927137123 Feb 25 12:30:54 PM PST 24 Feb 25 12:31:00 PM PST 24 125711044 ps
T1131 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2046733463 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 84011957 ps
T1132 /workspace/coverage/cover_reg_top/36.uart_intr_test.3778726557 Feb 25 12:31:20 PM PST 24 Feb 25 12:31:30 PM PST 24 17518120 ps
T1133 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.667237962 Feb 25 12:30:58 PM PST 24 Feb 25 12:31:00 PM PST 24 34750366 ps
T1134 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1120413829 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:46 PM PST 24 249494899 ps
T1135 /workspace/coverage/cover_reg_top/13.uart_csr_rw.37947919 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 45246866 ps
T99 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3833770031 Feb 25 12:30:23 PM PST 24 Feb 25 12:30:25 PM PST 24 324024117 ps
T1136 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.960413992 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 138412275 ps
T1137 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2506514649 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:53 PM PST 24 159946475 ps
T75 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2822385742 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:32 PM PST 24 125540441 ps
T1138 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1427402602 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 25711699 ps
T1139 /workspace/coverage/cover_reg_top/35.uart_intr_test.425851179 Feb 25 12:31:08 PM PST 24 Feb 25 12:31:08 PM PST 24 15322770 ps
T1140 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3228627871 Feb 25 12:30:53 PM PST 24 Feb 25 12:30:55 PM PST 24 53202356 ps
T1141 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1004002449 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:45 PM PST 24 85686803 ps
T1142 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1777670341 Feb 25 12:30:48 PM PST 24 Feb 25 12:30:49 PM PST 24 66186616 ps
T1143 /workspace/coverage/cover_reg_top/26.uart_intr_test.2595894945 Feb 25 12:31:23 PM PST 24 Feb 25 12:31:24 PM PST 24 14198224 ps
T1144 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2171523507 Feb 25 12:31:27 PM PST 24 Feb 25 12:31:28 PM PST 24 26150721 ps
T1145 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3539065759 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:47 PM PST 24 182228845 ps
T1146 /workspace/coverage/cover_reg_top/49.uart_intr_test.79773226 Feb 25 12:31:00 PM PST 24 Feb 25 12:31:02 PM PST 24 28622758 ps
T1147 /workspace/coverage/cover_reg_top/16.uart_csr_rw.4118978992 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 50099416 ps
T1148 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2452486939 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 35529771 ps
T1149 /workspace/coverage/cover_reg_top/1.uart_intr_test.2289478166 Feb 25 12:30:43 PM PST 24 Feb 25 12:30:44 PM PST 24 49608837 ps
T1150 /workspace/coverage/cover_reg_top/16.uart_intr_test.3205433066 Feb 25 12:30:53 PM PST 24 Feb 25 12:30:54 PM PST 24 22039841 ps
T94 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.621857101 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:54 PM PST 24 133429373 ps
T76 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2416120190 Feb 25 12:30:26 PM PST 24 Feb 25 12:30:26 PM PST 24 15805559 ps
T1151 /workspace/coverage/cover_reg_top/39.uart_intr_test.104461012 Feb 25 12:31:10 PM PST 24 Feb 25 12:31:10 PM PST 24 39004911 ps
T1152 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4112376665 Feb 25 12:30:22 PM PST 24 Feb 25 12:30:23 PM PST 24 36777370 ps
T1153 /workspace/coverage/cover_reg_top/31.uart_intr_test.1653339852 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:03 PM PST 24 14171214 ps
T1154 /workspace/coverage/cover_reg_top/37.uart_intr_test.1299815997 Feb 25 12:31:16 PM PST 24 Feb 25 12:31:16 PM PST 24 43508068 ps
T1155 /workspace/coverage/cover_reg_top/9.uart_intr_test.282431013 Feb 25 12:30:55 PM PST 24 Feb 25 12:31:06 PM PST 24 33682506 ps
T1156 /workspace/coverage/cover_reg_top/15.uart_intr_test.1534406141 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 26089342 ps
T1157 /workspace/coverage/cover_reg_top/24.uart_intr_test.1161868291 Feb 25 12:31:08 PM PST 24 Feb 25 12:31:09 PM PST 24 39324872 ps
T1158 /workspace/coverage/cover_reg_top/33.uart_intr_test.723589076 Feb 25 12:31:05 PM PST 24 Feb 25 12:31:06 PM PST 24 12513370 ps
T1159 /workspace/coverage/cover_reg_top/18.uart_csr_rw.268698345 Feb 25 12:31:15 PM PST 24 Feb 25 12:31:16 PM PST 24 14708368 ps
T77 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1173321136 Feb 25 12:30:24 PM PST 24 Feb 25 12:30:25 PM PST 24 63179559 ps
T1160 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1660665036 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:43 PM PST 24 33276173 ps
T1161 /workspace/coverage/cover_reg_top/44.uart_intr_test.2349818331 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:02 PM PST 24 29558826 ps
T1162 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2296047200 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:51 PM PST 24 186077629 ps
T1163 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2060475377 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:53 PM PST 24 30780744 ps
T1164 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.946407912 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:56 PM PST 24 27912929 ps
T78 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.429597219 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:58 PM PST 24 59765166 ps
T97 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4147775103 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 593238599 ps
T1165 /workspace/coverage/cover_reg_top/20.uart_intr_test.1744781010 Feb 25 12:31:08 PM PST 24 Feb 25 12:31:08 PM PST 24 15922240 ps
T1166 /workspace/coverage/cover_reg_top/29.uart_intr_test.25076686 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:05 PM PST 24 41209616 ps
T1167 /workspace/coverage/cover_reg_top/12.uart_intr_test.3401031253 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 14887621 ps
T1168 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3106970615 Feb 25 12:31:04 PM PST 24 Feb 25 12:31:06 PM PST 24 60634992 ps
T1169 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2449752764 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:43 PM PST 24 20124434 ps
T98 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3777798080 Feb 25 12:30:58 PM PST 24 Feb 25 12:31:05 PM PST 24 1666902357 ps
T101 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.300106860 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 190068606 ps
T1170 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2841877829 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:22 PM PST 24 12687375 ps
T1171 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2972923680 Feb 25 12:30:38 PM PST 24 Feb 25 12:30:38 PM PST 24 32202124 ps
T1172 /workspace/coverage/cover_reg_top/8.uart_intr_test.2363168265 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 27416424 ps
T1173 /workspace/coverage/cover_reg_top/14.uart_intr_test.2434611354 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 27607944 ps
T1174 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2391751481 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:47 PM PST 24 139967647 ps
T1175 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1672156306 Feb 25 12:30:41 PM PST 24 Feb 25 12:30:42 PM PST 24 312868034 ps
T1176 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2312389936 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:56 PM PST 24 50739471 ps
T95 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3178477554 Feb 25 12:30:57 PM PST 24 Feb 25 12:30:58 PM PST 24 55843934 ps
T1177 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3811931145 Feb 25 12:31:07 PM PST 24 Feb 25 12:31:08 PM PST 24 34279700 ps
T1178 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3271662056 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 19275888 ps
T409 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.219738101 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:56 PM PST 24 45531287 ps
T1179 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.102779091 Feb 25 12:30:41 PM PST 24 Feb 25 12:30:42 PM PST 24 28942225 ps
T1180 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3881041449 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:08 PM PST 24 14826175 ps
T1181 /workspace/coverage/cover_reg_top/4.uart_intr_test.2455974928 Feb 25 12:30:38 PM PST 24 Feb 25 12:30:38 PM PST 24 16023744 ps
T1182 /workspace/coverage/cover_reg_top/1.uart_tl_errors.127257991 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:52 PM PST 24 252386194 ps
T1183 /workspace/coverage/cover_reg_top/6.uart_intr_test.1642348222 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:39 PM PST 24 80833085 ps
T1184 /workspace/coverage/cover_reg_top/30.uart_intr_test.1911447656 Feb 25 12:31:04 PM PST 24 Feb 25 12:31:10 PM PST 24 37859531 ps
T1185 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2569415954 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:40 PM PST 24 18820108 ps
T1186 /workspace/coverage/cover_reg_top/43.uart_intr_test.536027676 Feb 25 12:31:12 PM PST 24 Feb 25 12:31:13 PM PST 24 33154851 ps
T1187 /workspace/coverage/cover_reg_top/18.uart_tl_errors.92357351 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:52 PM PST 24 415687566 ps
T1188 /workspace/coverage/cover_reg_top/17.uart_intr_test.452630530 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:05 PM PST 24 37123334 ps
T1189 /workspace/coverage/cover_reg_top/22.uart_intr_test.3931248596 Feb 25 12:31:30 PM PST 24 Feb 25 12:31:31 PM PST 24 12876118 ps
T1190 /workspace/coverage/cover_reg_top/10.uart_tl_errors.4214651206 Feb 25 12:30:40 PM PST 24 Feb 25 12:30:42 PM PST 24 422638695 ps
T96 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1088980495 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 52874782 ps
T410 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3871690014 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 93858780 ps
T1191 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.746859785 Feb 25 12:30:53 PM PST 24 Feb 25 12:30:54 PM PST 24 21252867 ps
T1192 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3766817296 Feb 25 12:31:08 PM PST 24 Feb 25 12:31:10 PM PST 24 169233058 ps
T79 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3830742284 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:04 PM PST 24 62458966 ps
T1193 /workspace/coverage/cover_reg_top/34.uart_intr_test.1123216542 Feb 25 12:31:10 PM PST 24 Feb 25 12:31:11 PM PST 24 71223085 ps
T1194 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3472744861 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 110005099 ps
T1195 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3823973591 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 51128274 ps
T1196 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2558756989 Feb 25 12:30:20 PM PST 24 Feb 25 12:30:21 PM PST 24 17999936 ps
T1197 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1542851029 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:58 PM PST 24 355685598 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2542021426 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:04 PM PST 24 343172790 ps
T1199 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1315374380 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:49 PM PST 24 170693761 ps
T1200 /workspace/coverage/cover_reg_top/25.uart_intr_test.1424886713 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:04 PM PST 24 46905070 ps
T1201 /workspace/coverage/cover_reg_top/28.uart_intr_test.3167029386 Feb 25 12:31:30 PM PST 24 Feb 25 12:31:31 PM PST 24 25210259 ps
T1202 /workspace/coverage/cover_reg_top/45.uart_intr_test.1155450722 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 27120163 ps
T1203 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2214725624 Feb 25 12:31:00 PM PST 24 Feb 25 12:31:02 PM PST 24 54657201 ps
T1204 /workspace/coverage/cover_reg_top/3.uart_intr_test.2291028419 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:20 PM PST 24 23255417 ps
T1205 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3583503637 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 75207131 ps
T81 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1245530489 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:36 PM PST 24 103225983 ps
T1206 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4260735781 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:58 PM PST 24 91076564 ps
T1207 /workspace/coverage/cover_reg_top/11.uart_intr_test.2179025091 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:37 PM PST 24 22578118 ps
T1208 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3395826967 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 12512710 ps
T1209 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1410156227 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 27519820 ps
T1210 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2129482850 Feb 25 12:30:56 PM PST 24 Feb 25 12:30:59 PM PST 24 121611087 ps
T1211 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3506902050 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:53 PM PST 24 26142959 ps
T1212 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3881305121 Feb 25 12:30:57 PM PST 24 Feb 25 12:30:59 PM PST 24 232682014 ps
T1213 /workspace/coverage/cover_reg_top/7.uart_intr_test.3481261270 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:54 PM PST 24 38056395 ps
T1214 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2294558991 Feb 25 12:31:06 PM PST 24 Feb 25 12:31:07 PM PST 24 37428143 ps
T1215 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3150947777 Feb 25 12:30:48 PM PST 24 Feb 25 12:30:53 PM PST 24 64516236 ps
T1216 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3491775274 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:52 PM PST 24 22156877 ps
T1217 /workspace/coverage/cover_reg_top/23.uart_intr_test.478961037 Feb 25 12:31:26 PM PST 24 Feb 25 12:31:26 PM PST 24 30909031 ps
T1218 /workspace/coverage/cover_reg_top/48.uart_intr_test.3659613308 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:53 PM PST 24 89194481 ps
T1219 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3593640234 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 18796192 ps
T1220 /workspace/coverage/cover_reg_top/19.uart_intr_test.964825084 Feb 25 12:31:11 PM PST 24 Feb 25 12:31:12 PM PST 24 13148622 ps
T1221 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1260229638 Feb 25 12:31:10 PM PST 24 Feb 25 12:31:11 PM PST 24 21530493 ps
T1222 /workspace/coverage/cover_reg_top/38.uart_intr_test.2323587399 Feb 25 12:31:05 PM PST 24 Feb 25 12:31:06 PM PST 24 49773878 ps
T1223 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.321439105 Feb 25 12:30:48 PM PST 24 Feb 25 12:30:49 PM PST 24 119618801 ps
T1224 /workspace/coverage/cover_reg_top/46.uart_intr_test.557992755 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:03 PM PST 24 23623003 ps
T1225 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2379975641 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:32 PM PST 24 45321486 ps
T1226 /workspace/coverage/cover_reg_top/42.uart_intr_test.3131383546 Feb 25 12:30:56 PM PST 24 Feb 25 12:31:02 PM PST 24 12927671 ps
T1227 /workspace/coverage/cover_reg_top/11.uart_tl_errors.96260439 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:37 PM PST 24 48972796 ps
T1228 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2768332406 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:52 PM PST 24 54256207 ps
T1229 /workspace/coverage/cover_reg_top/40.uart_intr_test.3996235714 Feb 25 12:30:57 PM PST 24 Feb 25 12:30:58 PM PST 24 13808020 ps
T1230 /workspace/coverage/cover_reg_top/2.uart_intr_test.125375794 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:55 PM PST 24 11520148 ps
T1231 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2497791776 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:52 PM PST 24 30410213 ps
T1232 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2133486867 Feb 25 12:31:07 PM PST 24 Feb 25 12:31:08 PM PST 24 16658150 ps
T1233 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3213411659 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:35 PM PST 24 26492673 ps
T1234 /workspace/coverage/cover_reg_top/0.uart_intr_test.2334425689 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:32 PM PST 24 47213958 ps
T1235 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3721540695 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:36 PM PST 24 37086944 ps
T1236 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2805369905 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 50306664 ps
T1237 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2499597145 Feb 25 12:31:25 PM PST 24 Feb 25 12:31:26 PM PST 24 43756173 ps
T1238 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2200209806 Feb 25 12:31:18 PM PST 24 Feb 25 12:31:18 PM PST 24 15139509 ps
T1239 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1755265353 Feb 25 12:30:55 PM PST 24 Feb 25 12:31:07 PM PST 24 120496401 ps
T1240 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3169728568 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:43 PM PST 24 134129731 ps
T80 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1627205085 Feb 25 12:30:26 PM PST 24 Feb 25 12:30:27 PM PST 24 40358418 ps
T408 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.244137662 Feb 25 12:30:50 PM PST 24 Feb 25 12:30:51 PM PST 24 86042311 ps

Test location /workspace/coverage/default/7.uart_rx_parity_err.2505004735
Short name T4
Test name
Test status
Simulation time 138430427744 ps
CPU time 77.16 seconds
Started Feb 25 01:32:58 PM PST 24
Finished Feb 25 01:34:15 PM PST 24
Peak memory 199628 kb
Host smart-889c6ca0-2a74-4144-b909-1b4c391541da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505004735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2505004735
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2569650542
Short name T15
Test name
Test status
Simulation time 83763824910 ps
CPU time 1691.67 seconds
Started Feb 25 01:33:55 PM PST 24
Finished Feb 25 02:02:07 PM PST 24
Peak memory 216176 kb
Host smart-3933e310-133a-479c-9568-4e84ce58cb1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569650542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2569650542
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.946156484
Short name T17
Test name
Test status
Simulation time 1251971440021 ps
CPU time 1388.91 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:58:15 PM PST 24
Peak memory 199648 kb
Host smart-7706e972-b188-4ede-8fdc-2ccd86b35f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946156484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.946156484
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.1266467239
Short name T22
Test name
Test status
Simulation time 531287724220 ps
CPU time 1350.69 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 01:57:39 PM PST 24
Peak memory 199708 kb
Host smart-15b04cb1-8b4d-4d9a-bd0f-4aca05e44667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266467239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1266467239
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3806911263
Short name T5
Test name
Test status
Simulation time 238096470683 ps
CPU time 36.91 seconds
Started Feb 25 01:39:25 PM PST 24
Finished Feb 25 01:40:02 PM PST 24
Peak memory 199640 kb
Host smart-028335e9-b533-4f3b-81a6-253b4e98cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806911263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3806911263
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.1020180650
Short name T418
Test name
Test status
Simulation time 257823586683 ps
CPU time 1367.45 seconds
Started Feb 25 01:37:22 PM PST 24
Finished Feb 25 02:00:12 PM PST 24
Peak memory 208116 kb
Host smart-87c19b90-510b-4f07-a385-ef88f4b60ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020180650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1020180650
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.4160720213
Short name T179
Test name
Test status
Simulation time 787582221124 ps
CPU time 198.52 seconds
Started Feb 25 01:33:37 PM PST 24
Finished Feb 25 01:36:56 PM PST 24
Peak memory 199588 kb
Host smart-1a4e80a3-89c6-44f8-bc19-72036f9acfe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160720213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4160720213
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3081095599
Short name T12
Test name
Test status
Simulation time 53541588936 ps
CPU time 234.48 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:36:57 PM PST 24
Peak memory 199676 kb
Host smart-96a69a2e-4956-46a0-a55d-f629da8184d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081095599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3081095599
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.4154205514
Short name T29
Test name
Test status
Simulation time 271156275866 ps
CPU time 398.78 seconds
Started Feb 25 01:38:04 PM PST 24
Finished Feb 25 01:44:43 PM PST 24
Peak memory 224540 kb
Host smart-c1e2c1ab-31e3-4da3-b80b-2a45fdec6ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154205514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4154205514
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1261110973
Short name T33
Test name
Test status
Simulation time 221446452 ps
CPU time 0.84 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:32:37 PM PST 24
Peak memory 217184 kb
Host smart-e8cc36eb-780d-4d36-9d19-75f74c64753d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261110973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1261110973
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/35.uart_stress_all.3785885304
Short name T373
Test name
Test status
Simulation time 454931604707 ps
CPU time 142.71 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:38:53 PM PST 24
Peak memory 208024 kb
Host smart-dcfabf0c-7f6a-4cd8-b1cd-6b1507327efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785885304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3785885304
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.429725402
Short name T41
Test name
Test status
Simulation time 57975265100 ps
CPU time 608.71 seconds
Started Feb 25 01:38:18 PM PST 24
Finished Feb 25 01:48:28 PM PST 24
Peak memory 224512 kb
Host smart-ce3f403e-1ff4-4e9b-80d0-a583e05f6a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429725402 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.429725402
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1291268635
Short name T73
Test name
Test status
Simulation time 15316803 ps
CPU time 0.59 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 194288 kb
Host smart-eb55960f-0d9b-48ef-a759-36780e4b5d63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291268635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1291268635
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1477609633
Short name T40
Test name
Test status
Simulation time 1526842765110 ps
CPU time 2195.69 seconds
Started Feb 25 01:38:55 PM PST 24
Finished Feb 25 02:15:32 PM PST 24
Peak memory 240940 kb
Host smart-184188fe-5b14-4559-a5f6-3df1b3a35164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477609633 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1477609633
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.1796124176
Short name T11
Test name
Test status
Simulation time 1328541047973 ps
CPU time 347.75 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:41:54 PM PST 24
Peak memory 199520 kb
Host smart-f70858cc-359a-4837-89a7-8b480f5c8c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796124176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1796124176
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all.2118585538
Short name T212
Test name
Test status
Simulation time 247662285168 ps
CPU time 548.02 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:44:06 PM PST 24
Peak memory 199664 kb
Host smart-36ed075e-53d9-440f-a1e8-4f5500a8b432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118585538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2118585538
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.430121081
Short name T354
Test name
Test status
Simulation time 178038080132 ps
CPU time 135.93 seconds
Started Feb 25 01:33:00 PM PST 24
Finished Feb 25 01:35:16 PM PST 24
Peak memory 199588 kb
Host smart-29b30d02-be76-45bf-b211-407f0f9335b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430121081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.430121081
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_alert_test.2786498402
Short name T102
Test name
Test status
Simulation time 76127631 ps
CPU time 0.57 seconds
Started Feb 25 01:33:56 PM PST 24
Finished Feb 25 01:33:57 PM PST 24
Peak memory 195060 kb
Host smart-0afd3f8b-ff2b-4ba2-9677-67a7bf2fd3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786498402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2786498402
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3777798080
Short name T98
Test name
Test status
Simulation time 1666902357 ps
CPU time 1.61 seconds
Started Feb 25 12:30:58 PM PST 24
Finished Feb 25 12:31:05 PM PST 24
Peak memory 199100 kb
Host smart-d57a3067-a801-4a27-b171-4d4a3de9e3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777798080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3777798080
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/30.uart_fifo_full.424488413
Short name T132
Test name
Test status
Simulation time 242016709080 ps
CPU time 95.45 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:37:22 PM PST 24
Peak memory 199696 kb
Host smart-94618ffe-feb1-4602-8b99-6ce23e6e4343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424488413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.424488413
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_stress_all.949146232
Short name T141
Test name
Test status
Simulation time 1165984858078 ps
CPU time 633.16 seconds
Started Feb 25 01:33:27 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 207972 kb
Host smart-e9dd3daa-4dab-4a67-8be3-ca722e18480f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949146232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.949146232
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2687563076
Short name T49
Test name
Test status
Simulation time 243522922265 ps
CPU time 42.15 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:41:13 PM PST 24
Peak memory 199604 kb
Host smart-a46a6d19-e823-43ed-98b5-b6e47986688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687563076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2687563076
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3127827179
Short name T226
Test name
Test status
Simulation time 91580709330 ps
CPU time 72.12 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:33:41 PM PST 24
Peak memory 199620 kb
Host smart-2d7632c2-28b7-4d6d-bc8e-0f6c1c44c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127827179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3127827179
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1404167426
Short name T349
Test name
Test status
Simulation time 144267190946 ps
CPU time 214.78 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:41:14 PM PST 24
Peak memory 199496 kb
Host smart-c0dc167e-9d0c-4622-8b52-eef0c6cf94fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404167426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1404167426
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.150460693
Short name T86
Test name
Test status
Simulation time 13820266 ps
CPU time 0.6 seconds
Started Feb 25 12:30:33 PM PST 24
Finished Feb 25 12:30:34 PM PST 24
Peak memory 195384 kb
Host smart-a38667fb-3455-49f8-8edf-0a85ecef8f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150460693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.150460693
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3359141889
Short name T332
Test name
Test status
Simulation time 151294533020 ps
CPU time 68.3 seconds
Started Feb 25 01:35:03 PM PST 24
Finished Feb 25 01:36:15 PM PST 24
Peak memory 199656 kb
Host smart-48030c78-019c-4cab-958c-0ca28b40e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359141889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3359141889
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3178477554
Short name T95
Test name
Test status
Simulation time 55843934 ps
CPU time 0.9 seconds
Started Feb 25 12:30:57 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 198480 kb
Host smart-ac9b3cf8-03c8-42cc-bef5-074f54fd0866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178477554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3178477554
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3379098463
Short name T151
Test name
Test status
Simulation time 127277789470 ps
CPU time 189.76 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:38:16 PM PST 24
Peak memory 199532 kb
Host smart-4b5b6333-d718-45bc-aba6-0f0e40fd7f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379098463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3379098463
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3959551146
Short name T116
Test name
Test status
Simulation time 127376570514 ps
CPU time 263 seconds
Started Feb 25 01:33:04 PM PST 24
Finished Feb 25 01:37:27 PM PST 24
Peak memory 216396 kb
Host smart-ac102db7-f84c-4832-a627-9ff9719cf12b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959551146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3959551146
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1527780774
Short name T127
Test name
Test status
Simulation time 28239445716 ps
CPU time 18.29 seconds
Started Feb 25 01:33:44 PM PST 24
Finished Feb 25 01:34:02 PM PST 24
Peak memory 199512 kb
Host smart-8b3fbd90-f448-4e28-8581-357afac77fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527780774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1527780774
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_noise_filter.178524162
Short name T28
Test name
Test status
Simulation time 221988724488 ps
CPU time 117.49 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 199632 kb
Host smart-ce0df486-c2b2-4b74-8a7a-845b7ce68b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178524162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.178524162
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4078552639
Short name T10
Test name
Test status
Simulation time 54757890294 ps
CPU time 24.94 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:39:27 PM PST 24
Peak memory 199640 kb
Host smart-2b7b6dfe-a18d-43d5-b64e-14b9c0a70b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078552639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4078552639
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1132715467
Short name T186
Test name
Test status
Simulation time 26961714801 ps
CPU time 14.2 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 199580 kb
Host smart-d6ce2860-b202-4cec-b716-3f5a908efcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132715467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1132715467
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2369815841
Short name T131
Test name
Test status
Simulation time 13278407798 ps
CPU time 5.77 seconds
Started Feb 25 01:39:39 PM PST 24
Finished Feb 25 01:39:45 PM PST 24
Peak memory 198888 kb
Host smart-62a78c6c-c451-44ff-8230-29059ae54949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369815841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2369815841
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1286290059
Short name T174
Test name
Test status
Simulation time 75260171940 ps
CPU time 123.24 seconds
Started Feb 25 01:40:24 PM PST 24
Finished Feb 25 01:42:27 PM PST 24
Peak memory 199664 kb
Host smart-8da6bbb5-d5f4-43cb-b49a-0d756febcb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286290059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1286290059
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3016375485
Short name T178
Test name
Test status
Simulation time 125231131607 ps
CPU time 35.51 seconds
Started Feb 25 01:37:48 PM PST 24
Finished Feb 25 01:38:23 PM PST 24
Peak memory 199432 kb
Host smart-54dbae34-8d63-4b64-946f-23796ce0dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016375485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3016375485
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2304920405
Short name T114
Test name
Test status
Simulation time 2019372212797 ps
CPU time 992.89 seconds
Started Feb 25 01:38:59 PM PST 24
Finished Feb 25 01:55:32 PM PST 24
Peak memory 217232 kb
Host smart-3a0aefc4-bfb4-4740-b0db-3fb62d657d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304920405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2304920405
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1046774600
Short name T328
Test name
Test status
Simulation time 88589128508 ps
CPU time 23.42 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:39:28 PM PST 24
Peak memory 199168 kb
Host smart-9934e231-1c4d-4019-a81a-b6f73fffd14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046774600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1046774600
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2064649706
Short name T145
Test name
Test status
Simulation time 29313080001 ps
CPU time 44.47 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:48 PM PST 24
Peak memory 199696 kb
Host smart-6720dffe-6582-45e9-abc2-9c77ea967bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064649706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2064649706
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3294419010
Short name T289
Test name
Test status
Simulation time 298033436195 ps
CPU time 28.98 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:40:20 PM PST 24
Peak memory 199428 kb
Host smart-d6cb1b8b-0098-4bb0-b635-d70a321cff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294419010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3294419010
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2909769176
Short name T149
Test name
Test status
Simulation time 50744254696 ps
CPU time 90.51 seconds
Started Feb 25 01:35:58 PM PST 24
Finished Feb 25 01:37:29 PM PST 24
Peak memory 199336 kb
Host smart-5134411d-1735-4cc6-b284-882a0c55a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909769176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2909769176
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4069956575
Short name T401
Test name
Test status
Simulation time 36743811377 ps
CPU time 30.1 seconds
Started Feb 25 01:33:27 PM PST 24
Finished Feb 25 01:33:57 PM PST 24
Peak memory 199620 kb
Host smart-777cb516-b5eb-40ef-b470-5ff5aa2130af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069956575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4069956575
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1707195429
Short name T185
Test name
Test status
Simulation time 23476682814 ps
CPU time 12.47 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:39:53 PM PST 24
Peak memory 199692 kb
Host smart-d2a23fe0-83be-44ad-9299-437edc5170b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707195429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1707195429
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3693494150
Short name T200
Test name
Test status
Simulation time 113721945047 ps
CPU time 82.09 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:41:24 PM PST 24
Peak memory 199680 kb
Host smart-97c37d58-d50d-4147-83ea-860c66e2dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693494150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3693494150
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3340869072
Short name T314
Test name
Test status
Simulation time 16623491059 ps
CPU time 28.09 seconds
Started Feb 25 01:40:16 PM PST 24
Finished Feb 25 01:40:45 PM PST 24
Peak memory 199292 kb
Host smart-8cc2f4d3-3915-4ff0-80ae-f61f15c54adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340869072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3340869072
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4143302735
Short name T136
Test name
Test status
Simulation time 312805344560 ps
CPU time 33.1 seconds
Started Feb 25 01:40:21 PM PST 24
Finished Feb 25 01:40:56 PM PST 24
Peak memory 199688 kb
Host smart-b330efcb-f4f4-44f5-b716-541983282414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143302735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4143302735
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1086745861
Short name T259
Test name
Test status
Simulation time 32787945889 ps
CPU time 286.75 seconds
Started Feb 25 01:37:15 PM PST 24
Finished Feb 25 01:42:01 PM PST 24
Peak memory 207916 kb
Host smart-d10a8662-f7a0-4758-9876-522facbae6bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086745861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1086745861
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.3898624263
Short name T294
Test name
Test status
Simulation time 461504000685 ps
CPU time 636.68 seconds
Started Feb 25 01:37:22 PM PST 24
Finished Feb 25 01:48:00 PM PST 24
Peak memory 199804 kb
Host smart-8f020cca-9c7c-4e5c-9f5a-9df0bc01d5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898624263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3898624263
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1091717676
Short name T196
Test name
Test status
Simulation time 161302976508 ps
CPU time 67.04 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:40:11 PM PST 24
Peak memory 199564 kb
Host smart-b5a75bc8-be7e-4526-9365-5798d7fa0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091717676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1091717676
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2792177886
Short name T309
Test name
Test status
Simulation time 35212416603 ps
CPU time 45.85 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:39:57 PM PST 24
Peak memory 199600 kb
Host smart-559abede-79e7-4a03-a993-c20e774d6a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792177886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2792177886
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1126306822
Short name T298
Test name
Test status
Simulation time 410331314636 ps
CPU time 40.44 seconds
Started Feb 25 01:39:35 PM PST 24
Finished Feb 25 01:40:16 PM PST 24
Peak memory 199796 kb
Host smart-ce855a72-7724-4edc-aeda-9566d1f42071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126306822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1126306822
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1003686521
Short name T372
Test name
Test status
Simulation time 18259340603 ps
CPU time 27.37 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:19 PM PST 24
Peak memory 199012 kb
Host smart-4d07e99a-46bb-4778-b673-4142f5a02070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003686521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1003686521
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.3072102415
Short name T402
Test name
Test status
Simulation time 5148618334934 ps
CPU time 8312.28 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 03:53:40 PM PST 24
Peak memory 208120 kb
Host smart-28c00e3d-6b14-490c-afef-31c5f31a243d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072102415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3072102415
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2031610454
Short name T220
Test name
Test status
Simulation time 54608589780 ps
CPU time 92.55 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:41:52 PM PST 24
Peak memory 199692 kb
Host smart-a1fbfdd5-743e-4a38-8e12-81ce56b27827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031610454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2031610454
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3424257741
Short name T258
Test name
Test status
Simulation time 86013145881 ps
CPU time 36.24 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:41:06 PM PST 24
Peak memory 199408 kb
Host smart-4372f506-6e7d-4c85-a7c2-b40716856c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424257741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3424257741
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2801537365
Short name T187
Test name
Test status
Simulation time 33397451551 ps
CPU time 47.81 seconds
Started Feb 25 01:38:01 PM PST 24
Finished Feb 25 01:38:49 PM PST 24
Peak memory 199220 kb
Host smart-3eb07a66-d7d5-4458-828f-9086f547f5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801537365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2801537365
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3609602805
Short name T905
Test name
Test status
Simulation time 88211093458 ps
CPU time 132.33 seconds
Started Feb 25 01:38:54 PM PST 24
Finished Feb 25 01:41:08 PM PST 24
Peak memory 199704 kb
Host smart-9d07fb45-f74f-4ff1-ad18-022a24893b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609602805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3609602805
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1554396155
Short name T183
Test name
Test status
Simulation time 69595756915 ps
CPU time 28.73 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 199492 kb
Host smart-817fcd4d-66f6-4163-a53b-1dffbbfc33ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554396155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1554396155
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3740105065
Short name T138
Test name
Test status
Simulation time 18597028276 ps
CPU time 30.59 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:39:51 PM PST 24
Peak memory 199544 kb
Host smart-c671b7c8-aec4-4e59-a069-51a6883fcea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740105065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3740105065
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3073288105
Short name T365
Test name
Test status
Simulation time 269320011271 ps
CPU time 46.59 seconds
Started Feb 25 01:39:33 PM PST 24
Finished Feb 25 01:40:20 PM PST 24
Peak memory 199588 kb
Host smart-7d1529ac-57c6-4a3c-9a92-9539abecfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073288105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3073288105
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2296848084
Short name T277
Test name
Test status
Simulation time 35827251974 ps
CPU time 50.61 seconds
Started Feb 25 01:39:43 PM PST 24
Finished Feb 25 01:40:34 PM PST 24
Peak memory 199148 kb
Host smart-b52d06b2-ef95-45e8-a018-c8e42520ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296848084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2296848084
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3234087382
Short name T206
Test name
Test status
Simulation time 51516891690 ps
CPU time 89.68 seconds
Started Feb 25 01:39:49 PM PST 24
Finished Feb 25 01:41:18 PM PST 24
Peak memory 199640 kb
Host smart-1aefe190-1459-4eeb-9b22-8f0ad1479ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234087382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3234087382
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1270975044
Short name T327
Test name
Test status
Simulation time 7116290128 ps
CPU time 11.81 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:40:12 PM PST 24
Peak memory 199560 kb
Host smart-c5e6f9bd-4891-4dee-b4c4-ea56277469e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270975044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1270975044
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1033383066
Short name T424
Test name
Test status
Simulation time 121962473592 ps
CPU time 207.21 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:38:34 PM PST 24
Peak memory 199612 kb
Host smart-274a7c6f-e7a3-41cb-b9b5-8a70b201a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033383066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1033383066
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.4260050693
Short name T241
Test name
Test status
Simulation time 75574276078 ps
CPU time 120.75 seconds
Started Feb 25 01:40:25 PM PST 24
Finished Feb 25 01:42:26 PM PST 24
Peak memory 199708 kb
Host smart-cd5a90d8-4dae-495c-aef7-bed099caf9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260050693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4260050693
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2193207282
Short name T407
Test name
Test status
Simulation time 187873930551 ps
CPU time 148.48 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 199600 kb
Host smart-7f3b9323-2b41-4631-9bcf-5b2ce7032959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193207282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2193207282
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3542161253
Short name T900
Test name
Test status
Simulation time 45409051735 ps
CPU time 77.48 seconds
Started Feb 25 01:36:40 PM PST 24
Finished Feb 25 01:37:58 PM PST 24
Peak memory 199640 kb
Host smart-b6b035d6-28dc-42a3-b941-92b81a1b24fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542161253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3542161253
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1773121107
Short name T263
Test name
Test status
Simulation time 130818945861 ps
CPU time 133.41 seconds
Started Feb 25 01:32:50 PM PST 24
Finished Feb 25 01:35:03 PM PST 24
Peak memory 199340 kb
Host smart-dcd26e54-e10f-4035-9d76-09b347c00795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773121107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1773121107
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.4138465180
Short name T192
Test name
Test status
Simulation time 129787086159 ps
CPU time 1169.61 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:57:19 PM PST 24
Peak memory 199672 kb
Host smart-48008fd7-5c11-4583-9a92-e328b5f02db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138465180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4138465180
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1806315704
Short name T963
Test name
Test status
Simulation time 52205504478 ps
CPU time 16.55 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:33:04 PM PST 24
Peak memory 199472 kb
Host smart-86424113-302f-4516-8988-54ec052531dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806315704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1806315704
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3538423771
Short name T471
Test name
Test status
Simulation time 44515581762 ps
CPU time 463.25 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 216308 kb
Host smart-5be60021-3ece-4864-994c-5e100c4c4ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538423771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3538423771
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3871690014
Short name T410
Test name
Test status
Simulation time 93858780 ps
CPU time 1.38 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 199292 kb
Host smart-76c64b05-a54e-46e5-9ab2-57e70b27d321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871690014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3871690014
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2269959274
Short name T195
Test name
Test status
Simulation time 13104829910 ps
CPU time 11.21 seconds
Started Feb 25 01:39:06 PM PST 24
Finished Feb 25 01:39:17 PM PST 24
Peak memory 199348 kb
Host smart-1ae4e47f-7746-44a0-bc91-883f576d18ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269959274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2269959274
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3149254096
Short name T476
Test name
Test status
Simulation time 46151251358 ps
CPU time 564.08 seconds
Started Feb 25 01:33:32 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 224384 kb
Host smart-e5722e10-d32c-415e-912e-0d4b7e515b72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149254096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3149254096
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1400075367
Short name T355
Test name
Test status
Simulation time 151732270735 ps
CPU time 63.35 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:40:15 PM PST 24
Peak memory 199044 kb
Host smart-cafa287b-cee9-48ce-a6f3-649fec53d541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400075367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1400075367
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3934781416
Short name T369
Test name
Test status
Simulation time 10607952799 ps
CPU time 17.51 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:39:28 PM PST 24
Peak memory 199592 kb
Host smart-4ed57b79-9b0d-4cff-9d43-d263ebf0b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934781416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3934781416
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3029831155
Short name T390
Test name
Test status
Simulation time 467057133261 ps
CPU time 326.54 seconds
Started Feb 25 01:33:43 PM PST 24
Finished Feb 25 01:39:10 PM PST 24
Peak memory 216008 kb
Host smart-0d8074e9-0a13-46ca-bc8e-012286ab4f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029831155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3029831155
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1079242849
Short name T215
Test name
Test status
Simulation time 196147994100 ps
CPU time 334.01 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:44:55 PM PST 24
Peak memory 199612 kb
Host smart-acb322cc-d7ad-4165-86e5-5ad368179bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079242849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1079242849
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.2180369885
Short name T293
Test name
Test status
Simulation time 178125241916 ps
CPU time 161.92 seconds
Started Feb 25 01:34:00 PM PST 24
Finished Feb 25 01:36:43 PM PST 24
Peak memory 199636 kb
Host smart-4dea3a48-4035-47fa-9450-f52a37f9b8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180369885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2180369885
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2818289071
Short name T157
Test name
Test status
Simulation time 21908362888 ps
CPU time 35.91 seconds
Started Feb 25 01:39:38 PM PST 24
Finished Feb 25 01:40:14 PM PST 24
Peak memory 199124 kb
Host smart-64a220ef-78c9-4479-88ac-6c4738ab123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818289071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2818289071
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3584583926
Short name T1062
Test name
Test status
Simulation time 97194433135 ps
CPU time 73.13 seconds
Started Feb 25 01:39:42 PM PST 24
Finished Feb 25 01:40:56 PM PST 24
Peak memory 199616 kb
Host smart-49ac3bf1-f99b-48fb-bb2f-6ef81e89cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584583926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3584583926
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1827535509
Short name T315
Test name
Test status
Simulation time 271113215646 ps
CPU time 80.06 seconds
Started Feb 25 01:39:39 PM PST 24
Finished Feb 25 01:41:00 PM PST 24
Peak memory 199616 kb
Host smart-7beaea5e-63c2-4c27-97f5-e8cc732de551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827535509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1827535509
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1604510866
Short name T400
Test name
Test status
Simulation time 201406912061 ps
CPU time 180.88 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:37:12 PM PST 24
Peak memory 216216 kb
Host smart-dd7c71c1-2df3-4b8d-bae3-51ab2838726e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604510866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1604510866
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2782679206
Short name T394
Test name
Test status
Simulation time 26661834418 ps
CPU time 12.91 seconds
Started Feb 25 01:39:57 PM PST 24
Finished Feb 25 01:40:10 PM PST 24
Peak memory 199096 kb
Host smart-54bc6986-b06f-4b93-ab78-ab36cbea8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782679206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2782679206
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2570013999
Short name T267
Test name
Test status
Simulation time 100305571477 ps
CPU time 23.27 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:14 PM PST 24
Peak memory 199556 kb
Host smart-4fecc4df-f1b1-4069-9cc9-1010aca0a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570013999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2570013999
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3440032763
Short name T384
Test name
Test status
Simulation time 135490803104 ps
CPU time 128.26 seconds
Started Feb 25 01:34:23 PM PST 24
Finished Feb 25 01:36:31 PM PST 24
Peak memory 199588 kb
Host smart-d98efe31-d81f-4727-8c07-07b3738ecc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440032763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3440032763
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2527089065
Short name T265
Test name
Test status
Simulation time 31850702998 ps
CPU time 34.02 seconds
Started Feb 25 01:34:24 PM PST 24
Finished Feb 25 01:34:58 PM PST 24
Peak memory 199548 kb
Host smart-04fdf039-4c8b-4195-a9b5-8c4b019d6b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527089065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2527089065
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2676864476
Short name T304
Test name
Test status
Simulation time 13719459553 ps
CPU time 22.64 seconds
Started Feb 25 01:40:01 PM PST 24
Finished Feb 25 01:40:23 PM PST 24
Peak memory 199640 kb
Host smart-73e77676-8079-4eed-9697-ad418d3b1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676864476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2676864476
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1291550793
Short name T316
Test name
Test status
Simulation time 39827437488 ps
CPU time 31.34 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:35:29 PM PST 24
Peak memory 199300 kb
Host smart-3304c987-3134-4f74-bea7-515a6a7bc6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291550793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1291550793
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3780300821
Short name T351
Test name
Test status
Simulation time 14607826111 ps
CPU time 21.14 seconds
Started Feb 25 01:40:04 PM PST 24
Finished Feb 25 01:40:26 PM PST 24
Peak memory 199640 kb
Host smart-1478bf2a-4d83-4e94-94d2-8a5672968ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780300821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3780300821
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3812297310
Short name T378
Test name
Test status
Simulation time 41911385785 ps
CPU time 9.78 seconds
Started Feb 25 01:34:59 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 199696 kb
Host smart-9c1a4a26-ff9c-44ea-a953-66e538981373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812297310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3812297310
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1545718772
Short name T156
Test name
Test status
Simulation time 14769071603 ps
CPU time 26.03 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:40:28 PM PST 24
Peak memory 199584 kb
Host smart-52b9c285-4551-41de-89e0-01af9d9443af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545718772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1545718772
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_perf.2936279672
Short name T285
Test name
Test status
Simulation time 6689502232 ps
CPU time 190.76 seconds
Started Feb 25 01:34:55 PM PST 24
Finished Feb 25 01:38:06 PM PST 24
Peak memory 199684 kb
Host smart-90d2ffb0-83f1-4f0a-8528-1e719b474eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936279672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2936279672
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.186403613
Short name T239
Test name
Test status
Simulation time 219045139541 ps
CPU time 342.15 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 199596 kb
Host smart-1e9978bc-f66f-45b6-ba5c-6a840beb8a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186403613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.186403613
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.156469790
Short name T295
Test name
Test status
Simulation time 32481911694 ps
CPU time 33.25 seconds
Started Feb 25 01:40:16 PM PST 24
Finished Feb 25 01:40:50 PM PST 24
Peak memory 199604 kb
Host smart-ae9efd4a-dcdb-4773-ba2f-5288ef8e3e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156469790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.156469790
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1347785987
Short name T268
Test name
Test status
Simulation time 16386670505 ps
CPU time 15.03 seconds
Started Feb 25 01:40:28 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 199440 kb
Host smart-1fcbf912-20a0-4286-88fb-dc5b4f46b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347785987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1347785987
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1507555252
Short name T348
Test name
Test status
Simulation time 23902527886 ps
CPU time 39.4 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:41:09 PM PST 24
Peak memory 199584 kb
Host smart-407c42c7-81ee-433b-ac85-03bc16ed679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507555252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1507555252
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.546992802
Short name T307
Test name
Test status
Simulation time 211574469989 ps
CPU time 212.55 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:44:04 PM PST 24
Peak memory 199608 kb
Host smart-2a948a22-8bda-4e65-b0a4-5ff9db3cf9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546992802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.546992802
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1032083195
Short name T403
Test name
Test status
Simulation time 20694352390 ps
CPU time 36.57 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:41:09 PM PST 24
Peak memory 199580 kb
Host smart-15cc17b3-ff61-401c-9ca9-0ea037da950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032083195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1032083195
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.506485970
Short name T386
Test name
Test status
Simulation time 350632606434 ps
CPU time 153.9 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 199652 kb
Host smart-462b63b0-0e99-40df-b408-a6f43a79b4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506485970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.506485970
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all.260479531
Short name T311
Test name
Test status
Simulation time 237570121114 ps
CPU time 957.73 seconds
Started Feb 25 01:36:14 PM PST 24
Finished Feb 25 01:52:12 PM PST 24
Peak memory 199640 kb
Host smart-cb4625d3-79a0-4fad-adf5-cdc5c480178f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260479531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.260479531
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3972052988
Short name T385
Test name
Test status
Simulation time 72814659802 ps
CPU time 25.12 seconds
Started Feb 25 01:36:58 PM PST 24
Finished Feb 25 01:37:23 PM PST 24
Peak memory 198748 kb
Host smart-ed36f0dd-efb5-4bdc-a650-c9be6246d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972052988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3972052988
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1094710048
Short name T312
Test name
Test status
Simulation time 131227368370 ps
CPU time 78.43 seconds
Started Feb 25 01:32:50 PM PST 24
Finished Feb 25 01:34:09 PM PST 24
Peak memory 199332 kb
Host smart-62f6ccc7-e986-4efe-9404-1d422e8bad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094710048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1094710048
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_stress_all.2192832480
Short name T282
Test name
Test status
Simulation time 1262814010116 ps
CPU time 240.17 seconds
Started Feb 25 01:32:34 PM PST 24
Finished Feb 25 01:36:35 PM PST 24
Peak memory 216236 kb
Host smart-a03cb435-17e1-412a-ae1d-5b3f1f53df9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192832480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2192832480
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3494315944
Short name T399
Test name
Test status
Simulation time 104991576656 ps
CPU time 42.91 seconds
Started Feb 25 01:36:57 PM PST 24
Finished Feb 25 01:37:40 PM PST 24
Peak memory 199536 kb
Host smart-ad859277-f612-4620-996a-8d869b582e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494315944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3494315944
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_stress_all.567482811
Short name T313
Test name
Test status
Simulation time 796323231415 ps
CPU time 1214.32 seconds
Started Feb 25 01:37:12 PM PST 24
Finished Feb 25 01:57:27 PM PST 24
Peak memory 199884 kb
Host smart-6c986dd3-747d-4e24-822b-d6e7ae67b91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567482811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.567482811
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.8401719
Short name T254
Test name
Test status
Simulation time 70019552333 ps
CPU time 34.93 seconds
Started Feb 25 01:37:28 PM PST 24
Finished Feb 25 01:38:04 PM PST 24
Peak memory 199580 kb
Host smart-28f5aa26-5360-41d3-9688-86ed42fe4bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8401719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.8401719
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_perf.18277971
Short name T27
Test name
Test status
Simulation time 5941794216 ps
CPU time 150.07 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:40:20 PM PST 24
Peak memory 199620 kb
Host smart-a763fb15-fe15-4a1b-b9c4-926edb12ba5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18277971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.18277971
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/5.uart_stress_all.3600359751
Short name T142
Test name
Test status
Simulation time 645142044959 ps
CPU time 509.37 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 199660 kb
Host smart-edf97976-1358-4d41-a162-a49bdae8d78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600359751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3600359751
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.400489631
Short name T346
Test name
Test status
Simulation time 126258135795 ps
CPU time 31.42 seconds
Started Feb 25 01:38:06 PM PST 24
Finished Feb 25 01:38:38 PM PST 24
Peak memory 199628 kb
Host smart-f9fa2196-17bc-4d0f-855d-e3d0d87c8691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400489631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.400489631
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1922354586
Short name T374
Test name
Test status
Simulation time 31992619932 ps
CPU time 21.25 seconds
Started Feb 25 01:38:21 PM PST 24
Finished Feb 25 01:38:43 PM PST 24
Peak memory 199072 kb
Host smart-4c3d653e-8e9a-4ac1-b76d-5aa5916c5587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922354586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1922354586
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3065170294
Short name T38
Test name
Test status
Simulation time 69347939990 ps
CPU time 762.58 seconds
Started Feb 25 01:32:46 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 216164 kb
Host smart-242f8ce6-6fae-4df1-94d9-8b2f0688dc7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065170294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3065170294
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2706815892
Short name T68
Test name
Test status
Simulation time 168428477275 ps
CPU time 1939.04 seconds
Started Feb 25 01:38:27 PM PST 24
Finished Feb 25 02:10:46 PM PST 24
Peak memory 224484 kb
Host smart-d5ddf23e-40a9-4f24-9c39-cbf1dfcc8a63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706815892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2706815892
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3646196232
Short name T397
Test name
Test status
Simulation time 17630654504 ps
CPU time 7.39 seconds
Started Feb 25 01:38:54 PM PST 24
Finished Feb 25 01:39:03 PM PST 24
Peak memory 199596 kb
Host smart-36e58420-efc7-4c88-a85c-3d7c77412707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646196232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3646196232
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.429597219
Short name T78
Test name
Test status
Simulation time 59765166 ps
CPU time 0.77 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 196208 kb
Host smart-48382e74-ef47-412e-b3a5-e6e9f2972a15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429597219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.429597219
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1755265353
Short name T1239
Test name
Test status
Simulation time 120496401 ps
CPU time 1.49 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:31:07 PM PST 24
Peak memory 197668 kb
Host smart-d914c07f-22ab-46b0-be2a-cfb89f3ab642
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755265353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1755265353
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2416120190
Short name T76
Test name
Test status
Simulation time 15805559 ps
CPU time 0.61 seconds
Started Feb 25 12:30:26 PM PST 24
Finished Feb 25 12:30:26 PM PST 24
Peak memory 195400 kb
Host smart-731ebbc0-cfe6-4b12-a962-82a6b02b1680
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416120190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2416120190
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3271662056
Short name T1178
Test name
Test status
Simulation time 19275888 ps
CPU time 0.89 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 199908 kb
Host smart-f05b4b20-3e33-458f-a675-0e7ce73b4d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271662056 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3271662056
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2334425689
Short name T1234
Test name
Test status
Simulation time 47213958 ps
CPU time 0.56 seconds
Started Feb 25 12:30:30 PM PST 24
Finished Feb 25 12:30:32 PM PST 24
Peak memory 194380 kb
Host smart-9331c06c-f6c4-4168-9afa-beaaad126e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334425689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2334425689
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.506217036
Short name T1129
Test name
Test status
Simulation time 23303179 ps
CPU time 0.65 seconds
Started Feb 25 12:30:53 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 194456 kb
Host smart-fa11093d-9ba8-4713-8bbd-a6e272ae0af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506217036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.506217036
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3868471353
Short name T1127
Test name
Test status
Simulation time 54759552 ps
CPU time 1.18 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 200020 kb
Host smart-7fd2b48e-770f-4e98-87d9-f3d20749fc7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868471353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3868471353
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3506902050
Short name T1211
Test name
Test status
Simulation time 26142959 ps
CPU time 0.79 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 196264 kb
Host smart-2ffbfe37-218f-4611-b6be-bc6c861a8fb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506902050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3506902050
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3879975927
Short name T1122
Test name
Test status
Simulation time 46200971 ps
CPU time 1.38 seconds
Started Feb 25 12:30:48 PM PST 24
Finished Feb 25 12:30:49 PM PST 24
Peak memory 197632 kb
Host smart-890af1b3-4644-4dcd-8774-c867b1bacb51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879975927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3879975927
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2127234033
Short name T1115
Test name
Test status
Simulation time 12766010 ps
CPU time 0.58 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:57 PM PST 24
Peak memory 195388 kb
Host smart-e1caefd5-9318-49fc-b7ae-441b53c14677
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127234033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2127234033
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3491775274
Short name T1216
Test name
Test status
Simulation time 22156877 ps
CPU time 1.03 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:52 PM PST 24
Peak memory 199844 kb
Host smart-d0b9319d-a1d3-412a-9a7c-d0023c83173d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491775274 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3491775274
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.727150897
Short name T90
Test name
Test status
Simulation time 12350277 ps
CPU time 0.55 seconds
Started Feb 25 12:30:31 PM PST 24
Finished Feb 25 12:30:33 PM PST 24
Peak memory 195392 kb
Host smart-94aea4b1-1321-4158-b4bb-95eed265a403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727150897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.727150897
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2289478166
Short name T1149
Test name
Test status
Simulation time 49608837 ps
CPU time 0.59 seconds
Started Feb 25 12:30:43 PM PST 24
Finished Feb 25 12:30:44 PM PST 24
Peak memory 194372 kb
Host smart-cb16c6eb-596c-4d87-b17e-ea130d9cb054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289478166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2289478166
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3593640234
Short name T1219
Test name
Test status
Simulation time 18796192 ps
CPU time 0.73 seconds
Started Feb 25 12:30:47 PM PST 24
Finished Feb 25 12:30:48 PM PST 24
Peak memory 196940 kb
Host smart-6420ac19-1570-4a82-a0ee-7c51dd2d13b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593640234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3593640234
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.127257991
Short name T1182
Test name
Test status
Simulation time 252386194 ps
CPU time 1.78 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:52 PM PST 24
Peak memory 200120 kb
Host smart-17226ebf-379c-4f38-9d0c-333a1377c5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127257991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.127257991
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4147775103
Short name T97
Test name
Test status
Simulation time 593238599 ps
CPU time 1.28 seconds
Started Feb 25 12:30:45 PM PST 24
Finished Feb 25 12:30:46 PM PST 24
Peak memory 198856 kb
Host smart-4fdbce18-88ec-4ac6-a2e4-738875fcf505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147775103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4147775103
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4260735781
Short name T1206
Test name
Test status
Simulation time 91076564 ps
CPU time 0.73 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 198116 kb
Host smart-312d4371-3936-4391-8697-90e42bf2effa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260735781 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4260735781
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1173321136
Short name T77
Test name
Test status
Simulation time 63179559 ps
CPU time 0.6 seconds
Started Feb 25 12:30:24 PM PST 24
Finished Feb 25 12:30:25 PM PST 24
Peak memory 195472 kb
Host smart-8b7f50b3-a5e5-4836-b93b-87d690c3c6e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173321136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1173321136
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.478835945
Short name T1123
Test name
Test status
Simulation time 20787577 ps
CPU time 0.54 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:56 PM PST 24
Peak memory 185176 kb
Host smart-db7e3c89-45ef-47b7-b33d-d996daf8d71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478835945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.478835945
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3153487733
Short name T85
Test name
Test status
Simulation time 46403794 ps
CPU time 0.66 seconds
Started Feb 25 12:30:31 PM PST 24
Finished Feb 25 12:30:32 PM PST 24
Peak memory 195512 kb
Host smart-70dc5068-05c7-46c1-8981-59c9e42503d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153487733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3153487733
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4214651206
Short name T1190
Test name
Test status
Simulation time 422638695 ps
CPU time 1.56 seconds
Started Feb 25 12:30:40 PM PST 24
Finished Feb 25 12:30:42 PM PST 24
Peak memory 200084 kb
Host smart-bb0da6f8-8bf1-498a-980c-1b44374fcbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214651206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4214651206
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.219738101
Short name T409
Test name
Test status
Simulation time 45531287 ps
CPU time 0.9 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:30:56 PM PST 24
Peak memory 198876 kb
Host smart-45703123-95b9-41f5-a055-ff3672e4b7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219738101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.219738101
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2046733463
Short name T1131
Test name
Test status
Simulation time 84011957 ps
CPU time 1 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 199884 kb
Host smart-683005c1-58d0-456d-8a67-678e93823f87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046733463 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2046733463
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3830742284
Short name T79
Test name
Test status
Simulation time 62458966 ps
CPU time 0.62 seconds
Started Feb 25 12:31:02 PM PST 24
Finished Feb 25 12:31:04 PM PST 24
Peak memory 195424 kb
Host smart-2ee7b8a3-104a-491d-be9e-66c63667f397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830742284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3830742284
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2179025091
Short name T1207
Test name
Test status
Simulation time 22578118 ps
CPU time 0.55 seconds
Started Feb 25 12:30:36 PM PST 24
Finished Feb 25 12:30:37 PM PST 24
Peak memory 185176 kb
Host smart-f47dc92f-8e81-4b10-b0f4-9252769e567b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179025091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2179025091
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.321439105
Short name T1223
Test name
Test status
Simulation time 119618801 ps
CPU time 0.78 seconds
Started Feb 25 12:30:48 PM PST 24
Finished Feb 25 12:30:49 PM PST 24
Peak memory 195812 kb
Host smart-d9586f23-5ebb-4034-83c2-802707163d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321439105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.321439105
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.96260439
Short name T1227
Test name
Test status
Simulation time 48972796 ps
CPU time 1.41 seconds
Started Feb 25 12:30:36 PM PST 24
Finished Feb 25 12:30:37 PM PST 24
Peak memory 200104 kb
Host smart-469f8197-2f6f-4566-bdfd-544b6814f7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96260439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.96260439
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2312389936
Short name T1176
Test name
Test status
Simulation time 50739471 ps
CPU time 1.02 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:30:56 PM PST 24
Peak memory 198872 kb
Host smart-43e3695a-9a6b-4745-8afe-9d74b70e531c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312389936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2312389936
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3040212404
Short name T1117
Test name
Test status
Simulation time 63611099 ps
CPU time 1.09 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 200104 kb
Host smart-614c558a-b7c4-46b1-8c0d-2a67f37dfcc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040212404 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3040212404
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2822385742
Short name T75
Test name
Test status
Simulation time 125540441 ps
CPU time 0.58 seconds
Started Feb 25 12:30:30 PM PST 24
Finished Feb 25 12:30:32 PM PST 24
Peak memory 195400 kb
Host smart-e2df9542-fdd4-4ff1-9184-61e74d921d96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822385742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2822385742
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3401031253
Short name T1167
Test name
Test status
Simulation time 14887621 ps
CPU time 0.57 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 185172 kb
Host smart-0eb3a6b5-79bc-401e-8c5a-7648eb26082c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401031253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3401031253
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1410156227
Short name T1209
Test name
Test status
Simulation time 27519820 ps
CPU time 0.62 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 194508 kb
Host smart-e487e1b3-6e10-485f-8f06-626d41e223f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410156227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1410156227
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1315374380
Short name T1199
Test name
Test status
Simulation time 170693761 ps
CPU time 1.9 seconds
Started Feb 25 12:30:47 PM PST 24
Finished Feb 25 12:30:49 PM PST 24
Peak memory 200088 kb
Host smart-7c0bd591-9208-4779-91c5-8d750a107b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315374380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1315374380
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.621857101
Short name T94
Test name
Test status
Simulation time 133429373 ps
CPU time 1.31 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 199248 kb
Host smart-43e536b6-7fd2-4616-9ec5-71d0ecc18e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621857101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.621857101
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2133486867
Short name T1232
Test name
Test status
Simulation time 16658150 ps
CPU time 0.62 seconds
Started Feb 25 12:31:07 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 196340 kb
Host smart-7ecfd7f0-7155-43df-8d02-7589f7492926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133486867 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2133486867
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.37947919
Short name T1135
Test name
Test status
Simulation time 45246866 ps
CPU time 0.58 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 195436 kb
Host smart-3c131a28-1d34-41a1-96ed-891f801edb12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37947919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.37947919
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1927137123
Short name T1130
Test name
Test status
Simulation time 125711044 ps
CPU time 0.56 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:31:00 PM PST 24
Peak memory 185140 kb
Host smart-805e7c25-84e5-4f5f-8987-78af5eca7699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927137123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1927137123
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2506514649
Short name T1137
Test name
Test status
Simulation time 159946475 ps
CPU time 0.74 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 196876 kb
Host smart-fbfdad8f-be0d-4c79-9d1c-bbdc4d0a10cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506514649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2506514649
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2923115958
Short name T1116
Test name
Test status
Simulation time 166618891 ps
CPU time 1.08 seconds
Started Feb 25 12:30:58 PM PST 24
Finished Feb 25 12:31:00 PM PST 24
Peak memory 199928 kb
Host smart-c49cb90d-47d0-4a3d-b44b-dfcbfdc3685e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923115958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2923115958
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1672156306
Short name T1175
Test name
Test status
Simulation time 312868034 ps
CPU time 1.01 seconds
Started Feb 25 12:30:41 PM PST 24
Finished Feb 25 12:30:42 PM PST 24
Peak memory 198748 kb
Host smart-d881e93f-010e-4ea3-9304-d0ea8d6b13b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672156306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1672156306
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3150947777
Short name T1215
Test name
Test status
Simulation time 64516236 ps
CPU time 0.68 seconds
Started Feb 25 12:30:48 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 197128 kb
Host smart-bdb00017-36ef-4d57-afa8-c74957803762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150947777 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3150947777
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3982092638
Short name T71
Test name
Test status
Simulation time 155762014 ps
CPU time 0.59 seconds
Started Feb 25 12:30:45 PM PST 24
Finished Feb 25 12:30:46 PM PST 24
Peak memory 195248 kb
Host smart-bb845a2d-30ce-4889-9bfc-714db59b0dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982092638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3982092638
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2434611354
Short name T1173
Test name
Test status
Simulation time 27607944 ps
CPU time 0.57 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 185172 kb
Host smart-4adfe0c9-3a89-4c58-9dec-afa00dc10b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434611354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2434611354
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2449752764
Short name T1169
Test name
Test status
Simulation time 20124434 ps
CPU time 0.68 seconds
Started Feb 25 12:30:42 PM PST 24
Finished Feb 25 12:30:43 PM PST 24
Peak memory 194724 kb
Host smart-3cb08dd0-a160-43f5-8941-9fc313d860b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449752764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2449752764
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2171523507
Short name T1144
Test name
Test status
Simulation time 26150721 ps
CPU time 1.24 seconds
Started Feb 25 12:31:27 PM PST 24
Finished Feb 25 12:31:28 PM PST 24
Peak memory 200136 kb
Host smart-0d67eaaa-3480-499a-bdd3-833d4d7c161a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171523507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2171523507
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.102779091
Short name T1179
Test name
Test status
Simulation time 28942225 ps
CPU time 0.62 seconds
Started Feb 25 12:30:41 PM PST 24
Finished Feb 25 12:30:42 PM PST 24
Peak memory 197280 kb
Host smart-1b0fb7da-c0f4-4e31-a359-e630f103ab54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102779091 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.102779091
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3106970615
Short name T1168
Test name
Test status
Simulation time 60634992 ps
CPU time 0.63 seconds
Started Feb 25 12:31:04 PM PST 24
Finished Feb 25 12:31:06 PM PST 24
Peak memory 195392 kb
Host smart-64c5a60b-20cc-49a6-9f47-48326d2c8443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106970615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3106970615
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1534406141
Short name T1156
Test name
Test status
Simulation time 26089342 ps
CPU time 0.52 seconds
Started Feb 25 12:30:47 PM PST 24
Finished Feb 25 12:30:48 PM PST 24
Peak memory 185200 kb
Host smart-0bb9c9b4-d00f-4085-ba02-856e3dbd589f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534406141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1534406141
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1660665036
Short name T1160
Test name
Test status
Simulation time 33276173 ps
CPU time 0.8 seconds
Started Feb 25 12:30:42 PM PST 24
Finished Feb 25 12:30:43 PM PST 24
Peak memory 195964 kb
Host smart-d385d2f6-96c1-4161-8d95-3e54589d55d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660665036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1660665036
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2084213857
Short name T1128
Test name
Test status
Simulation time 598149228 ps
CPU time 1.7 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 200120 kb
Host smart-b6893e85-68cc-4cb8-a03a-603c037b1ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084213857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2084213857
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2542021426
Short name T1198
Test name
Test status
Simulation time 343172790 ps
CPU time 1.34 seconds
Started Feb 25 12:31:02 PM PST 24
Finished Feb 25 12:31:04 PM PST 24
Peak memory 199204 kb
Host smart-863307ce-65ef-4d9d-8b3e-95b844855116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542021426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2542021426
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3823973591
Short name T1195
Test name
Test status
Simulation time 51128274 ps
CPU time 0.76 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 198408 kb
Host smart-1b681aed-2ffb-4785-9cd1-4a5cdca454e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823973591 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3823973591
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4118978992
Short name T1147
Test name
Test status
Simulation time 50099416 ps
CPU time 0.6 seconds
Started Feb 25 12:30:47 PM PST 24
Finished Feb 25 12:30:48 PM PST 24
Peak memory 195400 kb
Host smart-c273a31f-2f5c-49c0-a0ae-de190028b82f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118978992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4118978992
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3205433066
Short name T1150
Test name
Test status
Simulation time 22039841 ps
CPU time 0.57 seconds
Started Feb 25 12:30:53 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 185200 kb
Host smart-92dfb10f-22e2-4a29-9cf8-c0c12900aee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205433066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3205433066
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3415512114
Short name T89
Test name
Test status
Simulation time 12402799 ps
CPU time 0.62 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 195724 kb
Host smart-06f215c7-7930-433d-9ad1-bb3bfb68ab27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415512114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3415512114
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2497791776
Short name T1231
Test name
Test status
Simulation time 30410213 ps
CPU time 1.38 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:52 PM PST 24
Peak memory 200188 kb
Host smart-ccdddf16-a419-43bd-96ca-46048f6719d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497791776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2497791776
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2214725624
Short name T1203
Test name
Test status
Simulation time 54657201 ps
CPU time 0.96 seconds
Started Feb 25 12:31:00 PM PST 24
Finished Feb 25 12:31:02 PM PST 24
Peak memory 198912 kb
Host smart-3bbc6ddb-7f3b-4691-8a84-eb05e3403c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214725624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2214725624
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1777670341
Short name T1142
Test name
Test status
Simulation time 66186616 ps
CPU time 0.87 seconds
Started Feb 25 12:30:48 PM PST 24
Finished Feb 25 12:30:49 PM PST 24
Peak memory 199788 kb
Host smart-4549e71b-4e16-41c1-926a-24fe18488ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777670341 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1777670341
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2439200124
Short name T82
Test name
Test status
Simulation time 15255382 ps
CPU time 0.64 seconds
Started Feb 25 12:31:07 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 195468 kb
Host smart-c1467fcf-4833-4b2f-bcc5-57a24b801b6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439200124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2439200124
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.452630530
Short name T1188
Test name
Test status
Simulation time 37123334 ps
CPU time 0.55 seconds
Started Feb 25 12:31:03 PM PST 24
Finished Feb 25 12:31:05 PM PST 24
Peak memory 194400 kb
Host smart-cf43b583-5560-400c-a0a9-5d43f24e8043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452630530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.452630530
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4016495522
Short name T84
Test name
Test status
Simulation time 84126996 ps
CPU time 0.69 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 197576 kb
Host smart-b67dbaa4-26ee-4095-99b7-75565df52081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016495522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4016495522
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3881305121
Short name T1212
Test name
Test status
Simulation time 232682014 ps
CPU time 1.46 seconds
Started Feb 25 12:30:57 PM PST 24
Finished Feb 25 12:30:59 PM PST 24
Peak memory 200144 kb
Host smart-810e006d-5266-42de-a9a9-a62ff18e4aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881305121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3881305121
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4010184577
Short name T100
Test name
Test status
Simulation time 179351336 ps
CPU time 1.29 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 199248 kb
Host smart-63d2f5ce-5cb5-483e-869d-810365257e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010184577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4010184577
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2060475377
Short name T1163
Test name
Test status
Simulation time 30780744 ps
CPU time 0.82 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 199892 kb
Host smart-678c174e-65cf-4103-8249-46c126df65be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060475377 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2060475377
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.268698345
Short name T1159
Test name
Test status
Simulation time 14708368 ps
CPU time 0.55 seconds
Started Feb 25 12:31:15 PM PST 24
Finished Feb 25 12:31:16 PM PST 24
Peak memory 195420 kb
Host smart-78f6aff8-de2a-469a-9be6-0d6cf8f46fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268698345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.268698345
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.601461207
Short name T1124
Test name
Test status
Simulation time 12885866 ps
CPU time 0.55 seconds
Started Feb 25 12:30:48 PM PST 24
Finished Feb 25 12:30:49 PM PST 24
Peak memory 185092 kb
Host smart-fecc730e-2dcf-4216-93e5-523c71cc6559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601461207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.601461207
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3811931145
Short name T1177
Test name
Test status
Simulation time 34279700 ps
CPU time 0.79 seconds
Started Feb 25 12:31:07 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 196996 kb
Host smart-18c15d10-55de-4e96-9053-ec43bfda6c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811931145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3811931145
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.92357351
Short name T1187
Test name
Test status
Simulation time 415687566 ps
CPU time 1.43 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:52 PM PST 24
Peak memory 200092 kb
Host smart-fef4bbe6-152e-43c7-b27c-00a90f12e307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92357351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.92357351
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1088980495
Short name T96
Test name
Test status
Simulation time 52874782 ps
CPU time 0.93 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 198800 kb
Host smart-d5f739cb-3ee8-4e46-aa82-19282f4c70f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088980495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1088980495
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3228627871
Short name T1140
Test name
Test status
Simulation time 53202356 ps
CPU time 1.2 seconds
Started Feb 25 12:30:53 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 199944 kb
Host smart-fd8b4595-1a93-4f13-abc1-cd760f58ec17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228627871 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3228627871
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2200209806
Short name T1238
Test name
Test status
Simulation time 15139509 ps
CPU time 0.64 seconds
Started Feb 25 12:31:18 PM PST 24
Finished Feb 25 12:31:18 PM PST 24
Peak memory 195416 kb
Host smart-e6a113ca-b5a8-4a91-a5e5-bd0796d6415b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200209806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2200209806
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.964825084
Short name T1220
Test name
Test status
Simulation time 13148622 ps
CPU time 0.56 seconds
Started Feb 25 12:31:11 PM PST 24
Finished Feb 25 12:31:12 PM PST 24
Peak memory 194372 kb
Host smart-4023dae3-e808-4ac5-9a05-f647e55d175e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964825084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.964825084
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.746859785
Short name T1191
Test name
Test status
Simulation time 21252867 ps
CPU time 0.65 seconds
Started Feb 25 12:30:53 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 195692 kb
Host smart-1ebbb529-61d4-42eb-8eb1-2cc8ac719fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746859785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.746859785
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2499597145
Short name T1237
Test name
Test status
Simulation time 43756173 ps
CPU time 1.07 seconds
Started Feb 25 12:31:25 PM PST 24
Finished Feb 25 12:31:26 PM PST 24
Peak memory 199896 kb
Host smart-08316439-86d8-4586-93dc-3523c814c439
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499597145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2499597145
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.244137662
Short name T408
Test name
Test status
Simulation time 86042311 ps
CPU time 0.94 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 198868 kb
Host smart-5f8899ce-541e-4d71-8fdf-f776dfe55f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244137662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.244137662
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.102334876
Short name T1120
Test name
Test status
Simulation time 71052901 ps
CPU time 0.77 seconds
Started Feb 25 12:30:49 PM PST 24
Finished Feb 25 12:30:50 PM PST 24
Peak memory 195856 kb
Host smart-f66f0660-c28f-4213-91e6-18c62d758ed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102334876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.102334876
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2296047200
Short name T1162
Test name
Test status
Simulation time 186077629 ps
CPU time 2.34 seconds
Started Feb 25 12:30:49 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 196768 kb
Host smart-0d7bb768-1e7d-4e6e-95ac-147e392fb2c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296047200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2296047200
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3583503637
Short name T1205
Test name
Test status
Simulation time 75207131 ps
CPU time 0.76 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 198712 kb
Host smart-12de8707-37c3-4529-9480-106e6ebfc2e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583503637 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3583503637
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2569415954
Short name T1185
Test name
Test status
Simulation time 18820108 ps
CPU time 0.59 seconds
Started Feb 25 12:30:39 PM PST 24
Finished Feb 25 12:30:40 PM PST 24
Peak memory 195436 kb
Host smart-c591b10e-4fd9-49b6-a4e4-8e3939fe91cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569415954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2569415954
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.125375794
Short name T1230
Test name
Test status
Simulation time 11520148 ps
CPU time 0.53 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 185184 kb
Host smart-8bb0ffa7-2af1-47c9-b62d-ed4287368d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125375794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.125375794
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.960413992
Short name T1136
Test name
Test status
Simulation time 138412275 ps
CPU time 0.64 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 195536 kb
Host smart-1c453957-e2cc-4310-8352-e788578440ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960413992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.960413992
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2379975641
Short name T1225
Test name
Test status
Simulation time 45321486 ps
CPU time 1.15 seconds
Started Feb 25 12:30:30 PM PST 24
Finished Feb 25 12:30:32 PM PST 24
Peak memory 200120 kb
Host smart-563b1c6e-8fb7-48b2-893e-7cb6dd6092f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379975641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2379975641
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1120413829
Short name T1134
Test name
Test status
Simulation time 249494899 ps
CPU time 1.26 seconds
Started Feb 25 12:30:44 PM PST 24
Finished Feb 25 12:30:46 PM PST 24
Peak memory 199224 kb
Host smart-765b96bb-704e-410a-883c-0fdf1022bcba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120413829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1120413829
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1744781010
Short name T1165
Test name
Test status
Simulation time 15922240 ps
CPU time 0.55 seconds
Started Feb 25 12:31:08 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 185164 kb
Host smart-8026a8f5-334b-4577-94f7-8d87af4b53b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744781010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1744781010
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4002095878
Short name T1119
Test name
Test status
Simulation time 22128095 ps
CPU time 0.54 seconds
Started Feb 25 12:31:33 PM PST 24
Finished Feb 25 12:31:35 PM PST 24
Peak memory 185200 kb
Host smart-15e29e94-6b54-4203-b973-afdbdc955755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002095878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4002095878
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3931248596
Short name T1189
Test name
Test status
Simulation time 12876118 ps
CPU time 0.54 seconds
Started Feb 25 12:31:30 PM PST 24
Finished Feb 25 12:31:31 PM PST 24
Peak memory 185168 kb
Host smart-6db73368-0451-4af4-944b-67955c062406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931248596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3931248596
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.478961037
Short name T1217
Test name
Test status
Simulation time 30909031 ps
CPU time 0.55 seconds
Started Feb 25 12:31:26 PM PST 24
Finished Feb 25 12:31:26 PM PST 24
Peak memory 194388 kb
Host smart-d116e662-bae5-4326-a5dd-622c4009aa73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478961037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.478961037
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1161868291
Short name T1157
Test name
Test status
Simulation time 39324872 ps
CPU time 0.56 seconds
Started Feb 25 12:31:08 PM PST 24
Finished Feb 25 12:31:09 PM PST 24
Peak memory 194320 kb
Host smart-cc4a3b81-c28c-4c64-b961-f3665c6b1e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161868291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1161868291
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1424886713
Short name T1200
Test name
Test status
Simulation time 46905070 ps
CPU time 0.65 seconds
Started Feb 25 12:31:02 PM PST 24
Finished Feb 25 12:31:04 PM PST 24
Peak memory 185184 kb
Host smart-e3218f11-9ae9-4cf9-9b7f-3e97b792d3f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424886713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1424886713
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2595894945
Short name T1143
Test name
Test status
Simulation time 14198224 ps
CPU time 0.57 seconds
Started Feb 25 12:31:23 PM PST 24
Finished Feb 25 12:31:24 PM PST 24
Peak memory 185200 kb
Host smart-828bc144-b48c-42ec-a3b7-400defa816c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595894945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2595894945
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2846309355
Short name T1110
Test name
Test status
Simulation time 14158392 ps
CPU time 0.64 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 185176 kb
Host smart-7df49937-56d2-4d39-9e6f-4602192cd2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846309355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2846309355
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3167029386
Short name T1201
Test name
Test status
Simulation time 25210259 ps
CPU time 0.56 seconds
Started Feb 25 12:31:30 PM PST 24
Finished Feb 25 12:31:31 PM PST 24
Peak memory 185200 kb
Host smart-a0a7c1cb-c4f5-494d-afc7-9a9e1400f14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167029386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3167029386
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.25076686
Short name T1166
Test name
Test status
Simulation time 41209616 ps
CPU time 0.55 seconds
Started Feb 25 12:31:03 PM PST 24
Finished Feb 25 12:31:05 PM PST 24
Peak memory 185152 kb
Host smart-a579526b-1402-4e44-8dcf-ccbe474d4734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.25076686
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1627205085
Short name T80
Test name
Test status
Simulation time 40358418 ps
CPU time 0.66 seconds
Started Feb 25 12:30:26 PM PST 24
Finished Feb 25 12:30:27 PM PST 24
Peak memory 194676 kb
Host smart-dc2168e8-fb1c-4fa4-b29d-5aabc941d164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627205085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1627205085
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1542851029
Short name T1197
Test name
Test status
Simulation time 355685598 ps
CPU time 2.36 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 197668 kb
Host smart-43f25cdf-75f2-4c9f-9b48-70009dc6a566
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542851029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1542851029
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3395826967
Short name T1208
Test name
Test status
Simulation time 12512710 ps
CPU time 0.57 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 195384 kb
Host smart-522e689d-2f83-4d49-beb7-20b339fc13e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395826967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3395826967
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1004002449
Short name T1141
Test name
Test status
Simulation time 85686803 ps
CPU time 0.73 seconds
Started Feb 25 12:30:44 PM PST 24
Finished Feb 25 12:30:45 PM PST 24
Peak memory 198160 kb
Host smart-3a91118a-d318-4be3-8588-87cc0e90ab42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004002449 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1004002449
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3857260051
Short name T72
Test name
Test status
Simulation time 14474927 ps
CPU time 0.63 seconds
Started Feb 25 12:31:01 PM PST 24
Finished Feb 25 12:31:03 PM PST 24
Peak memory 195476 kb
Host smart-0900b901-2e46-4b67-ad98-9929ad55f65d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857260051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3857260051
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2291028419
Short name T1204
Test name
Test status
Simulation time 23255417 ps
CPU time 0.55 seconds
Started Feb 25 12:30:19 PM PST 24
Finished Feb 25 12:30:20 PM PST 24
Peak memory 185136 kb
Host smart-16f58050-ee08-4d73-89c2-24b196dd587a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291028419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2291028419
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2558756989
Short name T1196
Test name
Test status
Simulation time 17999936 ps
CPU time 0.64 seconds
Started Feb 25 12:30:20 PM PST 24
Finished Feb 25 12:30:21 PM PST 24
Peak memory 194628 kb
Host smart-08f3ca5c-f394-4f23-8ef8-9bc7debf0e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558756989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2558756989
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3794717232
Short name T1118
Test name
Test status
Simulation time 40691181 ps
CPU time 1.55 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 200092 kb
Host smart-bbdc6749-4b4c-41c2-a2b5-7a79c4a996eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794717232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3794717232
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3833770031
Short name T99
Test name
Test status
Simulation time 324024117 ps
CPU time 1.31 seconds
Started Feb 25 12:30:23 PM PST 24
Finished Feb 25 12:30:25 PM PST 24
Peak memory 199152 kb
Host smart-741278b6-040c-4b7c-8007-78a0a43aaa85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833770031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3833770031
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1911447656
Short name T1184
Test name
Test status
Simulation time 37859531 ps
CPU time 0.54 seconds
Started Feb 25 12:31:04 PM PST 24
Finished Feb 25 12:31:10 PM PST 24
Peak memory 185164 kb
Host smart-9029f32e-6476-43dc-8a9f-64681c07945b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911447656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1911447656
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1653339852
Short name T1153
Test name
Test status
Simulation time 14171214 ps
CPU time 0.67 seconds
Started Feb 25 12:31:01 PM PST 24
Finished Feb 25 12:31:03 PM PST 24
Peak memory 194348 kb
Host smart-f4468fc9-7c0c-490c-83c7-4496e1e27650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653339852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1653339852
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.680107603
Short name T1112
Test name
Test status
Simulation time 49917751 ps
CPU time 0.58 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 185152 kb
Host smart-caa5e89d-008e-4d65-bf6b-31b04f1a2735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680107603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.680107603
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.723589076
Short name T1158
Test name
Test status
Simulation time 12513370 ps
CPU time 0.57 seconds
Started Feb 25 12:31:05 PM PST 24
Finished Feb 25 12:31:06 PM PST 24
Peak memory 185148 kb
Host smart-a46efe30-6404-4deb-a626-d68870fd7109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723589076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.723589076
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1123216542
Short name T1193
Test name
Test status
Simulation time 71223085 ps
CPU time 0.56 seconds
Started Feb 25 12:31:10 PM PST 24
Finished Feb 25 12:31:11 PM PST 24
Peak memory 194380 kb
Host smart-a7a95042-de44-4e74-9937-486e5158d29f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123216542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1123216542
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.425851179
Short name T1139
Test name
Test status
Simulation time 15322770 ps
CPU time 0.57 seconds
Started Feb 25 12:31:08 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 185148 kb
Host smart-8d292724-7c5d-4121-8576-11521aa548af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425851179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.425851179
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3778726557
Short name T1132
Test name
Test status
Simulation time 17518120 ps
CPU time 0.58 seconds
Started Feb 25 12:31:20 PM PST 24
Finished Feb 25 12:31:30 PM PST 24
Peak memory 185412 kb
Host smart-3855ed6b-2a5e-47b1-bc27-3c5214c62535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778726557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3778726557
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1299815997
Short name T1154
Test name
Test status
Simulation time 43508068 ps
CPU time 0.55 seconds
Started Feb 25 12:31:16 PM PST 24
Finished Feb 25 12:31:16 PM PST 24
Peak memory 185200 kb
Host smart-f42986fc-fe74-49b4-993d-5bd1147077a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299815997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1299815997
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2323587399
Short name T1222
Test name
Test status
Simulation time 49773878 ps
CPU time 0.57 seconds
Started Feb 25 12:31:05 PM PST 24
Finished Feb 25 12:31:06 PM PST 24
Peak memory 194388 kb
Host smart-dde70d13-9bc7-4d0a-92a8-4ca9c0b1093e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323587399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2323587399
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.104461012
Short name T1151
Test name
Test status
Simulation time 39004911 ps
CPU time 0.55 seconds
Started Feb 25 12:31:10 PM PST 24
Finished Feb 25 12:31:10 PM PST 24
Peak memory 194372 kb
Host smart-2acfb5a7-cc9c-4bf9-bc78-9288048d6ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104461012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.104461012
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1245530489
Short name T81
Test name
Test status
Simulation time 103225983 ps
CPU time 0.75 seconds
Started Feb 25 12:30:35 PM PST 24
Finished Feb 25 12:30:36 PM PST 24
Peak memory 196112 kb
Host smart-fae103a1-63f5-420f-9ff1-ad12947aa919
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245530489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1245530489
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2391751481
Short name T1174
Test name
Test status
Simulation time 139967647 ps
CPU time 1.59 seconds
Started Feb 25 12:30:45 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 197632 kb
Host smart-15b55ef6-76aa-444b-881c-919a9c46b163
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391751481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2391751481
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2374606090
Short name T1121
Test name
Test status
Simulation time 11797570 ps
CPU time 0.57 seconds
Started Feb 25 12:30:45 PM PST 24
Finished Feb 25 12:30:45 PM PST 24
Peak memory 195424 kb
Host smart-8ca34663-9ccf-4a0a-ab65-9a11a37e43c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374606090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2374606090
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1260229638
Short name T1221
Test name
Test status
Simulation time 21530493 ps
CPU time 1.01 seconds
Started Feb 25 12:31:10 PM PST 24
Finished Feb 25 12:31:11 PM PST 24
Peak memory 200112 kb
Host smart-7d02d75d-480a-4cca-b4ec-dd61b90bc1a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260229638 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1260229638
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2841877829
Short name T1170
Test name
Test status
Simulation time 12687375 ps
CPU time 0.59 seconds
Started Feb 25 12:30:21 PM PST 24
Finished Feb 25 12:30:22 PM PST 24
Peak memory 195172 kb
Host smart-03c355a2-7e83-4311-8d8a-76b89653c111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841877829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2841877829
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2455974928
Short name T1181
Test name
Test status
Simulation time 16023744 ps
CPU time 0.58 seconds
Started Feb 25 12:30:38 PM PST 24
Finished Feb 25 12:30:38 PM PST 24
Peak memory 185184 kb
Host smart-11a66570-a1bf-4be6-80d6-d438b418bd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455974928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2455974928
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4112376665
Short name T1152
Test name
Test status
Simulation time 36777370 ps
CPU time 0.8 seconds
Started Feb 25 12:30:22 PM PST 24
Finished Feb 25 12:30:23 PM PST 24
Peak memory 197072 kb
Host smart-85ba17d2-1f81-4ecd-ac04-864379b64a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112376665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4112376665
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2129482850
Short name T1210
Test name
Test status
Simulation time 121611087 ps
CPU time 2.21 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:59 PM PST 24
Peak memory 200092 kb
Host smart-b8d02dd6-32cc-4373-bf75-29f62ba763e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129482850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2129482850
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2298661030
Short name T93
Test name
Test status
Simulation time 174765891 ps
CPU time 0.91 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 198748 kb
Host smart-4330b9c9-cb25-45b0-b509-5b0ab8c4dde2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298661030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2298661030
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3996235714
Short name T1229
Test name
Test status
Simulation time 13808020 ps
CPU time 0.53 seconds
Started Feb 25 12:30:57 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 185200 kb
Host smart-f4bd741d-5716-4dad-900a-3795a566a7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996235714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3996235714
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1871868566
Short name T1125
Test name
Test status
Simulation time 137708961 ps
CPU time 0.53 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:30:58 PM PST 24
Peak memory 185200 kb
Host smart-d099a5cf-0f3e-43b3-8102-20fb4f54a0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871868566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1871868566
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3131383546
Short name T1226
Test name
Test status
Simulation time 12927671 ps
CPU time 0.57 seconds
Started Feb 25 12:30:56 PM PST 24
Finished Feb 25 12:31:02 PM PST 24
Peak memory 185200 kb
Host smart-d964f1e2-2fde-4bfb-b7ff-7d2d42d3f19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131383546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3131383546
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.536027676
Short name T1186
Test name
Test status
Simulation time 33154851 ps
CPU time 0.57 seconds
Started Feb 25 12:31:12 PM PST 24
Finished Feb 25 12:31:13 PM PST 24
Peak memory 194384 kb
Host smart-444d7212-1385-4f8c-b9b1-af6fe5a6ae06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536027676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.536027676
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2349818331
Short name T1161
Test name
Test status
Simulation time 29558826 ps
CPU time 0.54 seconds
Started Feb 25 12:31:01 PM PST 24
Finished Feb 25 12:31:02 PM PST 24
Peak memory 185200 kb
Host smart-ba303c15-9217-4c83-bd61-22a8a978a93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349818331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2349818331
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1155450722
Short name T1202
Test name
Test status
Simulation time 27120163 ps
CPU time 0.54 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 194388 kb
Host smart-0d06e675-4a46-4b8d-8ab3-83b3642bdb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155450722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1155450722
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.557992755
Short name T1224
Test name
Test status
Simulation time 23623003 ps
CPU time 0.55 seconds
Started Feb 25 12:31:01 PM PST 24
Finished Feb 25 12:31:03 PM PST 24
Peak memory 185116 kb
Host smart-f25c69e8-6810-4b8f-9c0a-0d842a3e2d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557992755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.557992755
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.552053382
Short name T1114
Test name
Test status
Simulation time 53722676 ps
CPU time 0.55 seconds
Started Feb 25 12:31:00 PM PST 24
Finished Feb 25 12:31:02 PM PST 24
Peak memory 185160 kb
Host smart-3c8abc2b-6d66-4524-b557-a2d975633f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552053382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.552053382
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3659613308
Short name T1218
Test name
Test status
Simulation time 89194481 ps
CPU time 0.61 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 185200 kb
Host smart-33248c39-28fe-469d-8e4d-212a5aeb0c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659613308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3659613308
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.79773226
Short name T1146
Test name
Test status
Simulation time 28622758 ps
CPU time 0.64 seconds
Started Feb 25 12:31:00 PM PST 24
Finished Feb 25 12:31:02 PM PST 24
Peak memory 185152 kb
Host smart-2d761bed-6a34-4e4a-aa25-3f4251f22a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79773226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.79773226
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2768332406
Short name T1228
Test name
Test status
Simulation time 54256207 ps
CPU time 1.52 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:52 PM PST 24
Peak memory 200068 kb
Host smart-b83ce3dd-c8cb-41eb-8ef3-d57d4cbd78e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768332406 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2768332406
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2960042274
Short name T87
Test name
Test status
Simulation time 13801174 ps
CPU time 0.57 seconds
Started Feb 25 12:30:51 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 195388 kb
Host smart-2bd99610-19cb-4716-82a6-1f1957dfa35f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960042274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2960042274
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.709107968
Short name T1111
Test name
Test status
Simulation time 13780519 ps
CPU time 0.55 seconds
Started Feb 25 12:30:49 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 185184 kb
Host smart-c8bc11f5-42da-4796-ae85-7fa7e2cda727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709107968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.709107968
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2294558991
Short name T1214
Test name
Test status
Simulation time 37428143 ps
CPU time 0.62 seconds
Started Feb 25 12:31:06 PM PST 24
Finished Feb 25 12:31:07 PM PST 24
Peak memory 195516 kb
Host smart-93467767-c9c3-4c32-8b05-26fcc4699115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294558991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2294558991
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2452486939
Short name T1148
Test name
Test status
Simulation time 35529771 ps
CPU time 0.87 seconds
Started Feb 25 12:30:52 PM PST 24
Finished Feb 25 12:30:53 PM PST 24
Peak memory 199428 kb
Host smart-a02c73b4-783f-49a6-9ea7-a54450a6bda3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452486939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2452486939
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.300106860
Short name T101
Test name
Test status
Simulation time 190068606 ps
CPU time 0.94 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 197808 kb
Host smart-7ba38292-5430-4823-86a3-7398ee346f05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300106860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.300106860
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.946407912
Short name T1164
Test name
Test status
Simulation time 27912929 ps
CPU time 0.8 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:30:56 PM PST 24
Peak memory 199880 kb
Host smart-bf27f0d0-1fe8-423d-a580-3c571f63bb0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946407912 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.946407912
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2972923680
Short name T1171
Test name
Test status
Simulation time 32202124 ps
CPU time 0.6 seconds
Started Feb 25 12:30:38 PM PST 24
Finished Feb 25 12:30:38 PM PST 24
Peak memory 195368 kb
Host smart-c188024f-0770-4c71-a331-fa70bbed349c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972923680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2972923680
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1642348222
Short name T1183
Test name
Test status
Simulation time 80833085 ps
CPU time 0.53 seconds
Started Feb 25 12:30:39 PM PST 24
Finished Feb 25 12:30:39 PM PST 24
Peak memory 194452 kb
Host smart-ae68f409-7e06-4113-ae53-313acf2cbc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642348222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1642348222
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1661320813
Short name T83
Test name
Test status
Simulation time 33228312 ps
CPU time 0.63 seconds
Started Feb 25 12:30:49 PM PST 24
Finished Feb 25 12:30:50 PM PST 24
Peak memory 195536 kb
Host smart-f1a0da0f-928a-467b-b890-2e062572729b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661320813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1661320813
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.409515191
Short name T1113
Test name
Test status
Simulation time 773225684 ps
CPU time 1.35 seconds
Started Feb 25 12:30:20 PM PST 24
Finished Feb 25 12:30:22 PM PST 24
Peak memory 200128 kb
Host smart-4e5e008c-db36-4873-8b52-cf737e06e479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409515191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.409515191
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2771493776
Short name T91
Test name
Test status
Simulation time 144041874 ps
CPU time 0.93 seconds
Started Feb 25 12:30:44 PM PST 24
Finished Feb 25 12:30:45 PM PST 24
Peak memory 198844 kb
Host smart-76a756ee-ef54-4872-ba54-cb050855d239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771493776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2771493776
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3472744861
Short name T1194
Test name
Test status
Simulation time 110005099 ps
CPU time 0.81 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 199856 kb
Host smart-cc50d15b-ac55-4dee-adfa-035ac1b1d3a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472744861 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3472744861
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.923373294
Short name T74
Test name
Test status
Simulation time 65031835 ps
CPU time 0.54 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 195380 kb
Host smart-fe3383ca-7a53-4ad7-8ff4-bbd4be9ad89b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923373294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.923373294
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3481261270
Short name T1213
Test name
Test status
Simulation time 38056395 ps
CPU time 0.57 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 194372 kb
Host smart-f3a0a788-c532-4ee7-ad43-df099ec80b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481261270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3481261270
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2805369905
Short name T1236
Test name
Test status
Simulation time 50306664 ps
CPU time 0.72 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 197020 kb
Host smart-f5461230-f318-44a0-aaa6-96dc41fcb766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805369905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2805369905
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3213411659
Short name T1233
Test name
Test status
Simulation time 26492673 ps
CPU time 1.26 seconds
Started Feb 25 12:30:34 PM PST 24
Finished Feb 25 12:30:35 PM PST 24
Peak memory 200064 kb
Host smart-fbdf07db-d04b-4d86-8daa-051bd976c65f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213411659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3213411659
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4153109545
Short name T92
Test name
Test status
Simulation time 83866538 ps
CPU time 1.25 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 197888 kb
Host smart-e8172cf8-8bff-4ea2-bfa1-838f5e8d2ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153109545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4153109545
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1427402602
Short name T1138
Test name
Test status
Simulation time 25711699 ps
CPU time 1.22 seconds
Started Feb 25 12:30:54 PM PST 24
Finished Feb 25 12:30:55 PM PST 24
Peak memory 200068 kb
Host smart-c88d8b36-bcce-441f-9e4f-01a0fd5727e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427402602 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1427402602
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3721540695
Short name T1235
Test name
Test status
Simulation time 37086944 ps
CPU time 0.57 seconds
Started Feb 25 12:30:36 PM PST 24
Finished Feb 25 12:30:36 PM PST 24
Peak memory 195420 kb
Host smart-50021008-a6c4-4ccf-b9e0-f3c49d6d4a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721540695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3721540695
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2363168265
Short name T1172
Test name
Test status
Simulation time 27416424 ps
CPU time 0.56 seconds
Started Feb 25 12:30:46 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 185116 kb
Host smart-d9e7047f-2a77-4c09-bf4b-75abd9c93caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363168265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2363168265
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3881041449
Short name T1180
Test name
Test status
Simulation time 14826175 ps
CPU time 0.72 seconds
Started Feb 25 12:31:01 PM PST 24
Finished Feb 25 12:31:08 PM PST 24
Peak memory 196832 kb
Host smart-ba0e2b90-7bed-480f-81b4-b8af629283b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881041449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3881041449
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3766817296
Short name T1192
Test name
Test status
Simulation time 169233058 ps
CPU time 2.04 seconds
Started Feb 25 12:31:08 PM PST 24
Finished Feb 25 12:31:10 PM PST 24
Peak memory 200080 kb
Host smart-9e380cc3-d227-48ec-9ef8-fdbdbc741a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766817296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3766817296
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1622194293
Short name T1126
Test name
Test status
Simulation time 75610336 ps
CPU time 1.09 seconds
Started Feb 25 12:30:33 PM PST 24
Finished Feb 25 12:30:34 PM PST 24
Peak memory 199820 kb
Host smart-7b25276a-d9e4-46e5-a2d4-9d48d2497784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622194293 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1622194293
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2645279619
Short name T88
Test name
Test status
Simulation time 12594984 ps
CPU time 0.55 seconds
Started Feb 25 12:30:50 PM PST 24
Finished Feb 25 12:30:51 PM PST 24
Peak memory 195344 kb
Host smart-b7090f66-de59-4e27-8419-0ba56587adc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645279619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2645279619
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.282431013
Short name T1155
Test name
Test status
Simulation time 33682506 ps
CPU time 0.54 seconds
Started Feb 25 12:30:55 PM PST 24
Finished Feb 25 12:31:06 PM PST 24
Peak memory 185176 kb
Host smart-ef7f5f1c-9cec-406e-a2de-7d69e9aa5e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282431013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.282431013
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.667237962
Short name T1133
Test name
Test status
Simulation time 34750366 ps
CPU time 0.79 seconds
Started Feb 25 12:30:58 PM PST 24
Finished Feb 25 12:31:00 PM PST 24
Peak memory 196608 kb
Host smart-5c2caebb-6cf1-4109-994a-ab7e1d7f5864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667237962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.667237962
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3539065759
Short name T1145
Test name
Test status
Simulation time 182228845 ps
CPU time 2.39 seconds
Started Feb 25 12:30:44 PM PST 24
Finished Feb 25 12:30:47 PM PST 24
Peak memory 200176 kb
Host smart-de5a7332-a038-4742-9f2c-65b0f50dc7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539065759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3539065759
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3169728568
Short name T1240
Test name
Test status
Simulation time 134129731 ps
CPU time 0.93 seconds
Started Feb 25 12:30:42 PM PST 24
Finished Feb 25 12:30:43 PM PST 24
Peak memory 198880 kb
Host smart-ba7a6e38-1a45-473f-a735-8a0a3b642352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169728568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3169728568
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1828835209
Short name T3
Test name
Test status
Simulation time 13191579 ps
CPU time 0.56 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:32:29 PM PST 24
Peak memory 194080 kb
Host smart-e415835c-dc61-47de-81db-5dba80a06f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828835209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1828835209
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2400003169
Short name T749
Test name
Test status
Simulation time 91389732033 ps
CPU time 31.47 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:33:03 PM PST 24
Peak memory 198800 kb
Host smart-d61a7982-5b3d-415d-aaa6-5b4a9de68ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400003169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2400003169
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.112459718
Short name T449
Test name
Test status
Simulation time 153103557509 ps
CPU time 279.83 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:37:09 PM PST 24
Peak memory 199648 kb
Host smart-7c58e30a-0a88-4796-bc42-2eafc581da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112459718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.112459718
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.346873479
Short name T164
Test name
Test status
Simulation time 22374946149 ps
CPU time 35.21 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:33:04 PM PST 24
Peak memory 199548 kb
Host smart-7cab8e05-c307-4db2-8bd4-611101c0f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346873479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.346873479
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1838564217
Short name T16
Test name
Test status
Simulation time 424508771176 ps
CPU time 323.75 seconds
Started Feb 25 01:32:27 PM PST 24
Finished Feb 25 01:37:51 PM PST 24
Peak memory 199544 kb
Host smart-3253d030-123e-4d2b-b52f-202f8735e169
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838564217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1838564217
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1757868296
Short name T413
Test name
Test status
Simulation time 217839420668 ps
CPU time 366.92 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:38:39 PM PST 24
Peak memory 199660 kb
Host smart-9d4bfefa-448f-4f99-b234-f699e8f92657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757868296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1757868296
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2884064939
Short name T520
Test name
Test status
Simulation time 1397618594 ps
CPU time 2.59 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:32:31 PM PST 24
Peak memory 197752 kb
Host smart-eb202dd4-0c55-4184-a948-ab203924f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884064939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2884064939
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1964627967
Short name T885
Test name
Test status
Simulation time 76230963551 ps
CPU time 149.53 seconds
Started Feb 25 01:32:41 PM PST 24
Finished Feb 25 01:35:12 PM PST 24
Peak memory 199808 kb
Host smart-2436dde2-17a6-493f-840c-ac652ec164c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964627967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1964627967
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3715700317
Short name T417
Test name
Test status
Simulation time 15066179650 ps
CPU time 715.84 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 199596 kb
Host smart-1e449147-f7ca-4764-ab00-26515b2080ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715700317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3715700317
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.484606615
Short name T870
Test name
Test status
Simulation time 10297863032 ps
CPU time 14.91 seconds
Started Feb 25 01:32:41 PM PST 24
Finished Feb 25 01:32:56 PM PST 24
Peak memory 198732 kb
Host smart-3919211c-b267-4ad6-9d3d-bc2bba0fdce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484606615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.484606615
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2602401985
Short name T803
Test name
Test status
Simulation time 2469750469 ps
CPU time 1.7 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:34 PM PST 24
Peak memory 195068 kb
Host smart-afa127b2-e791-49ab-a273-3d4588e6cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602401985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2602401985
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1676143774
Short name T35
Test name
Test status
Simulation time 40812320 ps
CPU time 0.79 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:33 PM PST 24
Peak memory 217152 kb
Host smart-bb84ac6b-dfd0-4bae-a99b-966977f35995
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676143774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1676143774
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2328756007
Short name T443
Test name
Test status
Simulation time 11625198277 ps
CPU time 34.23 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:33:03 PM PST 24
Peak memory 199208 kb
Host smart-a11bb536-e1f1-40ba-bfbe-1b186576557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328756007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2328756007
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1135212227
Short name T883
Test name
Test status
Simulation time 1025739182858 ps
CPU time 345.3 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:38:18 PM PST 24
Peak memory 198768 kb
Host smart-44b5a7db-47c6-4fc5-b382-e2741f4e8610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135212227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1135212227
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2530061566
Short name T675
Test name
Test status
Simulation time 6660024876 ps
CPU time 9.23 seconds
Started Feb 25 01:32:41 PM PST 24
Finished Feb 25 01:32:52 PM PST 24
Peak memory 198652 kb
Host smart-f68cc30e-6fa4-4cf2-948e-2b73300e2a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530061566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2530061566
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3040310369
Short name T658
Test name
Test status
Simulation time 21713013744 ps
CPU time 9.36 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:32:47 PM PST 24
Peak memory 199340 kb
Host smart-68dd9c6e-7c21-46d6-a7df-aebc09421cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040310369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3040310369
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.219565574
Short name T600
Test name
Test status
Simulation time 11636900 ps
CPU time 0.55 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:32:32 PM PST 24
Peak memory 194056 kb
Host smart-871414a0-4756-420c-a8d1-052ed648879e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219565574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.219565574
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.674218073
Short name T888
Test name
Test status
Simulation time 288334447994 ps
CPU time 26.09 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:32:54 PM PST 24
Peak memory 199444 kb
Host smart-70314cc9-22ed-4698-aeca-8c8649f4bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674218073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.674218073
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.195696645
Short name T640
Test name
Test status
Simulation time 205466730853 ps
CPU time 23.93 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:32:55 PM PST 24
Peak memory 199580 kb
Host smart-cbab551a-b089-45fc-abbe-ec09e000be1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195696645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.195696645
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1339182390
Short name T754
Test name
Test status
Simulation time 116102362238 ps
CPU time 180.88 seconds
Started Feb 25 01:32:26 PM PST 24
Finished Feb 25 01:35:27 PM PST 24
Peak memory 199212 kb
Host smart-706432f2-266c-4f57-be7f-0f34437af37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339182390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1339182390
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3638662802
Short name T901
Test name
Test status
Simulation time 599010826958 ps
CPU time 985.17 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:48:57 PM PST 24
Peak memory 198308 kb
Host smart-b8ad0877-7a5e-4e29-a4aa-7fd3f9169731
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638662802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3638662802
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.463498270
Short name T548
Test name
Test status
Simulation time 140292350033 ps
CPU time 250.51 seconds
Started Feb 25 01:32:27 PM PST 24
Finished Feb 25 01:36:38 PM PST 24
Peak memory 199568 kb
Host smart-dd126e6c-95ee-4abf-97aa-93d6037c4a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463498270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.463498270
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.425119479
Short name T562
Test name
Test status
Simulation time 11220736457 ps
CPU time 11.8 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:44 PM PST 24
Peak memory 199232 kb
Host smart-36e68519-ba79-4768-b0c7-550efa92a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425119479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.425119479
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3529902086
Short name T1052
Test name
Test status
Simulation time 25966011061 ps
CPU time 45.77 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:33:18 PM PST 24
Peak memory 198300 kb
Host smart-1468bfcd-7d2d-49d4-9039-112ea8d156df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529902086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3529902086
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3866848501
Short name T586
Test name
Test status
Simulation time 24231281212 ps
CPU time 132.13 seconds
Started Feb 25 01:32:27 PM PST 24
Finished Feb 25 01:34:39 PM PST 24
Peak memory 199716 kb
Host smart-bbc6e927-a939-4da5-9e62-b1be2cae03b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866848501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3866848501
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.742639628
Short name T942
Test name
Test status
Simulation time 233361215154 ps
CPU time 59.62 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:33:27 PM PST 24
Peak memory 199704 kb
Host smart-903de5ab-adaa-4c90-ae20-61d40130f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742639628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.742639628
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1944002187
Short name T774
Test name
Test status
Simulation time 4269024738 ps
CPU time 7.54 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:32:39 PM PST 24
Peak memory 195340 kb
Host smart-ad8ac728-e916-46ff-a724-eb8d4027c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944002187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1944002187
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.932640247
Short name T34
Test name
Test status
Simulation time 208097725 ps
CPU time 0.86 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:32:30 PM PST 24
Peak memory 217104 kb
Host smart-fe1469b2-5990-4804-9670-9d8368ab022e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932640247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.932640247
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4158849264
Short name T425
Test name
Test status
Simulation time 447805181 ps
CPU time 2.28 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:32:34 PM PST 24
Peak memory 197552 kb
Host smart-02945d2f-6fc4-4b9c-acbb-442a0245e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158849264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4158849264
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3489431073
Short name T855
Test name
Test status
Simulation time 118903540877 ps
CPU time 779.81 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:45:28 PM PST 24
Peak memory 199640 kb
Host smart-96539167-b2e9-4b54-a3af-f5b0cd02cef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489431073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3489431073
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1881100195
Short name T469
Test name
Test status
Simulation time 2480396484 ps
CPU time 2.09 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:40 PM PST 24
Peak memory 198092 kb
Host smart-868959ed-e36f-41f4-aecb-b587738e030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881100195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1881100195
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3571919307
Short name T1054
Test name
Test status
Simulation time 296170258983 ps
CPU time 31.17 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:33:00 PM PST 24
Peak memory 199648 kb
Host smart-12f14bfd-4d23-4489-833c-c64c6c7a253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571919307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3571919307
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2357221288
Short name T914
Test name
Test status
Simulation time 15717916 ps
CPU time 0.53 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:33:14 PM PST 24
Peak memory 195104 kb
Host smart-608a8a86-1dd0-488a-87ac-a2730199b224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357221288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2357221288
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.845560967
Short name T668
Test name
Test status
Simulation time 42095262290 ps
CPU time 58.22 seconds
Started Feb 25 01:33:15 PM PST 24
Finished Feb 25 01:34:14 PM PST 24
Peak memory 199524 kb
Host smart-eec13103-0533-4feb-a1d9-48635624a20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845560967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.845560967
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4247123390
Short name T1075
Test name
Test status
Simulation time 24995917914 ps
CPU time 21.18 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:33:33 PM PST 24
Peak memory 199548 kb
Host smart-56180f38-e657-4b0c-b98f-846f086d2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247123390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4247123390
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.4116370712
Short name T133
Test name
Test status
Simulation time 30970641990 ps
CPU time 13.23 seconds
Started Feb 25 01:33:14 PM PST 24
Finished Feb 25 01:33:28 PM PST 24
Peak memory 199656 kb
Host smart-6e6cc66b-874f-4245-bcdc-04190a0bddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116370712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.4116370712
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.681491167
Short name T997
Test name
Test status
Simulation time 282680057167 ps
CPU time 238.57 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:37:12 PM PST 24
Peak memory 198464 kb
Host smart-4b8791b4-cdb3-4aca-8a95-8a01e53e83de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681491167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.681491167
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1674373086
Short name T62
Test name
Test status
Simulation time 61819375040 ps
CPU time 340.91 seconds
Started Feb 25 01:33:15 PM PST 24
Finished Feb 25 01:38:56 PM PST 24
Peak memory 199652 kb
Host smart-99f5c593-70ac-4027-8591-04151e32ba77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674373086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1674373086
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_perf.2561681890
Short name T232
Test name
Test status
Simulation time 18207139230 ps
CPU time 252.52 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:37:26 PM PST 24
Peak memory 199652 kb
Host smart-e8c02a6a-376f-45eb-a9b1-166b9d009132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561681890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2561681890
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1677529266
Short name T958
Test name
Test status
Simulation time 142475191606 ps
CPU time 109.18 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:35:02 PM PST 24
Peak memory 198880 kb
Host smart-08268dc9-0eb8-4051-87d6-89c144cebd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677529266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1677529266
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3778648611
Short name T711
Test name
Test status
Simulation time 1872488798 ps
CPU time 3.96 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:33:17 PM PST 24
Peak memory 195060 kb
Host smart-71ebc6d9-1a1d-4675-9cf0-97a0361acba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778648611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3778648611
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1946074600
Short name T466
Test name
Test status
Simulation time 666251537 ps
CPU time 1.58 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:33:15 PM PST 24
Peak memory 198792 kb
Host smart-57e2eca7-4d8e-4b0c-8132-79b21aa351b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946074600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1946074600
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3530759074
Short name T593
Test name
Test status
Simulation time 278754220501 ps
CPU time 139.48 seconds
Started Feb 25 01:33:13 PM PST 24
Finished Feb 25 01:35:33 PM PST 24
Peak memory 199596 kb
Host smart-c005f81c-e71f-4fb9-8965-245bd98eed56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530759074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3530759074
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2477578925
Short name T770
Test name
Test status
Simulation time 1066042807 ps
CPU time 2.74 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:33:15 PM PST 24
Peak memory 197896 kb
Host smart-a2359657-da83-4180-86d8-02e92b625617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477578925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2477578925
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3750785630
Short name T515
Test name
Test status
Simulation time 556623926637 ps
CPU time 55.64 seconds
Started Feb 25 01:33:16 PM PST 24
Finished Feb 25 01:34:11 PM PST 24
Peak memory 199608 kb
Host smart-83b83ea5-a5e1-4b0a-b467-f0a1a5423ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750785630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3750785630
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3497718299
Short name T884
Test name
Test status
Simulation time 62974013061 ps
CPU time 26.64 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:39:29 PM PST 24
Peak memory 199632 kb
Host smart-15515c9d-1487-487b-aea2-43b5e920e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497718299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3497718299
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1518874113
Short name T341
Test name
Test status
Simulation time 34767195115 ps
CPU time 53.93 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:39:56 PM PST 24
Peak memory 199624 kb
Host smart-cebbd3a6-9aab-4d7a-912f-057ac423173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518874113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1518874113
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4272787768
Short name T126
Test name
Test status
Simulation time 81918649211 ps
CPU time 30.02 seconds
Started Feb 25 01:39:01 PM PST 24
Finished Feb 25 01:39:32 PM PST 24
Peak memory 199688 kb
Host smart-2817463f-9bf4-451c-8621-487eb513f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272787768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4272787768
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2835275980
Short name T366
Test name
Test status
Simulation time 58947732932 ps
CPU time 26.3 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:30 PM PST 24
Peak memory 199428 kb
Host smart-29bed83a-8a9c-41b6-b7f9-fb05dc33cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835275980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2835275980
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.822586167
Short name T1023
Test name
Test status
Simulation time 28527456127 ps
CPU time 43.21 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:39:45 PM PST 24
Peak memory 199616 kb
Host smart-b6a3dd6c-82a7-42cc-b876-7427c1f31d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822586167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.822586167
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3662959165
Short name T1092
Test name
Test status
Simulation time 15684864060 ps
CPU time 25.69 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:39:26 PM PST 24
Peak memory 199204 kb
Host smart-073125f5-093b-4ee8-b0ef-df7ccd2b3652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662959165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3662959165
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1817110604
Short name T809
Test name
Test status
Simulation time 196240711622 ps
CPU time 89.76 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:40:35 PM PST 24
Peak memory 199620 kb
Host smart-5cb8b034-7e89-48b5-9c4c-6cc1aeb35b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817110604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1817110604
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.174717735
Short name T260
Test name
Test status
Simulation time 24928510402 ps
CPU time 12.32 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:17 PM PST 24
Peak memory 199716 kb
Host smart-30283f77-3999-418e-addb-31fc4fcc9d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174717735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.174717735
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3401673259
Short name T549
Test name
Test status
Simulation time 11957640 ps
CPU time 0.56 seconds
Started Feb 25 01:33:22 PM PST 24
Finished Feb 25 01:33:22 PM PST 24
Peak memory 195112 kb
Host smart-622888ea-51be-4ab9-a7a0-d51ff0a9409b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401673259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3401673259
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4097739747
Short name T2
Test name
Test status
Simulation time 55364807603 ps
CPU time 38.98 seconds
Started Feb 25 01:33:26 PM PST 24
Finished Feb 25 01:34:05 PM PST 24
Peak memory 199684 kb
Host smart-73b7b26b-22f1-4e0b-b45c-388897fb44ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097739747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4097739747
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3082286786
Short name T376
Test name
Test status
Simulation time 45847353047 ps
CPU time 36.45 seconds
Started Feb 25 01:33:25 PM PST 24
Finished Feb 25 01:34:02 PM PST 24
Peak memory 199660 kb
Host smart-07ef5f87-5512-4511-9050-062f458d9b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082286786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3082286786
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.64415159
Short name T243
Test name
Test status
Simulation time 113339051964 ps
CPU time 165.14 seconds
Started Feb 25 01:33:32 PM PST 24
Finished Feb 25 01:36:17 PM PST 24
Peak memory 199460 kb
Host smart-2789bed2-74bb-4dd6-bb4e-0cbd9750a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64415159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.64415159
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1717423795
Short name T431
Test name
Test status
Simulation time 1063341405621 ps
CPU time 1613.66 seconds
Started Feb 25 01:33:27 PM PST 24
Finished Feb 25 02:00:21 PM PST 24
Peak memory 199600 kb
Host smart-c61faa52-2a74-4e71-890a-50eb39e8d2c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717423795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1717423795
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1908052561
Short name T780
Test name
Test status
Simulation time 156218790551 ps
CPU time 126.45 seconds
Started Feb 25 01:33:28 PM PST 24
Finished Feb 25 01:35:34 PM PST 24
Peak memory 199712 kb
Host smart-2efc4af5-128c-4e21-ab57-bde51255fcf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908052561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1908052561
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.434817932
Short name T1065
Test name
Test status
Simulation time 44939555 ps
CPU time 0.59 seconds
Started Feb 25 01:33:18 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 194952 kb
Host smart-fe15bb42-17f3-4ee2-a3cc-9ebc2df276a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434817932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.434817932
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3229771940
Short name T752
Test name
Test status
Simulation time 248877997155 ps
CPU time 45.13 seconds
Started Feb 25 01:33:28 PM PST 24
Finished Feb 25 01:34:13 PM PST 24
Peak memory 197616 kb
Host smart-13a7980a-405e-435e-ad55-83bed6a5dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229771940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3229771940
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1975921619
Short name T757
Test name
Test status
Simulation time 27857653972 ps
CPU time 1257.84 seconds
Started Feb 25 01:33:31 PM PST 24
Finished Feb 25 01:54:29 PM PST 24
Peak memory 199672 kb
Host smart-4dc6823a-533c-4bd5-a63c-041981a2a121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975921619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1975921619
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1184620700
Short name T479
Test name
Test status
Simulation time 480404189 ps
CPU time 2.77 seconds
Started Feb 25 01:33:27 PM PST 24
Finished Feb 25 01:33:30 PM PST 24
Peak memory 197660 kb
Host smart-91c6d850-15f9-4c11-be3d-8f6a4045173c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184620700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1184620700
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3957368240
Short name T851
Test name
Test status
Simulation time 132950043409 ps
CPU time 136.78 seconds
Started Feb 25 01:33:21 PM PST 24
Finished Feb 25 01:35:38 PM PST 24
Peak memory 198896 kb
Host smart-56cc62d8-d55d-4359-a1ab-9f30a4da815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957368240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3957368240
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2227893378
Short name T441
Test name
Test status
Simulation time 6040896985 ps
CPU time 2.04 seconds
Started Feb 25 01:33:22 PM PST 24
Finished Feb 25 01:33:24 PM PST 24
Peak memory 195392 kb
Host smart-8c4fe0af-5924-465f-be15-3a47ddec0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227893378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2227893378
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3101668640
Short name T445
Test name
Test status
Simulation time 884382610 ps
CPU time 3.52 seconds
Started Feb 25 01:33:20 PM PST 24
Finished Feb 25 01:33:23 PM PST 24
Peak memory 197432 kb
Host smart-08bc4a84-54b5-4ddf-b86f-f3b3e6e55ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101668640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3101668640
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2722599989
Short name T835
Test name
Test status
Simulation time 6146309129 ps
CPU time 21.43 seconds
Started Feb 25 01:33:26 PM PST 24
Finished Feb 25 01:33:47 PM PST 24
Peak memory 199284 kb
Host smart-6967fcdf-c6ca-497a-ba20-72fb4c3529c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722599989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2722599989
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1739362723
Short name T910
Test name
Test status
Simulation time 175360067604 ps
CPU time 118.45 seconds
Started Feb 25 01:33:26 PM PST 24
Finished Feb 25 01:35:25 PM PST 24
Peak memory 199616 kb
Host smart-0959b6f6-2f69-4f12-ab24-a484db6083fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739362723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1739362723
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.148832382
Short name T122
Test name
Test status
Simulation time 21756625378 ps
CPU time 9.75 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:14 PM PST 24
Peak memory 199756 kb
Host smart-18ef21e1-8617-470e-8e8e-57475b786984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148832382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.148832382
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2968477217
Short name T930
Test name
Test status
Simulation time 17313747387 ps
CPU time 10.68 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:39:12 PM PST 24
Peak memory 199312 kb
Host smart-47d49b9a-b051-45d5-a551-4fd57c37994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968477217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2968477217
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1920926696
Short name T891
Test name
Test status
Simulation time 29156485629 ps
CPU time 25.23 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:29 PM PST 24
Peak memory 199556 kb
Host smart-767b01dd-f8f5-48d2-aaab-3d3e9ebd83e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920926696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1920926696
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2217205082
Short name T158
Test name
Test status
Simulation time 108363714518 ps
CPU time 45.34 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:39:51 PM PST 24
Peak memory 199708 kb
Host smart-0de46a62-5583-4ece-ac2e-97804c53bf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217205082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2217205082
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2195903467
Short name T230
Test name
Test status
Simulation time 21049366332 ps
CPU time 18.59 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:23 PM PST 24
Peak memory 199544 kb
Host smart-a8075f89-8d95-456e-be38-b6f026da1909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195903467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2195903467
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3447203945
Short name T201
Test name
Test status
Simulation time 137763394724 ps
CPU time 211.82 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:42:32 PM PST 24
Peak memory 199648 kb
Host smart-6670e416-eacd-4978-a700-fed254213d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447203945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3447203945
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1344593852
Short name T693
Test name
Test status
Simulation time 12225075393 ps
CPU time 20.63 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:39:26 PM PST 24
Peak memory 198068 kb
Host smart-67c431c0-d35b-4825-b38a-f599d68b8b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344593852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1344593852
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2885454320
Short name T660
Test name
Test status
Simulation time 46947573 ps
CPU time 0.54 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:33:37 PM PST 24
Peak memory 194012 kb
Host smart-d8356d55-f67f-4317-95a1-44d91fbfd9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885454320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2885454320
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3782716111
Short name T1107
Test name
Test status
Simulation time 213887353392 ps
CPU time 125.6 seconds
Started Feb 25 01:33:31 PM PST 24
Finished Feb 25 01:35:36 PM PST 24
Peak memory 199624 kb
Host smart-e3bacbfb-b93e-4310-8804-028f6a415819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782716111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3782716111
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.946027923
Short name T985
Test name
Test status
Simulation time 55615731396 ps
CPU time 49.64 seconds
Started Feb 25 01:33:30 PM PST 24
Finished Feb 25 01:34:20 PM PST 24
Peak memory 198972 kb
Host smart-d022a65c-da1e-4937-8b9c-ffbf85f1e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946027923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.946027923
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1706256903
Short name T502
Test name
Test status
Simulation time 39199284907 ps
CPU time 17.41 seconds
Started Feb 25 01:33:26 PM PST 24
Finished Feb 25 01:33:43 PM PST 24
Peak memory 195080 kb
Host smart-cba788a8-30b9-48bd-ac90-eafc43e67a6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706256903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1706256903
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.598132644
Short name T854
Test name
Test status
Simulation time 78101017922 ps
CPU time 164.64 seconds
Started Feb 25 01:33:33 PM PST 24
Finished Feb 25 01:36:17 PM PST 24
Peak memory 199660 kb
Host smart-a8880311-5e5e-484e-a0ed-f3a8f7cf2cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598132644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.598132644
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.343684299
Short name T830
Test name
Test status
Simulation time 1308846029 ps
CPU time 3.04 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:33:40 PM PST 24
Peak memory 197756 kb
Host smart-0b5abc9d-b7d1-4116-8c13-6b2f4f0db0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343684299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.343684299
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3851993423
Short name T1045
Test name
Test status
Simulation time 15073040409 ps
CPU time 6.82 seconds
Started Feb 25 01:33:26 PM PST 24
Finished Feb 25 01:33:33 PM PST 24
Peak memory 194388 kb
Host smart-1ff8a943-ac17-4eda-9266-16adf1122465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851993423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3851993423
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2450483542
Short name T733
Test name
Test status
Simulation time 13277779044 ps
CPU time 157.13 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:36:15 PM PST 24
Peak memory 199624 kb
Host smart-a4bcb7cc-47c7-4dff-89dc-f40e50d5253e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450483542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2450483542
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2190324058
Short name T986
Test name
Test status
Simulation time 4048485382 ps
CPU time 30.36 seconds
Started Feb 25 01:33:30 PM PST 24
Finished Feb 25 01:34:00 PM PST 24
Peak memory 198016 kb
Host smart-243744d8-79fa-426e-9d93-4b7c01959d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190324058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2190324058
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4042875730
Short name T478
Test name
Test status
Simulation time 50064810199 ps
CPU time 42.21 seconds
Started Feb 25 01:33:37 PM PST 24
Finished Feb 25 01:34:19 PM PST 24
Peak memory 199664 kb
Host smart-74c0dcf6-ae9d-482a-bc09-0d41399b21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042875730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4042875730
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4206766790
Short name T1007
Test name
Test status
Simulation time 3051202484 ps
CPU time 1.52 seconds
Started Feb 25 01:33:28 PM PST 24
Finished Feb 25 01:33:30 PM PST 24
Peak memory 195092 kb
Host smart-ae1bcb4e-63f6-4cbe-8dd9-06077acb3132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206766790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4206766790
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1231705961
Short name T496
Test name
Test status
Simulation time 5835013538 ps
CPU time 8.57 seconds
Started Feb 25 01:33:25 PM PST 24
Finished Feb 25 01:33:34 PM PST 24
Peak memory 199064 kb
Host smart-a11fa9aa-4c9f-40ca-9373-0eb8b283678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231705961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1231705961
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.576522974
Short name T115
Test name
Test status
Simulation time 65956139332 ps
CPU time 131.29 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:35:49 PM PST 24
Peak memory 215612 kb
Host smart-0bb77529-b385-44f2-bf29-8c4e075649a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576522974 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.576522974
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3037793159
Short name T932
Test name
Test status
Simulation time 1404558119 ps
CPU time 1.73 seconds
Started Feb 25 01:33:41 PM PST 24
Finished Feb 25 01:33:42 PM PST 24
Peak memory 197824 kb
Host smart-6b033d7b-b00e-45be-b5c9-f976a5b69f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037793159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3037793159
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2325148585
Short name T787
Test name
Test status
Simulation time 13152781391 ps
CPU time 11.53 seconds
Started Feb 25 01:33:28 PM PST 24
Finished Feb 25 01:33:39 PM PST 24
Peak memory 199460 kb
Host smart-55821953-968b-45f0-b6aa-7fc3dbc983b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325148585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2325148585
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.198763939
Short name T255
Test name
Test status
Simulation time 106412683194 ps
CPU time 107.2 seconds
Started Feb 25 01:39:06 PM PST 24
Finished Feb 25 01:40:53 PM PST 24
Peak memory 199620 kb
Host smart-88a69d90-6614-4dd4-a588-9e4834b66c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198763939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.198763939
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1646612974
Short name T1024
Test name
Test status
Simulation time 277776130841 ps
CPU time 701.3 seconds
Started Feb 25 01:39:02 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 199632 kb
Host smart-6b4e7c07-1b24-4fc1-9918-8a1f7cc00d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646612974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1646612974
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1519837158
Short name T344
Test name
Test status
Simulation time 29946757619 ps
CPU time 24.99 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:39:30 PM PST 24
Peak memory 199664 kb
Host smart-9e23eb0e-16f7-44c9-b455-99faf77230bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519837158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1519837158
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1238196581
Short name T229
Test name
Test status
Simulation time 18818084220 ps
CPU time 32.36 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:39:37 PM PST 24
Peak memory 199532 kb
Host smart-fbdfb255-5230-4b55-825d-6574fde687d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238196581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1238196581
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1794119031
Short name T203
Test name
Test status
Simulation time 88016379877 ps
CPU time 34.48 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:39:45 PM PST 24
Peak memory 198572 kb
Host smart-b603404a-c840-4d64-8f3f-622ef57acad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794119031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1794119031
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2885291276
Short name T235
Test name
Test status
Simulation time 22300180373 ps
CPU time 149.12 seconds
Started Feb 25 01:39:13 PM PST 24
Finished Feb 25 01:41:43 PM PST 24
Peak memory 199652 kb
Host smart-0703e0ed-8753-4b5d-8521-925a20419c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885291276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2885291276
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.492112589
Short name T162
Test name
Test status
Simulation time 34578515959 ps
CPU time 29.37 seconds
Started Feb 25 01:39:12 PM PST 24
Finished Feb 25 01:39:41 PM PST 24
Peak memory 199532 kb
Host smart-12a6f005-67c4-48b3-b3b5-53ba588b73af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492112589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.492112589
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3971984796
Short name T180
Test name
Test status
Simulation time 182217481447 ps
CPU time 47.28 seconds
Started Feb 25 01:39:11 PM PST 24
Finished Feb 25 01:39:59 PM PST 24
Peak memory 199396 kb
Host smart-7ba51618-93fc-4ac6-b849-0328f7f5545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971984796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3971984796
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.4242980830
Short name T998
Test name
Test status
Simulation time 11717280 ps
CPU time 0.56 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:33:49 PM PST 24
Peak memory 195100 kb
Host smart-87a9d1f6-d49f-4b35-99f2-afee05734c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242980830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4242980830
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1838585926
Short name T415
Test name
Test status
Simulation time 38367984243 ps
CPU time 63.66 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:34:39 PM PST 24
Peak memory 199664 kb
Host smart-d6ac4a80-1bb8-421f-8827-199d287feaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838585926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1838585926
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3446338646
Short name T507
Test name
Test status
Simulation time 82049646879 ps
CPU time 50.95 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:34:29 PM PST 24
Peak memory 199620 kb
Host smart-203e3916-0459-4f26-8d99-f80943846a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446338646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3446338646
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.4228063432
Short name T486
Test name
Test status
Simulation time 74252764988 ps
CPU time 25.71 seconds
Started Feb 25 01:33:37 PM PST 24
Finished Feb 25 01:34:03 PM PST 24
Peak memory 199392 kb
Host smart-dfb8d258-eaa6-49b7-849b-f8fa1ada2dc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228063432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4228063432
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3235018379
Short name T523
Test name
Test status
Simulation time 278096743851 ps
CPU time 454.64 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:41:11 PM PST 24
Peak memory 199704 kb
Host smart-ce16fab9-04e5-40d9-b094-be06f8ae03d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235018379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3235018379
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3199771535
Short name T169
Test name
Test status
Simulation time 204114996228 ps
CPU time 78.09 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:34:56 PM PST 24
Peak memory 199764 kb
Host smart-bda56ca0-b645-4903-b78e-1328062afec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199771535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3199771535
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3297630252
Short name T805
Test name
Test status
Simulation time 15230685716 ps
CPU time 829.87 seconds
Started Feb 25 01:33:35 PM PST 24
Finished Feb 25 01:47:25 PM PST 24
Peak memory 199568 kb
Host smart-e5846888-c007-4201-a901-cae0333407f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297630252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3297630252
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2919731212
Short name T626
Test name
Test status
Simulation time 2906668657 ps
CPU time 21.11 seconds
Started Feb 25 01:33:37 PM PST 24
Finished Feb 25 01:33:59 PM PST 24
Peak memory 198360 kb
Host smart-cefa779f-9962-4310-beaa-9804220abc4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919731212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2919731212
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.359047710
Short name T13
Test name
Test status
Simulation time 11551891774 ps
CPU time 4.89 seconds
Started Feb 25 01:33:37 PM PST 24
Finished Feb 25 01:33:42 PM PST 24
Peak memory 196496 kb
Host smart-f1851820-e639-4f86-856c-63f8232287eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359047710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.359047710
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2730233782
Short name T569
Test name
Test status
Simulation time 1508129458 ps
CPU time 2.71 seconds
Started Feb 25 01:33:35 PM PST 24
Finished Feb 25 01:33:38 PM PST 24
Peak memory 195044 kb
Host smart-2047cf84-6db0-4dc4-9db0-43d082328f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730233782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2730233782
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1198746562
Short name T937
Test name
Test status
Simulation time 5520233693 ps
CPU time 7.61 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:33:45 PM PST 24
Peak memory 198876 kb
Host smart-5bdb5d86-4b94-499a-b4f6-49db6723017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198746562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1198746562
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.615405514
Short name T689
Test name
Test status
Simulation time 585349697709 ps
CPU time 115.08 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:35:32 PM PST 24
Peak memory 199804 kb
Host smart-2361e966-12b3-4cd4-8368-8977f993f275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615405514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.615405514
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2976315082
Short name T705
Test name
Test status
Simulation time 1209879270 ps
CPU time 2.94 seconds
Started Feb 25 01:33:38 PM PST 24
Finished Feb 25 01:33:41 PM PST 24
Peak memory 199244 kb
Host smart-f74c39ac-fcfa-48e8-8bf9-dec41570da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976315082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2976315082
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2778926148
Short name T1090
Test name
Test status
Simulation time 72164145077 ps
CPU time 19.74 seconds
Started Feb 25 01:33:36 PM PST 24
Finished Feb 25 01:33:56 PM PST 24
Peak memory 197320 kb
Host smart-3006b80b-031c-4ca5-8f02-e7deea8bc6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778926148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2778926148
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4179834236
Short name T744
Test name
Test status
Simulation time 39608048736 ps
CPU time 39.81 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:39:51 PM PST 24
Peak memory 199716 kb
Host smart-11b4b13e-5d1c-44a6-baab-87b2b78ee492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179834236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4179834236
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.309616256
Short name T610
Test name
Test status
Simulation time 27098667631 ps
CPU time 14.69 seconds
Started Feb 25 01:39:09 PM PST 24
Finished Feb 25 01:39:24 PM PST 24
Peak memory 199440 kb
Host smart-cea5f8a9-5b4c-467c-abdd-e0c74f41aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309616256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.309616256
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1298781909
Short name T993
Test name
Test status
Simulation time 19154152855 ps
CPU time 20.14 seconds
Started Feb 25 01:39:13 PM PST 24
Finished Feb 25 01:39:33 PM PST 24
Peak memory 198520 kb
Host smart-dd347c13-ee59-45d9-8ee5-db30acac2443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298781909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1298781909
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1235407750
Short name T398
Test name
Test status
Simulation time 48018858921 ps
CPU time 39.63 seconds
Started Feb 25 01:39:11 PM PST 24
Finished Feb 25 01:39:51 PM PST 24
Peak memory 199040 kb
Host smart-47fbfb5e-c186-480f-a384-e79c63cc4e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235407750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1235407750
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3014468002
Short name T338
Test name
Test status
Simulation time 20406944675 ps
CPU time 18.54 seconds
Started Feb 25 01:39:10 PM PST 24
Finished Feb 25 01:39:30 PM PST 24
Peak memory 199624 kb
Host smart-4b298fa6-ee53-4cad-bb3e-9930b4c95232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014468002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3014468002
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4164128337
Short name T329
Test name
Test status
Simulation time 20738543551 ps
CPU time 18.19 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:39:39 PM PST 24
Peak memory 199312 kb
Host smart-02836bdd-5137-4c1b-9f06-12cf20fbc900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164128337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4164128337
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2045999280
Short name T288
Test name
Test status
Simulation time 42218910182 ps
CPU time 43.78 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:40:04 PM PST 24
Peak memory 199620 kb
Host smart-337968a3-fb86-4741-ae01-b1de73b69854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045999280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2045999280
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2730628546
Short name T987
Test name
Test status
Simulation time 13313273 ps
CPU time 0.56 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:33:46 PM PST 24
Peak memory 195112 kb
Host smart-dcdf4664-6911-4bb2-b539-331f210737fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730628546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2730628546
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3766869573
Short name T789
Test name
Test status
Simulation time 92717188307 ps
CPU time 65.84 seconds
Started Feb 25 01:33:45 PM PST 24
Finished Feb 25 01:34:51 PM PST 24
Peak memory 199552 kb
Host smart-38393bb0-1eaf-4f29-a917-243ca76c850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766869573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3766869573
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3247064686
Short name T216
Test name
Test status
Simulation time 8853255997 ps
CPU time 8.56 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:33:55 PM PST 24
Peak memory 199108 kb
Host smart-a112f4d4-da97-4881-a9d1-2cfc73d68b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247064686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3247064686
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.468686741
Short name T857
Test name
Test status
Simulation time 36320649645 ps
CPU time 69.68 seconds
Started Feb 25 01:33:51 PM PST 24
Finished Feb 25 01:35:01 PM PST 24
Peak memory 199620 kb
Host smart-815412b6-fc25-44bb-b573-04f7438bee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468686741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.468686741
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.48641633
Short name T524
Test name
Test status
Simulation time 170846547471 ps
CPU time 270.63 seconds
Started Feb 25 01:33:49 PM PST 24
Finished Feb 25 01:38:20 PM PST 24
Peak memory 198684 kb
Host smart-e3638ef9-6d09-467f-89ea-138e065b1249
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48641633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.48641633
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3145904774
Short name T1035
Test name
Test status
Simulation time 108141632214 ps
CPU time 320.12 seconds
Started Feb 25 01:33:47 PM PST 24
Finished Feb 25 01:39:07 PM PST 24
Peak memory 199584 kb
Host smart-1068b9fd-8128-4876-a44d-68bd1253afd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145904774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3145904774
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1350638551
Short name T827
Test name
Test status
Simulation time 2544769638 ps
CPU time 2.98 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 196484 kb
Host smart-1ef313c4-f6c5-4b3e-a6b5-a95389b6844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350638551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1350638551
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2594624769
Short name T634
Test name
Test status
Simulation time 89988807054 ps
CPU time 143.81 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:36:10 PM PST 24
Peak memory 198572 kb
Host smart-d311d448-7be3-4d2b-b971-12e12413fa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594624769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2594624769
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3222588946
Short name T590
Test name
Test status
Simulation time 18017021049 ps
CPU time 1030.48 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:50:57 PM PST 24
Peak memory 199552 kb
Host smart-72eae9e1-29e5-4900-9ad8-4d0eaf7eea9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222588946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3222588946
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3328800308
Short name T889
Test name
Test status
Simulation time 3269550343 ps
CPU time 11.66 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:33:58 PM PST 24
Peak memory 197580 kb
Host smart-d2fd893d-24a9-4c6f-a419-05eadebbb54d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328800308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3328800308
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1107709935
Short name T559
Test name
Test status
Simulation time 38711004779 ps
CPU time 31.78 seconds
Started Feb 25 01:33:47 PM PST 24
Finished Feb 25 01:34:19 PM PST 24
Peak memory 199464 kb
Host smart-0815b1db-49f9-4217-97e1-5df157a08def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107709935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1107709935
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.248524190
Short name T969
Test name
Test status
Simulation time 34745679351 ps
CPU time 57.48 seconds
Started Feb 25 01:33:46 PM PST 24
Finished Feb 25 01:34:43 PM PST 24
Peak memory 195440 kb
Host smart-1e69ab47-bd25-48ac-a40a-93acb77be288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248524190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.248524190
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3961462181
Short name T1010
Test name
Test status
Simulation time 298116601 ps
CPU time 1.11 seconds
Started Feb 25 01:33:44 PM PST 24
Finished Feb 25 01:33:45 PM PST 24
Peak memory 198048 kb
Host smart-23307b02-c5d0-45a2-ae83-04c0a803d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961462181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3961462181
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1760336940
Short name T847
Test name
Test status
Simulation time 686232691 ps
CPU time 2.55 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 197608 kb
Host smart-ccbb93d1-a227-405c-9c55-e3483b7b00fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760336940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1760336940
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4124487977
Short name T724
Test name
Test status
Simulation time 78516137358 ps
CPU time 38.19 seconds
Started Feb 25 01:33:47 PM PST 24
Finished Feb 25 01:34:25 PM PST 24
Peak memory 199712 kb
Host smart-daeaa44a-d07c-4cb4-ad93-ad246edf1608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124487977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4124487977
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1850578195
Short name T1049
Test name
Test status
Simulation time 25466210735 ps
CPU time 36.92 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:39:58 PM PST 24
Peak memory 199700 kb
Host smart-ec70d490-90ae-4f2c-8112-328933671962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850578195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1850578195
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.161588710
Short name T48
Test name
Test status
Simulation time 18241806247 ps
CPU time 31.72 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:39:52 PM PST 24
Peak memory 199100 kb
Host smart-fbad8e87-0247-4b2c-be62-7b49c6f80782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161588710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.161588710
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1495609421
Short name T635
Test name
Test status
Simulation time 24742513078 ps
CPU time 34.21 seconds
Started Feb 25 01:39:24 PM PST 24
Finished Feb 25 01:39:58 PM PST 24
Peak memory 199044 kb
Host smart-2f74ac98-b4c7-43c9-9229-602f3f9e820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495609421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1495609421
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.55921920
Short name T642
Test name
Test status
Simulation time 34739652041 ps
CPU time 18.33 seconds
Started Feb 25 01:39:25 PM PST 24
Finished Feb 25 01:39:44 PM PST 24
Peak memory 199540 kb
Host smart-9f19df87-d547-4921-ba36-62eee255a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55921920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.55921920
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2295501655
Short name T280
Test name
Test status
Simulation time 97087040814 ps
CPU time 140.37 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:41:41 PM PST 24
Peak memory 199624 kb
Host smart-a66aeb77-8065-4330-9171-428ce934d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295501655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2295501655
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.167672994
Short name T172
Test name
Test status
Simulation time 21413339255 ps
CPU time 8.51 seconds
Started Feb 25 01:39:25 PM PST 24
Finished Feb 25 01:39:33 PM PST 24
Peak memory 199472 kb
Host smart-e02f0662-c94b-44a5-8e8f-3f109558a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167672994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.167672994
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4029457305
Short name T1059
Test name
Test status
Simulation time 107817165671 ps
CPU time 18.58 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:39:39 PM PST 24
Peak memory 198300 kb
Host smart-e5bc5827-b3cc-4300-ae69-bae38cf4a47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029457305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4029457305
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.944791843
Short name T324
Test name
Test status
Simulation time 101779915735 ps
CPU time 60.36 seconds
Started Feb 25 01:39:23 PM PST 24
Finished Feb 25 01:40:24 PM PST 24
Peak memory 199624 kb
Host smart-7f4fbe2b-a893-4bba-b4b5-308ae886eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944791843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.944791843
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.251244785
Short name T1063
Test name
Test status
Simulation time 30411601976 ps
CPU time 26.53 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:39:48 PM PST 24
Peak memory 199628 kb
Host smart-1e5bcedb-a6db-4f50-ad19-6777ec951c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251244785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.251244785
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3083256372
Short name T621
Test name
Test status
Simulation time 303808495917 ps
CPU time 899.64 seconds
Started Feb 25 01:33:49 PM PST 24
Finished Feb 25 01:48:49 PM PST 24
Peak memory 199532 kb
Host smart-e34d1541-b33d-4a44-8f4c-b56e8b672b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083256372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3083256372
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1092372454
Short name T1044
Test name
Test status
Simulation time 94339032950 ps
CPU time 75.03 seconds
Started Feb 25 01:33:49 PM PST 24
Finished Feb 25 01:35:04 PM PST 24
Peak memory 198952 kb
Host smart-8aa15a4f-7ddb-4fe9-930b-40b06a4b08f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092372454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1092372454
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.419161759
Short name T897
Test name
Test status
Simulation time 45840915837 ps
CPU time 14.1 seconds
Started Feb 25 01:33:45 PM PST 24
Finished Feb 25 01:34:00 PM PST 24
Peak memory 197608 kb
Host smart-81f0889b-301d-4599-be30-0f4d3af47183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419161759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.419161759
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.157964199
Short name T547
Test name
Test status
Simulation time 356260280355 ps
CPU time 582.12 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:43:30 PM PST 24
Peak memory 199576 kb
Host smart-f01a2fa5-e1b3-4c13-9dc9-65ca6da38b89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157964199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.157964199
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1668108133
Short name T1066
Test name
Test status
Simulation time 130568783256 ps
CPU time 661.14 seconds
Started Feb 25 01:34:04 PM PST 24
Finished Feb 25 01:45:06 PM PST 24
Peak memory 199716 kb
Host smart-a5c7eaac-be25-4400-824e-08718e0d0a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668108133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1668108133
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3351094643
Short name T604
Test name
Test status
Simulation time 8669856677 ps
CPU time 4.95 seconds
Started Feb 25 01:33:56 PM PST 24
Finished Feb 25 01:34:02 PM PST 24
Peak memory 198228 kb
Host smart-c153baf2-b3d2-4b63-baed-3aeb063637eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351094643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3351094643
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.485191161
Short name T51
Test name
Test status
Simulation time 110714691618 ps
CPU time 40.59 seconds
Started Feb 25 01:33:47 PM PST 24
Finished Feb 25 01:34:27 PM PST 24
Peak memory 198584 kb
Host smart-2528c73c-e258-4dc7-a965-c36a5b5f8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485191161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.485191161
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1522735370
Short name T570
Test name
Test status
Simulation time 13215049219 ps
CPU time 129.21 seconds
Started Feb 25 01:33:57 PM PST 24
Finished Feb 25 01:36:07 PM PST 24
Peak memory 199648 kb
Host smart-2d156860-c777-4093-af0c-edd64fb30137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522735370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1522735370
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3360079957
Short name T765
Test name
Test status
Simulation time 3458709994 ps
CPU time 7.44 seconds
Started Feb 25 01:33:45 PM PST 24
Finished Feb 25 01:33:53 PM PST 24
Peak memory 198024 kb
Host smart-e00ca261-5a34-436e-a549-0671b3ee3e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360079957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3360079957
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2612023207
Short name T396
Test name
Test status
Simulation time 377422179563 ps
CPU time 813.5 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:47:22 PM PST 24
Peak memory 199636 kb
Host smart-19a8f449-2ba4-4c7f-abaa-8486372b5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612023207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2612023207
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1332154040
Short name T563
Test name
Test status
Simulation time 35838611995 ps
CPU time 5.89 seconds
Started Feb 25 01:33:45 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 195036 kb
Host smart-b192baa8-f184-4b76-9650-4e1f56505562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332154040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1332154040
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3534351637
Short name T467
Test name
Test status
Simulation time 270896756 ps
CPU time 1.05 seconds
Started Feb 25 01:33:45 PM PST 24
Finished Feb 25 01:33:47 PM PST 24
Peak memory 197648 kb
Host smart-7bcd6960-6cd2-4487-b7ff-8d2e780bf25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534351637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3534351637
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2328539528
Short name T1093
Test name
Test status
Simulation time 2153960592 ps
CPU time 1.68 seconds
Started Feb 25 01:33:50 PM PST 24
Finished Feb 25 01:33:52 PM PST 24
Peak memory 197376 kb
Host smart-b76eeae8-1dfc-4b6f-9668-06e528da1104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328539528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2328539528
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2032381419
Short name T663
Test name
Test status
Simulation time 62718632444 ps
CPU time 47.51 seconds
Started Feb 25 01:33:48 PM PST 24
Finished Feb 25 01:34:36 PM PST 24
Peak memory 199416 kb
Host smart-0c59dea0-469e-40b8-9d4f-7291bf23a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032381419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2032381419
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.6038135
Short name T153
Test name
Test status
Simulation time 60576853606 ps
CPU time 88.02 seconds
Started Feb 25 01:39:21 PM PST 24
Finished Feb 25 01:40:49 PM PST 24
Peak memory 199624 kb
Host smart-3edcd7fa-62a6-4fcb-a9e5-e214fea037c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6038135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.6038135
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2842104352
Short name T684
Test name
Test status
Simulation time 25000658227 ps
CPU time 38.82 seconds
Started Feb 25 01:39:20 PM PST 24
Finished Feb 25 01:39:59 PM PST 24
Peak memory 199488 kb
Host smart-15efd26c-508e-47bf-b1ea-39265a36f11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842104352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2842104352
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1624566602
Short name T1085
Test name
Test status
Simulation time 75273040869 ps
CPU time 33.33 seconds
Started Feb 25 01:39:37 PM PST 24
Finished Feb 25 01:40:11 PM PST 24
Peak memory 199684 kb
Host smart-3756d94d-393b-403b-a41c-6f0ccd9b9ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624566602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1624566602
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3336652054
Short name T1073
Test name
Test status
Simulation time 77066381668 ps
CPU time 32.32 seconds
Started Feb 25 01:39:35 PM PST 24
Finished Feb 25 01:40:08 PM PST 24
Peak memory 199332 kb
Host smart-b3f7ac55-ce9b-46ad-b47e-d63e8106cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336652054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3336652054
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2201487049
Short name T1091
Test name
Test status
Simulation time 111418217476 ps
CPU time 52.26 seconds
Started Feb 25 01:39:39 PM PST 24
Finished Feb 25 01:40:32 PM PST 24
Peak memory 199492 kb
Host smart-1f88cf95-31fa-489e-86b4-4f1929987c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201487049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2201487049
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2879161723
Short name T140
Test name
Test status
Simulation time 5964108784 ps
CPU time 3.99 seconds
Started Feb 25 01:39:33 PM PST 24
Finished Feb 25 01:39:37 PM PST 24
Peak memory 198968 kb
Host smart-c4336148-9d15-404b-be56-b6930e5401d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879161723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2879161723
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3874887461
Short name T878
Test name
Test status
Simulation time 31313983 ps
CPU time 0.53 seconds
Started Feb 25 01:34:06 PM PST 24
Finished Feb 25 01:34:08 PM PST 24
Peak memory 194984 kb
Host smart-02c4dfbe-0f7c-4a60-b428-ffc1bba81f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874887461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3874887461
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.262433454
Short name T864
Test name
Test status
Simulation time 30370755954 ps
CPU time 25.42 seconds
Started Feb 25 01:33:54 PM PST 24
Finished Feb 25 01:34:19 PM PST 24
Peak memory 199632 kb
Host smart-65c7ca0d-6887-4120-a370-42b05ae7745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262433454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.262433454
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2109344418
Short name T379
Test name
Test status
Simulation time 26727465259 ps
CPU time 43.54 seconds
Started Feb 25 01:33:58 PM PST 24
Finished Feb 25 01:34:42 PM PST 24
Peak memory 199668 kb
Host smart-677fbd89-3a2b-4506-9f75-60a5d192180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109344418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2109344418
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2948329704
Short name T143
Test name
Test status
Simulation time 12565122320 ps
CPU time 18.41 seconds
Started Feb 25 01:33:54 PM PST 24
Finished Feb 25 01:34:13 PM PST 24
Peak memory 199400 kb
Host smart-a8c18dd0-cc5a-4ea5-822f-2cbfba612f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948329704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2948329704
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.749106010
Short name T740
Test name
Test status
Simulation time 200215431815 ps
CPU time 179.52 seconds
Started Feb 25 01:33:55 PM PST 24
Finished Feb 25 01:36:55 PM PST 24
Peak memory 198400 kb
Host smart-3453ca3b-93b0-415c-a4e1-706724a55a94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749106010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.749106010
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1248539484
Short name T657
Test name
Test status
Simulation time 71415426808 ps
CPU time 717.04 seconds
Started Feb 25 01:33:53 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 199636 kb
Host smart-a17d1ccb-f325-447f-9bd9-0c272cfc57d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248539484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1248539484
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1945588475
Short name T21
Test name
Test status
Simulation time 10824927168 ps
CPU time 19.95 seconds
Started Feb 25 01:33:55 PM PST 24
Finished Feb 25 01:34:15 PM PST 24
Peak memory 198156 kb
Host smart-73958c4d-e322-4ecb-9f56-abe0b47b2027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945588475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1945588475
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.994447060
Short name T624
Test name
Test status
Simulation time 24298110035 ps
CPU time 9.79 seconds
Started Feb 25 01:34:05 PM PST 24
Finished Feb 25 01:34:15 PM PST 24
Peak memory 197712 kb
Host smart-104f03aa-bedb-4750-a41a-386094569b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994447060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.994447060
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2026537585
Short name T453
Test name
Test status
Simulation time 31054317807 ps
CPU time 229.74 seconds
Started Feb 25 01:34:00 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 199616 kb
Host smart-3b37745f-2390-41d3-85ef-2e3801056a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026537585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2026537585
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2462250278
Short name T620
Test name
Test status
Simulation time 184866731609 ps
CPU time 118.34 seconds
Started Feb 25 01:33:54 PM PST 24
Finished Feb 25 01:35:52 PM PST 24
Peak memory 199632 kb
Host smart-4f166442-07b8-41d9-bbd3-10491f465702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462250278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2462250278
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.783985730
Short name T874
Test name
Test status
Simulation time 3348530434 ps
CPU time 1.88 seconds
Started Feb 25 01:34:02 PM PST 24
Finished Feb 25 01:34:05 PM PST 24
Peak memory 195444 kb
Host smart-4460214c-2508-4c9c-b95c-3b487274b3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783985730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.783985730
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3158927374
Short name T925
Test name
Test status
Simulation time 6150324383 ps
CPU time 11.81 seconds
Started Feb 25 01:34:02 PM PST 24
Finished Feb 25 01:34:14 PM PST 24
Peak memory 198320 kb
Host smart-47ccd7bf-0bdc-46ac-a91a-ca31d357a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158927374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3158927374
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.401956021
Short name T853
Test name
Test status
Simulation time 163508384844 ps
CPU time 285.1 seconds
Started Feb 25 01:33:54 PM PST 24
Finished Feb 25 01:38:39 PM PST 24
Peak memory 215340 kb
Host smart-0a6164b6-6b41-479f-8891-879c4c223f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401956021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.401956021
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2316303800
Short name T1031
Test name
Test status
Simulation time 119265941020 ps
CPU time 359.67 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:40:03 PM PST 24
Peak memory 210272 kb
Host smart-e763728a-de6c-4e9d-afd5-098a801c3f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316303800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2316303800
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.389462848
Short name T822
Test name
Test status
Simulation time 12209471031 ps
CPU time 6 seconds
Started Feb 25 01:34:00 PM PST 24
Finished Feb 25 01:34:06 PM PST 24
Peak memory 199020 kb
Host smart-fa0130d3-68f3-4efb-9838-7f81c21e3b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389462848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.389462848
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3536326376
Short name T420
Test name
Test status
Simulation time 77317677726 ps
CPU time 33.72 seconds
Started Feb 25 01:33:53 PM PST 24
Finished Feb 25 01:34:27 PM PST 24
Peak memory 199604 kb
Host smart-f6702daf-296f-45a0-9b6b-30573a76b45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536326376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3536326376
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2312636845
Short name T911
Test name
Test status
Simulation time 31969004733 ps
CPU time 16.26 seconds
Started Feb 25 01:39:35 PM PST 24
Finished Feb 25 01:39:52 PM PST 24
Peak memory 199644 kb
Host smart-1944f531-dbba-40fc-a404-7f76927913c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312636845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2312636845
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3646031184
Short name T221
Test name
Test status
Simulation time 95142811650 ps
CPU time 145.37 seconds
Started Feb 25 01:39:35 PM PST 24
Finished Feb 25 01:42:01 PM PST 24
Peak memory 199584 kb
Host smart-74f95cb8-b942-40cc-b01a-efd710b59b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646031184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3646031184
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2392812037
Short name T331
Test name
Test status
Simulation time 10106183984 ps
CPU time 17.9 seconds
Started Feb 25 01:39:38 PM PST 24
Finished Feb 25 01:39:56 PM PST 24
Peak memory 199704 kb
Host smart-82cf0052-93e3-4e13-963b-3b0ba4f176c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392812037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2392812037
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1580033216
Short name T281
Test name
Test status
Simulation time 142335510351 ps
CPU time 17.67 seconds
Started Feb 25 01:39:35 PM PST 24
Finished Feb 25 01:39:53 PM PST 24
Peak memory 199648 kb
Host smart-3e387b14-2661-4856-a76e-d9b203d07f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580033216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1580033216
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3775633706
Short name T155
Test name
Test status
Simulation time 54199640524 ps
CPU time 6.93 seconds
Started Feb 25 01:39:39 PM PST 24
Finished Feb 25 01:39:46 PM PST 24
Peak memory 198516 kb
Host smart-7435fca5-d7d7-4d30-8529-4eb8b062e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775633706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3775633706
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2346414813
Short name T656
Test name
Test status
Simulation time 54528872609 ps
CPU time 44.38 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:40:24 PM PST 24
Peak memory 199624 kb
Host smart-ddd52a66-accd-4370-a21d-7bbfbeabad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346414813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2346414813
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.593266019
Short name T59
Test name
Test status
Simulation time 10365169717 ps
CPU time 8.19 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 199572 kb
Host smart-b635f672-d33c-4f6a-8355-7d8268de9c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593266019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.593266019
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3364466659
Short name T921
Test name
Test status
Simulation time 274834662949 ps
CPU time 97.4 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 199704 kb
Host smart-8d9f4e11-c946-41d3-8562-be808fc2b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364466659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3364466659
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.715655262
Short name T601
Test name
Test status
Simulation time 37484374 ps
CPU time 0.55 seconds
Started Feb 25 01:34:00 PM PST 24
Finished Feb 25 01:34:01 PM PST 24
Peak memory 195100 kb
Host smart-95705323-aced-4f65-8d4c-3cd766a57c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715655262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.715655262
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1530269393
Short name T1020
Test name
Test status
Simulation time 44980216315 ps
CPU time 38.7 seconds
Started Feb 25 01:34:06 PM PST 24
Finished Feb 25 01:34:46 PM PST 24
Peak memory 199500 kb
Host smart-5107a620-4573-4399-8898-552731a90f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530269393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1530269393
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.200390597
Short name T697
Test name
Test status
Simulation time 77342994989 ps
CPU time 63.39 seconds
Started Feb 25 01:34:05 PM PST 24
Finished Feb 25 01:35:08 PM PST 24
Peak memory 199576 kb
Host smart-3d4f9abd-497b-4bc6-ac3e-15f5886db69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200390597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.200390597
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2086927011
Short name T1028
Test name
Test status
Simulation time 8622828070 ps
CPU time 7.71 seconds
Started Feb 25 01:34:06 PM PST 24
Finished Feb 25 01:34:15 PM PST 24
Peak memory 199448 kb
Host smart-cf50b87d-86aa-4ddb-8f81-00d851b7fcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086927011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2086927011
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2391435460
Short name T829
Test name
Test status
Simulation time 19748065782 ps
CPU time 30.37 seconds
Started Feb 25 01:34:01 PM PST 24
Finished Feb 25 01:34:32 PM PST 24
Peak memory 197128 kb
Host smart-e3265a07-6665-4ab3-b584-aaaf3f44c2f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391435460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2391435460
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1875312665
Short name T643
Test name
Test status
Simulation time 98934383758 ps
CPU time 977.4 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:50:22 PM PST 24
Peak memory 199712 kb
Host smart-be58fe2e-bece-4527-aec3-6229bea6fb0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875312665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1875312665
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.722232203
Short name T499
Test name
Test status
Simulation time 3520045705 ps
CPU time 6.09 seconds
Started Feb 25 01:34:00 PM PST 24
Finished Feb 25 01:34:06 PM PST 24
Peak memory 195820 kb
Host smart-19cd152e-09a7-483c-a0af-1ace5c616c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722232203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.722232203
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2498810371
Short name T808
Test name
Test status
Simulation time 82385780820 ps
CPU time 189.18 seconds
Started Feb 25 01:34:08 PM PST 24
Finished Feb 25 01:37:17 PM PST 24
Peak memory 208040 kb
Host smart-48f9c4b8-1bda-4b43-814e-11accf5d75d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498810371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2498810371
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.200311569
Short name T696
Test name
Test status
Simulation time 8094220374 ps
CPU time 222.93 seconds
Started Feb 25 01:34:07 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 199608 kb
Host smart-d32f1483-36aa-4864-94f9-524b5ac15bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200311569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.200311569
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2285685074
Short name T841
Test name
Test status
Simulation time 1514682772 ps
CPU time 6.1 seconds
Started Feb 25 01:34:04 PM PST 24
Finished Feb 25 01:34:11 PM PST 24
Peak memory 197428 kb
Host smart-a1435cad-61cb-4891-9810-f89f3aafd917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285685074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2285685074
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3246691382
Short name T680
Test name
Test status
Simulation time 126984287088 ps
CPU time 83.65 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:35:28 PM PST 24
Peak memory 198992 kb
Host smart-fca69d5a-a90e-4549-ac65-6e7e1431a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246691382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3246691382
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2212192388
Short name T550
Test name
Test status
Simulation time 3688192118 ps
CPU time 0.94 seconds
Started Feb 25 01:34:07 PM PST 24
Finished Feb 25 01:34:08 PM PST 24
Peak memory 195368 kb
Host smart-821e43c8-86e0-436a-9fae-e1623afcfae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212192388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2212192388
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2685473030
Short name T539
Test name
Test status
Simulation time 693314772 ps
CPU time 3.03 seconds
Started Feb 25 01:34:06 PM PST 24
Finished Feb 25 01:34:10 PM PST 24
Peak memory 197912 kb
Host smart-e14726d6-3b9f-406a-9cb3-0e1fe3347a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685473030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2685473030
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1319856142
Short name T908
Test name
Test status
Simulation time 199441783519 ps
CPU time 307.05 seconds
Started Feb 25 01:34:07 PM PST 24
Finished Feb 25 01:39:15 PM PST 24
Peak memory 199716 kb
Host smart-79de22a2-28d7-4b16-9dc3-1c60a027e75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319856142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1319856142
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2584438944
Short name T996
Test name
Test status
Simulation time 6875364885 ps
CPU time 23.86 seconds
Started Feb 25 01:34:08 PM PST 24
Finished Feb 25 01:34:32 PM PST 24
Peak memory 198812 kb
Host smart-59865937-5ddb-43e2-a925-8eac664ec912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584438944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2584438944
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4237592775
Short name T836
Test name
Test status
Simulation time 98124121577 ps
CPU time 44.81 seconds
Started Feb 25 01:34:07 PM PST 24
Finished Feb 25 01:34:52 PM PST 24
Peak memory 199632 kb
Host smart-c9066396-ca3c-4b52-a154-c126c89d773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237592775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4237592775
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3059059684
Short name T821
Test name
Test status
Simulation time 222383279773 ps
CPU time 45.66 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:40:27 PM PST 24
Peak memory 199264 kb
Host smart-9bf72b1f-0b4d-41e8-a0cc-1d12b0fd1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059059684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3059059684
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.354651109
Short name T543
Test name
Test status
Simulation time 4932019006 ps
CPU time 8.62 seconds
Started Feb 25 01:39:41 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 198800 kb
Host smart-30040f83-7fcc-4704-8766-460e2ec2ce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354651109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.354651109
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.261223929
Short name T352
Test name
Test status
Simulation time 13618723328 ps
CPU time 25.35 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:40:06 PM PST 24
Peak memory 199344 kb
Host smart-91e34602-d86c-427c-bd1b-181e7ef4c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261223929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.261223929
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.540859972
Short name T297
Test name
Test status
Simulation time 34688291773 ps
CPU time 61.42 seconds
Started Feb 25 01:39:42 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 199572 kb
Host smart-4de2d9fe-643d-4f27-9fda-e92b740858ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540859972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.540859972
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2160292138
Short name T247
Test name
Test status
Simulation time 130863170841 ps
CPU time 33.89 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:40:14 PM PST 24
Peak memory 199548 kb
Host smart-cac8c57a-102b-43e1-81a6-b15373eaa1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160292138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2160292138
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.135026320
Short name T227
Test name
Test status
Simulation time 15687144270 ps
CPU time 23.71 seconds
Started Feb 25 01:39:40 PM PST 24
Finished Feb 25 01:40:05 PM PST 24
Peak memory 199372 kb
Host smart-9bd50b52-b5d6-42fa-af91-502f0ac9adf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135026320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.135026320
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4224244185
Short name T1100
Test name
Test status
Simulation time 23842390 ps
CPU time 0.53 seconds
Started Feb 25 01:34:12 PM PST 24
Finished Feb 25 01:34:12 PM PST 24
Peak memory 194152 kb
Host smart-a20e7e0d-7e79-4632-8f5b-cdf43f5c5a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224244185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4224244185
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3746074318
Short name T300
Test name
Test status
Simulation time 205855388306 ps
CPU time 158.84 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:36:42 PM PST 24
Peak memory 199684 kb
Host smart-81ec76bb-19b3-40d9-9d96-45110f59feb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746074318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3746074318
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1428265661
Short name T173
Test name
Test status
Simulation time 299136011799 ps
CPU time 27.45 seconds
Started Feb 25 01:34:02 PM PST 24
Finished Feb 25 01:34:30 PM PST 24
Peak memory 198996 kb
Host smart-808f6280-82a7-4d22-8047-13319d0521bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428265661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1428265661
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2030166148
Short name T1039
Test name
Test status
Simulation time 89609773972 ps
CPU time 45.93 seconds
Started Feb 25 01:34:02 PM PST 24
Finished Feb 25 01:34:49 PM PST 24
Peak memory 199572 kb
Host smart-dcf9c0af-3ac3-4079-a066-be12f7e51245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030166148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2030166148
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1171620848
Short name T782
Test name
Test status
Simulation time 484945799117 ps
CPU time 173.49 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:36:58 PM PST 24
Peak memory 196452 kb
Host smart-751ada78-37b0-4ac3-9abc-3cbb6919a9f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171620848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1171620848
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.718723558
Short name T317
Test name
Test status
Simulation time 115725852630 ps
CPU time 472.73 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:42:04 PM PST 24
Peak memory 199688 kb
Host smart-1572042c-d09c-44fc-a5fb-e3af9aff122a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718723558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.718723558
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.815035170
Short name T1069
Test name
Test status
Simulation time 10269648846 ps
CPU time 22.26 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:34:34 PM PST 24
Peak memory 198720 kb
Host smart-97329e70-022a-43f5-9da9-07cbc9a69f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815035170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.815035170
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2405726068
Short name T612
Test name
Test status
Simulation time 72319321214 ps
CPU time 135.88 seconds
Started Feb 25 01:34:02 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 198804 kb
Host smart-ef92ce7e-f6a1-4c6a-9132-b44aa7a8a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405726068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2405726068
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3665520185
Short name T197
Test name
Test status
Simulation time 19463358914 ps
CPU time 1069.81 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:52:02 PM PST 24
Peak memory 199624 kb
Host smart-bd57d280-7fb5-4b5a-b3e1-21dd5f37e6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665520185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3665520185
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2406592952
Short name T732
Test name
Test status
Simulation time 2875557500 ps
CPU time 10.88 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:34:15 PM PST 24
Peak memory 197672 kb
Host smart-f15e3608-36a0-480e-bd23-40b332b1e47b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406592952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2406592952
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.307107841
Short name T1048
Test name
Test status
Simulation time 59072676774 ps
CPU time 43.81 seconds
Started Feb 25 01:34:06 PM PST 24
Finished Feb 25 01:34:51 PM PST 24
Peak memory 199556 kb
Host smart-3219e28b-f864-4da7-8032-e8bf5c406a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307107841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.307107841
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2699821378
Short name T1084
Test name
Test status
Simulation time 677305473 ps
CPU time 0.95 seconds
Started Feb 25 01:34:01 PM PST 24
Finished Feb 25 01:34:03 PM PST 24
Peak memory 194956 kb
Host smart-5f591de1-f4ee-4d69-ab56-51858dd72fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699821378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2699821378
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1226822263
Short name T437
Test name
Test status
Simulation time 272876782 ps
CPU time 1.82 seconds
Started Feb 25 01:34:07 PM PST 24
Finished Feb 25 01:34:09 PM PST 24
Peak memory 198016 kb
Host smart-ea8fb401-e70d-448e-862f-9ec31a07c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226822263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1226822263
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.247804498
Short name T906
Test name
Test status
Simulation time 65238190939 ps
CPU time 406.14 seconds
Started Feb 25 01:34:13 PM PST 24
Finished Feb 25 01:40:59 PM PST 24
Peak memory 199620 kb
Host smart-9c557a03-7813-4185-b8e6-d7ea94f10a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247804498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.247804498
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2419963170
Short name T922
Test name
Test status
Simulation time 798260695 ps
CPU time 2.83 seconds
Started Feb 25 01:34:10 PM PST 24
Finished Feb 25 01:34:13 PM PST 24
Peak memory 197600 kb
Host smart-d6764647-631c-4c27-a70f-012ae470deee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419963170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2419963170
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2483924400
Short name T219
Test name
Test status
Simulation time 53273359359 ps
CPU time 102.12 seconds
Started Feb 25 01:34:03 PM PST 24
Finished Feb 25 01:35:46 PM PST 24
Peak memory 199636 kb
Host smart-317e1824-8648-4ea1-9640-a38b9f22e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483924400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2483924400
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3800643974
Short name T223
Test name
Test status
Simulation time 11003799846 ps
CPU time 16.12 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:40:06 PM PST 24
Peak memory 199564 kb
Host smart-26929e4d-2608-4fb9-9bc9-41815c00e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800643974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3800643974
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.4100715042
Short name T65
Test name
Test status
Simulation time 4780072657 ps
CPU time 8.06 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:39:58 PM PST 24
Peak memory 197568 kb
Host smart-cfc2acc7-4881-459f-aba9-761918e8b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100715042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.4100715042
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2475087862
Short name T813
Test name
Test status
Simulation time 39175422161 ps
CPU time 24.39 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:40:15 PM PST 24
Peak memory 199644 kb
Host smart-0d09e2fe-349d-4f84-867e-977647aeb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475087862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2475087862
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1202561561
Short name T815
Test name
Test status
Simulation time 58447959523 ps
CPU time 31.81 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:40:22 PM PST 24
Peak memory 199664 kb
Host smart-5a1d2dd4-a74a-47bf-9d33-f803da7d0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202561561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1202561561
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2989780707
Short name T171
Test name
Test status
Simulation time 16081750871 ps
CPU time 23.42 seconds
Started Feb 25 01:39:52 PM PST 24
Finished Feb 25 01:40:15 PM PST 24
Peak memory 199596 kb
Host smart-e0ad58da-5706-4bc7-9a56-8f6d93dad1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989780707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2989780707
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2641368676
Short name T250
Test name
Test status
Simulation time 4754244656 ps
CPU time 8.42 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:00 PM PST 24
Peak memory 199724 kb
Host smart-b19925e7-95d7-479a-a016-a45f15775525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641368676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2641368676
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2440610206
Short name T745
Test name
Test status
Simulation time 42741382 ps
CPU time 0.53 seconds
Started Feb 25 01:34:22 PM PST 24
Finished Feb 25 01:34:22 PM PST 24
Peak memory 195048 kb
Host smart-80cce90e-c6bc-4aff-a2cd-59c86f9b44f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440610206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2440610206
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1936809624
Short name T121
Test name
Test status
Simulation time 151832256508 ps
CPU time 296.44 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:39:08 PM PST 24
Peak memory 199644 kb
Host smart-46442a30-66c4-4f8c-89d8-09d12a479d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936809624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1936809624
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3888663256
Short name T299
Test name
Test status
Simulation time 268176958809 ps
CPU time 49.24 seconds
Started Feb 25 01:34:10 PM PST 24
Finished Feb 25 01:34:59 PM PST 24
Peak memory 199696 kb
Host smart-f52dc53c-bf8b-440a-95ab-e23da9c36e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888663256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3888663256
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3292314882
Short name T55
Test name
Test status
Simulation time 107582768466 ps
CPU time 173.06 seconds
Started Feb 25 01:34:12 PM PST 24
Finished Feb 25 01:37:05 PM PST 24
Peak memory 199672 kb
Host smart-c42cc129-935e-440f-bc92-7db1ce63398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292314882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3292314882
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2100695491
Short name T887
Test name
Test status
Simulation time 1865471563404 ps
CPU time 2919.12 seconds
Started Feb 25 01:34:12 PM PST 24
Finished Feb 25 02:22:52 PM PST 24
Peak memory 199628 kb
Host smart-e077fd7e-780b-44f3-ac0b-26fa5f32d0b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100695491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2100695491
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.984762351
Short name T582
Test name
Test status
Simulation time 129676076172 ps
CPU time 359.26 seconds
Started Feb 25 01:34:22 PM PST 24
Finished Feb 25 01:40:21 PM PST 24
Peak memory 199652 kb
Host smart-623b6f78-625c-40f9-a052-d70875781670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984762351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.984762351
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2899377678
Short name T546
Test name
Test status
Simulation time 5157604132 ps
CPU time 12.42 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:34:34 PM PST 24
Peak memory 198900 kb
Host smart-a2d0724b-7dee-4ef8-830b-fdef81ddaa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899377678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2899377678
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2654127624
Short name T959
Test name
Test status
Simulation time 77070221041 ps
CPU time 142.17 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:36:33 PM PST 24
Peak memory 199688 kb
Host smart-67b4b486-43a4-4b21-9d76-8460bcfe8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654127624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2654127624
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2768406966
Short name T691
Test name
Test status
Simulation time 16490069693 ps
CPU time 801 seconds
Started Feb 25 01:34:22 PM PST 24
Finished Feb 25 01:47:43 PM PST 24
Peak memory 199572 kb
Host smart-05ed811a-59b7-4d6b-bbb1-d73f247244ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768406966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2768406966
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.173825125
Short name T831
Test name
Test status
Simulation time 61917443510 ps
CPU time 89.55 seconds
Started Feb 25 01:34:24 PM PST 24
Finished Feb 25 01:35:53 PM PST 24
Peak memory 199700 kb
Host smart-65407537-ca94-4da5-91b2-398a46945da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173825125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.173825125
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.410882151
Short name T439
Test name
Test status
Simulation time 4587859181 ps
CPU time 1.69 seconds
Started Feb 25 01:34:12 PM PST 24
Finished Feb 25 01:34:14 PM PST 24
Peak memory 195352 kb
Host smart-c041b049-eb4c-42e1-978b-e09ce9a50c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410882151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.410882151
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3938038469
Short name T880
Test name
Test status
Simulation time 6074183039 ps
CPU time 7.74 seconds
Started Feb 25 01:34:09 PM PST 24
Finished Feb 25 01:34:17 PM PST 24
Peak memory 198464 kb
Host smart-d46e5c05-55f1-4bed-b996-98d2ac695c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938038469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3938038469
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2783559003
Short name T755
Test name
Test status
Simulation time 511092536411 ps
CPU time 533.84 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:43:15 PM PST 24
Peak memory 199616 kb
Host smart-fa0b00f8-8a17-46d0-ad21-6dba5ec7ecd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783559003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2783559003
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2766069496
Short name T639
Test name
Test status
Simulation time 26237885968 ps
CPU time 297.56 seconds
Started Feb 25 01:34:22 PM PST 24
Finished Feb 25 01:39:20 PM PST 24
Peak memory 211392 kb
Host smart-0d4d7a3f-e1bb-4a75-ba68-73f80b70cfe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766069496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2766069496
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2916628301
Short name T489
Test name
Test status
Simulation time 19062020481 ps
CPU time 10.85 seconds
Started Feb 25 01:34:23 PM PST 24
Finished Feb 25 01:34:34 PM PST 24
Peak memory 199528 kb
Host smart-92fd9f1d-fb58-429c-93eb-c6b9baa92806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916628301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2916628301
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3672156229
Short name T165
Test name
Test status
Simulation time 3765234333 ps
CPU time 2.35 seconds
Started Feb 25 01:34:11 PM PST 24
Finished Feb 25 01:34:14 PM PST 24
Peak memory 197760 kb
Host smart-50cc8c1b-977f-4c61-b37d-a804c5895764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672156229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3672156229
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3847947077
Short name T759
Test name
Test status
Simulation time 22716214009 ps
CPU time 11.97 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:04 PM PST 24
Peak memory 199312 kb
Host smart-4e4391fe-a2cc-4322-9fdb-03c2d4820f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847947077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3847947077
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1315135788
Short name T207
Test name
Test status
Simulation time 121766443926 ps
CPU time 14.28 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:06 PM PST 24
Peak memory 199432 kb
Host smart-775d41cd-d1ea-49da-b0e2-91a14202c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315135788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1315135788
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3742150601
Short name T283
Test name
Test status
Simulation time 112282576126 ps
CPU time 46.35 seconds
Started Feb 25 01:39:57 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 199636 kb
Host smart-128d8a6e-448b-4db6-9ca8-38836c93d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742150601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3742150601
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1003042357
Short name T154
Test name
Test status
Simulation time 14063292455 ps
CPU time 24.19 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:16 PM PST 24
Peak memory 199584 kb
Host smart-42f65548-e7ae-413e-b064-82be93f4101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003042357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1003042357
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.704977192
Short name T211
Test name
Test status
Simulation time 12867488390 ps
CPU time 23.24 seconds
Started Feb 25 01:39:52 PM PST 24
Finished Feb 25 01:40:16 PM PST 24
Peak memory 199680 kb
Host smart-1ae4a23a-a9b6-4424-9995-7b680a49f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704977192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.704977192
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.90098118
Short name T1103
Test name
Test status
Simulation time 8517809068 ps
CPU time 17.26 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:09 PM PST 24
Peak memory 199272 kb
Host smart-3e82fdff-58ef-461e-8372-cc11b0aa582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90098118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.90098118
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.304684605
Short name T377
Test name
Test status
Simulation time 66630269935 ps
CPU time 32.59 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:40:23 PM PST 24
Peak memory 199524 kb
Host smart-3b37971b-c6a7-4658-b47f-a6f7eb414450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304684605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.304684605
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3102776378
Short name T978
Test name
Test status
Simulation time 117100364501 ps
CPU time 194.72 seconds
Started Feb 25 01:39:50 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 199576 kb
Host smart-aed2ea11-2783-4e67-8d2e-5e6f098d27c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102776378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3102776378
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4206452506
Short name T278
Test name
Test status
Simulation time 30022100530 ps
CPU time 66.01 seconds
Started Feb 25 01:39:51 PM PST 24
Finished Feb 25 01:40:57 PM PST 24
Peak memory 199628 kb
Host smart-e4a294c0-927c-479f-81ff-ca4b10510b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206452506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4206452506
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1558454109
Short name T764
Test name
Test status
Simulation time 19042889 ps
CPU time 0.56 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:32:37 PM PST 24
Peak memory 195040 kb
Host smart-32ddb93f-e06e-4350-89f5-07cf55d07cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558454109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1558454109
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1062290527
Short name T389
Test name
Test status
Simulation time 153421584537 ps
CPU time 88.95 seconds
Started Feb 25 01:32:41 PM PST 24
Finished Feb 25 01:34:11 PM PST 24
Peak memory 199636 kb
Host smart-0f9d7ce1-0a76-4c2b-8332-28bb463fc64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062290527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1062290527
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.275979766
Short name T1055
Test name
Test status
Simulation time 86495808837 ps
CPU time 36.91 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:33:06 PM PST 24
Peak memory 198852 kb
Host smart-3329017d-5737-409e-b856-11b9229300cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275979766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.275979766
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1415956101
Short name T217
Test name
Test status
Simulation time 268698738049 ps
CPU time 36.04 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:33:05 PM PST 24
Peak memory 198924 kb
Host smart-5c42fcda-cc20-4f98-8d14-6c05bedcd469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415956101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1415956101
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2007560761
Short name T190
Test name
Test status
Simulation time 394706781670 ps
CPU time 693.47 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:44:05 PM PST 24
Peak memory 199696 kb
Host smart-e75bef99-0cb9-46f8-9227-a1456b233b82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007560761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2007560761
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.732356994
Short name T1057
Test name
Test status
Simulation time 205188499888 ps
CPU time 580.55 seconds
Started Feb 25 01:32:39 PM PST 24
Finished Feb 25 01:42:20 PM PST 24
Peak memory 199572 kb
Host smart-451e0c88-05ac-407c-81e9-f1584ec88542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732356994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.732356994
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1515128311
Short name T979
Test name
Test status
Simulation time 7557998620 ps
CPU time 4.52 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:42 PM PST 24
Peak memory 199572 kb
Host smart-44b84a31-b6be-4ed4-a68c-3859c13dce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515128311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1515128311
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.981888575
Short name T615
Test name
Test status
Simulation time 5022977021 ps
CPU time 7.83 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:45 PM PST 24
Peak memory 195364 kb
Host smart-9b766670-d80a-4701-851e-911129072542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981888575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.981888575
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3256746820
Short name T784
Test name
Test status
Simulation time 11795780671 ps
CPU time 178.94 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:35:36 PM PST 24
Peak memory 199636 kb
Host smart-e9845159-3fde-4acf-a29e-558fe5349423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256746820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3256746820
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3554318506
Short name T866
Test name
Test status
Simulation time 3930708143 ps
CPU time 11.34 seconds
Started Feb 25 01:32:30 PM PST 24
Finished Feb 25 01:32:41 PM PST 24
Peak memory 198300 kb
Host smart-e86e7c77-9a59-4875-a25f-57c44944026d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554318506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3554318506
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1173147567
Short name T245
Test name
Test status
Simulation time 93648122735 ps
CPU time 81.81 seconds
Started Feb 25 01:32:35 PM PST 24
Finished Feb 25 01:33:57 PM PST 24
Peak memory 198824 kb
Host smart-27eb807e-e07f-449b-935d-fc1b29d84fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173147567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1173147567
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2202099905
Short name T428
Test name
Test status
Simulation time 36751833116 ps
CPU time 15.54 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:53 PM PST 24
Peak memory 195084 kb
Host smart-aad0f439-c03b-4df7-9dda-a54dc626b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202099905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2202099905
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.2277773251
Short name T7
Test name
Test status
Simulation time 5470615260 ps
CPU time 23.66 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:32:54 PM PST 24
Peak memory 199096 kb
Host smart-4e73289a-236a-44f1-b2e8-b2a3b612b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277773251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2277773251
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3062671232
Short name T591
Test name
Test status
Simulation time 61181756878 ps
CPU time 91.38 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:34:21 PM PST 24
Peak memory 199316 kb
Host smart-9be9cfcb-132d-4b60-85fb-bf8e77c88667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062671232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3062671232
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1516926239
Short name T118
Test name
Test status
Simulation time 256508810915 ps
CPU time 682.44 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:44:12 PM PST 24
Peak memory 215896 kb
Host smart-934f1d3c-c19d-4609-911b-cde86c68c911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516926239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1516926239
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.4210025662
Short name T631
Test name
Test status
Simulation time 6177120659 ps
CPU time 18.22 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:32:54 PM PST 24
Peak memory 199116 kb
Host smart-05b5c7e1-9bf7-4333-be4c-0eda098c9659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210025662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4210025662
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_alert_test.509455214
Short name T540
Test name
Test status
Simulation time 13822616 ps
CPU time 0.56 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:34:58 PM PST 24
Peak memory 194068 kb
Host smart-a206f743-2736-4c36-b616-29e33218fe72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509455214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.509455214
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.202668242
Short name T872
Test name
Test status
Simulation time 41162921111 ps
CPU time 35.29 seconds
Started Feb 25 01:34:24 PM PST 24
Finished Feb 25 01:35:00 PM PST 24
Peak memory 199460 kb
Host smart-785a3a9c-99b1-4e08-8342-8bb4b738d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202668242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.202668242
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_intr.2249542201
Short name T148
Test name
Test status
Simulation time 234818193228 ps
CPU time 393.9 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:40:55 PM PST 24
Peak memory 198904 kb
Host smart-a1d0cbe3-fa1f-497d-83bc-c67303d356bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249542201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2249542201
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1704920905
Short name T681
Test name
Test status
Simulation time 83504177326 ps
CPU time 172.72 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 199632 kb
Host smart-d5a82974-9faf-44aa-9ede-522d4a5cb42d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704920905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1704920905
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2027073498
Short name T972
Test name
Test status
Simulation time 4543205711 ps
CPU time 13.04 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:34:34 PM PST 24
Peak memory 198268 kb
Host smart-2fe8b9c4-ff34-4568-9a2a-85fd2bf64fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027073498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2027073498
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1702809042
Short name T440
Test name
Test status
Simulation time 119998047229 ps
CPU time 57.97 seconds
Started Feb 25 01:34:23 PM PST 24
Finished Feb 25 01:35:21 PM PST 24
Peak memory 208104 kb
Host smart-e2e7c554-0c90-4fc1-9287-da8c9a334a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702809042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1702809042
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.166466538
Short name T913
Test name
Test status
Simulation time 20998273012 ps
CPU time 1023.65 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:52:01 PM PST 24
Peak memory 199628 kb
Host smart-0dafe5d9-d83f-400b-84b7-d614c27197b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166466538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.166466538
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4254665412
Short name T535
Test name
Test status
Simulation time 3859554378 ps
CPU time 10.35 seconds
Started Feb 25 01:34:25 PM PST 24
Finished Feb 25 01:34:36 PM PST 24
Peak memory 198208 kb
Host smart-6d90bf14-1eb5-41eb-a73c-558013717823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254665412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4254665412
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1790457721
Short name T360
Test name
Test status
Simulation time 61745649684 ps
CPU time 12.87 seconds
Started Feb 25 01:34:23 PM PST 24
Finished Feb 25 01:34:36 PM PST 24
Peak memory 199608 kb
Host smart-35f38ee9-de5a-4290-a7a7-5d4c71fe1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790457721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1790457721
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4250323431
Short name T846
Test name
Test status
Simulation time 3119415367 ps
CPU time 1.9 seconds
Started Feb 25 01:34:24 PM PST 24
Finished Feb 25 01:34:27 PM PST 24
Peak memory 194976 kb
Host smart-85473503-9369-4977-bd31-1c0fd69548c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250323431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4250323431
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2925842309
Short name T909
Test name
Test status
Simulation time 639947540 ps
CPU time 2.07 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:34:23 PM PST 24
Peak memory 198124 kb
Host smart-300a9fc0-3f36-4e70-b24e-d44bfb7267ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925842309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2925842309
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.307919588
Short name T800
Test name
Test status
Simulation time 414778300 ps
CPU time 1.74 seconds
Started Feb 25 01:34:21 PM PST 24
Finished Feb 25 01:34:23 PM PST 24
Peak memory 197916 kb
Host smart-6dececdd-b2b4-4b1d-ad3b-fd3368c07d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307919588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.307919588
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3396216441
Short name T63
Test name
Test status
Simulation time 75478631190 ps
CPU time 33.28 seconds
Started Feb 25 01:34:23 PM PST 24
Finished Feb 25 01:34:56 PM PST 24
Peak memory 199500 kb
Host smart-10d4bba1-3fe3-4588-a159-bddf33f5655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396216441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3396216441
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.136252237
Short name T368
Test name
Test status
Simulation time 38219116308 ps
CPU time 25.02 seconds
Started Feb 25 01:40:03 PM PST 24
Finished Feb 25 01:40:28 PM PST 24
Peak memory 199492 kb
Host smart-b75ce621-bed1-4421-9e7e-77c48153280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136252237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.136252237
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.188349410
Short name T367
Test name
Test status
Simulation time 47552451594 ps
CPU time 36.32 seconds
Started Feb 25 01:40:05 PM PST 24
Finished Feb 25 01:40:41 PM PST 24
Peak memory 199604 kb
Host smart-b3fc49eb-2753-4e87-9e94-e09a55dce344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188349410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.188349410
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3739527016
Short name T339
Test name
Test status
Simulation time 37680748587 ps
CPU time 48.19 seconds
Started Feb 25 01:40:00 PM PST 24
Finished Feb 25 01:40:48 PM PST 24
Peak memory 199548 kb
Host smart-ba9d02db-52b5-46d9-b088-0f109854e7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739527016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3739527016
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4080202292
Short name T343
Test name
Test status
Simulation time 19598327140 ps
CPU time 15.41 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:40:16 PM PST 24
Peak memory 197340 kb
Host smart-ddb67bca-8855-4179-98eb-2d83842a7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080202292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4080202292
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3352658868
Short name T337
Test name
Test status
Simulation time 395751170377 ps
CPU time 126.84 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:42:09 PM PST 24
Peak memory 199356 kb
Host smart-381b9c36-b8b5-4f59-a7e0-874f16a5c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352658868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3352658868
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3792533730
Short name T718
Test name
Test status
Simulation time 13889272639 ps
CPU time 20.12 seconds
Started Feb 25 01:40:03 PM PST 24
Finished Feb 25 01:40:23 PM PST 24
Peak memory 199076 kb
Host smart-b6d251e8-6d64-4b95-804c-451890f815c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792533730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3792533730
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3587107984
Short name T761
Test name
Test status
Simulation time 84906732259 ps
CPU time 76.54 seconds
Started Feb 25 01:40:05 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 199644 kb
Host smart-1e675274-8167-481a-b6cc-af761ab329d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587107984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3587107984
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3776673041
Short name T302
Test name
Test status
Simulation time 16188302608 ps
CPU time 25.69 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:40:26 PM PST 24
Peak memory 199132 kb
Host smart-dcf31488-6d16-4235-bdc2-6b68607bd7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776673041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3776673041
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.499368309
Short name T598
Test name
Test status
Simulation time 88358377251 ps
CPU time 64 seconds
Started Feb 25 01:40:00 PM PST 24
Finished Feb 25 01:41:05 PM PST 24
Peak memory 199460 kb
Host smart-0c50a085-29a4-42ee-9ae8-af8bc06c29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499368309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.499368309
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3932332392
Short name T1060
Test name
Test status
Simulation time 16890616 ps
CPU time 0.56 seconds
Started Feb 25 01:34:52 PM PST 24
Finished Feb 25 01:34:54 PM PST 24
Peak memory 195192 kb
Host smart-080e0567-371a-4145-b3af-dc6cbac9439b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932332392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3932332392
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3023790353
Short name T237
Test name
Test status
Simulation time 66630396200 ps
CPU time 60.22 seconds
Started Feb 25 01:34:56 PM PST 24
Finished Feb 25 01:35:57 PM PST 24
Peak memory 199500 kb
Host smart-b1f4acb9-6b5d-4a1b-b18a-c88f185fd1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023790353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3023790353
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2484784968
Short name T876
Test name
Test status
Simulation time 179448310291 ps
CPU time 266.05 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:39:25 PM PST 24
Peak memory 198696 kb
Host smart-389c715e-c355-4038-9994-02cdabe81656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484784968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2484784968
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1989833056
Short name T946
Test name
Test status
Simulation time 10857236887 ps
CPU time 19.93 seconds
Started Feb 25 01:34:59 PM PST 24
Finished Feb 25 01:35:19 PM PST 24
Peak memory 199636 kb
Host smart-5a27d05b-f432-4c74-8a4f-ae8a2bc6aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989833056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1989833056
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3808357404
Short name T527
Test name
Test status
Simulation time 168566283860 ps
CPU time 127.99 seconds
Started Feb 25 01:34:59 PM PST 24
Finished Feb 25 01:37:07 PM PST 24
Peak memory 199656 kb
Host smart-2c48cb30-a566-4510-b87c-7e84987a2c31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808357404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3808357404
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.885871587
Short name T730
Test name
Test status
Simulation time 93252198303 ps
CPU time 234.41 seconds
Started Feb 25 01:34:59 PM PST 24
Finished Feb 25 01:38:53 PM PST 24
Peak memory 199636 kb
Host smart-935f4a57-dff5-4485-8c4d-5f6eac1b7fbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885871587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.885871587
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1128143598
Short name T1086
Test name
Test status
Simulation time 5655528208 ps
CPU time 4.7 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:35:02 PM PST 24
Peak memory 198596 kb
Host smart-847a52e7-f452-49a0-84a1-b7d98873f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128143598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1128143598
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.21237404
Short name T928
Test name
Test status
Simulation time 99458851998 ps
CPU time 44.84 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:35:51 PM PST 24
Peak memory 199480 kb
Host smart-07d45aae-cf9e-437a-949d-8c29be2703a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21237404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.21237404
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.295760205
Short name T692
Test name
Test status
Simulation time 9994541105 ps
CPU time 599.24 seconds
Started Feb 25 01:34:33 PM PST 24
Finished Feb 25 01:44:33 PM PST 24
Peak memory 199700 kb
Host smart-39c6ebce-a757-4371-9b04-e792ec0f831b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295760205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.295760205
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3131782744
Short name T1068
Test name
Test status
Simulation time 1841070662 ps
CPU time 9.3 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:35:08 PM PST 24
Peak memory 197896 kb
Host smart-cfb5cdbc-a68c-4246-9573-7693bdcf71de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131782744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3131782744
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3139163511
Short name T756
Test name
Test status
Simulation time 740778081 ps
CPU time 1.55 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:34:59 PM PST 24
Peak memory 195060 kb
Host smart-ba89e405-ca94-4051-8ee7-784c761d3377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139163511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3139163511
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1369560698
Short name T607
Test name
Test status
Simulation time 5346852254 ps
CPU time 17.19 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:35:14 PM PST 24
Peak memory 198932 kb
Host smart-942aaca3-33fc-47da-b46e-ea2945eea0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369560698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1369560698
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3746829391
Short name T619
Test name
Test status
Simulation time 2865186652 ps
CPU time 2.98 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:35:01 PM PST 24
Peak memory 198016 kb
Host smart-9561627b-9f70-4997-a054-809cc49f5cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746829391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3746829391
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3713947839
Short name T973
Test name
Test status
Simulation time 7991038421 ps
CPU time 12.74 seconds
Started Feb 25 01:34:57 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 198396 kb
Host smart-c62f1346-14ce-48ad-bcd5-de734e440b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713947839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3713947839
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2791172508
Short name T225
Test name
Test status
Simulation time 91688903417 ps
CPU time 37.7 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:40:40 PM PST 24
Peak memory 199556 kb
Host smart-64127bb7-aa5c-4ac6-b9a8-c041492b7f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791172508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2791172508
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1502327893
Short name T319
Test name
Test status
Simulation time 107159942410 ps
CPU time 85.96 seconds
Started Feb 25 01:40:05 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 199688 kb
Host smart-30df9543-f771-4c95-b250-357bdc2117e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502327893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1502327893
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.386833688
Short name T810
Test name
Test status
Simulation time 44496870451 ps
CPU time 18.83 seconds
Started Feb 25 01:40:00 PM PST 24
Finished Feb 25 01:40:20 PM PST 24
Peak memory 199044 kb
Host smart-3a66d3ed-5d68-4592-8a68-06c42600c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386833688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.386833688
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.438644088
Short name T927
Test name
Test status
Simulation time 115748571104 ps
CPU time 43.43 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:40:42 PM PST 24
Peak memory 199540 kb
Host smart-2dae3154-3329-4fd6-8254-b2ce899c88ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438644088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.438644088
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3361130678
Short name T1104
Test name
Test status
Simulation time 38895221877 ps
CPU time 16.16 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:40:18 PM PST 24
Peak memory 198012 kb
Host smart-ded24188-3e8d-4e3a-8ccb-912d8efd8603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361130678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3361130678
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1167747597
Short name T213
Test name
Test status
Simulation time 145338132486 ps
CPU time 31.3 seconds
Started Feb 25 01:40:03 PM PST 24
Finished Feb 25 01:40:34 PM PST 24
Peak memory 198824 kb
Host smart-2bf2df56-7dfb-4b98-9b12-36b9a9319e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167747597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1167747597
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1364537137
Short name T1087
Test name
Test status
Simulation time 97308180248 ps
CPU time 141.39 seconds
Started Feb 25 01:40:01 PM PST 24
Finished Feb 25 01:42:23 PM PST 24
Peak memory 199396 kb
Host smart-8d045e05-4f02-4b49-a5b5-c40bf9c19aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364537137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1364537137
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4263351069
Short name T330
Test name
Test status
Simulation time 34265330325 ps
CPU time 60.64 seconds
Started Feb 25 01:40:03 PM PST 24
Finished Feb 25 01:41:04 PM PST 24
Peak memory 199736 kb
Host smart-c544e88b-b461-414a-b407-41a5b15d1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263351069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4263351069
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1621017423
Short name T812
Test name
Test status
Simulation time 22617562 ps
CPU time 0.54 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:07 PM PST 24
Peak memory 195096 kb
Host smart-623c0633-7a89-4faf-bbf1-02c46fa46531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621017423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1621017423
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2233699757
Short name T150
Test name
Test status
Simulation time 77388174711 ps
CPU time 60.47 seconds
Started Feb 25 01:35:05 PM PST 24
Finished Feb 25 01:36:07 PM PST 24
Peak memory 199536 kb
Host smart-9d2f10c1-dd11-4d3a-ae6e-61d9344725e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233699757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2233699757
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4139745833
Short name T318
Test name
Test status
Simulation time 46403485192 ps
CPU time 153.05 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 01:37:46 PM PST 24
Peak memory 199728 kb
Host smart-d18b5a81-6f70-4df5-a5af-bfff496ef06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139745833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4139745833
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_noise_filter.153378830
Short name T838
Test name
Test status
Simulation time 153905534912 ps
CPU time 71.34 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:36:11 PM PST 24
Peak memory 207964 kb
Host smart-88f2d3c9-1962-40c1-8b3c-8567b1cb7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153378830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.153378830
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1155106524
Short name T763
Test name
Test status
Simulation time 20167473632 ps
CPU time 529.75 seconds
Started Feb 25 01:35:10 PM PST 24
Finished Feb 25 01:44:00 PM PST 24
Peak memory 199692 kb
Host smart-9d19823a-c4e5-4691-8d39-7c76ef545b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155106524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1155106524
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2662581712
Short name T492
Test name
Test status
Simulation time 3226486462 ps
CPU time 24.23 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:35:24 PM PST 24
Peak memory 198200 kb
Host smart-ea474ebe-6503-4ac7-ba4a-7fd6d11a549b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662581712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2662581712
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3531741114
Short name T564
Test name
Test status
Simulation time 84314866094 ps
CPU time 14.93 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:22 PM PST 24
Peak memory 199388 kb
Host smart-3025ea8a-ac69-4181-8d82-ba352bd60237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531741114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3531741114
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1678423029
Short name T448
Test name
Test status
Simulation time 5410281321 ps
CPU time 2.86 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 195464 kb
Host smart-e3384ff1-5a5b-4ef6-8914-d29db3f72898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678423029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1678423029
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1476342766
Short name T462
Test name
Test status
Simulation time 656073315 ps
CPU time 1.38 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 197664 kb
Host smart-8ce5717e-e631-4083-8750-a9102fc4284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476342766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1476342766
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3893778540
Short name T1108
Test name
Test status
Simulation time 2338044776 ps
CPU time 2.12 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 198736 kb
Host smart-4085bfb6-b5f4-467d-bafc-8f8c29de1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893778540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3893778540
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3350279660
Short name T44
Test name
Test status
Simulation time 50297325409 ps
CPU time 13.46 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:21 PM PST 24
Peak memory 199628 kb
Host smart-654fe760-2521-43c7-8715-b99db7c86ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350279660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3350279660
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3794198986
Short name T209
Test name
Test status
Simulation time 32006678018 ps
CPU time 10.22 seconds
Started Feb 25 01:40:00 PM PST 24
Finished Feb 25 01:40:11 PM PST 24
Peak memory 199344 kb
Host smart-c133e929-1442-49e8-a337-9f8f55b82594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794198986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3794198986
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4208706992
Short name T712
Test name
Test status
Simulation time 100843211774 ps
CPU time 15.92 seconds
Started Feb 25 01:40:03 PM PST 24
Finished Feb 25 01:40:19 PM PST 24
Peak memory 199040 kb
Host smart-2d48f28f-19ca-4aa2-ab66-38c1c1f9469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208706992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4208706992
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.727815981
Short name T728
Test name
Test status
Simulation time 24129250554 ps
CPU time 44.32 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 199584 kb
Host smart-61bdc91f-cf70-40c6-8cf0-6ca67e2a0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727815981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.727815981
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1451666518
Short name T356
Test name
Test status
Simulation time 190111118916 ps
CPU time 317.18 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:45:19 PM PST 24
Peak memory 199632 kb
Host smart-34488c61-f10e-4239-aee3-52eac9f3b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451666518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1451666518
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1776104047
Short name T661
Test name
Test status
Simulation time 32570459110 ps
CPU time 11.99 seconds
Started Feb 25 01:40:02 PM PST 24
Finished Feb 25 01:40:14 PM PST 24
Peak memory 199292 kb
Host smart-76c93d08-ebed-413e-9e33-bfa6aefa9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776104047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1776104047
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1276377854
Short name T347
Test name
Test status
Simulation time 124943782161 ps
CPU time 96.78 seconds
Started Feb 25 01:39:59 PM PST 24
Finished Feb 25 01:41:36 PM PST 24
Peak memory 199620 kb
Host smart-3c7188ca-a4c9-4bb9-819f-631cbd0c9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276377854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1276377854
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3241828362
Short name T371
Test name
Test status
Simulation time 30099028365 ps
CPU time 51.97 seconds
Started Feb 25 01:40:05 PM PST 24
Finished Feb 25 01:40:57 PM PST 24
Peak memory 199624 kb
Host smart-1b560287-9d38-47af-8d8e-2fee0caf1b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241828362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3241828362
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2245070300
Short name T193
Test name
Test status
Simulation time 130174908910 ps
CPU time 93.13 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:41:53 PM PST 24
Peak memory 199564 kb
Host smart-42ac1a48-1c41-418f-849b-faf5e396e409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245070300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2245070300
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2966378608
Short name T674
Test name
Test status
Simulation time 14994033 ps
CPU time 0.56 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:35:02 PM PST 24
Peak memory 195096 kb
Host smart-0f751653-b942-4186-83af-c951f01ff7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966378608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2966378608
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2922776903
Short name T345
Test name
Test status
Simulation time 91940904432 ps
CPU time 13.7 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:21 PM PST 24
Peak memory 198500 kb
Host smart-fb633354-6d7a-4212-8d10-d1466f96aa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922776903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2922776903
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2898595908
Short name T240
Test name
Test status
Simulation time 94202834158 ps
CPU time 71.73 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:36:20 PM PST 24
Peak memory 199560 kb
Host smart-b7b7e3fa-e979-4e43-b75c-89445d92a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898595908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2898595908
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.185460795
Short name T1005
Test name
Test status
Simulation time 67321263912 ps
CPU time 110.21 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:36:58 PM PST 24
Peak memory 199596 kb
Host smart-0864d496-22f7-4078-94a3-717af19a047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185460795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.185460795
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3377201606
Short name T773
Test name
Test status
Simulation time 2371232255508 ps
CPU time 3123 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 02:27:16 PM PST 24
Peak memory 199140 kb
Host smart-107dedf8-3a94-4b08-b07d-3788f699538a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377201606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3377201606
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2963060438
Short name T113
Test name
Test status
Simulation time 94501660894 ps
CPU time 676.34 seconds
Started Feb 25 01:34:58 PM PST 24
Finished Feb 25 01:46:15 PM PST 24
Peak memory 199564 kb
Host smart-6a743d99-85ed-4522-804a-0574d0d10689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963060438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2963060438
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4131675883
Short name T23
Test name
Test status
Simulation time 1117270997 ps
CPU time 2.48 seconds
Started Feb 25 01:35:03 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 197744 kb
Host smart-0d541f89-146e-4bea-ad4a-37062f689d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131675883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4131675883
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4115579309
Short name T430
Test name
Test status
Simulation time 23729181392 ps
CPU time 40.32 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 01:35:54 PM PST 24
Peak memory 196148 kb
Host smart-5745c0ad-fc45-4f22-93af-7ee470075525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115579309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4115579309
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1121751418
Short name T882
Test name
Test status
Simulation time 18971682513 ps
CPU time 459.24 seconds
Started Feb 25 01:35:03 PM PST 24
Finished Feb 25 01:42:45 PM PST 24
Peak memory 199692 kb
Host smart-d9333408-c510-49f0-b8d7-dee672d193b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121751418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1121751418
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4009452526
Short name T638
Test name
Test status
Simulation time 130498550 ps
CPU time 0.66 seconds
Started Feb 25 01:35:05 PM PST 24
Finished Feb 25 01:35:07 PM PST 24
Peak memory 195044 kb
Host smart-5efac134-1fcf-463a-9cd3-457b7ad7ee68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4009452526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4009452526
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3735895047
Short name T926
Test name
Test status
Simulation time 145495690277 ps
CPU time 203.03 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:38:30 PM PST 24
Peak memory 198804 kb
Host smart-ca36a696-6c7e-4829-aeef-df9eaacfa08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735895047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3735895047
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1647959869
Short name T944
Test name
Test status
Simulation time 867413630 ps
CPU time 0.96 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 195000 kb
Host smart-f60c1615-2591-40f7-9060-ea40f7a7ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647959869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1647959869
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4008807097
Short name T452
Test name
Test status
Simulation time 11073889123 ps
CPU time 12.7 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:20 PM PST 24
Peak memory 198504 kb
Host smart-764310c8-b3b9-4d52-904e-71de67a528a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008807097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4008807097
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1077603011
Short name T760
Test name
Test status
Simulation time 164261485797 ps
CPU time 1019.29 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:52:06 PM PST 24
Peak memory 199664 kb
Host smart-e8859e94-9a87-495b-a75b-237a8b3a86ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077603011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1077603011
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1439197066
Short name T605
Test name
Test status
Simulation time 582667794 ps
CPU time 1.63 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:35:03 PM PST 24
Peak memory 199488 kb
Host smart-d730341e-dbb5-42b1-9991-531dd424991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439197066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1439197066
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1083779041
Short name T553
Test name
Test status
Simulation time 88757632811 ps
CPU time 151.37 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 199692 kb
Host smart-d3648c2f-c62e-4357-a8dd-92460d0914e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083779041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1083779041
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2008577978
Short name T679
Test name
Test status
Simulation time 151661188312 ps
CPU time 73.83 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 199688 kb
Host smart-b28afbec-4d0d-41b7-969d-275106c4ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008577978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2008577978
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3688296029
Short name T266
Test name
Test status
Simulation time 18191403313 ps
CPU time 7.05 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:40:27 PM PST 24
Peak memory 199564 kb
Host smart-bdbb7aa4-a7df-4a20-afb8-6663fbd34179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688296029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3688296029
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1546321738
Short name T703
Test name
Test status
Simulation time 146206773839 ps
CPU time 231.33 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:44:11 PM PST 24
Peak memory 199576 kb
Host smart-33867eaa-4b43-492a-8151-8cd667c6b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546321738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1546321738
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1507579068
Short name T323
Test name
Test status
Simulation time 147379758162 ps
CPU time 275.42 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 199620 kb
Host smart-40e4fde7-4db4-42bd-ba2a-7c301ecafffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507579068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1507579068
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3052002739
Short name T218
Test name
Test status
Simulation time 137902720098 ps
CPU time 104.82 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:42:03 PM PST 24
Peak memory 199652 kb
Host smart-50d743de-0724-481f-94c4-ff6f5c788a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052002739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3052002739
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2443852253
Short name T742
Test name
Test status
Simulation time 112290315143 ps
CPU time 56.8 seconds
Started Feb 25 01:40:24 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 199624 kb
Host smart-0069288d-1fef-49bd-9ad5-4e14596ba9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443852253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2443852253
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2561843949
Short name T124
Test name
Test status
Simulation time 31077165240 ps
CPU time 11.49 seconds
Started Feb 25 01:40:22 PM PST 24
Finished Feb 25 01:40:34 PM PST 24
Peak memory 198704 kb
Host smart-874cc8e5-53e1-40e9-88df-010dba5f0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561843949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2561843949
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2843517909
Short name T907
Test name
Test status
Simulation time 108702122706 ps
CPU time 47.59 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:41:05 PM PST 24
Peak memory 199636 kb
Host smart-68ab9abd-83be-42f3-8cc4-19c24583ccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843517909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2843517909
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3390938482
Short name T326
Test name
Test status
Simulation time 21222637331 ps
CPU time 52.82 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:41:11 PM PST 24
Peak memory 199644 kb
Host smart-5478f32d-71f9-4545-9bc2-1930fb808701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390938482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3390938482
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3260852340
Short name T105
Test name
Test status
Simulation time 11570876 ps
CPU time 0.57 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:08 PM PST 24
Peak memory 195092 kb
Host smart-6f842ece-db6f-408e-990c-cff3d9bf1282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260852340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3260852340
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1798975937
Short name T650
Test name
Test status
Simulation time 107840706145 ps
CPU time 82.97 seconds
Started Feb 25 01:35:05 PM PST 24
Finished Feb 25 01:36:29 PM PST 24
Peak memory 199540 kb
Host smart-632822f5-ec1f-4056-9276-c6f2be4e3440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798975937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1798975937
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.383885875
Short name T123
Test name
Test status
Simulation time 66239139016 ps
CPU time 28.72 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 01:35:37 PM PST 24
Peak memory 199612 kb
Host smart-06e0eff3-6a96-4fe7-a76c-d0d59b7193b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383885875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.383885875
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2836389326
Short name T807
Test name
Test status
Simulation time 43960653263 ps
CPU time 36.5 seconds
Started Feb 25 01:35:03 PM PST 24
Finished Feb 25 01:35:42 PM PST 24
Peak memory 199640 kb
Host smart-807f14ee-ace6-445c-9707-66f246c5e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836389326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2836389326
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3533675693
Short name T816
Test name
Test status
Simulation time 16743281455 ps
CPU time 23.07 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:30 PM PST 24
Peak memory 199108 kb
Host smart-bba9eee7-f524-430f-a2e1-36e3bca098d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533675693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3533675693
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2370801871
Short name T531
Test name
Test status
Simulation time 138647578190 ps
CPU time 776.58 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:48:04 PM PST 24
Peak memory 199616 kb
Host smart-117af89f-fb6b-4e6e-bb9e-be5a9b64f1ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370801871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2370801871
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2601630473
Short name T514
Test name
Test status
Simulation time 7675797126 ps
CPU time 17.24 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:25 PM PST 24
Peak memory 199224 kb
Host smart-d305538c-ae4f-4972-b5b2-72fd6e9e4296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601630473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2601630473
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1553950001
Short name T902
Test name
Test status
Simulation time 130649275030 ps
CPU time 48.03 seconds
Started Feb 25 01:35:01 PM PST 24
Finished Feb 25 01:35:50 PM PST 24
Peak memory 199792 kb
Host smart-5ecef3f8-9892-46e3-aa24-7876f213fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553950001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1553950001
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1874353459
Short name T534
Test name
Test status
Simulation time 1985828969 ps
CPU time 1.15 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 01:35:09 PM PST 24
Peak memory 197684 kb
Host smart-e421a7dd-8f4e-4681-a885-96ffcbf9e7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874353459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1874353459
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4104195049
Short name T256
Test name
Test status
Simulation time 34379980230 ps
CPU time 26.99 seconds
Started Feb 25 01:35:02 PM PST 24
Finished Feb 25 01:35:29 PM PST 24
Peak memory 199588 kb
Host smart-1a0de053-7c1f-4ac7-a807-25572814ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104195049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4104195049
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1730748962
Short name T1029
Test name
Test status
Simulation time 3328962922 ps
CPU time 5.91 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:35:12 PM PST 24
Peak memory 195096 kb
Host smart-d2df787c-c128-4958-b4ce-ce324dea210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730748962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1730748962
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1523480078
Short name T9
Test name
Test status
Simulation time 84416713 ps
CPU time 0.9 seconds
Started Feb 25 01:35:02 PM PST 24
Finished Feb 25 01:35:03 PM PST 24
Peak memory 196224 kb
Host smart-940cbae3-8513-422a-8465-c7d20481c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523480078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1523480078
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2913142228
Short name T472
Test name
Test status
Simulation time 102609279032 ps
CPU time 253.19 seconds
Started Feb 25 01:35:10 PM PST 24
Finished Feb 25 01:39:23 PM PST 24
Peak memory 215284 kb
Host smart-20169dd1-99fe-4dc7-8c28-f86b5be5155f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913142228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2913142228
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.602427399
Short name T1014
Test name
Test status
Simulation time 6896361266 ps
CPU time 13.41 seconds
Started Feb 25 01:35:02 PM PST 24
Finished Feb 25 01:35:16 PM PST 24
Peak memory 198948 kb
Host smart-eced2768-5db6-4650-9813-480e833ae70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602427399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.602427399
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2813119762
Short name T412
Test name
Test status
Simulation time 258846683699 ps
CPU time 118.3 seconds
Started Feb 25 01:34:53 PM PST 24
Finished Feb 25 01:36:53 PM PST 24
Peak memory 199600 kb
Host smart-3d0aec10-d178-4d75-9edd-62674395acbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813119762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2813119762
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.832443544
Short name T64
Test name
Test status
Simulation time 22976242864 ps
CPU time 17.23 seconds
Started Feb 25 01:40:18 PM PST 24
Finished Feb 25 01:40:35 PM PST 24
Peak memory 198340 kb
Host smart-e037762e-15e7-4e57-9c1f-cdb0d19135ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832443544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.832443544
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1842298875
Short name T45
Test name
Test status
Simulation time 182269005079 ps
CPU time 25.25 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 199568 kb
Host smart-086c5d18-d272-4407-ab73-d0aaa102b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842298875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1842298875
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1225390485
Short name T1043
Test name
Test status
Simulation time 100308230649 ps
CPU time 45.17 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:41:05 PM PST 24
Peak memory 199128 kb
Host smart-c0ebaf34-56a3-478c-b5f2-50694e594010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225390485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1225390485
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1859241374
Short name T954
Test name
Test status
Simulation time 126191733053 ps
CPU time 61.48 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 199556 kb
Host smart-2600eaba-0088-4b25-9987-17076b0f64e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859241374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1859241374
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1263169288
Short name T144
Test name
Test status
Simulation time 108381131479 ps
CPU time 23.93 seconds
Started Feb 25 01:40:16 PM PST 24
Finished Feb 25 01:40:41 PM PST 24
Peak memory 199396 kb
Host smart-7f3acdd8-e423-4890-b8d8-f84e73e0130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263169288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1263169288
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1580419971
Short name T673
Test name
Test status
Simulation time 28271142685 ps
CPU time 24.74 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 199552 kb
Host smart-0ae4ef07-b944-4339-a3e4-acc122ff233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580419971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1580419971
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3555263885
Short name T794
Test name
Test status
Simulation time 34201606873 ps
CPU time 51.95 seconds
Started Feb 25 01:40:19 PM PST 24
Finished Feb 25 01:41:12 PM PST 24
Peak memory 199352 kb
Host smart-9a0467ce-6608-41c1-abfb-d082a8339a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555263885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3555263885
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1597940850
Short name T1053
Test name
Test status
Simulation time 109477620535 ps
CPU time 207.81 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 199628 kb
Host smart-98444fd8-9a60-4102-b392-ada5ab164402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597940850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1597940850
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1470299734
Short name T1019
Test name
Test status
Simulation time 11278043 ps
CPU time 0.54 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:35:08 PM PST 24
Peak memory 194020 kb
Host smart-c4b30215-4634-4bd7-8154-f944ddf6bbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470299734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1470299734
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.422238193
Short name T977
Test name
Test status
Simulation time 42803026817 ps
CPU time 31.4 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:35:38 PM PST 24
Peak memory 199644 kb
Host smart-d402364e-bfe9-47f3-9aae-cef4cfe32ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422238193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.422238193
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2024471459
Short name T1079
Test name
Test status
Simulation time 87466717959 ps
CPU time 72.61 seconds
Started Feb 25 01:35:03 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 199700 kb
Host smart-07944bfe-5e86-4a34-a229-5443d97d885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024471459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2024471459
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2826363234
Short name T334
Test name
Test status
Simulation time 12971079365 ps
CPU time 20.9 seconds
Started Feb 25 01:34:59 PM PST 24
Finished Feb 25 01:35:20 PM PST 24
Peak memory 199524 kb
Host smart-ca5f336e-80a6-46de-b231-0b5f5f8ff60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826363234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2826363234
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2456985548
Short name T890
Test name
Test status
Simulation time 995789752442 ps
CPU time 1569.83 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 02:01:19 PM PST 24
Peak memory 199528 kb
Host smart-620605f5-af3b-494b-9c96-778e139166db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456985548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2456985548
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2516319249
Short name T895
Test name
Test status
Simulation time 89219562673 ps
CPU time 564.66 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:44:25 PM PST 24
Peak memory 199716 kb
Host smart-9e31768d-07c6-4be3-adaa-a1dec4545cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516319249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2516319249
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.966772640
Short name T662
Test name
Test status
Simulation time 10797022952 ps
CPU time 22.74 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:35:22 PM PST 24
Peak memory 199584 kb
Host smart-2f238de1-7eb2-437e-87d5-f36a4a134b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966772640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.966772640
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2606605035
Short name T1077
Test name
Test status
Simulation time 48065844645 ps
CPU time 52.83 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:36:00 PM PST 24
Peak memory 198648 kb
Host smart-ce89da93-8a80-4f44-8264-ca97106c6345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606605035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2606605035
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2165620689
Short name T797
Test name
Test status
Simulation time 10608842749 ps
CPU time 652.49 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 199620 kb
Host smart-362dd13e-859e-4c72-9c38-4adde58c028d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165620689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2165620689
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.781903883
Short name T551
Test name
Test status
Simulation time 1894234812 ps
CPU time 10.88 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:35:11 PM PST 24
Peak memory 197712 kb
Host smart-56506587-8ee9-471b-9637-84106b2085c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781903883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.781903883
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.669995211
Short name T301
Test name
Test status
Simulation time 232776642669 ps
CPU time 92.63 seconds
Started Feb 25 01:35:00 PM PST 24
Finished Feb 25 01:36:32 PM PST 24
Peak memory 199688 kb
Host smart-ff538125-d0a9-4d36-9a0d-e0741e0d96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669995211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.669995211
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2975072091
Short name T555
Test name
Test status
Simulation time 5552736899 ps
CPU time 9.81 seconds
Started Feb 25 01:35:05 PM PST 24
Finished Feb 25 01:35:16 PM PST 24
Peak memory 195480 kb
Host smart-8854ba6c-3312-4412-bf64-6cb8f7e4b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975072091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2975072091
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2909230637
Short name T739
Test name
Test status
Simulation time 1018402675 ps
CPU time 1.9 seconds
Started Feb 25 01:35:10 PM PST 24
Finished Feb 25 01:35:12 PM PST 24
Peak memory 197888 kb
Host smart-29e9a023-6578-42e8-adfa-150bb082f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909230637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2909230637
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.4012616470
Short name T704
Test name
Test status
Simulation time 655570228810 ps
CPU time 324.73 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:40:31 PM PST 24
Peak memory 199584 kb
Host smart-80082aff-8be4-4ba8-9d8b-ec9d5464a976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012616470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4012616470
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1607069912
Short name T814
Test name
Test status
Simulation time 1251260551 ps
CPU time 3.11 seconds
Started Feb 25 01:35:06 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 197600 kb
Host smart-e9104432-8393-4f39-ad59-c7454296fb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607069912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1607069912
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2898362024
Short name T975
Test name
Test status
Simulation time 245134162722 ps
CPU time 28.76 seconds
Started Feb 25 01:35:11 PM PST 24
Finished Feb 25 01:35:40 PM PST 24
Peak memory 199488 kb
Host smart-d82bb0b2-df3a-4b18-990d-01fa6ab975bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898362024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2898362024
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.349929629
Short name T320
Test name
Test status
Simulation time 131697879550 ps
CPU time 123.46 seconds
Started Feb 25 01:40:20 PM PST 24
Finished Feb 25 01:42:24 PM PST 24
Peak memory 199360 kb
Host smart-65d5b5d1-3a89-4f2e-8b27-532e12506d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349929629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.349929629
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1005935816
Short name T995
Test name
Test status
Simulation time 163472401612 ps
CPU time 275.77 seconds
Started Feb 25 01:40:17 PM PST 24
Finished Feb 25 01:44:54 PM PST 24
Peak memory 199540 kb
Host smart-2d1f3bb7-a925-4a3e-b89b-aa3dcd301d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005935816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1005935816
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2090053257
Short name T421
Test name
Test status
Simulation time 23940590524 ps
CPU time 49.09 seconds
Started Feb 25 01:40:16 PM PST 24
Finished Feb 25 01:41:05 PM PST 24
Peak memory 199496 kb
Host smart-1b73c0d2-1557-48ef-8d87-ee99f8345e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090053257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2090053257
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.889840935
Short name T790
Test name
Test status
Simulation time 86488930084 ps
CPU time 129.11 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:42:39 PM PST 24
Peak memory 199604 kb
Host smart-06bd459a-2240-4b2e-9c4f-b9c0c43d2abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889840935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.889840935
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1248848312
Short name T818
Test name
Test status
Simulation time 43641974993 ps
CPU time 71.88 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:41:43 PM PST 24
Peak memory 199624 kb
Host smart-6f4d0834-1364-47f3-a72d-c9e0811e66f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248848312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1248848312
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2528733423
Short name T776
Test name
Test status
Simulation time 11754143 ps
CPU time 0.54 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 01:35:08 PM PST 24
Peak memory 195100 kb
Host smart-b9dc9399-4380-4020-8325-4071587df6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528733423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2528733423
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2717038557
Short name T649
Test name
Test status
Simulation time 32866054748 ps
CPU time 81.21 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:36:28 PM PST 24
Peak memory 199648 kb
Host smart-b85b913f-018e-480a-b42a-2320c4b3d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717038557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2717038557
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_intr.4021460328
Short name T672
Test name
Test status
Simulation time 1736267754232 ps
CPU time 3293.18 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 02:30:00 PM PST 24
Peak memory 199560 kb
Host smart-376205b5-87a3-4a39-b4fd-54475b119996
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021460328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4021460328
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.403374517
Short name T915
Test name
Test status
Simulation time 140283248641 ps
CPU time 346.38 seconds
Started Feb 25 01:35:16 PM PST 24
Finished Feb 25 01:41:02 PM PST 24
Peak memory 199596 kb
Host smart-4aeb18b5-ae9b-4eda-a84f-439c1fbb5146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403374517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.403374517
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3417714875
Short name T919
Test name
Test status
Simulation time 1924559793 ps
CPU time 3.53 seconds
Started Feb 25 01:35:15 PM PST 24
Finished Feb 25 01:35:19 PM PST 24
Peak memory 197768 kb
Host smart-b63b98e8-ca62-4582-9045-6c3798aee96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417714875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3417714875
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2611055771
Short name T1080
Test name
Test status
Simulation time 180045715676 ps
CPU time 118.75 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:37:05 PM PST 24
Peak memory 199244 kb
Host smart-f9093a6a-2c9b-4d6b-ba6d-b53075707cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611055771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2611055771
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2669288808
Short name T983
Test name
Test status
Simulation time 7360929929 ps
CPU time 440.68 seconds
Started Feb 25 01:35:18 PM PST 24
Finished Feb 25 01:42:42 PM PST 24
Peak memory 199516 kb
Host smart-762f99f0-8c5a-40b8-97a3-262c6dcb1574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669288808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2669288808
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1991659787
Short name T641
Test name
Test status
Simulation time 6183824642 ps
CPU time 54.21 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:36:01 PM PST 24
Peak memory 198504 kb
Host smart-59a4015c-d271-48a0-a817-9887cc02ec3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991659787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1991659787
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4048152862
Short name T616
Test name
Test status
Simulation time 22165736838 ps
CPU time 35.79 seconds
Started Feb 25 01:35:12 PM PST 24
Finished Feb 25 01:35:48 PM PST 24
Peak memory 199424 kb
Host smart-e51f710f-240a-4a45-acf4-97bae290d27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048152862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4048152862
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1668011655
Short name T802
Test name
Test status
Simulation time 3703015504 ps
CPU time 5.69 seconds
Started Feb 25 01:35:08 PM PST 24
Finished Feb 25 01:35:14 PM PST 24
Peak memory 195368 kb
Host smart-80487181-0e32-4e59-bc2b-9fe2715a13e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668011655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1668011655
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3277943470
Short name T970
Test name
Test status
Simulation time 6448887487 ps
CPU time 5.67 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:35:12 PM PST 24
Peak memory 199508 kb
Host smart-8f8a8631-17ff-4c44-98a2-17e0000c692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277943470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3277943470
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3792906764
Short name T130
Test name
Test status
Simulation time 314557370206 ps
CPU time 1330.41 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 01:57:23 PM PST 24
Peak memory 199732 kb
Host smart-1b94cce4-737d-406b-93aa-034dddcfd467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792906764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3792906764
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1418909121
Short name T741
Test name
Test status
Simulation time 13650713282 ps
CPU time 165.04 seconds
Started Feb 25 01:35:07 PM PST 24
Finished Feb 25 01:37:53 PM PST 24
Peak memory 209184 kb
Host smart-4dceef14-478a-475d-882a-f2c9d71790da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418909121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1418909121
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3671848907
Short name T1081
Test name
Test status
Simulation time 1431597633 ps
CPU time 2.21 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 01:35:15 PM PST 24
Peak memory 198960 kb
Host smart-e922399c-13ca-4db3-8115-1f47ac29ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671848907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3671848907
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.783185163
Short name T208
Test name
Test status
Simulation time 52015219182 ps
CPU time 22.87 seconds
Started Feb 25 01:35:04 PM PST 24
Finished Feb 25 01:35:29 PM PST 24
Peak memory 199636 kb
Host smart-c394daff-5a17-42f8-9e0e-92408b61b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783185163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.783185163
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2762858679
Short name T603
Test name
Test status
Simulation time 44768027442 ps
CPU time 37.86 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:41:07 PM PST 24
Peak memory 199444 kb
Host smart-e0f92406-b3c3-4ab1-ad97-df52b312dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762858679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2762858679
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2138570739
Short name T202
Test name
Test status
Simulation time 26957616714 ps
CPU time 38.33 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:41:08 PM PST 24
Peak memory 199568 kb
Host smart-f7e0646f-6264-420b-8edc-80aaf9d99f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138570739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2138570739
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.4257675981
Short name T798
Test name
Test status
Simulation time 108184374205 ps
CPU time 276.53 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:45:06 PM PST 24
Peak memory 199660 kb
Host smart-6dbf3b3c-6c1b-4dd2-a328-261289b9ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257675981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4257675981
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2433677120
Short name T772
Test name
Test status
Simulation time 20046605977 ps
CPU time 17.57 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:40:46 PM PST 24
Peak memory 199700 kb
Host smart-6de234ca-c604-46c6-94b8-9c5967f0bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433677120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2433677120
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3585813501
Short name T137
Test name
Test status
Simulation time 85455904371 ps
CPU time 41.47 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:41:11 PM PST 24
Peak memory 199620 kb
Host smart-05d43885-e9d3-4743-9947-f4f37ae31ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585813501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3585813501
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2194792187
Short name T686
Test name
Test status
Simulation time 71234107542 ps
CPU time 24.42 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:40:53 PM PST 24
Peak memory 198852 kb
Host smart-c77b09cf-16de-43b8-94b4-da41f7f0376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194792187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2194792187
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3037438012
Short name T727
Test name
Test status
Simulation time 108524870 ps
CPU time 0.55 seconds
Started Feb 25 01:35:17 PM PST 24
Finished Feb 25 01:35:20 PM PST 24
Peak memory 194172 kb
Host smart-6a892930-b253-4e0f-ba08-ab8da52da6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037438012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3037438012
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1450222463
Short name T358
Test name
Test status
Simulation time 103920623195 ps
CPU time 36.99 seconds
Started Feb 25 01:35:19 PM PST 24
Finished Feb 25 01:35:59 PM PST 24
Peak memory 199368 kb
Host smart-eac7f3aa-4beb-468a-8d9a-d7c7047ef9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450222463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1450222463
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.603874704
Short name T370
Test name
Test status
Simulation time 30398016066 ps
CPU time 14.51 seconds
Started Feb 25 01:35:13 PM PST 24
Finished Feb 25 01:35:28 PM PST 24
Peak memory 199640 kb
Host smart-346f7113-e0ed-462a-8d2e-e36e053c51f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603874704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.603874704
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3531194671
Short name T577
Test name
Test status
Simulation time 133211765249 ps
CPU time 71.88 seconds
Started Feb 25 01:35:11 PM PST 24
Finished Feb 25 01:36:23 PM PST 24
Peak memory 199548 kb
Host smart-55b5af33-472f-43c9-afa4-02d2036c2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531194671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3531194671
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.431198928
Short name T687
Test name
Test status
Simulation time 558717137676 ps
CPU time 174.63 seconds
Started Feb 25 01:35:23 PM PST 24
Finished Feb 25 01:38:18 PM PST 24
Peak memory 199636 kb
Host smart-9efdaa2e-5483-4b7e-8135-88c7810f4c12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431198928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.431198928
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1990486052
Short name T943
Test name
Test status
Simulation time 123030395715 ps
CPU time 821.53 seconds
Started Feb 25 01:35:19 PM PST 24
Finished Feb 25 01:49:03 PM PST 24
Peak memory 199628 kb
Host smart-b789a6a1-02ba-4f95-af29-0cb1972129c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990486052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1990486052
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1045880732
Short name T708
Test name
Test status
Simulation time 2649707228 ps
CPU time 1.05 seconds
Started Feb 25 01:35:20 PM PST 24
Finished Feb 25 01:35:23 PM PST 24
Peak memory 196604 kb
Host smart-f01dc7ed-732d-4ce3-a68c-744186a282a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045880732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1045880732
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1878285588
Short name T128
Test name
Test status
Simulation time 42293926535 ps
CPU time 81.65 seconds
Started Feb 25 01:35:18 PM PST 24
Finished Feb 25 01:36:43 PM PST 24
Peak memory 199812 kb
Host smart-d0a6d4b5-193e-4cc7-b3b6-348e1e541d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878285588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1878285588
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3388299026
Short name T860
Test name
Test status
Simulation time 26062849438 ps
CPU time 329.14 seconds
Started Feb 25 01:35:20 PM PST 24
Finished Feb 25 01:40:51 PM PST 24
Peak memory 199584 kb
Host smart-1fef36e7-85b3-456a-9c6c-36ccc7facc35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388299026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3388299026
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.544732512
Short name T877
Test name
Test status
Simulation time 3320189127 ps
CPU time 2.93 seconds
Started Feb 25 01:35:20 PM PST 24
Finished Feb 25 01:35:25 PM PST 24
Peak memory 198040 kb
Host smart-211417fc-15f4-4e75-b71c-626f9006b8fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544732512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.544732512
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1819986884
Short name T595
Test name
Test status
Simulation time 118018088446 ps
CPU time 46.53 seconds
Started Feb 25 01:35:17 PM PST 24
Finished Feb 25 01:36:07 PM PST 24
Peak memory 199620 kb
Host smart-96fb158a-0ba5-4ab4-8454-c0825d7697c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819986884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1819986884
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3651070710
Short name T632
Test name
Test status
Simulation time 1825675529 ps
CPU time 2.01 seconds
Started Feb 25 01:35:18 PM PST 24
Finished Feb 25 01:35:22 PM PST 24
Peak memory 194908 kb
Host smart-4a2a1b71-e9b2-4089-ab0e-f2bdbfd8c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651070710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3651070710
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1001108280
Short name T512
Test name
Test status
Simulation time 633907804 ps
CPU time 1.92 seconds
Started Feb 25 01:35:19 PM PST 24
Finished Feb 25 01:35:24 PM PST 24
Peak memory 197972 kb
Host smart-7447b9ff-d596-49a7-847d-7546b6f67b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001108280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1001108280
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2490047052
Short name T1089
Test name
Test status
Simulation time 57633530228 ps
CPU time 1337.62 seconds
Started Feb 25 01:35:18 PM PST 24
Finished Feb 25 01:57:39 PM PST 24
Peak memory 199700 kb
Host smart-8f8b8e71-b107-43c7-ac1d-5568bbcdc6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490047052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2490047052
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1754976820
Short name T37
Test name
Test status
Simulation time 81655841692 ps
CPU time 226.28 seconds
Started Feb 25 01:35:17 PM PST 24
Finished Feb 25 01:39:06 PM PST 24
Peak memory 212496 kb
Host smart-65c8b583-a912-41a4-b522-0d34f27a62a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754976820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1754976820
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2738566011
Short name T521
Test name
Test status
Simulation time 7958162655 ps
CPU time 8.58 seconds
Started Feb 25 01:35:17 PM PST 24
Finished Feb 25 01:35:29 PM PST 24
Peak memory 199112 kb
Host smart-21a74c1e-d0c4-4d1a-aea4-fe4606ad4180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738566011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2738566011
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.736048261
Short name T1018
Test name
Test status
Simulation time 35245704222 ps
CPU time 48.33 seconds
Started Feb 25 01:35:18 PM PST 24
Finished Feb 25 01:36:10 PM PST 24
Peak memory 199592 kb
Host smart-583b00e6-e4ae-49bf-9cff-f7ca01105dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736048261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.736048261
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3102037111
Short name T594
Test name
Test status
Simulation time 11370027643 ps
CPU time 10.31 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:40:41 PM PST 24
Peak memory 199620 kb
Host smart-36b28f11-6e5a-48c5-8a34-263a9bd5e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102037111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3102037111
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2271927401
Short name T276
Test name
Test status
Simulation time 148202527522 ps
CPU time 49.29 seconds
Started Feb 25 01:40:29 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 199592 kb
Host smart-bfdf6684-4cf0-4038-8b19-a4de732653de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271927401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2271927401
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.97906912
Short name T633
Test name
Test status
Simulation time 111997626659 ps
CPU time 30.62 seconds
Started Feb 25 01:40:26 PM PST 24
Finished Feb 25 01:40:57 PM PST 24
Peak memory 199612 kb
Host smart-1a58e6b2-7c3f-4242-a00d-c2e1dbf20385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97906912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.97906912
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.893541789
Short name T228
Test name
Test status
Simulation time 78298600631 ps
CPU time 63.16 seconds
Started Feb 25 01:40:26 PM PST 24
Finished Feb 25 01:41:29 PM PST 24
Peak memory 199568 kb
Host smart-9415bd28-b2a8-4ac9-b224-3cf2a759ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893541789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.893541789
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3826802056
Short name T893
Test name
Test status
Simulation time 27425719372 ps
CPU time 16.64 seconds
Started Feb 25 01:40:34 PM PST 24
Finished Feb 25 01:40:51 PM PST 24
Peak memory 199704 kb
Host smart-8badcce2-f445-4e9f-8f94-7d65f8ee310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826802056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3826802056
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3066351864
Short name T955
Test name
Test status
Simulation time 60213129108 ps
CPU time 157.51 seconds
Started Feb 25 01:40:39 PM PST 24
Finished Feb 25 01:43:17 PM PST 24
Peak memory 199608 kb
Host smart-e80d3e85-406c-45f0-9339-0251c0f32152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066351864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3066351864
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1890826585
Short name T333
Test name
Test status
Simulation time 18878884313 ps
CPU time 27.24 seconds
Started Feb 25 01:40:32 PM PST 24
Finished Feb 25 01:40:59 PM PST 24
Peak memory 198480 kb
Host smart-edd2bbee-c6da-47fe-ab06-cc4314cb66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890826585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1890826585
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2741680502
Short name T204
Test name
Test status
Simulation time 20363957817 ps
CPU time 26.46 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:40:58 PM PST 24
Peak memory 199692 kb
Host smart-732ce157-b008-437a-af02-a1e7598fc31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741680502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2741680502
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4160686806
Short name T110
Test name
Test status
Simulation time 94312084947 ps
CPU time 76.7 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:41:48 PM PST 24
Peak memory 199188 kb
Host smart-2c33f370-879f-4f23-afd5-939ec82c553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160686806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4160686806
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.151863098
Short name T949
Test name
Test status
Simulation time 38676636 ps
CPU time 0.55 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:35:37 PM PST 24
Peak memory 194980 kb
Host smart-8c91db5e-1694-4cbd-8d45-714744542f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151863098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.151863098
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.235493420
Short name T960
Test name
Test status
Simulation time 67321652283 ps
CPU time 42.73 seconds
Started Feb 25 01:35:19 PM PST 24
Finished Feb 25 01:36:04 PM PST 24
Peak memory 199624 kb
Host smart-c1a8ba6f-e891-4274-91a7-a1993cb0a52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235493420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.235493420
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3534893403
Short name T981
Test name
Test status
Simulation time 36514137800 ps
CPU time 56.36 seconds
Started Feb 25 01:35:30 PM PST 24
Finished Feb 25 01:36:27 PM PST 24
Peak memory 199708 kb
Host smart-5160d0d8-3669-4049-9c01-fb9abfeb77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534893403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3534893403
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2714148283
Short name T839
Test name
Test status
Simulation time 77404219831 ps
CPU time 28.15 seconds
Started Feb 25 01:35:27 PM PST 24
Finished Feb 25 01:35:56 PM PST 24
Peak memory 199660 kb
Host smart-c6de4c60-b06d-4800-9567-65ac855a3e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714148283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2714148283
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.956198833
Short name T832
Test name
Test status
Simulation time 98958789601 ps
CPU time 181.59 seconds
Started Feb 25 01:35:29 PM PST 24
Finished Feb 25 01:38:31 PM PST 24
Peak memory 198748 kb
Host smart-e2330d98-c282-47aa-8d91-9d0d0ce323e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956198833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.956198833
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2591675097
Short name T1102
Test name
Test status
Simulation time 95688607324 ps
CPU time 364.76 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:41:41 PM PST 24
Peak memory 199632 kb
Host smart-bf0e6435-ff57-4c56-bead-6887513758aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591675097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2591675097
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2608239050
Short name T526
Test name
Test status
Simulation time 3120573907 ps
CPU time 6.22 seconds
Started Feb 25 01:35:30 PM PST 24
Finished Feb 25 01:35:36 PM PST 24
Peak memory 197372 kb
Host smart-ec64e2db-f784-427a-b36c-1cc68b0473bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608239050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2608239050
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2969879065
Short name T1030
Test name
Test status
Simulation time 168180831519 ps
CPU time 74.78 seconds
Started Feb 25 01:35:34 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 198848 kb
Host smart-cb05f9ef-04be-47cc-98a4-7908795e4ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969879065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2969879065
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4129325997
Short name T1022
Test name
Test status
Simulation time 36143876436 ps
CPU time 249.47 seconds
Started Feb 25 01:35:37 PM PST 24
Finished Feb 25 01:39:47 PM PST 24
Peak memory 199700 kb
Host smart-aef19215-4a89-4e32-9ae0-2dd07a2e43a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129325997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4129325997
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3210997237
Short name T1082
Test name
Test status
Simulation time 2150078518 ps
CPU time 21.32 seconds
Started Feb 25 01:35:32 PM PST 24
Finished Feb 25 01:35:54 PM PST 24
Peak memory 197800 kb
Host smart-68fd17bc-6f05-4fb1-88e6-5654c6e19ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210997237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3210997237
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2920979556
Short name T262
Test name
Test status
Simulation time 171268030842 ps
CPU time 170.43 seconds
Started Feb 25 01:35:28 PM PST 24
Finished Feb 25 01:38:18 PM PST 24
Peak memory 198336 kb
Host smart-3c1d00d1-8b79-42ef-ae8c-8adfe2d5f717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920979556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2920979556
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1914723000
Short name T31
Test name
Test status
Simulation time 2864073661 ps
CPU time 2.57 seconds
Started Feb 25 01:35:29 PM PST 24
Finished Feb 25 01:35:32 PM PST 24
Peak memory 195192 kb
Host smart-7c12cf07-f48b-479c-8c2d-d73852640d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914723000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1914723000
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3322804436
Short name T948
Test name
Test status
Simulation time 648752587 ps
CPU time 2.08 seconds
Started Feb 25 01:35:16 PM PST 24
Finished Feb 25 01:35:19 PM PST 24
Peak memory 198028 kb
Host smart-c03a4f64-7c0d-4555-8a9b-9e5dd35659d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322804436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3322804436
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.885139426
Short name T236
Test name
Test status
Simulation time 150457899577 ps
CPU time 105.4 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:37:21 PM PST 24
Peak memory 199568 kb
Host smart-26582f18-9114-4b4f-ac48-41d5d0ba67de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885139426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.885139426
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1956202415
Short name T475
Test name
Test status
Simulation time 20602034165 ps
CPU time 257.09 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:39:54 PM PST 24
Peak memory 215512 kb
Host smart-8cf3437c-90cf-4bd5-88a8-02d8e862fbf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956202415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1956202415
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1402028743
Short name T850
Test name
Test status
Simulation time 9073685671 ps
CPU time 10.6 seconds
Started Feb 25 01:35:29 PM PST 24
Finished Feb 25 01:35:39 PM PST 24
Peak memory 199552 kb
Host smart-fc4ea182-5c54-413f-b36b-340d1cd0ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402028743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1402028743
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2918608140
Short name T488
Test name
Test status
Simulation time 19248649257 ps
CPU time 15.97 seconds
Started Feb 25 01:35:17 PM PST 24
Finished Feb 25 01:35:35 PM PST 24
Peak memory 197348 kb
Host smart-0d8ff65a-3f7d-49ae-8b7d-3cac5c6399c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918608140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2918608140
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.892490842
Short name T353
Test name
Test status
Simulation time 8936948620 ps
CPU time 14.13 seconds
Started Feb 25 01:40:41 PM PST 24
Finished Feb 25 01:40:55 PM PST 24
Peak memory 199624 kb
Host smart-ce0ab71f-53d1-4f8c-9c94-bb92938ba4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892490842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.892490842
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3417053410
Short name T826
Test name
Test status
Simulation time 179483258864 ps
CPU time 51.9 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:41:25 PM PST 24
Peak memory 199536 kb
Host smart-471111fb-609d-4776-abf5-2204e5576c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417053410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3417053410
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2731740734
Short name T777
Test name
Test status
Simulation time 93614520341 ps
CPU time 152.22 seconds
Started Feb 25 01:40:32 PM PST 24
Finished Feb 25 01:43:05 PM PST 24
Peak memory 199572 kb
Host smart-8c5eb84b-bc4e-4c2b-8e0b-f982828fe7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731740734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2731740734
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1166935754
Short name T184
Test name
Test status
Simulation time 53722230088 ps
CPU time 76.74 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:41:48 PM PST 24
Peak memory 198880 kb
Host smart-2b64bb4b-e89a-492b-8a7c-5edd5a0dc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166935754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1166935754
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.727649558
Short name T923
Test name
Test status
Simulation time 38615337172 ps
CPU time 60.74 seconds
Started Feb 25 01:40:30 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 198716 kb
Host smart-9560672e-18ab-457b-b3b8-1dc89b721533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727649558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.727649558
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3606073126
Short name T175
Test name
Test status
Simulation time 165138482815 ps
CPU time 270.86 seconds
Started Feb 25 01:40:34 PM PST 24
Finished Feb 25 01:45:05 PM PST 24
Peak memory 199664 kb
Host smart-36b090b0-450f-4373-be98-a67545b6c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606073126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3606073126
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.707677606
Short name T613
Test name
Test status
Simulation time 87870263985 ps
CPU time 17.03 seconds
Started Feb 25 01:40:39 PM PST 24
Finished Feb 25 01:40:56 PM PST 24
Peak memory 199564 kb
Host smart-41a2114f-99a4-4515-82b6-12d420c10948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707677606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.707677606
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.690288598
Short name T296
Test name
Test status
Simulation time 105558102157 ps
CPU time 67.55 seconds
Started Feb 25 01:40:32 PM PST 24
Finished Feb 25 01:41:40 PM PST 24
Peak memory 199484 kb
Host smart-638fdd05-7904-4d30-b4c0-ebfda3c87f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690288598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.690288598
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.574354665
Short name T182
Test name
Test status
Simulation time 122483037129 ps
CPU time 34.32 seconds
Started Feb 25 01:40:40 PM PST 24
Finished Feb 25 01:41:14 PM PST 24
Peak memory 199648 kb
Host smart-32403ce8-ab7c-4b7b-ad6c-50d1c6eb2753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574354665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.574354665
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2900337510
Short name T305
Test name
Test status
Simulation time 17611034526 ps
CPU time 26.61 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:40:58 PM PST 24
Peak memory 198628 kb
Host smart-0e475918-3dd2-43b4-9db7-d5870316a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900337510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2900337510
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2050846377
Short name T525
Test name
Test status
Simulation time 31654215 ps
CPU time 0.54 seconds
Started Feb 25 01:35:45 PM PST 24
Finished Feb 25 01:35:46 PM PST 24
Peak memory 195120 kb
Host smart-9d9f8dcb-659d-4cb8-9f41-dc4f6a9d0ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050846377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2050846377
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.433095767
Short name T580
Test name
Test status
Simulation time 171617196602 ps
CPU time 275.18 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:40:11 PM PST 24
Peak memory 199700 kb
Host smart-3ea5c65c-9c45-4734-977b-bc3121137d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433095767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.433095767
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.135604476
Short name T54
Test name
Test status
Simulation time 15147465369 ps
CPU time 12.5 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:35:49 PM PST 24
Peak memory 198192 kb
Host smart-261cf40e-4fd3-4b2e-a125-26b501890346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135604476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.135604476
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.379613390
Short name T392
Test name
Test status
Simulation time 26710606890 ps
CPU time 12.47 seconds
Started Feb 25 01:35:38 PM PST 24
Finished Feb 25 01:35:51 PM PST 24
Peak memory 199640 kb
Host smart-fd115917-f9f3-4b16-80c7-6b5f7dd1390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379613390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.379613390
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2417076210
Short name T249
Test name
Test status
Simulation time 82196518449 ps
CPU time 172.22 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:38:28 PM PST 24
Peak memory 199500 kb
Host smart-b3362e88-9baf-4913-a6b5-06e0b1d0dbbf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417076210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2417076210
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.538382886
Short name T873
Test name
Test status
Simulation time 187621815360 ps
CPU time 1076.31 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:53:43 PM PST 24
Peak memory 199636 kb
Host smart-05ed0a3b-ceaa-4bc8-a714-3471388bd291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538382886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.538382886
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1009799008
Short name T558
Test name
Test status
Simulation time 5392704199 ps
CPU time 13.19 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:35:59 PM PST 24
Peak memory 199208 kb
Host smart-629bc071-b10f-440f-86f0-bdb6cce23fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009799008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1009799008
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.628802132
Short name T565
Test name
Test status
Simulation time 40379295211 ps
CPU time 65.6 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:36:42 PM PST 24
Peak memory 199084 kb
Host smart-9408a07e-d22c-4920-978a-65f954228c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628802132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.628802132
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.846975040
Short name T152
Test name
Test status
Simulation time 4398245371 ps
CPU time 241.26 seconds
Started Feb 25 01:35:48 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 199616 kb
Host smart-fc7438a8-9fbb-47a4-92b2-5eb49ca1dd2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846975040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.846975040
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1463193410
Short name T108
Test name
Test status
Simulation time 71958021066 ps
CPU time 52.13 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:36:38 PM PST 24
Peak memory 198388 kb
Host smart-81a2a48e-27b3-483a-9152-849242dfe2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463193410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1463193410
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1561028809
Short name T947
Test name
Test status
Simulation time 33899932493 ps
CPU time 50.59 seconds
Started Feb 25 01:35:48 PM PST 24
Finished Feb 25 01:36:39 PM PST 24
Peak memory 195088 kb
Host smart-62d2735b-76a1-4377-b22e-3cf31c0b6ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561028809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1561028809
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.229523804
Short name T468
Test name
Test status
Simulation time 526148932 ps
CPU time 1.23 seconds
Started Feb 25 01:35:36 PM PST 24
Finished Feb 25 01:35:37 PM PST 24
Peak memory 197908 kb
Host smart-9c5376f2-cb50-40b8-955a-1f40d626de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229523804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.229523804
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.384674724
Short name T817
Test name
Test status
Simulation time 1124101475505 ps
CPU time 3126.59 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 02:27:54 PM PST 24
Peak memory 199708 kb
Host smart-cdb0ebbb-3ac2-44d1-a2e1-bd55db57bdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384674724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.384674724
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.478128748
Short name T532
Test name
Test status
Simulation time 1322580625 ps
CPU time 1.55 seconds
Started Feb 25 01:35:49 PM PST 24
Finished Feb 25 01:35:51 PM PST 24
Peak memory 197596 kb
Host smart-7e19707b-d68b-4eb6-8cf3-9cbf92e03c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478128748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.478128748
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3826542054
Short name T622
Test name
Test status
Simulation time 110087826250 ps
CPU time 221.15 seconds
Started Feb 25 01:35:41 PM PST 24
Finished Feb 25 01:39:23 PM PST 24
Peak memory 199804 kb
Host smart-8098f424-f4d6-41db-8e7b-14daa4fe0cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826542054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3826542054
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1808900056
Short name T224
Test name
Test status
Simulation time 352575269303 ps
CPU time 34.43 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:41:08 PM PST 24
Peak memory 199464 kb
Host smart-7975d710-a993-4d63-b2a8-128efcdc8f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808900056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1808900056
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2700801141
Short name T552
Test name
Test status
Simulation time 233551891437 ps
CPU time 253.64 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 199468 kb
Host smart-e668151b-8f95-46e0-be7a-d14327407064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700801141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2700801141
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1375899271
Short name T825
Test name
Test status
Simulation time 48178140460 ps
CPU time 26.65 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:40:59 PM PST 24
Peak memory 199624 kb
Host smart-e33c32ae-40cc-47d9-93c7-e507ce24de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375899271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1375899271
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1293624728
Short name T701
Test name
Test status
Simulation time 54610980480 ps
CPU time 87.56 seconds
Started Feb 25 01:40:31 PM PST 24
Finished Feb 25 01:41:59 PM PST 24
Peak memory 199656 kb
Host smart-b93a4399-501e-41ee-9dba-c966fd6d18f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293624728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1293624728
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3908816528
Short name T176
Test name
Test status
Simulation time 194320074870 ps
CPU time 22.62 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:40:56 PM PST 24
Peak memory 199584 kb
Host smart-f60271b4-2cc7-426c-bd4d-4eb74919f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908816528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3908816528
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.340813626
Short name T856
Test name
Test status
Simulation time 58213375732 ps
CPU time 85.69 seconds
Started Feb 25 01:40:33 PM PST 24
Finished Feb 25 01:41:59 PM PST 24
Peak memory 199528 kb
Host smart-b8c5add2-6f19-434b-b722-0bc091550d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340813626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.340813626
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1482436571
Short name T781
Test name
Test status
Simulation time 124299704978 ps
CPU time 92.04 seconds
Started Feb 25 01:40:36 PM PST 24
Finished Feb 25 01:42:08 PM PST 24
Peak memory 199672 kb
Host smart-be332879-1765-4adc-ac64-9727cb9ed186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482436571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1482436571
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2474560994
Short name T768
Test name
Test status
Simulation time 117738730219 ps
CPU time 98.13 seconds
Started Feb 25 01:40:34 PM PST 24
Finished Feb 25 01:42:12 PM PST 24
Peak memory 199628 kb
Host smart-e9e7b5d8-bd01-493e-a839-943fbd52c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474560994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2474560994
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2788843650
Short name T719
Test name
Test status
Simulation time 14058610 ps
CPU time 0.55 seconds
Started Feb 25 01:32:50 PM PST 24
Finished Feb 25 01:32:50 PM PST 24
Peak memory 194812 kb
Host smart-31f5d316-bf4c-47f1-aa33-0701d6c5d787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788843650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2788843650
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2340214994
Short name T682
Test name
Test status
Simulation time 24356636490 ps
CPU time 37.74 seconds
Started Feb 25 01:32:35 PM PST 24
Finished Feb 25 01:33:12 PM PST 24
Peak memory 199356 kb
Host smart-0a73ed54-cedc-42f6-b39a-8900fe6ed96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340214994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2340214994
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2453859482
Short name T700
Test name
Test status
Simulation time 161015603787 ps
CPU time 59.57 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:33:49 PM PST 24
Peak memory 199304 kb
Host smart-ddf53e36-b629-4088-8054-fc5a10477ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453859482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2453859482
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1309682197
Short name T516
Test name
Test status
Simulation time 64685395625 ps
CPU time 40.47 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 199296 kb
Host smart-fdb8391a-6812-482e-b6ad-0d60b5dde84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309682197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1309682197
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3422236393
Short name T579
Test name
Test status
Simulation time 942750560684 ps
CPU time 1442.62 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:56:39 PM PST 24
Peak memory 198744 kb
Host smart-faf80a81-afb3-40ac-8627-bed7a0382075
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422236393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3422236393
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1065035556
Short name T804
Test name
Test status
Simulation time 93120059739 ps
CPU time 852.49 seconds
Started Feb 25 01:32:41 PM PST 24
Finished Feb 25 01:46:54 PM PST 24
Peak memory 199576 kb
Host smart-c0fbd854-13e3-4608-9a42-cdf0cea86a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065035556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1065035556
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.163653256
Short name T778
Test name
Test status
Simulation time 12955433193 ps
CPU time 20.21 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:32:58 PM PST 24
Peak memory 198068 kb
Host smart-7c125a50-eb77-4d01-993a-40c202e7c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163653256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.163653256
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.843967815
Short name T1034
Test name
Test status
Simulation time 160491225416 ps
CPU time 150.01 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:35:03 PM PST 24
Peak memory 199736 kb
Host smart-0d45b114-a47e-4859-9901-8a333246bd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843967815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.843967815
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.569216191
Short name T801
Test name
Test status
Simulation time 13896370268 ps
CPU time 803.05 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:46:01 PM PST 24
Peak memory 199624 kb
Host smart-84ff7932-f02c-4108-b463-9ca12f5b81c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569216191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.569216191
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.854220002
Short name T61
Test name
Test status
Simulation time 3069372943 ps
CPU time 11.96 seconds
Started Feb 25 01:32:35 PM PST 24
Finished Feb 25 01:32:47 PM PST 24
Peak memory 198096 kb
Host smart-e4cabc8c-b7bb-43a9-aa0b-9dd973bbcfb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854220002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.854220002
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.190564274
Short name T896
Test name
Test status
Simulation time 299969776565 ps
CPU time 414.37 seconds
Started Feb 25 01:32:36 PM PST 24
Finished Feb 25 01:39:30 PM PST 24
Peak memory 199584 kb
Host smart-30b0b192-d611-4e7b-9bad-55b63ee7bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190564274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.190564274
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.67630654
Short name T477
Test name
Test status
Simulation time 43589562530 ps
CPU time 16.71 seconds
Started Feb 25 01:32:39 PM PST 24
Finished Feb 25 01:32:56 PM PST 24
Peak memory 195296 kb
Host smart-80c099db-e73b-4fe0-bf24-f44fe7900b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67630654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.67630654
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1257992458
Short name T103
Test name
Test status
Simulation time 181418848 ps
CPU time 0.77 seconds
Started Feb 25 01:32:34 PM PST 24
Finished Feb 25 01:32:35 PM PST 24
Peak memory 217144 kb
Host smart-4934de3c-0260-480e-88b4-48776ae2c89c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257992458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1257992458
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1252039966
Short name T664
Test name
Test status
Simulation time 6365715361 ps
CPU time 8.43 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:32:42 PM PST 24
Peak memory 199008 kb
Host smart-46c1fa8a-2b87-44aa-bba3-af4049cfc76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252039966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1252039966
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1696819132
Short name T459
Test name
Test status
Simulation time 7096929850 ps
CPU time 10.6 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:32:44 PM PST 24
Peak memory 199152 kb
Host smart-82ee55ba-d587-41cb-bf53-838dc62535ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696819132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1696819132
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.923236431
Short name T1109
Test name
Test status
Simulation time 42401411944 ps
CPU time 8.24 seconds
Started Feb 25 01:32:50 PM PST 24
Finished Feb 25 01:32:59 PM PST 24
Peak memory 199136 kb
Host smart-8c75bba8-9e89-4dc2-8d9f-7441d2917375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923236431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.923236431
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1856103886
Short name T32
Test name
Test status
Simulation time 14293019 ps
CPU time 0.58 seconds
Started Feb 25 01:36:03 PM PST 24
Finished Feb 25 01:36:04 PM PST 24
Peak memory 195132 kb
Host smart-4a29e73b-b5e3-492d-9950-9437a16b3738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856103886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1856103886
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2895245282
Short name T655
Test name
Test status
Simulation time 76455334615 ps
CPU time 31.26 seconds
Started Feb 25 01:35:48 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 199600 kb
Host smart-259fa621-cceb-4b9a-92ea-1ddfcabc20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895245282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2895245282
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.4048309779
Short name T290
Test name
Test status
Simulation time 55620490445 ps
CPU time 22.48 seconds
Started Feb 25 01:35:54 PM PST 24
Finished Feb 25 01:36:16 PM PST 24
Peak memory 199640 kb
Host smart-66a621fa-78f1-4763-8201-f092ee63e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048309779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4048309779
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.922160071
Short name T189
Test name
Test status
Simulation time 535532390214 ps
CPU time 772.03 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:48:38 PM PST 24
Peak memory 199648 kb
Host smart-b8698166-0867-4ab9-a5cb-2ae83a681197
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922160071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.922160071
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2489816400
Short name T785
Test name
Test status
Simulation time 109159498058 ps
CPU time 684.93 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 01:47:13 PM PST 24
Peak memory 199636 kb
Host smart-7d2aba0b-f521-47fc-8ab6-127a3f8be6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489816400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2489816400
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.754085248
Short name T484
Test name
Test status
Simulation time 5518737481 ps
CPU time 3.81 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:35:50 PM PST 24
Peak memory 198296 kb
Host smart-ad81852a-f9b6-45c8-bf6e-01df6f54c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754085248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.754085248
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2451221394
Short name T736
Test name
Test status
Simulation time 133567239468 ps
CPU time 76.55 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:37:03 PM PST 24
Peak memory 199876 kb
Host smart-a81f9713-d9c1-432e-bcec-756a74476901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451221394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2451221394
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.84590373
Short name T53
Test name
Test status
Simulation time 13984750325 ps
CPU time 162.88 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 01:38:30 PM PST 24
Peak memory 199432 kb
Host smart-cd25686e-08e4-45ff-8025-04ffc819fe06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84590373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.84590373
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2478719166
Short name T286
Test name
Test status
Simulation time 15531490593 ps
CPU time 20.3 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 01:36:08 PM PST 24
Peak memory 198592 kb
Host smart-aa9f18a8-a328-4d5f-aedc-50f2492f4148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478719166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2478719166
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1330218157
Short name T862
Test name
Test status
Simulation time 4634650902 ps
CPU time 2.69 seconds
Started Feb 25 01:35:48 PM PST 24
Finished Feb 25 01:35:51 PM PST 24
Peak memory 195460 kb
Host smart-194fd531-4b10-4408-85b0-6fb7f9a5b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330218157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1330218157
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.460638440
Short name T434
Test name
Test status
Simulation time 307037374 ps
CPU time 1.7 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 01:35:49 PM PST 24
Peak memory 197332 kb
Host smart-549bf72c-02a0-43e2-adec-be31f0a55622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460638440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.460638440
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1845649171
Short name T578
Test name
Test status
Simulation time 957061383971 ps
CPU time 1165.27 seconds
Started Feb 25 01:35:47 PM PST 24
Finished Feb 25 01:55:12 PM PST 24
Peak memory 199736 kb
Host smart-5472c1ca-c5f2-433c-967b-7f2e915016cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845649171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1845649171
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2589519589
Short name T463
Test name
Test status
Simulation time 12580705924 ps
CPU time 30.87 seconds
Started Feb 25 01:35:54 PM PST 24
Finished Feb 25 01:36:25 PM PST 24
Peak memory 198816 kb
Host smart-2cde9c03-a6b9-4232-b74f-09f7b721cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589519589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2589519589
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2566039962
Short name T587
Test name
Test status
Simulation time 18310185109 ps
CPU time 17.59 seconds
Started Feb 25 01:35:46 PM PST 24
Finished Feb 25 01:36:04 PM PST 24
Peak memory 199528 kb
Host smart-387e45e8-afa9-45a6-ac36-b5460329c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566039962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2566039962
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.29696766
Short name T490
Test name
Test status
Simulation time 12346382 ps
CPU time 0.54 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:36:07 PM PST 24
Peak memory 194140 kb
Host smart-d41c656e-886b-4f55-a854-99ebfa2884c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29696766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.29696766
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.297093722
Short name T574
Test name
Test status
Simulation time 80867258096 ps
CPU time 36.52 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:41 PM PST 24
Peak memory 199700 kb
Host smart-2e98d390-a027-49ac-bd77-9c89ac193f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297093722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.297093722
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.794194195
Short name T381
Test name
Test status
Simulation time 95934553040 ps
CPU time 80.4 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:37:26 PM PST 24
Peak memory 199712 kb
Host smart-cb2501f5-a5db-4715-9f21-bbd55e6a340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794194195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.794194195
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2196314503
Short name T859
Test name
Test status
Simulation time 134110513867 ps
CPU time 211.18 seconds
Started Feb 25 01:36:01 PM PST 24
Finished Feb 25 01:39:34 PM PST 24
Peak memory 199272 kb
Host smart-26ebb14e-a7d8-42b7-af3f-c43455d04cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196314503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2196314503
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2276857553
Short name T793
Test name
Test status
Simulation time 586372301632 ps
CPU time 951.99 seconds
Started Feb 25 01:36:03 PM PST 24
Finished Feb 25 01:51:55 PM PST 24
Peak memory 199552 kb
Host smart-df2d0a05-da7b-42c1-b6b6-034625d46a09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276857553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2276857553
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_loopback.1574154838
Short name T571
Test name
Test status
Simulation time 7246424204 ps
CPU time 5.13 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:10 PM PST 24
Peak memory 198092 kb
Host smart-b9ffa3ef-49fe-419f-93a2-737878437d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574154838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1574154838
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3003054511
Short name T159
Test name
Test status
Simulation time 57458449467 ps
CPU time 22.85 seconds
Started Feb 25 01:36:07 PM PST 24
Finished Feb 25 01:36:30 PM PST 24
Peak memory 197028 kb
Host smart-477a3824-d2f1-4c51-80d9-8fdc9dc5c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003054511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3003054511
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2479610615
Short name T465
Test name
Test status
Simulation time 25140749865 ps
CPU time 1312.57 seconds
Started Feb 25 01:36:03 PM PST 24
Finished Feb 25 01:57:56 PM PST 24
Peak memory 199672 kb
Host smart-1455aee8-b42e-4918-9d88-b13006d6a3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479610615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2479610615
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3587887630
Short name T1042
Test name
Test status
Simulation time 1474332334 ps
CPU time 15.59 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 197788 kb
Host smart-fba880d4-8b12-4562-973c-e02ad0713bda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587887630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3587887630
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3346938353
Short name T427
Test name
Test status
Simulation time 38465838235 ps
CPU time 49.83 seconds
Started Feb 25 01:36:00 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 199708 kb
Host smart-facc9f37-1754-437d-b735-d4549ce3a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346938353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3346938353
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.359547426
Short name T924
Test name
Test status
Simulation time 1816566877 ps
CPU time 1.32 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:06 PM PST 24
Peak memory 194948 kb
Host smart-356b1ebf-e206-41df-8a15-c12795f9e589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359547426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.359547426
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.565371157
Short name T446
Test name
Test status
Simulation time 5967486591 ps
CPU time 28.93 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:33 PM PST 24
Peak memory 198784 kb
Host smart-bad5669b-af12-441c-898a-235109cd3b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565371157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.565371157
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.850698095
Short name T709
Test name
Test status
Simulation time 36674437546 ps
CPU time 160.34 seconds
Started Feb 25 01:36:07 PM PST 24
Finished Feb 25 01:38:47 PM PST 24
Peak memory 199636 kb
Host smart-e4093a7e-8a3d-46e3-8596-27a6dd1f310e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850698095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.850698095
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3824825122
Short name T1009
Test name
Test status
Simulation time 1573012431 ps
CPU time 2.2 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:36:08 PM PST 24
Peak memory 197640 kb
Host smart-1ee0763f-b018-47f3-a90b-5da58a3087b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824825122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3824825122
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1021471518
Short name T953
Test name
Test status
Simulation time 42744842676 ps
CPU time 20.11 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:24 PM PST 24
Peak memory 196708 kb
Host smart-a4f1d0cf-b7bd-4f1b-b4c4-73ac1c7c2a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021471518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1021471518
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.500416818
Short name T495
Test name
Test status
Simulation time 13721853 ps
CPU time 0.54 seconds
Started Feb 25 01:36:09 PM PST 24
Finished Feb 25 01:36:10 PM PST 24
Peak memory 194004 kb
Host smart-b3f9547a-2ac8-424a-9902-95dd6e2bd22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500416818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.500416818
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2043419974
Short name T391
Test name
Test status
Simulation time 87128239877 ps
CPU time 32.44 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:36:39 PM PST 24
Peak memory 199520 kb
Host smart-d0bb7df6-5f1e-4a32-bdd5-3ee5f577d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043419974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2043419974
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2928324581
Short name T1026
Test name
Test status
Simulation time 189915858188 ps
CPU time 305.7 seconds
Started Feb 25 01:35:59 PM PST 24
Finished Feb 25 01:41:06 PM PST 24
Peak memory 199568 kb
Host smart-24658adb-24e7-4c1d-9359-bc10457f5243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928324581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2928324581
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.149802591
Short name T688
Test name
Test status
Simulation time 26161442469 ps
CPU time 19.48 seconds
Started Feb 25 01:36:00 PM PST 24
Finished Feb 25 01:36:20 PM PST 24
Peak memory 199592 kb
Host smart-abab7520-a472-4f52-b227-c307460d4166
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149802591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.149802591
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2807433882
Short name T966
Test name
Test status
Simulation time 180797138437 ps
CPU time 679.39 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:47:24 PM PST 24
Peak memory 199732 kb
Host smart-4858fc67-2a70-4a77-b0b4-5c5492def6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807433882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2807433882
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1595997161
Short name T487
Test name
Test status
Simulation time 9268737629 ps
CPU time 2.66 seconds
Started Feb 25 01:36:02 PM PST 24
Finished Feb 25 01:36:05 PM PST 24
Peak memory 197288 kb
Host smart-03e0b254-8539-499a-aac2-6c4511fca2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595997161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1595997161
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2583425052
Short name T536
Test name
Test status
Simulation time 7609462671 ps
CPU time 14.06 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 197976 kb
Host smart-0c333ecc-1d81-4a89-8103-7d5408285b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583425052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2583425052
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.4173137830
Short name T964
Test name
Test status
Simulation time 8316031403 ps
CPU time 483.02 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:44:07 PM PST 24
Peak memory 199704 kb
Host smart-bbf432f5-ec13-4d37-a65e-f1a988e12e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173137830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4173137830
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3117219834
Short name T505
Test name
Test status
Simulation time 2651248022 ps
CPU time 25.27 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:30 PM PST 24
Peak memory 197588 kb
Host smart-85ba8b7a-cd12-4275-ad2f-d6eccc7bbdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117219834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3117219834
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4289107340
Short name T916
Test name
Test status
Simulation time 93641509082 ps
CPU time 24.8 seconds
Started Feb 25 01:36:01 PM PST 24
Finished Feb 25 01:36:26 PM PST 24
Peak memory 198968 kb
Host smart-b2f36c79-ff12-4bab-a8af-dc5488e9df11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289107340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4289107340
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.333791416
Short name T775
Test name
Test status
Simulation time 40631333167 ps
CPU time 56.35 seconds
Started Feb 25 01:36:01 PM PST 24
Finished Feb 25 01:36:59 PM PST 24
Peak memory 194992 kb
Host smart-92065858-f1f6-4e42-a23f-ef89219e9135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333791416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.333791416
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.4146489534
Short name T461
Test name
Test status
Simulation time 275043952 ps
CPU time 1.19 seconds
Started Feb 25 01:36:07 PM PST 24
Finished Feb 25 01:36:08 PM PST 24
Peak memory 198004 kb
Host smart-00db92c2-906b-4e87-8b50-13245496c3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146489534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4146489534
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1480235722
Short name T30
Test name
Test status
Simulation time 33044599625 ps
CPU time 530.47 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 215244 kb
Host smart-52da8140-2703-44d9-a4a6-195ee6970aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480235722 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1480235722
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2955083470
Short name T444
Test name
Test status
Simulation time 2029321245 ps
CPU time 1.92 seconds
Started Feb 25 01:35:59 PM PST 24
Finished Feb 25 01:36:01 PM PST 24
Peak memory 197428 kb
Host smart-6c217459-b377-44c1-8d8d-c6be5ee861f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955083470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2955083470
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3950354617
Short name T844
Test name
Test status
Simulation time 83536423311 ps
CPU time 89.88 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:37:35 PM PST 24
Peak memory 199636 kb
Host smart-05e05cb8-2481-4e95-bde0-28bff279c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950354617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3950354617
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1951045306
Short name T865
Test name
Test status
Simulation time 13316817 ps
CPU time 0.55 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:36:09 PM PST 24
Peak memory 195100 kb
Host smart-1bb5c671-13f5-4d2a-ada7-fa229b4daa72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951045306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1951045306
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.191057651
Short name T934
Test name
Test status
Simulation time 38211728383 ps
CPU time 58.28 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:37:03 PM PST 24
Peak memory 199660 kb
Host smart-30555bf7-f655-4642-9f77-32a408d582f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191057651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.191057651
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2860549837
Short name T205
Test name
Test status
Simulation time 448594510612 ps
CPU time 162.31 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:38:51 PM PST 24
Peak memory 199592 kb
Host smart-75710dbb-419f-4eaa-91ec-4f76d1b3debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860549837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2860549837
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.999526349
Short name T1001
Test name
Test status
Simulation time 46428510852 ps
CPU time 20.34 seconds
Started Feb 25 01:36:04 PM PST 24
Finished Feb 25 01:36:25 PM PST 24
Peak memory 199656 kb
Host smart-39afc814-12b3-4215-9a58-3d890d1ec17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999526349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.999526349
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.397836166
Short name T965
Test name
Test status
Simulation time 13821993284 ps
CPU time 9.45 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:36:24 PM PST 24
Peak memory 197952 kb
Host smart-7f5b7f4c-b6ce-45a3-b173-6e5bdb2158ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397836166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.397836166
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.678208183
Short name T952
Test name
Test status
Simulation time 140478477364 ps
CPU time 1144.98 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:55:20 PM PST 24
Peak memory 199632 kb
Host smart-73f585d6-b522-44b6-887e-b9c7f141b45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678208183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.678208183
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4037966486
Short name T481
Test name
Test status
Simulation time 10820051077 ps
CPU time 37.51 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:43 PM PST 24
Peak memory 198316 kb
Host smart-68c7d76b-1582-46da-a782-97c6532a4cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037966486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4037966486
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.175197877
Short name T654
Test name
Test status
Simulation time 87465316337 ps
CPU time 73.46 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:37:22 PM PST 24
Peak memory 199932 kb
Host smart-64d06552-a37f-4942-b196-5958a0f4b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175197877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.175197877
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2715515996
Short name T869
Test name
Test status
Simulation time 22616280074 ps
CPU time 404.69 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 199664 kb
Host smart-7713dc08-c74e-4f6f-8d2b-144888ed92ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715515996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2715515996
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2325272194
Short name T46
Test name
Test status
Simulation time 1913583253 ps
CPU time 18.92 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:36:25 PM PST 24
Peak memory 197744 kb
Host smart-7ba916ee-24b9-4a9d-b819-3beeecf72778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325272194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2325272194
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1909293803
Short name T405
Test name
Test status
Simulation time 197913732870 ps
CPU time 18.91 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:36:27 PM PST 24
Peak memory 198900 kb
Host smart-6d1b26db-3059-4df4-90e7-00ae9570c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909293803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1909293803
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1711847032
Short name T713
Test name
Test status
Simulation time 39456720232 ps
CPU time 35.28 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 195396 kb
Host smart-fe349832-2560-413c-8de6-0f459e4fd1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711847032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1711847032
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1485764537
Short name T956
Test name
Test status
Simulation time 6054709534 ps
CPU time 8.38 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:14 PM PST 24
Peak memory 198468 kb
Host smart-d8b787aa-02bb-4865-9987-9c0555df543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485764537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1485764537
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3551549169
Short name T39
Test name
Test status
Simulation time 64353561382 ps
CPU time 222.23 seconds
Started Feb 25 01:36:07 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 215824 kb
Host smart-af78f82e-daa1-4b9c-90ce-9c93f044dd71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551549169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3551549169
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1907770393
Short name T112
Test name
Test status
Simulation time 6875068399 ps
CPU time 25.57 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:30 PM PST 24
Peak memory 199176 kb
Host smart-e4eb2f23-4b0c-47a8-baca-4df5b84a331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907770393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1907770393
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.800115674
Short name T160
Test name
Test status
Simulation time 89526227516 ps
CPU time 23.92 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:36:29 PM PST 24
Peak memory 199640 kb
Host smart-aa1293c6-ced5-4ebc-afee-e9a89c737661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800115674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.800115674
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1785174110
Short name T795
Test name
Test status
Simulation time 23099242 ps
CPU time 0.56 seconds
Started Feb 25 01:36:22 PM PST 24
Finished Feb 25 01:36:22 PM PST 24
Peak memory 195032 kb
Host smart-0d4d8962-8189-458c-b743-9647523c1b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785174110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1785174110
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1069170403
Short name T698
Test name
Test status
Simulation time 103159089275 ps
CPU time 75.85 seconds
Started Feb 25 01:36:05 PM PST 24
Finished Feb 25 01:37:21 PM PST 24
Peak memory 199612 kb
Host smart-f31a12e2-06df-4a15-9821-ba72a8e634d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069170403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1069170403
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1391895308
Short name T181
Test name
Test status
Simulation time 20888461019 ps
CPU time 36.63 seconds
Started Feb 25 01:36:13 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 199704 kb
Host smart-a05c91b6-d2ef-432c-8a25-64184b3f83b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391895308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1391895308
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2831952410
Short name T1038
Test name
Test status
Simulation time 78204520756 ps
CPU time 54.59 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:37:09 PM PST 24
Peak memory 199700 kb
Host smart-d7dfef65-8fb1-4758-bfe6-12a6ecb6c6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831952410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2831952410
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3354944015
Short name T779
Test name
Test status
Simulation time 16393640964 ps
CPU time 27.49 seconds
Started Feb 25 01:36:19 PM PST 24
Finished Feb 25 01:36:46 PM PST 24
Peak memory 198212 kb
Host smart-c92fec1f-003f-4b15-aea1-3a2381eb172a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354944015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3354944015
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3137888721
Short name T931
Test name
Test status
Simulation time 88074874290 ps
CPU time 233.75 seconds
Started Feb 25 01:36:14 PM PST 24
Finished Feb 25 01:40:08 PM PST 24
Peak memory 199672 kb
Host smart-bad1dbea-5f04-42ea-a0eb-392dc421c300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137888721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3137888721
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3829660817
Short name T1033
Test name
Test status
Simulation time 4797634602 ps
CPU time 6.11 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:36:21 PM PST 24
Peak memory 198032 kb
Host smart-c3892e84-f453-4d03-b6d8-8f73dee81e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829660817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3829660817
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1525039341
Short name T47
Test name
Test status
Simulation time 44093015921 ps
CPU time 73.97 seconds
Started Feb 25 01:36:20 PM PST 24
Finished Feb 25 01:37:35 PM PST 24
Peak memory 198392 kb
Host smart-a6cff1d8-9304-4089-921d-fad3fc32fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525039341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1525039341
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3865309520
Short name T1037
Test name
Test status
Simulation time 7940329091 ps
CPU time 469.02 seconds
Started Feb 25 01:36:13 PM PST 24
Finished Feb 25 01:44:03 PM PST 24
Peak memory 199692 kb
Host smart-c75d9691-a5fe-425b-9f6b-e7dd8d3a1193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865309520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3865309520
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1366453991
Short name T823
Test name
Test status
Simulation time 673287415 ps
CPU time 2.03 seconds
Started Feb 25 01:36:16 PM PST 24
Finished Feb 25 01:36:18 PM PST 24
Peak memory 197640 kb
Host smart-4f5f52aa-0c18-4caa-a842-6691b5e14881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366453991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1366453991
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2584523105
Short name T404
Test name
Test status
Simulation time 117742773491 ps
CPU time 199.75 seconds
Started Feb 25 01:36:14 PM PST 24
Finished Feb 25 01:39:34 PM PST 24
Peak memory 199652 kb
Host smart-7280612f-fc3e-4621-ba08-ef7a6b3ed3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584523105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2584523105
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.312676885
Short name T497
Test name
Test status
Simulation time 4205949711 ps
CPU time 5 seconds
Started Feb 25 01:36:23 PM PST 24
Finished Feb 25 01:36:28 PM PST 24
Peak memory 195376 kb
Host smart-6ef1b5de-87be-41e3-a07b-d89530918384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312676885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.312676885
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1301991047
Short name T989
Test name
Test status
Simulation time 709346282 ps
CPU time 1.53 seconds
Started Feb 25 01:36:08 PM PST 24
Finished Feb 25 01:36:10 PM PST 24
Peak memory 198100 kb
Host smart-3beac9f9-b3da-46dd-ab22-d2f5c34df2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301991047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1301991047
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2944589869
Short name T837
Test name
Test status
Simulation time 1401449213 ps
CPU time 3.36 seconds
Started Feb 25 01:36:17 PM PST 24
Finished Feb 25 01:36:20 PM PST 24
Peak memory 197952 kb
Host smart-6ee432dc-a281-442e-9ef0-4c0b640ef4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944589869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2944589869
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2101095933
Short name T585
Test name
Test status
Simulation time 83089199765 ps
CPU time 64.49 seconds
Started Feb 25 01:36:06 PM PST 24
Finished Feb 25 01:37:10 PM PST 24
Peak memory 199648 kb
Host smart-3cb1e33f-bd2c-4c4c-a67c-70287d9720cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101095933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2101095933
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.816051386
Short name T863
Test name
Test status
Simulation time 20613835 ps
CPU time 0.56 seconds
Started Feb 25 01:36:29 PM PST 24
Finished Feb 25 01:36:30 PM PST 24
Peak memory 195068 kb
Host smart-c12942ec-e914-44eb-b29d-fa655248a67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816051386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.816051386
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.4061594513
Short name T653
Test name
Test status
Simulation time 164941787156 ps
CPU time 222.65 seconds
Started Feb 25 01:36:13 PM PST 24
Finished Feb 25 01:39:56 PM PST 24
Peak memory 199552 kb
Host smart-239bfc7c-458d-4426-b61d-217758a6cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061594513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4061594513
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1867432951
Short name T614
Test name
Test status
Simulation time 101692110745 ps
CPU time 169.6 seconds
Started Feb 25 01:36:16 PM PST 24
Finished Feb 25 01:39:06 PM PST 24
Peak memory 199672 kb
Host smart-2b7100c2-30b6-44a9-adbb-f9d14193090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867432951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1867432951
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.330451667
Short name T1000
Test name
Test status
Simulation time 72686537758 ps
CPU time 32.14 seconds
Started Feb 25 01:36:15 PM PST 24
Finished Feb 25 01:36:47 PM PST 24
Peak memory 199640 kb
Host smart-5aed736e-4cbc-4657-9474-64a5b6dd1dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330451667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.330451667
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3589532507
Short name T1067
Test name
Test status
Simulation time 45856749061 ps
CPU time 19.03 seconds
Started Feb 25 01:36:36 PM PST 24
Finished Feb 25 01:36:55 PM PST 24
Peak memory 197732 kb
Host smart-27a0ed53-4655-45f7-91e9-bbae029c697e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589532507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3589532507
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3111294629
Short name T767
Test name
Test status
Simulation time 55441005424 ps
CPU time 97.2 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:38:07 PM PST 24
Peak memory 199656 kb
Host smart-78eb91e7-7318-4b26-8f6b-622e0829fbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111294629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3111294629
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2219120589
Short name T519
Test name
Test status
Simulation time 1427586870 ps
CPU time 1.51 seconds
Started Feb 25 01:36:36 PM PST 24
Finished Feb 25 01:36:38 PM PST 24
Peak memory 197672 kb
Host smart-97c82f87-bde2-4510-835a-350cd52b9677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219120589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2219120589
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2481295701
Short name T867
Test name
Test status
Simulation time 233467765924 ps
CPU time 63.36 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:37:33 PM PST 24
Peak memory 199800 kb
Host smart-2d42ab21-4107-48d6-af81-bd4db3751096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481295701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2481295701
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.436272806
Short name T450
Test name
Test status
Simulation time 11116482896 ps
CPU time 149.28 seconds
Started Feb 25 01:36:31 PM PST 24
Finished Feb 25 01:39:01 PM PST 24
Peak memory 199500 kb
Host smart-7bb55275-e2e1-422f-b033-c1b42d483a31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436272806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.436272806
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1807247621
Short name T791
Test name
Test status
Simulation time 440846950 ps
CPU time 5.35 seconds
Started Feb 25 01:36:21 PM PST 24
Finished Feb 25 01:36:27 PM PST 24
Peak memory 197440 kb
Host smart-c2550e7f-2adb-4a08-8f2d-44abed997bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807247621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1807247621
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.677330757
Short name T848
Test name
Test status
Simulation time 70367265053 ps
CPU time 109.78 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:38:20 PM PST 24
Peak memory 198920 kb
Host smart-d3a05f8a-e18d-4d24-aede-e4470ba02c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677330757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.677330757
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.809188362
Short name T720
Test name
Test status
Simulation time 2916857099 ps
CPU time 4.23 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:36:34 PM PST 24
Peak memory 195076 kb
Host smart-0e28124c-ed27-477e-b070-918a8584340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809188362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.809188362
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2605377797
Short name T498
Test name
Test status
Simulation time 313531347 ps
CPU time 1.06 seconds
Started Feb 25 01:36:17 PM PST 24
Finished Feb 25 01:36:18 PM PST 24
Peak memory 197860 kb
Host smart-43e2a78f-9660-454e-9679-14156ae3d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605377797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2605377797
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1232842136
Short name T589
Test name
Test status
Simulation time 683042354 ps
CPU time 1.58 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:36:31 PM PST 24
Peak memory 197860 kb
Host smart-84011cbe-abaa-4d98-a363-ca603224dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232842136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1232842136
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.468702320
Short name T161
Test name
Test status
Simulation time 122612980295 ps
CPU time 51.96 seconds
Started Feb 25 01:36:21 PM PST 24
Finished Feb 25 01:37:13 PM PST 24
Peak memory 199732 kb
Host smart-428c11ca-54f3-4a83-9f15-6fc57d965c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468702320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.468702320
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.137415422
Short name T572
Test name
Test status
Simulation time 33704408 ps
CPU time 0.57 seconds
Started Feb 25 01:36:43 PM PST 24
Finished Feb 25 01:36:45 PM PST 24
Peak memory 195096 kb
Host smart-625dce23-ba71-4020-9f3c-acae8a805183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137415422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.137415422
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1948387245
Short name T357
Test name
Test status
Simulation time 56885800469 ps
CPU time 23.17 seconds
Started Feb 25 01:36:31 PM PST 24
Finished Feb 25 01:36:55 PM PST 24
Peak memory 199612 kb
Host smart-a5d71d99-5f48-4134-b7a1-98aed3719726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948387245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1948387245
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3581490061
Short name T363
Test name
Test status
Simulation time 155349004587 ps
CPU time 59.75 seconds
Started Feb 25 01:36:30 PM PST 24
Finished Feb 25 01:37:30 PM PST 24
Peak memory 199532 kb
Host smart-9864f07d-640d-4e77-84eb-d46e9af27cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581490061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3581490061
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.2523214294
Short name T573
Test name
Test status
Simulation time 234104701851 ps
CPU time 350.06 seconds
Started Feb 25 01:36:41 PM PST 24
Finished Feb 25 01:42:31 PM PST 24
Peak memory 199296 kb
Host smart-05071b34-c8e5-4022-9081-9bc1b520ca66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523214294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2523214294
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1600323917
Short name T500
Test name
Test status
Simulation time 76330810750 ps
CPU time 221.98 seconds
Started Feb 25 01:36:40 PM PST 24
Finished Feb 25 01:40:22 PM PST 24
Peak memory 199640 kb
Host smart-66a38adc-6bbb-49c5-8e5c-bdb9350e0b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600323917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1600323917
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1006345833
Short name T483
Test name
Test status
Simulation time 3780098905 ps
CPU time 3.36 seconds
Started Feb 25 01:36:37 PM PST 24
Finished Feb 25 01:36:42 PM PST 24
Peak memory 197672 kb
Host smart-3f04ff1a-0f1e-46bb-a461-ebd9abe17b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006345833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1006345833
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3773281082
Short name T568
Test name
Test status
Simulation time 19719504344 ps
CPU time 29.55 seconds
Started Feb 25 01:36:43 PM PST 24
Finished Feb 25 01:37:14 PM PST 24
Peak memory 198280 kb
Host smart-41972a87-1b73-4cff-8537-e8e913f4c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773281082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3773281082
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3077033711
Short name T961
Test name
Test status
Simulation time 23426111518 ps
CPU time 1134.11 seconds
Started Feb 25 01:36:38 PM PST 24
Finished Feb 25 01:55:33 PM PST 24
Peak memory 199704 kb
Host smart-c099b942-99e0-4ed9-afc4-ba2d8505ceb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077033711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3077033711
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2188139075
Short name T292
Test name
Test status
Simulation time 14157857379 ps
CPU time 21.65 seconds
Started Feb 25 01:36:42 PM PST 24
Finished Feb 25 01:37:04 PM PST 24
Peak memory 198088 kb
Host smart-5f6344f7-7a78-403f-8441-60990c790b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188139075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2188139075
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3338007795
Short name T637
Test name
Test status
Simulation time 1574862806 ps
CPU time 3.07 seconds
Started Feb 25 01:36:41 PM PST 24
Finished Feb 25 01:36:44 PM PST 24
Peak memory 195112 kb
Host smart-1600db25-aaf0-444e-bef9-2ec7af4f0801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338007795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3338007795
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3190628748
Short name T583
Test name
Test status
Simulation time 963379318 ps
CPU time 1.82 seconds
Started Feb 25 01:36:35 PM PST 24
Finished Feb 25 01:36:36 PM PST 24
Peak memory 198476 kb
Host smart-09d16e31-19a3-44f8-9f23-ee15aa5630fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190628748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3190628748
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1892621230
Short name T382
Test name
Test status
Simulation time 296959218502 ps
CPU time 110.44 seconds
Started Feb 25 01:36:41 PM PST 24
Finished Feb 25 01:38:31 PM PST 24
Peak memory 208736 kb
Host smart-dd79c067-06d2-412e-a547-b142401115a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892621230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1892621230
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3981390227
Short name T36
Test name
Test status
Simulation time 6957341823 ps
CPU time 85.99 seconds
Started Feb 25 01:36:40 PM PST 24
Finished Feb 25 01:38:06 PM PST 24
Peak memory 208100 kb
Host smart-7f242c3a-082d-4fd6-bb44-e3886320caab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981390227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3981390227
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3362858416
Short name T422
Test name
Test status
Simulation time 1585083113 ps
CPU time 1.81 seconds
Started Feb 25 01:36:38 PM PST 24
Finished Feb 25 01:36:40 PM PST 24
Peak memory 197984 kb
Host smart-6b499e82-d2da-4867-b815-b2c7592c68c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362858416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3362858416
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.514141171
Short name T881
Test name
Test status
Simulation time 258400423950 ps
CPU time 53.52 seconds
Started Feb 25 01:36:29 PM PST 24
Finished Feb 25 01:37:23 PM PST 24
Peak memory 199568 kb
Host smart-7cb3ea9d-b312-46fa-a0fe-9bace897c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514141171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.514141171
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.56787865
Short name T1101
Test name
Test status
Simulation time 35408903 ps
CPU time 0.57 seconds
Started Feb 25 01:36:47 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 195184 kb
Host smart-1e957027-2642-4ecb-8d5c-f9a43bce7e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56787865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.56787865
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4129929055
Short name T886
Test name
Test status
Simulation time 148910288309 ps
CPU time 69.1 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:37:48 PM PST 24
Peak memory 199436 kb
Host smart-fae4bc60-1df9-4658-9d15-7617b7d9416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129929055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4129929055
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2835852310
Short name T1032
Test name
Test status
Simulation time 21326661516 ps
CPU time 52.4 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:37:31 PM PST 24
Peak memory 199644 kb
Host smart-7a12d45a-98f4-4ec5-857f-a1abc992e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835852310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2835852310
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2296035439
Short name T238
Test name
Test status
Simulation time 85456228994 ps
CPU time 27.16 seconds
Started Feb 25 01:36:38 PM PST 24
Finished Feb 25 01:37:05 PM PST 24
Peak memory 199468 kb
Host smart-e8ebc3bc-5cd7-492d-9705-ee1b339b1feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296035439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2296035439
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2384637670
Short name T871
Test name
Test status
Simulation time 124794482074 ps
CPU time 327.61 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:42:06 PM PST 24
Peak memory 199584 kb
Host smart-66f068b4-2604-4679-8384-b92d7993cd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384637670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2384637670
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2670838605
Short name T530
Test name
Test status
Simulation time 3175895025 ps
CPU time 2.12 seconds
Started Feb 25 01:36:41 PM PST 24
Finished Feb 25 01:36:44 PM PST 24
Peak memory 197976 kb
Host smart-88aca551-9bac-4c53-bcb9-556b9eee59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670838605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2670838605
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3398476873
Short name T510
Test name
Test status
Simulation time 6669657594 ps
CPU time 24.49 seconds
Started Feb 25 01:36:40 PM PST 24
Finished Feb 25 01:37:05 PM PST 24
Peak memory 198184 kb
Host smart-f00a7a37-660f-4f97-bd64-fc8f4f19c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398476873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3398476873
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4251569776
Short name T894
Test name
Test status
Simulation time 11027919825 ps
CPU time 643.51 seconds
Started Feb 25 01:36:43 PM PST 24
Finished Feb 25 01:47:28 PM PST 24
Peak memory 199436 kb
Host smart-a9f55e36-befa-4f74-a69c-09df34a680fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251569776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4251569776
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1752205460
Short name T272
Test name
Test status
Simulation time 40812005020 ps
CPU time 68.73 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:37:48 PM PST 24
Peak memory 199720 kb
Host smart-f48ad2ba-7ec5-4044-bfa5-2fe38c5b01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752205460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1752205460
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2775580123
Short name T599
Test name
Test status
Simulation time 33695295676 ps
CPU time 26.2 seconds
Started Feb 25 01:36:41 PM PST 24
Finished Feb 25 01:37:07 PM PST 24
Peak memory 195480 kb
Host smart-22a5c8a7-d2e6-4063-b025-e79c008fdb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775580123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2775580123
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1669262543
Short name T1072
Test name
Test status
Simulation time 6110941470 ps
CPU time 5.66 seconds
Started Feb 25 01:36:38 PM PST 24
Finished Feb 25 01:36:44 PM PST 24
Peak memory 199536 kb
Host smart-db7b97aa-2389-471d-8e1c-ae7986720806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669262543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1669262543
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1912919086
Short name T273
Test name
Test status
Simulation time 75145372052 ps
CPU time 60.36 seconds
Started Feb 25 01:36:49 PM PST 24
Finished Feb 25 01:37:51 PM PST 24
Peak memory 199700 kb
Host smart-ab778806-ced5-4bf7-9fb3-475ebe95b35c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912919086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1912919086
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1079601747
Short name T950
Test name
Test status
Simulation time 20469247797 ps
CPU time 171.45 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:39:31 PM PST 24
Peak memory 209380 kb
Host smart-ed91628d-c7f7-4df4-b6a3-a1a75de5965e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079601747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1079601747
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4108779823
Short name T556
Test name
Test status
Simulation time 2372825608 ps
CPU time 2.08 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:36:42 PM PST 24
Peak memory 197984 kb
Host smart-361c75ad-1200-44f3-9f57-6cb7fac97d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108779823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4108779823
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1869909146
Short name T1017
Test name
Test status
Simulation time 126733866478 ps
CPU time 43.91 seconds
Started Feb 25 01:36:39 PM PST 24
Finished Feb 25 01:37:23 PM PST 24
Peak memory 199716 kb
Host smart-38ba873b-b8ad-4e1c-9fce-aa2540654952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869909146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1869909146
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.980506605
Short name T990
Test name
Test status
Simulation time 51616081 ps
CPU time 0.61 seconds
Started Feb 25 01:36:53 PM PST 24
Finished Feb 25 01:36:54 PM PST 24
Peak memory 195096 kb
Host smart-67662f0a-2ccb-4d3a-b05f-1f95a67dcdeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980506605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.980506605
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3447607195
Short name T625
Test name
Test status
Simulation time 14881223365 ps
CPU time 49.14 seconds
Started Feb 25 01:36:48 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 199352 kb
Host smart-60e0c2ec-2a13-4672-8976-9d92d93e2c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447607195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3447607195
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1949007683
Short name T783
Test name
Test status
Simulation time 42630447420 ps
CPU time 18.75 seconds
Started Feb 25 01:36:48 PM PST 24
Finished Feb 25 01:37:08 PM PST 24
Peak memory 198632 kb
Host smart-c6ad1a21-aad5-49ca-96f6-236681040c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949007683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1949007683
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3779510598
Short name T170
Test name
Test status
Simulation time 117267654443 ps
CPU time 53.86 seconds
Started Feb 25 01:36:52 PM PST 24
Finished Feb 25 01:37:46 PM PST 24
Peak memory 199612 kb
Host smart-eab4ee3d-e20b-4e82-ad37-3dd3e6a4e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779510598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3779510598
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.4103784741
Short name T677
Test name
Test status
Simulation time 457056426055 ps
CPU time 722.11 seconds
Started Feb 25 01:36:50 PM PST 24
Finished Feb 25 01:48:53 PM PST 24
Peak memory 199560 kb
Host smart-53518864-98d8-4811-bbed-ece853c5937e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103784741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4103784741
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.201163976
Short name T1096
Test name
Test status
Simulation time 227085006541 ps
CPU time 486.87 seconds
Started Feb 25 01:36:47 PM PST 24
Finished Feb 25 01:44:56 PM PST 24
Peak memory 199636 kb
Host smart-42f7fbb4-b759-4c47-8832-ef8de27695ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201163976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.201163976
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.583228515
Short name T608
Test name
Test status
Simulation time 7157564864 ps
CPU time 27.69 seconds
Started Feb 25 01:36:51 PM PST 24
Finished Feb 25 01:37:19 PM PST 24
Peak memory 198196 kb
Host smart-2daced32-5b93-4afc-9bbc-4319b43dd146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583228515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.583228515
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2272726623
Short name T1016
Test name
Test status
Simulation time 144700128287 ps
CPU time 167.53 seconds
Started Feb 25 01:36:53 PM PST 24
Finished Feb 25 01:39:41 PM PST 24
Peak memory 208028 kb
Host smart-4027d746-83bb-4f0e-8a20-b4cb4996286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272726623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2272726623
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3301588899
Short name T868
Test name
Test status
Simulation time 25744613582 ps
CPU time 568.38 seconds
Started Feb 25 01:36:46 PM PST 24
Finished Feb 25 01:46:17 PM PST 24
Peak memory 199636 kb
Host smart-a7a45c32-ea28-4714-8d67-afa66903cb84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301588899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3301588899
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.411652606
Short name T480
Test name
Test status
Simulation time 2015296597 ps
CPU time 8.22 seconds
Started Feb 25 01:36:47 PM PST 24
Finished Feb 25 01:36:57 PM PST 24
Peak memory 197316 kb
Host smart-635b5d73-e912-417c-a2be-340a8ac6a785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411652606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.411652606
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3555813224
Short name T936
Test name
Test status
Simulation time 85480379223 ps
CPU time 21.68 seconds
Started Feb 25 01:36:50 PM PST 24
Finished Feb 25 01:37:12 PM PST 24
Peak memory 198744 kb
Host smart-d09d38b2-a84b-4891-a291-b6cd25b167e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555813224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3555813224
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.322928621
Short name T561
Test name
Test status
Simulation time 3086793112 ps
CPU time 3.39 seconds
Started Feb 25 01:36:55 PM PST 24
Finished Feb 25 01:36:58 PM PST 24
Peak memory 195040 kb
Host smart-4f90e1c4-1f36-4dc3-a1cf-c934479d21dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322928621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.322928621
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4112475971
Short name T575
Test name
Test status
Simulation time 674288730 ps
CPU time 2.83 seconds
Started Feb 25 01:36:55 PM PST 24
Finished Feb 25 01:36:58 PM PST 24
Peak memory 198004 kb
Host smart-02f0eb20-eb3b-45d6-890c-c838a93cd1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112475971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4112475971
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1713026865
Short name T364
Test name
Test status
Simulation time 456647433984 ps
CPU time 596.87 seconds
Started Feb 25 01:36:55 PM PST 24
Finished Feb 25 01:46:52 PM PST 24
Peak memory 207996 kb
Host smart-95e47485-c1e7-4722-a71a-66d65fcb4b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713026865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1713026865
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1764201306
Short name T609
Test name
Test status
Simulation time 826796735 ps
CPU time 2.46 seconds
Started Feb 25 01:36:52 PM PST 24
Finished Feb 25 01:36:55 PM PST 24
Peak memory 198080 kb
Host smart-f8fb3cd5-fcb5-4cc2-9bbc-a9595bba0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764201306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1764201306
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1191548157
Short name T991
Test name
Test status
Simulation time 126658892085 ps
CPU time 89.32 seconds
Started Feb 25 01:36:49 PM PST 24
Finished Feb 25 01:38:19 PM PST 24
Peak memory 199572 kb
Host smart-b1d3c1d2-fc32-4703-8d6e-9d5922bdb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191548157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1191548157
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3820589570
Short name T861
Test name
Test status
Simulation time 12861553 ps
CPU time 0.56 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 01:37:00 PM PST 24
Peak memory 195020 kb
Host smart-e2aabb3e-e288-4f0e-a87d-7f1cd0dc7300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820589570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3820589570
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.565445058
Short name T786
Test name
Test status
Simulation time 38676551099 ps
CPU time 49.69 seconds
Started Feb 25 01:36:55 PM PST 24
Finished Feb 25 01:37:46 PM PST 24
Peak memory 199660 kb
Host smart-ba6b8a24-e694-4b3c-b7ad-d3df32e6914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565445058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.565445058
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.941241525
Short name T611
Test name
Test status
Simulation time 44881826932 ps
CPU time 14.69 seconds
Started Feb 25 01:36:47 PM PST 24
Finished Feb 25 01:37:04 PM PST 24
Peak memory 199016 kb
Host smart-9f110842-f470-4e16-bdbe-ddbe8c97bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941241525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.941241525
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.230923754
Short name T771
Test name
Test status
Simulation time 100537948040 ps
CPU time 74.48 seconds
Started Feb 25 01:36:48 PM PST 24
Finished Feb 25 01:38:04 PM PST 24
Peak memory 199368 kb
Host smart-ec66a0fb-a269-41d2-8b2a-b0a7d5bfc197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230923754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.230923754
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1362982615
Short name T938
Test name
Test status
Simulation time 181428258747 ps
CPU time 1416.78 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 02:00:36 PM PST 24
Peak memory 199628 kb
Host smart-3e0c2a2a-5180-4e8c-9d2e-8f380cc9d794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362982615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1362982615
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2238241722
Short name T1041
Test name
Test status
Simulation time 3684823551 ps
CPU time 5.63 seconds
Started Feb 25 01:36:58 PM PST 24
Finished Feb 25 01:37:04 PM PST 24
Peak memory 197272 kb
Host smart-cd051238-3bdb-4543-b6a0-15fb3cf3c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238241722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2238241722
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.574568855
Short name T464
Test name
Test status
Simulation time 134964164814 ps
CPU time 64.6 seconds
Started Feb 25 01:36:48 PM PST 24
Finished Feb 25 01:37:54 PM PST 24
Peak memory 199264 kb
Host smart-17084b42-14d3-49c8-818b-300ea1e6b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574568855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.574568855
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1568549897
Short name T60
Test name
Test status
Simulation time 19569320648 ps
CPU time 1073.18 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 01:54:53 PM PST 24
Peak memory 199608 kb
Host smart-d5f07658-a260-4e35-b9fb-d0000bc32211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568549897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1568549897
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3553658507
Short name T645
Test name
Test status
Simulation time 4349683925 ps
CPU time 37.22 seconds
Started Feb 25 01:36:51 PM PST 24
Finished Feb 25 01:37:28 PM PST 24
Peak memory 198384 kb
Host smart-9aa71421-63c5-4a4a-b1ad-4dda4b61690d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553658507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3553658507
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.600697594
Short name T442
Test name
Test status
Simulation time 3744551610 ps
CPU time 1.99 seconds
Started Feb 25 01:36:53 PM PST 24
Finished Feb 25 01:36:55 PM PST 24
Peak memory 195376 kb
Host smart-1ecbf95a-6194-47d6-8082-ce3518784fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600697594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.600697594
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1129349983
Short name T8
Test name
Test status
Simulation time 758825753 ps
CPU time 2.05 seconds
Started Feb 25 01:36:49 PM PST 24
Finished Feb 25 01:36:52 PM PST 24
Peak memory 198964 kb
Host smart-78186779-bbdc-43fd-af4c-fee9fb8b8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129349983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1129349983
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2749619261
Short name T929
Test name
Test status
Simulation time 256944463112 ps
CPU time 412.77 seconds
Started Feb 25 01:37:02 PM PST 24
Finished Feb 25 01:43:55 PM PST 24
Peak memory 199604 kb
Host smart-fc6c562d-ce5b-48fc-993c-4083accc6866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749619261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2749619261
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3194563091
Short name T25
Test name
Test status
Simulation time 9580858985 ps
CPU time 8.41 seconds
Started Feb 25 01:37:01 PM PST 24
Finished Feb 25 01:37:10 PM PST 24
Peak memory 199592 kb
Host smart-0f2bad61-0ceb-44d3-9f1d-268747bba31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194563091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3194563091
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1333412100
Short name T665
Test name
Test status
Simulation time 100800813736 ps
CPU time 48.27 seconds
Started Feb 25 01:36:50 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 199584 kb
Host smart-20923750-dfef-416b-a843-a27fe4b84922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333412100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1333412100
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2044988174
Short name T743
Test name
Test status
Simulation time 17876304 ps
CPU time 0.53 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:32:39 PM PST 24
Peak memory 195032 kb
Host smart-1a7231be-8471-46ba-b6f3-637fa813a72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044988174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2044988174
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3377050879
Short name T1095
Test name
Test status
Simulation time 151843730846 ps
CPU time 242.81 seconds
Started Feb 25 01:32:34 PM PST 24
Finished Feb 25 01:36:37 PM PST 24
Peak memory 199568 kb
Host smart-b300d579-a8e7-42e4-bd1e-0e2e07e59896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377050879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3377050879
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.983893846
Short name T706
Test name
Test status
Simulation time 285542352318 ps
CPU time 456.43 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:40:26 PM PST 24
Peak memory 199332 kb
Host smart-a2bfa949-2e55-4642-ae7a-142253db7bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983893846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.983893846
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4229437726
Short name T537
Test name
Test status
Simulation time 4535224439 ps
CPU time 10.69 seconds
Started Feb 25 01:32:39 PM PST 24
Finished Feb 25 01:32:50 PM PST 24
Peak memory 198920 kb
Host smart-3e79209d-51cc-4021-88b4-233d1d767502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229437726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4229437726
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4226988477
Short name T416
Test name
Test status
Simulation time 76282624047 ps
CPU time 127.29 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:34:44 PM PST 24
Peak memory 199644 kb
Host smart-eb6b9e04-3716-4b18-a9ef-6ddd54b232cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226988477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4226988477
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4155465187
Short name T788
Test name
Test status
Simulation time 15444518380 ps
CPU time 209.17 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:36:07 PM PST 24
Peak memory 199616 kb
Host smart-51aa52f0-cc87-40c6-846a-a9aea0930668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155465187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4155465187
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.533726608
Short name T58
Test name
Test status
Simulation time 678708739 ps
CPU time 2.61 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:32:36 PM PST 24
Peak memory 197376 kb
Host smart-c5a40e85-79b0-4cbb-affc-8ddbff535372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533726608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.533726608
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2985635411
Short name T725
Test name
Test status
Simulation time 134374571466 ps
CPU time 189.5 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:35:43 PM PST 24
Peak memory 199676 kb
Host smart-8cf02058-565d-4926-9b08-fbdcd2aa1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985635411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2985635411
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2969492523
Short name T522
Test name
Test status
Simulation time 30044775110 ps
CPU time 14.18 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:52 PM PST 24
Peak memory 195368 kb
Host smart-d410a37b-4569-4b25-8ed3-5fd0b12512b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969492523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2969492523
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3127459898
Short name T104
Test name
Test status
Simulation time 114311954 ps
CPU time 0.81 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:38 PM PST 24
Peak memory 217068 kb
Host smart-9cd8cc6a-9441-45ad-a896-976e31ce530c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127459898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3127459898
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3882196761
Short name T435
Test name
Test status
Simulation time 583102043 ps
CPU time 1.69 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:32:35 PM PST 24
Peak memory 198000 kb
Host smart-db1fd5cd-9532-4243-af94-220475ae29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882196761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3882196761
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.409415469
Short name T511
Test name
Test status
Simulation time 551618227 ps
CPU time 1.33 seconds
Started Feb 25 01:32:37 PM PST 24
Finished Feb 25 01:32:38 PM PST 24
Peak memory 196288 kb
Host smart-13da0981-2ee1-4c69-a5d1-1736ad3f1a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409415469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.409415469
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3099365319
Short name T163
Test name
Test status
Simulation time 26563263912 ps
CPU time 18.79 seconds
Started Feb 25 01:32:34 PM PST 24
Finished Feb 25 01:32:53 PM PST 24
Peak memory 199632 kb
Host smart-f5bd4255-cee2-4065-8faf-ad5d3b59c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099365319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3099365319
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2424662881
Short name T538
Test name
Test status
Simulation time 38438691 ps
CPU time 0.55 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:37:12 PM PST 24
Peak memory 195112 kb
Host smart-1f9b90bd-8565-4ffc-9ed9-d8939eb1d674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424662881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2424662881
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.612502525
Short name T106
Test name
Test status
Simulation time 9826957569 ps
CPU time 16.52 seconds
Started Feb 25 01:36:56 PM PST 24
Finished Feb 25 01:37:13 PM PST 24
Peak memory 197844 kb
Host smart-5b4d6380-2069-4c54-b1d6-762e3de42a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612502525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.612502525
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.919090950
Short name T651
Test name
Test status
Simulation time 54519027959 ps
CPU time 64.13 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 01:38:03 PM PST 24
Peak memory 199700 kb
Host smart-553b3da8-16df-4458-8d3c-a06ebba8b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919090950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.919090950
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.4021261556
Short name T845
Test name
Test status
Simulation time 55135505235 ps
CPU time 94.83 seconds
Started Feb 25 01:37:02 PM PST 24
Finished Feb 25 01:38:37 PM PST 24
Peak memory 199588 kb
Host smart-cc05f107-b79f-42b1-9300-2a94c65c1f2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021261556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4021261556
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2248590130
Short name T671
Test name
Test status
Simulation time 99709552669 ps
CPU time 574.28 seconds
Started Feb 25 01:37:01 PM PST 24
Finished Feb 25 01:46:36 PM PST 24
Peak memory 199588 kb
Host smart-6983955b-ba98-4064-a373-8b198a39ca76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248590130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2248590130
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_noise_filter.897422777
Short name T429
Test name
Test status
Simulation time 29328916282 ps
CPU time 24.89 seconds
Started Feb 25 01:37:01 PM PST 24
Finished Feb 25 01:37:26 PM PST 24
Peak memory 198176 kb
Host smart-57daba4e-27da-42f7-b39b-420505d1464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897422777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.897422777
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1612806712
Short name T799
Test name
Test status
Simulation time 13641496768 ps
CPU time 831.7 seconds
Started Feb 25 01:36:57 PM PST 24
Finished Feb 25 01:50:48 PM PST 24
Peak memory 199396 kb
Host smart-a43e57e9-484c-41ed-b836-081b8c32b72f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612806712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1612806712
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1414179367
Short name T576
Test name
Test status
Simulation time 3761110644 ps
CPU time 23.84 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 01:37:23 PM PST 24
Peak memory 197988 kb
Host smart-00a515f7-4cb1-43cf-9b94-98906d0d1a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414179367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1414179367
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4057851504
Short name T1004
Test name
Test status
Simulation time 110186752105 ps
CPU time 170.67 seconds
Started Feb 25 01:36:57 PM PST 24
Finished Feb 25 01:39:48 PM PST 24
Peak memory 199724 kb
Host smart-10155f8a-ebb6-4397-8219-6d99898deca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057851504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4057851504
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1747841460
Short name T647
Test name
Test status
Simulation time 3224792880 ps
CPU time 3.19 seconds
Started Feb 25 01:37:02 PM PST 24
Finished Feb 25 01:37:06 PM PST 24
Peak memory 195464 kb
Host smart-d112a660-e8df-4d1c-829b-9569ca7268a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747841460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1747841460
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3452385295
Short name T834
Test name
Test status
Simulation time 5954983033 ps
CPU time 17.14 seconds
Started Feb 25 01:37:01 PM PST 24
Finished Feb 25 01:37:19 PM PST 24
Peak memory 199056 kb
Host smart-154ce4e7-54c9-4dd9-9d0f-ca84fbd10929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452385295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3452385295
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3882175974
Short name T690
Test name
Test status
Simulation time 3637544867 ps
CPU time 1.67 seconds
Started Feb 25 01:36:59 PM PST 24
Finished Feb 25 01:37:02 PM PST 24
Peak memory 198280 kb
Host smart-89181b25-d1dd-439b-aa9b-5a5c72f5a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882175974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3882175974
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1866725689
Short name T852
Test name
Test status
Simulation time 80228678639 ps
CPU time 123.8 seconds
Started Feb 25 01:37:01 PM PST 24
Finished Feb 25 01:39:05 PM PST 24
Peak memory 198936 kb
Host smart-e0779c2b-e563-4ae0-9152-34cffdf480fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866725689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1866725689
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1326278080
Short name T738
Test name
Test status
Simulation time 15122873 ps
CPU time 0.57 seconds
Started Feb 25 01:37:12 PM PST 24
Finished Feb 25 01:37:13 PM PST 24
Peak memory 195104 kb
Host smart-fd578beb-060e-46a3-aa37-588fe467574d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326278080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1326278080
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2690389127
Short name T940
Test name
Test status
Simulation time 78078450891 ps
CPU time 35.06 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:37:46 PM PST 24
Peak memory 199604 kb
Host smart-7a4956ff-a8b5-4a95-b6b8-d3ca02207f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690389127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2690389127
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3803369714
Short name T380
Test name
Test status
Simulation time 120278070115 ps
CPU time 34.27 seconds
Started Feb 25 01:37:14 PM PST 24
Finished Feb 25 01:37:49 PM PST 24
Peak memory 199680 kb
Host smart-9f6a4a3b-9ed2-41ba-bb5b-17b036ddefd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803369714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3803369714
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.442114144
Short name T264
Test name
Test status
Simulation time 32444023632 ps
CPU time 13.73 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:37:25 PM PST 24
Peak memory 198180 kb
Host smart-b85c99b3-1f4e-4138-b093-8e557602ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442114144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.442114144
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1418364579
Short name T541
Test name
Test status
Simulation time 185502224047 ps
CPU time 64.04 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:38:16 PM PST 24
Peak memory 198636 kb
Host smart-a863829e-0f7a-4a3a-a2c4-eec226ae623f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418364579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1418364579
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3258364578
Short name T935
Test name
Test status
Simulation time 76514067561 ps
CPU time 705.72 seconds
Started Feb 25 01:37:17 PM PST 24
Finished Feb 25 01:49:04 PM PST 24
Peak memory 199656 kb
Host smart-c1686411-b9e0-4d62-b87a-ab19e7ce39bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258364578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3258364578
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_noise_filter.924109633
Short name T722
Test name
Test status
Simulation time 211577480071 ps
CPU time 118.49 seconds
Started Feb 25 01:37:15 PM PST 24
Finished Feb 25 01:39:14 PM PST 24
Peak memory 207960 kb
Host smart-2f0075a3-11f7-4e33-95de-3b4704dc1e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924109633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.924109633
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3112979726
Short name T769
Test name
Test status
Simulation time 9631063308 ps
CPU time 306.15 seconds
Started Feb 25 01:37:12 PM PST 24
Finished Feb 25 01:42:18 PM PST 24
Peak memory 199652 kb
Host smart-7f4f2ad8-5a55-47f5-9c9b-b6b72bf648d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112979726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3112979726
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1066009337
Short name T892
Test name
Test status
Simulation time 3826992815 ps
CPU time 35.06 seconds
Started Feb 25 01:37:13 PM PST 24
Finished Feb 25 01:37:48 PM PST 24
Peak memory 197888 kb
Host smart-6dfb7569-6a8a-4d76-b666-0ffeb32e73f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066009337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1066009337
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1087759268
Short name T325
Test name
Test status
Simulation time 77780297377 ps
CPU time 129.68 seconds
Started Feb 25 01:37:12 PM PST 24
Finished Feb 25 01:39:22 PM PST 24
Peak memory 199548 kb
Host smart-f8f55d64-22b0-4ee4-b30e-f5e9c6dfe352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087759268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1087759268
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.516707970
Short name T506
Test name
Test status
Simulation time 41040910791 ps
CPU time 25 seconds
Started Feb 25 01:37:17 PM PST 24
Finished Feb 25 01:37:42 PM PST 24
Peak memory 195156 kb
Host smart-1086f61e-1831-4e15-9166-348c3cbffc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516707970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.516707970
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2091402762
Short name T606
Test name
Test status
Simulation time 5992503649 ps
CPU time 22.19 seconds
Started Feb 25 01:37:12 PM PST 24
Finished Feb 25 01:37:35 PM PST 24
Peak memory 198952 kb
Host smart-87f06c03-8a85-46ab-b615-1fc78f3874eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091402762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2091402762
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1701657183
Short name T129
Test name
Test status
Simulation time 278647056734 ps
CPU time 306.71 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:42:18 PM PST 24
Peak memory 199588 kb
Host smart-56a7f713-f478-4eb1-b9a4-c64d42319a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701657183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1701657183
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3592402405
Short name T1105
Test name
Test status
Simulation time 1853655891 ps
CPU time 2.56 seconds
Started Feb 25 01:37:14 PM PST 24
Finished Feb 25 01:37:16 PM PST 24
Peak memory 197880 kb
Host smart-64b80684-5801-4ff1-af18-d0cc52d32ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592402405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3592402405
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1932355969
Short name T139
Test name
Test status
Simulation time 58370691417 ps
CPU time 81.63 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:38:33 PM PST 24
Peak memory 199628 kb
Host smart-b757c273-588e-4caf-b155-d2f4c951d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932355969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1932355969
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2855071219
Short name T517
Test name
Test status
Simulation time 19908912 ps
CPU time 0.58 seconds
Started Feb 25 01:37:27 PM PST 24
Finished Feb 25 01:37:29 PM PST 24
Peak memory 195112 kb
Host smart-0f25919a-658b-4c78-9d5d-82cb7e03c306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855071219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2855071219
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.546876756
Short name T362
Test name
Test status
Simulation time 50255062889 ps
CPU time 49.31 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:38:12 PM PST 24
Peak memory 199568 kb
Host smart-04d85a1b-d3f2-4054-afd9-3c65bfd07857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546876756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.546876756
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3476374518
Short name T1056
Test name
Test status
Simulation time 151404185747 ps
CPU time 63.25 seconds
Started Feb 25 01:37:23 PM PST 24
Finished Feb 25 01:38:28 PM PST 24
Peak memory 198620 kb
Host smart-0846c1a3-143c-447d-b4d5-8982a157e8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476374518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3476374518
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2012087159
Short name T820
Test name
Test status
Simulation time 135480620391 ps
CPU time 15.76 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 199680 kb
Host smart-6bc80f7e-488a-4fb5-a4cc-27f0e03b731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012087159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2012087159
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.178790174
Short name T411
Test name
Test status
Simulation time 29952683035 ps
CPU time 48.2 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:38:11 PM PST 24
Peak memory 199656 kb
Host smart-437349df-0499-4d70-b66a-6bc51abee596
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178790174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.178790174
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3922647817
Short name T667
Test name
Test status
Simulation time 65984360214 ps
CPU time 147.68 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:39:49 PM PST 24
Peak memory 199660 kb
Host smart-9dcb2b77-b971-4aa6-9a1e-5ce196e0ce68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922647817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3922647817
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1627418839
Short name T20
Test name
Test status
Simulation time 1560205159 ps
CPU time 4.49 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:28 PM PST 24
Peak memory 197592 kb
Host smart-ed02fa24-9f1f-40b1-b272-b76c0360dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627418839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1627418839
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3106637373
Short name T1058
Test name
Test status
Simulation time 264090051069 ps
CPU time 90.33 seconds
Started Feb 25 01:37:22 PM PST 24
Finished Feb 25 01:38:54 PM PST 24
Peak memory 207804 kb
Host smart-c1e84ede-1608-4e9a-8645-92c41c29bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106637373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3106637373
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1533635499
Short name T618
Test name
Test status
Simulation time 11610232652 ps
CPU time 170.44 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:40:13 PM PST 24
Peak memory 199696 kb
Host smart-1227742b-bcae-4dc1-8715-5df561179c82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1533635499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1533635499
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3100389933
Short name T670
Test name
Test status
Simulation time 2199421684 ps
CPU time 10.75 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:34 PM PST 24
Peak memory 197756 kb
Host smart-9f5da9d8-59ee-41ce-b944-e2a9cd9c2114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100389933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3100389933
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.393931511
Short name T1011
Test name
Test status
Simulation time 119011573931 ps
CPU time 129.24 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:39:32 PM PST 24
Peak memory 199608 kb
Host smart-9334ef04-6ac3-4d96-9937-72700fdf910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393931511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.393931511
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2811715332
Short name T833
Test name
Test status
Simulation time 36558408305 ps
CPU time 7.46 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:37:29 PM PST 24
Peak memory 195060 kb
Host smart-14fe1bb4-30c8-46f4-b7a9-a94e67c94386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811715332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2811715332
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4247425625
Short name T806
Test name
Test status
Simulation time 317862842 ps
CPU time 1.06 seconds
Started Feb 25 01:37:11 PM PST 24
Finished Feb 25 01:37:12 PM PST 24
Peak memory 197868 kb
Host smart-fed460f8-5c2f-48da-aa96-8883ca403000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247425625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4247425625
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3354988215
Short name T710
Test name
Test status
Simulation time 907951107 ps
CPU time 3.17 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:26 PM PST 24
Peak memory 198080 kb
Host smart-3bf1d778-7615-4ff9-a301-63b9fe6172d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354988215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3354988215
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2896489669
Short name T214
Test name
Test status
Simulation time 103149775298 ps
CPU time 203.23 seconds
Started Feb 25 01:37:14 PM PST 24
Finished Feb 25 01:40:38 PM PST 24
Peak memory 199660 kb
Host smart-c01695eb-d486-4c3b-a701-e6e46e01931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896489669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2896489669
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2089335085
Short name T976
Test name
Test status
Simulation time 21751588 ps
CPU time 0.57 seconds
Started Feb 25 01:37:29 PM PST 24
Finished Feb 25 01:37:29 PM PST 24
Peak memory 195100 kb
Host smart-477eb2fa-9d97-410d-9fdd-31b8f2fdf258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089335085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2089335085
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2348237198
Short name T824
Test name
Test status
Simulation time 23149403068 ps
CPU time 48.47 seconds
Started Feb 25 01:37:27 PM PST 24
Finished Feb 25 01:38:17 PM PST 24
Peak memory 199536 kb
Host smart-f18b6f12-86e2-4c1c-80bc-4e8414227e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348237198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2348237198
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3981816094
Short name T306
Test name
Test status
Simulation time 44865574870 ps
CPU time 35.88 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:58 PM PST 24
Peak memory 199580 kb
Host smart-650375d1-3d63-4bc1-a01d-c3ef096c4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981816094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3981816094
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2499810210
Short name T194
Test name
Test status
Simulation time 112346872979 ps
CPU time 46.66 seconds
Started Feb 25 01:37:22 PM PST 24
Finished Feb 25 01:38:09 PM PST 24
Peak memory 199704 kb
Host smart-b9b26214-4051-4acc-ae07-7c3fcc9acdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499810210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2499810210
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1308851355
Short name T753
Test name
Test status
Simulation time 70504503825 ps
CPU time 140.4 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:39:42 PM PST 24
Peak memory 199620 kb
Host smart-54d0d998-5bb0-4f49-99ca-263faa15b15b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308851355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1308851355
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3660712038
Short name T828
Test name
Test status
Simulation time 95505748940 ps
CPU time 549.38 seconds
Started Feb 25 01:37:22 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 199648 kb
Host smart-b894af29-abb2-42d0-8300-d1e13e4a74c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660712038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3660712038
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2588775974
Short name T1012
Test name
Test status
Simulation time 134788126 ps
CPU time 1 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:24 PM PST 24
Peak memory 197488 kb
Host smart-ebfe70d9-7c3f-4def-8a7f-2746d468f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588775974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2588775974
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1665607354
Short name T748
Test name
Test status
Simulation time 29314410354 ps
CPU time 51.86 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:38:14 PM PST 24
Peak memory 196520 kb
Host smart-e878d605-a265-4af6-b385-b0fb633950c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665607354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1665607354
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.4042470666
Short name T1050
Test name
Test status
Simulation time 21940081521 ps
CPU time 280.79 seconds
Started Feb 25 01:37:19 PM PST 24
Finished Feb 25 01:42:03 PM PST 24
Peak memory 199636 kb
Host smart-6ce8da24-2bc3-4b74-94ef-69482bf3f9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042470666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4042470666
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4136313658
Short name T18
Test name
Test status
Simulation time 3395794830 ps
CPU time 7.32 seconds
Started Feb 25 01:37:25 PM PST 24
Finished Feb 25 01:37:33 PM PST 24
Peak memory 198196 kb
Host smart-cd80fd10-1b95-4223-81a8-a899fa3ac2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136313658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4136313658
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.981305960
Short name T592
Test name
Test status
Simulation time 16401711333 ps
CPU time 6.59 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:37:28 PM PST 24
Peak memory 198936 kb
Host smart-3fa493bf-ac05-476b-84b2-cebd55b3c583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981305960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.981305960
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1663891830
Short name T819
Test name
Test status
Simulation time 549964212 ps
CPU time 1.57 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:23 PM PST 24
Peak memory 195024 kb
Host smart-4651c10b-4058-4a55-b9cc-9b281d1ab099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663891830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1663891830
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.801222708
Short name T968
Test name
Test status
Simulation time 286595327 ps
CPU time 1.39 seconds
Started Feb 25 01:37:23 PM PST 24
Finished Feb 25 01:37:25 PM PST 24
Peak memory 197908 kb
Host smart-69adfa5f-fadc-4b54-8eec-9280cc460e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801222708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.801222708
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3719960770
Short name T470
Test name
Test status
Simulation time 28236911643 ps
CPU time 331.33 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 213940 kb
Host smart-e036b009-fbff-4405-9877-516bc5400105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719960770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3719960770
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2716319774
Short name T501
Test name
Test status
Simulation time 6766392414 ps
CPU time 20.64 seconds
Started Feb 25 01:37:20 PM PST 24
Finished Feb 25 01:37:42 PM PST 24
Peak memory 199188 kb
Host smart-7f7031a6-44fd-4290-aac1-59b28b47472c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716319774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2716319774
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1317254982
Short name T56
Test name
Test status
Simulation time 140639322892 ps
CPU time 28.09 seconds
Started Feb 25 01:37:21 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 199644 kb
Host smart-a3b9f7f3-730a-43e7-95a8-228aa77747e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317254982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1317254982
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2616435651
Short name T491
Test name
Test status
Simulation time 19507877 ps
CPU time 0.56 seconds
Started Feb 25 01:37:30 PM PST 24
Finished Feb 25 01:37:31 PM PST 24
Peak memory 195036 kb
Host smart-720d71f5-5a70-413f-895e-82b89e784b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616435651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2616435651
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1733698234
Short name T1003
Test name
Test status
Simulation time 59026234270 ps
CPU time 47.82 seconds
Started Feb 25 01:37:29 PM PST 24
Finished Feb 25 01:38:17 PM PST 24
Peak memory 199360 kb
Host smart-be2a59f4-b4df-4d45-ace7-2eec29b79ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733698234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1733698234
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1189089999
Short name T340
Test name
Test status
Simulation time 237049461317 ps
CPU time 614.67 seconds
Started Feb 25 01:37:37 PM PST 24
Finished Feb 25 01:47:52 PM PST 24
Peak memory 199644 kb
Host smart-76c94630-f38c-4763-a207-3e589e55cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189089999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1189089999
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.2115683503
Short name T125
Test name
Test status
Simulation time 42897711972 ps
CPU time 81.37 seconds
Started Feb 25 01:37:32 PM PST 24
Finished Feb 25 01:38:54 PM PST 24
Peak memory 199528 kb
Host smart-d94ee739-4833-4869-93f7-12071aad4d53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115683503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2115683503
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2361297058
Short name T597
Test name
Test status
Simulation time 46801975766 ps
CPU time 223.76 seconds
Started Feb 25 01:37:37 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 199652 kb
Host smart-9f22fee4-1b4f-41ea-8de5-03d92ea4217a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361297058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2361297058
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.521045647
Short name T1078
Test name
Test status
Simulation time 6764971144 ps
CPU time 9.63 seconds
Started Feb 25 01:37:31 PM PST 24
Finished Feb 25 01:37:40 PM PST 24
Peak memory 198696 kb
Host smart-e72f3f6d-eb98-4d2b-9cc5-7869882c570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521045647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.521045647
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.589335657
Short name T933
Test name
Test status
Simulation time 148562351694 ps
CPU time 19.03 seconds
Started Feb 25 01:37:32 PM PST 24
Finished Feb 25 01:37:51 PM PST 24
Peak memory 195632 kb
Host smart-79d1f408-713f-4d9f-80b6-7cf69a73e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589335657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.589335657
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1290750355
Short name T898
Test name
Test status
Simulation time 12380340190 ps
CPU time 179.42 seconds
Started Feb 25 01:37:31 PM PST 24
Finished Feb 25 01:40:30 PM PST 24
Peak memory 199504 kb
Host smart-aab4d9f0-3659-4bfe-bfee-f9d69b8b794b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290750355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1290750355
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1746326296
Short name T19
Test name
Test status
Simulation time 6620484326 ps
CPU time 37.9 seconds
Started Feb 25 01:37:28 PM PST 24
Finished Feb 25 01:38:07 PM PST 24
Peak memory 197888 kb
Host smart-8fb44553-f33e-40e7-a123-6df7996078ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746326296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1746326296
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.369324044
Short name T545
Test name
Test status
Simulation time 174618045544 ps
CPU time 85.49 seconds
Started Feb 25 01:37:28 PM PST 24
Finished Feb 25 01:38:54 PM PST 24
Peak memory 199624 kb
Host smart-9cc81b1d-09d7-4101-9df8-6b87736bd9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369324044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.369324044
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2796859563
Short name T436
Test name
Test status
Simulation time 1685412838 ps
CPU time 3.42 seconds
Started Feb 25 01:37:34 PM PST 24
Finished Feb 25 01:37:38 PM PST 24
Peak memory 195108 kb
Host smart-b70db2a1-e829-4c64-8ea4-6e07d825c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796859563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2796859563
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.901296906
Short name T707
Test name
Test status
Simulation time 6105697885 ps
CPU time 7.6 seconds
Started Feb 25 01:37:37 PM PST 24
Finished Feb 25 01:37:45 PM PST 24
Peak memory 198948 kb
Host smart-3bd1a711-ee29-44e8-9582-826d113f8f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901296906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.901296906
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.890348199
Short name T168
Test name
Test status
Simulation time 110936965257 ps
CPU time 107.16 seconds
Started Feb 25 01:37:27 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 208220 kb
Host smart-4d43e45b-9820-4dc5-8d73-671d85d24811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890348199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.890348199
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.48019037
Short name T433
Test name
Test status
Simulation time 998251215 ps
CPU time 1.91 seconds
Started Feb 25 01:37:27 PM PST 24
Finished Feb 25 01:37:31 PM PST 24
Peak memory 197792 kb
Host smart-b57bccea-0147-4f12-83c1-42f74208f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48019037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.48019037
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.20319865
Short name T560
Test name
Test status
Simulation time 69416375928 ps
CPU time 75.9 seconds
Started Feb 25 01:37:32 PM PST 24
Finished Feb 25 01:38:48 PM PST 24
Peak memory 199560 kb
Host smart-f20ca409-ed89-4850-8a54-590c6a894c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20319865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.20319865
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1593269397
Short name T694
Test name
Test status
Simulation time 18685471 ps
CPU time 0.55 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 195108 kb
Host smart-d0e773a6-3584-492c-b943-09e7935ff697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593269397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1593269397
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3708542472
Short name T1061
Test name
Test status
Simulation time 17219207987 ps
CPU time 25.5 seconds
Started Feb 25 01:37:36 PM PST 24
Finished Feb 25 01:38:01 PM PST 24
Peak memory 199700 kb
Host smart-49e9b342-6fb3-467a-896a-326d3ae717c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708542472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3708542472
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3749910913
Short name T843
Test name
Test status
Simulation time 92341479145 ps
CPU time 141.84 seconds
Started Feb 25 01:37:39 PM PST 24
Finished Feb 25 01:40:01 PM PST 24
Peak memory 198964 kb
Host smart-55b2b11a-f1e2-481b-938e-e29c80364c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749910913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3749910913
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.337705690
Short name T146
Test name
Test status
Simulation time 68823635793 ps
CPU time 29.89 seconds
Started Feb 25 01:37:40 PM PST 24
Finished Feb 25 01:38:10 PM PST 24
Peak memory 199704 kb
Host smart-213f7661-6d8c-48bd-bb03-ee468f1865a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337705690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.337705690
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3813300660
Short name T248
Test name
Test status
Simulation time 477952288801 ps
CPU time 205.27 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:41:04 PM PST 24
Peak memory 199348 kb
Host smart-931e4c57-9ac2-45e1-95b7-da550c83ac7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813300660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3813300660
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1558142262
Short name T715
Test name
Test status
Simulation time 96225439482 ps
CPU time 366.3 seconds
Started Feb 25 01:37:43 PM PST 24
Finished Feb 25 01:43:49 PM PST 24
Peak memory 199720 kb
Host smart-b62b83c8-e4f6-489e-af0d-6a0f84c264bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558142262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1558142262
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2808743862
Short name T222
Test name
Test status
Simulation time 63008363728 ps
CPU time 25.29 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:38:03 PM PST 24
Peak memory 199812 kb
Host smart-87367692-7bb3-4dcf-b089-02a9a975e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808743862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2808743862
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.537404506
Short name T291
Test name
Test status
Simulation time 12610735256 ps
CPU time 32.32 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:38:10 PM PST 24
Peak memory 199628 kb
Host smart-0d1867f2-d92c-4877-ae8e-cdc6c5d37b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537404506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.537404506
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2575196806
Short name T1021
Test name
Test status
Simulation time 2261219620 ps
CPU time 6.78 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:37:56 PM PST 24
Peak memory 197656 kb
Host smart-da955ed2-8e93-42f9-a99d-02ede0bbc4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575196806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2575196806
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2580321813
Short name T917
Test name
Test status
Simulation time 140783879276 ps
CPU time 85.95 seconds
Started Feb 25 01:37:41 PM PST 24
Finished Feb 25 01:39:07 PM PST 24
Peak memory 199584 kb
Host smart-87d112f6-364b-4fcc-b2d1-3f4ccb54179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580321813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2580321813
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.691727842
Short name T426
Test name
Test status
Simulation time 3528779630 ps
CPU time 3.35 seconds
Started Feb 25 01:37:37 PM PST 24
Finished Feb 25 01:37:41 PM PST 24
Peak memory 195316 kb
Host smart-8f091fb6-df96-4604-856f-3bce94117f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691727842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.691727842
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1600913868
Short name T542
Test name
Test status
Simulation time 5284834500 ps
CPU time 20.27 seconds
Started Feb 25 01:37:36 PM PST 24
Finished Feb 25 01:37:57 PM PST 24
Peak memory 198196 kb
Host smart-cc5d3861-5f8a-4027-a4ed-bcf664f702fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600913868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1600913868
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3204826714
Short name T342
Test name
Test status
Simulation time 291076073743 ps
CPU time 251.04 seconds
Started Feb 25 01:37:40 PM PST 24
Finished Feb 25 01:41:51 PM PST 24
Peak memory 199676 kb
Host smart-9aff6f21-fc6f-41ac-a17c-5079270d0c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204826714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3204826714
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.460891492
Short name T70
Test name
Test status
Simulation time 318252166852 ps
CPU time 1139.52 seconds
Started Feb 25 01:37:39 PM PST 24
Finished Feb 25 01:56:39 PM PST 24
Peak memory 224400 kb
Host smart-239eeea0-3b90-4fcc-ab79-0a15324f3371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460891492 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.460891492
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2428403346
Short name T623
Test name
Test status
Simulation time 1020555445 ps
CPU time 3.16 seconds
Started Feb 25 01:37:39 PM PST 24
Finished Feb 25 01:37:42 PM PST 24
Peak memory 198084 kb
Host smart-b01e07e5-3a94-4a23-bc5a-03779bdd8b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428403346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2428403346
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.537931298
Short name T646
Test name
Test status
Simulation time 94145246039 ps
CPU time 128.03 seconds
Started Feb 25 01:37:35 PM PST 24
Finished Feb 25 01:39:43 PM PST 24
Peak memory 199640 kb
Host smart-8e37efa1-f162-49e7-ab66-0e44e4208d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537931298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.537931298
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2936165748
Short name T652
Test name
Test status
Simulation time 33609089 ps
CPU time 0.55 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 194112 kb
Host smart-5e5f60b5-676a-42ae-aa6b-118ef0ca04d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936165748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2936165748
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2413306908
Short name T644
Test name
Test status
Simulation time 25207652500 ps
CPU time 34.13 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:38:23 PM PST 24
Peak memory 199616 kb
Host smart-a1f68725-8898-473f-8aea-b7f44ea86cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413306908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2413306908
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.3053682724
Short name T941
Test name
Test status
Simulation time 277097939818 ps
CPU time 426.46 seconds
Started Feb 25 01:37:39 PM PST 24
Finished Feb 25 01:44:46 PM PST 24
Peak memory 196256 kb
Host smart-10baf0f6-c11b-46cb-8686-ec1754e97d11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053682724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3053682724
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1287707431
Short name T414
Test name
Test status
Simulation time 163945249685 ps
CPU time 880.55 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:52:31 PM PST 24
Peak memory 199716 kb
Host smart-3e1bef53-2b4e-425f-bce9-7fc7753aa23b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287707431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1287707431
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.609676036
Short name T493
Test name
Test status
Simulation time 9862658823 ps
CPU time 9.33 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:37:58 PM PST 24
Peak memory 198224 kb
Host smart-0a7c34fb-50a7-4bc5-9faa-33a24ee7b910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609676036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.609676036
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3865548164
Short name T1097
Test name
Test status
Simulation time 182644457910 ps
CPU time 170.98 seconds
Started Feb 25 01:37:37 PM PST 24
Finished Feb 25 01:40:28 PM PST 24
Peak memory 199820 kb
Host smart-2c90e98a-a825-4bf5-bcab-8b820bfdf26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865548164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3865548164
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3403576373
Short name T485
Test name
Test status
Simulation time 1839059172 ps
CPU time 12.56 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:37:51 PM PST 24
Peak memory 197720 kb
Host smart-915addda-e8b5-40e2-b4cd-c435356f6b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403576373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3403576373
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3242208960
Short name T375
Test name
Test status
Simulation time 13658163069 ps
CPU time 22.6 seconds
Started Feb 25 01:37:51 PM PST 24
Finished Feb 25 01:38:13 PM PST 24
Peak memory 197256 kb
Host smart-1e364306-0c90-44ac-bdaa-658431af071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242208960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3242208960
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1900613407
Short name T438
Test name
Test status
Simulation time 709638246 ps
CPU time 1.82 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:37:52 PM PST 24
Peak memory 194912 kb
Host smart-e1d1016b-aecf-46bb-beee-fcbcbee5dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900613407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1900613407
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3761148159
Short name T447
Test name
Test status
Simulation time 293850427 ps
CPU time 1.51 seconds
Started Feb 25 01:37:38 PM PST 24
Finished Feb 25 01:37:40 PM PST 24
Peak memory 197832 kb
Host smart-9b4ac4a2-3736-49a7-b7cf-3c030df45d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761148159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3761148159
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4200153778
Short name T1006
Test name
Test status
Simulation time 875002022 ps
CPU time 2.05 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:37:51 PM PST 24
Peak memory 197580 kb
Host smart-d8022e61-be6d-41ed-a638-ae99bbcfea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200153778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4200153778
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2051009156
Short name T246
Test name
Test status
Simulation time 68693093298 ps
CPU time 113.76 seconds
Started Feb 25 01:37:40 PM PST 24
Finished Feb 25 01:39:34 PM PST 24
Peak memory 199580 kb
Host smart-e7af3e5a-9b21-4a7e-8633-eb2e7a823a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051009156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2051009156
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2180522193
Short name T6
Test name
Test status
Simulation time 164054662 ps
CPU time 0.57 seconds
Started Feb 25 01:38:03 PM PST 24
Finished Feb 25 01:38:03 PM PST 24
Peak memory 195024 kb
Host smart-7b7e871e-3eb2-4239-9e63-16fc4db4b49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180522193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2180522193
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3341751565
Short name T275
Test name
Test status
Simulation time 19006314368 ps
CPU time 30.8 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:38:21 PM PST 24
Peak memory 199628 kb
Host smart-6b558c1f-bd98-4422-907c-34bd04d3f806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341751565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3341751565
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4270653053
Short name T951
Test name
Test status
Simulation time 38255012542 ps
CPU time 62.62 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:38:52 PM PST 24
Peak memory 199060 kb
Host smart-cac96b76-04c7-4b78-97c3-3e82483d443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270653053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4270653053
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1147974806
Short name T1040
Test name
Test status
Simulation time 22831561104 ps
CPU time 11.03 seconds
Started Feb 25 01:37:49 PM PST 24
Finished Feb 25 01:38:00 PM PST 24
Peak memory 199472 kb
Host smart-9f1f370a-761e-4442-8d9b-048c8084d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147974806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1147974806
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1272338720
Short name T980
Test name
Test status
Simulation time 677686743648 ps
CPU time 436.88 seconds
Started Feb 25 01:37:51 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 198068 kb
Host smart-46e6d3a5-710c-4122-ad17-27a34da98ded
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272338720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1272338720
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.334962481
Short name T1088
Test name
Test status
Simulation time 131130858697 ps
CPU time 489.39 seconds
Started Feb 25 01:38:02 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 199652 kb
Host smart-59017bd2-8788-4e80-837b-85d4d9b28d63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334962481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.334962481
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1789584643
Short name T482
Test name
Test status
Simulation time 5571864252 ps
CPU time 3.97 seconds
Started Feb 25 01:37:55 PM PST 24
Finished Feb 25 01:37:59 PM PST 24
Peak memory 198952 kb
Host smart-8212b0b3-aa05-4154-a44d-932a785ad984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789584643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1789584643
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2989833632
Short name T513
Test name
Test status
Simulation time 20980536551 ps
CPU time 31.9 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:38:22 PM PST 24
Peak memory 196260 kb
Host smart-fc91eaeb-dba7-445c-9072-1a86d35bbbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989833632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2989833632
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.581816612
Short name T751
Test name
Test status
Simulation time 10482793222 ps
CPU time 518.96 seconds
Started Feb 25 01:37:56 PM PST 24
Finished Feb 25 01:46:35 PM PST 24
Peak memory 199620 kb
Host smart-a644d216-cea1-4b71-a8dc-dfff473cbab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581816612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.581816612
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2656893922
Short name T945
Test name
Test status
Simulation time 2396799966 ps
CPU time 14.1 seconds
Started Feb 25 01:37:50 PM PST 24
Finished Feb 25 01:38:04 PM PST 24
Peak memory 198156 kb
Host smart-d605f5a4-4409-435c-b452-0458b2462ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656893922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2656893922
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4023171353
Short name T387
Test name
Test status
Simulation time 119967404331 ps
CPU time 160.34 seconds
Started Feb 25 01:37:54 PM PST 24
Finished Feb 25 01:40:34 PM PST 24
Peak memory 199608 kb
Host smart-90dcefa6-0a7f-49cd-9843-6612be570acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023171353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4023171353
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.450541725
Short name T842
Test name
Test status
Simulation time 4547102456 ps
CPU time 1.78 seconds
Started Feb 25 01:37:48 PM PST 24
Finished Feb 25 01:37:50 PM PST 24
Peak memory 195376 kb
Host smart-e3a12ebf-b983-4866-a971-ac70d0b312ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450541725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.450541725
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.778171910
Short name T52
Test name
Test status
Simulation time 149753675 ps
CPU time 0.78 seconds
Started Feb 25 01:37:56 PM PST 24
Finished Feb 25 01:37:57 PM PST 24
Peak memory 197232 kb
Host smart-09923fa3-a431-4061-b04f-5c83d7e79aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778171910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.778171910
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3221244213
Short name T1064
Test name
Test status
Simulation time 325850249407 ps
CPU time 484.61 seconds
Started Feb 25 01:38:03 PM PST 24
Finished Feb 25 01:46:08 PM PST 24
Peak memory 208056 kb
Host smart-39d52ba5-7b50-4035-86a6-72c573cd4f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221244213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3221244213
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.915653569
Short name T26
Test name
Test status
Simulation time 896857268 ps
CPU time 2.31 seconds
Started Feb 25 01:37:51 PM PST 24
Finished Feb 25 01:37:53 PM PST 24
Peak memory 197204 kb
Host smart-bbf67ba5-dfdc-4c14-ac41-d35182ba11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915653569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.915653569
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.500130685
Short name T454
Test name
Test status
Simulation time 38473341667 ps
CPU time 67.04 seconds
Started Feb 25 01:37:55 PM PST 24
Finished Feb 25 01:39:02 PM PST 24
Peak memory 199620 kb
Host smart-e8a449d6-f9a4-4a1f-ae6c-7b5e93962f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500130685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.500130685
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.879459781
Short name T544
Test name
Test status
Simulation time 40508337 ps
CPU time 0.56 seconds
Started Feb 25 01:38:09 PM PST 24
Finished Feb 25 01:38:11 PM PST 24
Peak memory 195092 kb
Host smart-3544415b-ee4c-4177-b3f6-ad0710af4eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879459781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.879459781
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3056235024
Short name T678
Test name
Test status
Simulation time 136129966809 ps
CPU time 74.12 seconds
Started Feb 25 01:38:02 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 199604 kb
Host smart-1957b8cd-2e11-4a38-9f99-9055eba93de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056235024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3056235024
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1585115100
Short name T1070
Test name
Test status
Simulation time 188238036969 ps
CPU time 269.93 seconds
Started Feb 25 01:38:08 PM PST 24
Finished Feb 25 01:42:38 PM PST 24
Peak memory 199548 kb
Host smart-d5cb66cd-8701-4bd2-8d34-4cd7260f1c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585115100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1585115100
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4089244091
Short name T361
Test name
Test status
Simulation time 108749976318 ps
CPU time 82.53 seconds
Started Feb 25 01:38:03 PM PST 24
Finished Feb 25 01:39:26 PM PST 24
Peak memory 199620 kb
Host smart-6b9f6453-560c-4ae7-af44-ec49edaa8aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089244091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4089244091
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1319874786
Short name T957
Test name
Test status
Simulation time 13521139857 ps
CPU time 3.08 seconds
Started Feb 25 01:38:04 PM PST 24
Finished Feb 25 01:38:07 PM PST 24
Peak memory 196116 kb
Host smart-499d66b4-a1c8-4a3f-87a0-14a81f48d0df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319874786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1319874786
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3893060939
Short name T918
Test name
Test status
Simulation time 75657512082 ps
CPU time 233.3 seconds
Started Feb 25 01:38:10 PM PST 24
Finished Feb 25 01:42:03 PM PST 24
Peak memory 199532 kb
Host smart-457834db-0d57-4d35-bf4b-84dd2eb4e610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893060939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3893060939
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1721224445
Short name T50
Test name
Test status
Simulation time 64770956789 ps
CPU time 18.04 seconds
Started Feb 25 01:38:02 PM PST 24
Finished Feb 25 01:38:20 PM PST 24
Peak memory 197832 kb
Host smart-3e50a003-ef96-48fc-8760-21919f55b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721224445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1721224445
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1247963964
Short name T840
Test name
Test status
Simulation time 22304875440 ps
CPU time 244.93 seconds
Started Feb 25 01:38:06 PM PST 24
Finished Feb 25 01:42:11 PM PST 24
Peak memory 199620 kb
Host smart-012d07c6-a56a-4d50-9282-628b338f9952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247963964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1247963964
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1220188844
Short name T726
Test name
Test status
Simulation time 2256574489 ps
CPU time 2.6 seconds
Started Feb 25 01:38:04 PM PST 24
Finished Feb 25 01:38:07 PM PST 24
Peak memory 195192 kb
Host smart-2be5535b-fb2e-4841-8c91-caec5a96a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220188844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1220188844
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.273011223
Short name T503
Test name
Test status
Simulation time 957447819 ps
CPU time 2.28 seconds
Started Feb 25 01:38:01 PM PST 24
Finished Feb 25 01:38:03 PM PST 24
Peak memory 198036 kb
Host smart-054ed51f-8f70-4ec7-b52b-321a9f034ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273011223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.273011223
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3154383407
Short name T166
Test name
Test status
Simulation time 85020461833 ps
CPU time 76.37 seconds
Started Feb 25 01:38:12 PM PST 24
Finished Feb 25 01:39:29 PM PST 24
Peak memory 198044 kb
Host smart-3e69ee5a-e58e-411e-aca1-d6bcb483669d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154383407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3154383407
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.44660754
Short name T899
Test name
Test status
Simulation time 1352386072 ps
CPU time 2 seconds
Started Feb 25 01:38:04 PM PST 24
Finished Feb 25 01:38:06 PM PST 24
Peak memory 197992 kb
Host smart-8633426e-3044-4d92-8131-c1945cb75755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44660754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.44660754
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.54387535
Short name T188
Test name
Test status
Simulation time 46062099688 ps
CPU time 47.94 seconds
Started Feb 25 01:38:04 PM PST 24
Finished Feb 25 01:38:52 PM PST 24
Peak memory 199536 kb
Host smart-6a894c75-e18d-4ba1-9695-e18ccc5eff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54387535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.54387535
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.735502639
Short name T1083
Test name
Test status
Simulation time 44498065 ps
CPU time 0.55 seconds
Started Feb 25 01:38:15 PM PST 24
Finished Feb 25 01:38:16 PM PST 24
Peak memory 195076 kb
Host smart-4682dbf0-7a70-48ac-8305-cfd3dd60d311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735502639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.735502639
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3896654124
Short name T766
Test name
Test status
Simulation time 150669005358 ps
CPU time 113.28 seconds
Started Feb 25 01:38:15 PM PST 24
Finished Feb 25 01:40:08 PM PST 24
Peak memory 198856 kb
Host smart-196005e2-327c-4684-860a-8aaaabce0f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896654124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3896654124
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1333299096
Short name T999
Test name
Test status
Simulation time 173040112007 ps
CPU time 116 seconds
Started Feb 25 01:38:08 PM PST 24
Finished Feb 25 01:40:04 PM PST 24
Peak memory 199428 kb
Host smart-30b11c3d-f7c4-4c54-b194-d3810d0da05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333299096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1333299096
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3676058048
Short name T669
Test name
Test status
Simulation time 72974842782 ps
CPU time 427.65 seconds
Started Feb 25 01:38:12 PM PST 24
Finished Feb 25 01:45:20 PM PST 24
Peak memory 199628 kb
Host smart-5d4f93ac-da02-44a3-be86-2ea8d15f40ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676058048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3676058048
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1028961234
Short name T509
Test name
Test status
Simulation time 173634979715 ps
CPU time 255.8 seconds
Started Feb 25 01:38:08 PM PST 24
Finished Feb 25 01:42:24 PM PST 24
Peak memory 198688 kb
Host smart-cfd1b742-2186-4a76-aed1-0ddb8b3ac38a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028961234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1028961234
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2710912624
Short name T423
Test name
Test status
Simulation time 114632314706 ps
CPU time 1089.64 seconds
Started Feb 25 01:38:07 PM PST 24
Finished Feb 25 01:56:17 PM PST 24
Peak memory 199716 kb
Host smart-988dfeee-52cf-4504-ac9b-0271b393607e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710912624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2710912624
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3376185871
Short name T666
Test name
Test status
Simulation time 8593297916 ps
CPU time 4.57 seconds
Started Feb 25 01:38:10 PM PST 24
Finished Feb 25 01:38:15 PM PST 24
Peak memory 198360 kb
Host smart-21cabcca-08fc-439d-9f44-737af060a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376185871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3376185871
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.674651794
Short name T630
Test name
Test status
Simulation time 64286257091 ps
CPU time 156.24 seconds
Started Feb 25 01:38:09 PM PST 24
Finished Feb 25 01:40:46 PM PST 24
Peak memory 198080 kb
Host smart-3628d2c0-331a-4c4b-96e1-784016fb6cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674651794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.674651794
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3566924237
Short name T714
Test name
Test status
Simulation time 22483182240 ps
CPU time 335.89 seconds
Started Feb 25 01:38:11 PM PST 24
Finished Feb 25 01:43:47 PM PST 24
Peak memory 199620 kb
Host smart-2b8d416b-e3b4-4c06-92fa-5ed9bdb99368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566924237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3566924237
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3771201619
Short name T676
Test name
Test status
Simulation time 2060761690 ps
CPU time 8.64 seconds
Started Feb 25 01:38:10 PM PST 24
Finished Feb 25 01:38:19 PM PST 24
Peak memory 197280 kb
Host smart-30d8c6ef-5e2c-499e-964c-aeca67bf686c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771201619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3771201619
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3735041914
Short name T456
Test name
Test status
Simulation time 74337669723 ps
CPU time 28.43 seconds
Started Feb 25 01:38:08 PM PST 24
Finished Feb 25 01:38:36 PM PST 24
Peak memory 199148 kb
Host smart-5aefdba8-1dd1-43b0-9c00-c972f74ba710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735041914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3735041914
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3932849281
Short name T992
Test name
Test status
Simulation time 4214678554 ps
CPU time 2.18 seconds
Started Feb 25 01:38:15 PM PST 24
Finished Feb 25 01:38:18 PM PST 24
Peak memory 195360 kb
Host smart-676b40f0-8080-420f-aae1-bb0d374cd94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932849281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3932849281
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1981514557
Short name T460
Test name
Test status
Simulation time 10545512004 ps
CPU time 15.05 seconds
Started Feb 25 01:38:13 PM PST 24
Finished Feb 25 01:38:28 PM PST 24
Peak memory 199236 kb
Host smart-68d58306-2778-4b20-ab30-e5a2cd7b3b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981514557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1981514557
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.4242948299
Short name T383
Test name
Test status
Simulation time 243837917091 ps
CPU time 511.38 seconds
Started Feb 25 01:38:12 PM PST 24
Finished Feb 25 01:46:44 PM PST 24
Peak memory 199520 kb
Host smart-9f91174d-a16e-4492-9ec8-18227393c679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242948299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.4242948299
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3375612711
Short name T1098
Test name
Test status
Simulation time 49514844843 ps
CPU time 235.4 seconds
Started Feb 25 01:38:07 PM PST 24
Finished Feb 25 01:42:02 PM PST 24
Peak memory 216124 kb
Host smart-13f36ef2-50a2-4766-84c3-b34dd87bac64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375612711 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3375612711
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2763148523
Short name T533
Test name
Test status
Simulation time 905073295 ps
CPU time 2.65 seconds
Started Feb 25 01:38:13 PM PST 24
Finished Feb 25 01:38:16 PM PST 24
Peak memory 197988 kb
Host smart-7a11ad74-2946-46bc-af31-c581cc44eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763148523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2763148523
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.520770992
Short name T659
Test name
Test status
Simulation time 30711639042 ps
CPU time 13.19 seconds
Started Feb 25 01:38:12 PM PST 24
Finished Feb 25 01:38:26 PM PST 24
Peak memory 199556 kb
Host smart-834453fb-8588-434a-933c-8911d080ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520770992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.520770992
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3603374156
Short name T962
Test name
Test status
Simulation time 17413699 ps
CPU time 0.56 seconds
Started Feb 25 01:32:45 PM PST 24
Finished Feb 25 01:32:46 PM PST 24
Peak memory 195096 kb
Host smart-75833478-f153-4cc4-bc08-df455aa3c462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603374156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3603374156
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.269879002
Short name T746
Test name
Test status
Simulation time 32450044711 ps
CPU time 48.04 seconds
Started Feb 25 01:32:50 PM PST 24
Finished Feb 25 01:33:38 PM PST 24
Peak memory 199332 kb
Host smart-dec1feb3-b98c-4446-aa3f-d111c147d616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269879002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.269879002
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3920433010
Short name T717
Test name
Test status
Simulation time 19757576620 ps
CPU time 31.07 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:33:09 PM PST 24
Peak memory 199616 kb
Host smart-8d8323c9-73d2-4bf6-8011-ae960739da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920433010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3920433010
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3936774095
Short name T257
Test name
Test status
Simulation time 96480097186 ps
CPU time 39.35 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:33:17 PM PST 24
Peak memory 199480 kb
Host smart-522424e9-2697-4752-b0be-cca59d005cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936774095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3936774095
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3146265868
Short name T628
Test name
Test status
Simulation time 262173595067 ps
CPU time 254.1 seconds
Started Feb 25 01:32:42 PM PST 24
Finished Feb 25 01:36:57 PM PST 24
Peak memory 199712 kb
Host smart-9694a992-233e-4ccb-bb75-9e9dd808690d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146265868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3146265868
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2520736120
Short name T1036
Test name
Test status
Simulation time 121247571007 ps
CPU time 635.49 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:43:32 PM PST 24
Peak memory 198312 kb
Host smart-2e69dbd8-a570-4ac3-8534-702d881e723e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520736120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2520736120
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1604091205
Short name T528
Test name
Test status
Simulation time 509536906 ps
CPU time 0.8 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:32:48 PM PST 24
Peak memory 195224 kb
Host smart-667932a7-6f56-4abe-8369-12d690606f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604091205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1604091205
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2475363864
Short name T750
Test name
Test status
Simulation time 21124744442 ps
CPU time 38.57 seconds
Started Feb 25 01:32:51 PM PST 24
Finished Feb 25 01:33:29 PM PST 24
Peak memory 198328 kb
Host smart-f7c49607-d028-4b2e-981c-ce6abbdc2b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475363864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2475363864
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1902851658
Short name T135
Test name
Test status
Simulation time 27035848525 ps
CPU time 332.91 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:38:29 PM PST 24
Peak memory 199516 kb
Host smart-c4f2228a-a90e-4e52-873f-8bf53bc2135e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902851658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1902851658
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3725979406
Short name T982
Test name
Test status
Simulation time 2789704881 ps
CPU time 26.59 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:33:05 PM PST 24
Peak memory 198064 kb
Host smart-3cd022e1-200f-4d8b-ba68-a6d41d17e0c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725979406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3725979406
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2073003280
Short name T284
Test name
Test status
Simulation time 37089985864 ps
CPU time 15.8 seconds
Started Feb 25 01:32:45 PM PST 24
Finished Feb 25 01:33:01 PM PST 24
Peak memory 197616 kb
Host smart-692fe6ea-5c60-4710-8249-b094b370a031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073003280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2073003280
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.181959256
Short name T451
Test name
Test status
Simulation time 2026115248 ps
CPU time 3.68 seconds
Started Feb 25 01:32:48 PM PST 24
Finished Feb 25 01:32:52 PM PST 24
Peak memory 194956 kb
Host smart-15e762e0-0a17-4300-a097-9f901e10ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181959256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.181959256
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3012722078
Short name T432
Test name
Test status
Simulation time 283078530 ps
CPU time 1.44 seconds
Started Feb 25 01:32:44 PM PST 24
Finished Feb 25 01:32:46 PM PST 24
Peak memory 198392 kb
Host smart-3a3f7a34-62fe-46d7-b77a-ed92abd545fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012722078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3012722078
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2823773285
Short name T107
Test name
Test status
Simulation time 491873076 ps
CPU time 1.87 seconds
Started Feb 25 01:32:46 PM PST 24
Finished Feb 25 01:32:48 PM PST 24
Peak memory 197828 kb
Host smart-573875c7-888b-4d19-b93c-3973c72188cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823773285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2823773285
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.659488567
Short name T1015
Test name
Test status
Simulation time 55535753765 ps
CPU time 49.93 seconds
Started Feb 25 01:32:44 PM PST 24
Finished Feb 25 01:33:35 PM PST 24
Peak memory 199496 kb
Host smart-73aadf1e-7cc6-4d8f-9dea-3efab55a265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659488567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.659488567
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.10080953
Short name T253
Test name
Test status
Simulation time 133012257455 ps
CPU time 258.74 seconds
Started Feb 25 01:38:10 PM PST 24
Finished Feb 25 01:42:29 PM PST 24
Peak memory 199696 kb
Host smart-ce6f0a39-c3ff-4727-9b2e-567925ffce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10080953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.10080953
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1333748879
Short name T120
Test name
Test status
Simulation time 38441467663 ps
CPU time 316.22 seconds
Started Feb 25 01:38:08 PM PST 24
Finished Feb 25 01:43:24 PM PST 24
Peak memory 213240 kb
Host smart-a9098615-c6a9-4b6c-8b1f-4b5ec2d4d209
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333748879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1333748879
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2695537724
Short name T252
Test name
Test status
Simulation time 26456894079 ps
CPU time 40.6 seconds
Started Feb 25 01:38:09 PM PST 24
Finished Feb 25 01:38:51 PM PST 24
Peak memory 199620 kb
Host smart-01af4ffd-c016-429c-b359-87d130a9ff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695537724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2695537724
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1168031837
Short name T350
Test name
Test status
Simulation time 282538666552 ps
CPU time 722.43 seconds
Started Feb 25 01:38:11 PM PST 24
Finished Feb 25 01:50:13 PM PST 24
Peak memory 216120 kb
Host smart-66d618c0-9632-428d-ac84-21c5c52f7dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168031837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1168031837
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.70200595
Short name T393
Test name
Test status
Simulation time 60046268963 ps
CPU time 647.03 seconds
Started Feb 25 01:38:07 PM PST 24
Finished Feb 25 01:48:54 PM PST 24
Peak memory 215052 kb
Host smart-cd773900-9f2e-4f21-a9ae-f1802f793eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70200595 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.70200595
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3565260441
Short name T191
Test name
Test status
Simulation time 43264481409 ps
CPU time 17.38 seconds
Started Feb 25 01:38:19 PM PST 24
Finished Feb 25 01:38:37 PM PST 24
Peak memory 199600 kb
Host smart-3d459d74-21df-4453-adfd-3d04bc0da834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565260441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3565260441
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2472630578
Short name T1046
Test name
Test status
Simulation time 173324543716 ps
CPU time 756.45 seconds
Started Feb 25 01:38:21 PM PST 24
Finished Feb 25 01:50:58 PM PST 24
Peak memory 216304 kb
Host smart-ed633701-8e3c-4de0-9364-814ac07c3885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472630578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2472630578
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1668948124
Short name T1002
Test name
Test status
Simulation time 145545826561 ps
CPU time 64.9 seconds
Started Feb 25 01:38:19 PM PST 24
Finished Feb 25 01:39:25 PM PST 24
Peak memory 199632 kb
Host smart-9c6cabbb-17c8-47fe-9521-e23e0d02e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668948124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1668948124
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.21128192
Short name T1099
Test name
Test status
Simulation time 37694718202 ps
CPU time 58.73 seconds
Started Feb 25 01:38:20 PM PST 24
Finished Feb 25 01:39:20 PM PST 24
Peak memory 198896 kb
Host smart-3d02742e-8413-4bad-8979-8802b4a35353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21128192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.21128192
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.208048044
Short name T994
Test name
Test status
Simulation time 45970075527 ps
CPU time 44.08 seconds
Started Feb 25 01:38:18 PM PST 24
Finished Feb 25 01:39:03 PM PST 24
Peak memory 199588 kb
Host smart-fcf0242e-ab31-4dcc-ad9f-5595feda5d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208048044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.208048044
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.337857238
Short name T42
Test name
Test status
Simulation time 369628281078 ps
CPU time 516.19 seconds
Started Feb 25 01:38:19 PM PST 24
Finished Feb 25 01:46:56 PM PST 24
Peak memory 216328 kb
Host smart-859c47c0-a415-40ef-8f4f-fc47a1585e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337857238 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.337857238
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.970049755
Short name T322
Test name
Test status
Simulation time 120675839095 ps
CPU time 46.96 seconds
Started Feb 25 01:38:19 PM PST 24
Finished Feb 25 01:39:07 PM PST 24
Peak memory 199624 kb
Host smart-fe024f2c-dab4-4ef4-8494-be26d6489a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970049755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.970049755
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.887069647
Short name T244
Test name
Test status
Simulation time 30893516190 ps
CPU time 51.66 seconds
Started Feb 25 01:38:18 PM PST 24
Finished Feb 25 01:39:11 PM PST 24
Peak memory 199604 kb
Host smart-ede7d6f9-2dfa-4b72-ad03-c04140e2001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887069647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.887069647
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3633897242
Short name T111
Test name
Test status
Simulation time 16021904 ps
CPU time 0.56 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:32:57 PM PST 24
Peak memory 193888 kb
Host smart-438f069b-3157-42a3-a780-663289aa874c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633897242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3633897242
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1617778690
Short name T721
Test name
Test status
Simulation time 148839347349 ps
CPU time 45.62 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:33:33 PM PST 24
Peak memory 199352 kb
Host smart-bd6ef748-5ad8-4cad-abda-a4760861cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617778690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1617778690
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4075803280
Short name T988
Test name
Test status
Simulation time 77552126065 ps
CPU time 24.05 seconds
Started Feb 25 01:32:44 PM PST 24
Finished Feb 25 01:33:09 PM PST 24
Peak memory 198904 kb
Host smart-82573ae3-e7de-49ab-9996-37b752bc18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075803280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4075803280
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1599619874
Short name T581
Test name
Test status
Simulation time 59386694908 ps
CPU time 81.13 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:34:17 PM PST 24
Peak memory 199312 kb
Host smart-525f07a1-2b76-4462-8d12-830aca8b994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599619874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1599619874
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1482381935
Short name T858
Test name
Test status
Simulation time 389452252546 ps
CPU time 604.05 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 199612 kb
Host smart-6edb0aaf-512e-4b1d-ab78-29920ba53e7b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482381935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1482381935
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1322313321
Short name T685
Test name
Test status
Simulation time 324295013928 ps
CPU time 269.35 seconds
Started Feb 25 01:32:51 PM PST 24
Finished Feb 25 01:37:20 PM PST 24
Peak memory 199424 kb
Host smart-fb0b3517-364e-494e-9c6d-8eac76cbcbac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322313321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1322313321
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.591904041
Short name T596
Test name
Test status
Simulation time 9880310495 ps
CPU time 6.84 seconds
Started Feb 25 01:32:48 PM PST 24
Finished Feb 25 01:32:55 PM PST 24
Peak memory 198988 kb
Host smart-5608fd3e-aca5-4633-a593-636ae99cb1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591904041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.591904041
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4105753300
Short name T458
Test name
Test status
Simulation time 152216170537 ps
CPU time 85.48 seconds
Started Feb 25 01:32:46 PM PST 24
Finished Feb 25 01:34:12 PM PST 24
Peak memory 199828 kb
Host smart-5d6e06f7-592c-476e-991e-1a4993179f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105753300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4105753300
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.61794165
Short name T627
Test name
Test status
Simulation time 5760959449 ps
CPU time 272 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:37:19 PM PST 24
Peak memory 199616 kb
Host smart-cdefd7bc-1015-4fc7-8859-ef3724789a73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61794165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.61794165
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3570179010
Short name T811
Test name
Test status
Simulation time 161232640 ps
CPU time 0.74 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:32:50 PM PST 24
Peak memory 195036 kb
Host smart-7f291318-6cb6-4d57-9ce7-3e53eff87da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570179010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3570179010
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.900902553
Short name T762
Test name
Test status
Simulation time 2760335984 ps
CPU time 5.02 seconds
Started Feb 25 01:32:45 PM PST 24
Finished Feb 25 01:32:50 PM PST 24
Peak memory 195000 kb
Host smart-efaa9015-0eb2-4d80-89cd-ebf5678a6a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900902553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.900902553
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1009928011
Short name T723
Test name
Test status
Simulation time 6212306572 ps
CPU time 25.79 seconds
Started Feb 25 01:32:46 PM PST 24
Finished Feb 25 01:33:12 PM PST 24
Peak memory 198956 kb
Host smart-e813e30a-4ffa-4801-b0d0-98c9e15dd189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009928011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1009928011
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.650652701
Short name T971
Test name
Test status
Simulation time 567218145278 ps
CPU time 226.37 seconds
Started Feb 25 01:32:44 PM PST 24
Finished Feb 25 01:36:31 PM PST 24
Peak memory 207980 kb
Host smart-4207d6fe-c695-4fe5-9464-d1cf52581c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650652701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.650652701
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.57762040
Short name T529
Test name
Test status
Simulation time 420471472 ps
CPU time 1.91 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:32:58 PM PST 24
Peak memory 198032 kb
Host smart-3f87abd1-7128-40fc-b40c-1c627e733666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57762040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.57762040
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2228069115
Short name T455
Test name
Test status
Simulation time 65020932364 ps
CPU time 28.43 seconds
Started Feb 25 01:32:49 PM PST 24
Finished Feb 25 01:33:18 PM PST 24
Peak memory 197616 kb
Host smart-7ee9d77d-e08e-4b6b-a671-6259c10ead28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228069115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2228069115
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1957160175
Short name T406
Test name
Test status
Simulation time 66008385435 ps
CPU time 27.23 seconds
Started Feb 25 01:38:19 PM PST 24
Finished Feb 25 01:38:47 PM PST 24
Peak memory 199500 kb
Host smart-c38c2366-015b-45b0-bf24-f8185d5b6f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957160175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1957160175
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3392629928
Short name T287
Test name
Test status
Simulation time 15988481551 ps
CPU time 23.23 seconds
Started Feb 25 01:38:18 PM PST 24
Finished Feb 25 01:38:43 PM PST 24
Peak memory 198468 kb
Host smart-ed3e3139-0512-41c2-8e75-9c9a18ed4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392629928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3392629928
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1949711243
Short name T271
Test name
Test status
Simulation time 91239064055 ps
CPU time 39.76 seconds
Started Feb 25 01:38:20 PM PST 24
Finished Feb 25 01:39:01 PM PST 24
Peak memory 199464 kb
Host smart-ef0bed73-848a-493b-8079-b7c9ef529c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949711243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1949711243
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3427043763
Short name T67
Test name
Test status
Simulation time 119098684609 ps
CPU time 214.37 seconds
Started Feb 25 01:38:27 PM PST 24
Finished Feb 25 01:42:01 PM PST 24
Peak memory 216308 kb
Host smart-80a2ea5c-0ff4-4aa1-b471-8b1052d28da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427043763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3427043763
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2756373340
Short name T567
Test name
Test status
Simulation time 205307189901 ps
CPU time 53.98 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:39:21 PM PST 24
Peak memory 199424 kb
Host smart-a6c0042a-8dc4-4ac2-81ba-9cc1bc6c97ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756373340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2756373340
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1034407461
Short name T904
Test name
Test status
Simulation time 20418873755 ps
CPU time 34.84 seconds
Started Feb 25 01:38:29 PM PST 24
Finished Feb 25 01:39:04 PM PST 24
Peak memory 199636 kb
Host smart-c6bef60e-7163-4bfb-868f-ebb4dd6188f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034407461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1034407461
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1648449229
Short name T119
Test name
Test status
Simulation time 318482318359 ps
CPU time 764.75 seconds
Started Feb 25 01:38:28 PM PST 24
Finished Feb 25 01:51:13 PM PST 24
Peak memory 230832 kb
Host smart-ad06b093-3684-47a6-b24a-20c8d743da6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648449229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1648449229
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3143480260
Short name T336
Test name
Test status
Simulation time 151594865398 ps
CPU time 124.82 seconds
Started Feb 25 01:38:28 PM PST 24
Finished Feb 25 01:40:33 PM PST 24
Peak memory 199584 kb
Host smart-dd77437d-7c5b-4733-a828-eba704bd98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143480260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3143480260
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1807939826
Short name T269
Test name
Test status
Simulation time 93781954449 ps
CPU time 63.69 seconds
Started Feb 25 01:38:28 PM PST 24
Finished Feb 25 01:39:32 PM PST 24
Peak memory 199620 kb
Host smart-d301743d-b8af-418c-82ba-caa0b2db0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807939826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1807939826
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.168129582
Short name T984
Test name
Test status
Simulation time 47668283872 ps
CPU time 37.78 seconds
Started Feb 25 01:38:25 PM PST 24
Finished Feb 25 01:39:03 PM PST 24
Peak memory 199112 kb
Host smart-e14d5779-8a6f-4691-91ac-8c24df59032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168129582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.168129582
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1557503281
Short name T335
Test name
Test status
Simulation time 37072649007 ps
CPU time 19.43 seconds
Started Feb 25 01:38:27 PM PST 24
Finished Feb 25 01:38:46 PM PST 24
Peak memory 199624 kb
Host smart-be1725c2-cda7-4abf-a7f8-e9a8221b31b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557503281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1557503281
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2840078956
Short name T473
Test name
Test status
Simulation time 98711306016 ps
CPU time 592.84 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:48:19 PM PST 24
Peak memory 225476 kb
Host smart-451e302d-d787-4863-aa12-fed8f9c5c93d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840078956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2840078956
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2223790176
Short name T14
Test name
Test status
Simulation time 43719611884 ps
CPU time 65.51 seconds
Started Feb 25 01:38:27 PM PST 24
Finished Feb 25 01:39:33 PM PST 24
Peak memory 199600 kb
Host smart-4c0fb571-dce6-4f06-ac9f-32c32f43530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223790176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2223790176
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1479758101
Short name T1025
Test name
Test status
Simulation time 51382295 ps
CPU time 0.54 seconds
Started Feb 25 01:32:52 PM PST 24
Finished Feb 25 01:32:52 PM PST 24
Peak memory 194252 kb
Host smart-24613650-b72e-459b-837a-6901eced3148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479758101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1479758101
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2639062731
Short name T310
Test name
Test status
Simulation time 50350974053 ps
CPU time 18.34 seconds
Started Feb 25 01:32:45 PM PST 24
Finished Feb 25 01:33:04 PM PST 24
Peak memory 199660 kb
Host smart-c20641ba-dea2-44f5-9afe-bc4d2e0adf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639062731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2639062731
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4274361446
Short name T177
Test name
Test status
Simulation time 54658349563 ps
CPU time 99.82 seconds
Started Feb 25 01:33:00 PM PST 24
Finished Feb 25 01:34:40 PM PST 24
Peak memory 199488 kb
Host smart-61407fd3-bc00-4c34-a274-f256016e30a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274361446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4274361446
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.451914274
Short name T629
Test name
Test status
Simulation time 163701672229 ps
CPU time 79.58 seconds
Started Feb 25 01:32:53 PM PST 24
Finished Feb 25 01:34:13 PM PST 24
Peak memory 199696 kb
Host smart-2ffbbcfb-a748-4fb8-9a55-43722e9c57bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451914274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.451914274
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1083203815
Short name T636
Test name
Test status
Simulation time 147378569009 ps
CPU time 343.29 seconds
Started Feb 25 01:32:53 PM PST 24
Finished Feb 25 01:38:36 PM PST 24
Peak memory 199596 kb
Host smart-0c25cbc7-c3ed-44f3-918f-6ae4bd4e28be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083203815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1083203815
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.933011418
Short name T557
Test name
Test status
Simulation time 13811066062 ps
CPU time 6.91 seconds
Started Feb 25 01:33:00 PM PST 24
Finished Feb 25 01:33:07 PM PST 24
Peak memory 199140 kb
Host smart-b6fff31c-1a1b-4252-b50d-c31e16c29256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933011418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.933011418
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.866582602
Short name T617
Test name
Test status
Simulation time 93306827725 ps
CPU time 174.76 seconds
Started Feb 25 01:32:53 PM PST 24
Finished Feb 25 01:35:48 PM PST 24
Peak memory 199916 kb
Host smart-04ef4075-6172-4820-a8c2-c59b10634f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866582602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.866582602
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1943854618
Short name T303
Test name
Test status
Simulation time 12765139886 ps
CPU time 167.77 seconds
Started Feb 25 01:33:00 PM PST 24
Finished Feb 25 01:35:48 PM PST 24
Peak memory 199524 kb
Host smart-c4656d35-7b1a-46b8-9ab5-23c73a69ea2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943854618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1943854618
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3448073609
Short name T518
Test name
Test status
Simulation time 678894360 ps
CPU time 5.74 seconds
Started Feb 25 01:32:53 PM PST 24
Finished Feb 25 01:32:58 PM PST 24
Peak memory 197908 kb
Host smart-82a746cd-48ed-4f91-87f6-6d283022dad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448073609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3448073609
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1239989838
Short name T967
Test name
Test status
Simulation time 3457105495 ps
CPU time 6.16 seconds
Started Feb 25 01:32:59 PM PST 24
Finished Feb 25 01:33:05 PM PST 24
Peak memory 195456 kb
Host smart-2c2791c1-d95f-4a1b-a6dc-6be83799bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239989838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1239989838
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3689416005
Short name T457
Test name
Test status
Simulation time 5890467067 ps
CPU time 7.99 seconds
Started Feb 25 01:32:47 PM PST 24
Finished Feb 25 01:32:55 PM PST 24
Peak memory 199124 kb
Host smart-1b55ce36-4ca7-4667-9491-66583825655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689416005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3689416005
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2070260568
Short name T903
Test name
Test status
Simulation time 241409076818 ps
CPU time 579.05 seconds
Started Feb 25 01:32:54 PM PST 24
Finished Feb 25 01:42:33 PM PST 24
Peak memory 199576 kb
Host smart-856eba49-5140-4f59-8413-9e28bfe3fc24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070260568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2070260568
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3337823894
Short name T737
Test name
Test status
Simulation time 15917120979 ps
CPU time 92.71 seconds
Started Feb 25 01:32:56 PM PST 24
Finished Feb 25 01:34:29 PM PST 24
Peak memory 207892 kb
Host smart-8a57ed8a-2bf4-49a0-b4de-df2d8693f0f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337823894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3337823894
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2014257853
Short name T1076
Test name
Test status
Simulation time 2531132988 ps
CPU time 2.68 seconds
Started Feb 25 01:32:55 PM PST 24
Finished Feb 25 01:32:58 PM PST 24
Peak memory 198244 kb
Host smart-b3f9a8ea-2668-4e8b-9056-995ac3bda741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014257853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2014257853
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2925990543
Short name T734
Test name
Test status
Simulation time 77478898961 ps
CPU time 110.52 seconds
Started Feb 25 01:32:48 PM PST 24
Finished Feb 25 01:34:39 PM PST 24
Peak memory 199592 kb
Host smart-020fb7fb-8627-4836-ab87-e08eee889101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925990543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2925990543
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2627894416
Short name T588
Test name
Test status
Simulation time 5820697281 ps
CPU time 8 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:38:34 PM PST 24
Peak memory 196440 kb
Host smart-8f3b9261-ea19-4ba4-a287-6fbcde98b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627894416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2627894416
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.389593176
Short name T233
Test name
Test status
Simulation time 44448691848 ps
CPU time 74.64 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:39:41 PM PST 24
Peak memory 199636 kb
Host smart-ff0a3d56-8846-43f9-a61f-fb74aee6a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389593176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.389593176
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3101755895
Short name T796
Test name
Test status
Simulation time 151171532999 ps
CPU time 56.09 seconds
Started Feb 25 01:38:25 PM PST 24
Finished Feb 25 01:39:21 PM PST 24
Peak memory 199680 kb
Host smart-c931b437-e373-4aee-8217-5ecee3bca8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101755895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3101755895
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2429370746
Short name T974
Test name
Test status
Simulation time 212339235252 ps
CPU time 380.02 seconds
Started Feb 25 01:38:26 PM PST 24
Finished Feb 25 01:44:47 PM PST 24
Peak memory 199348 kb
Host smart-973bf2e6-ecba-498b-a047-3ec2a0ac2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429370746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2429370746
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3265542026
Short name T321
Test name
Test status
Simulation time 58441656056 ps
CPU time 96.39 seconds
Started Feb 25 01:38:27 PM PST 24
Finished Feb 25 01:40:03 PM PST 24
Peak memory 199564 kb
Host smart-29b9d724-5aee-46f5-bad3-1d240c8a3fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265542026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3265542026
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2934452942
Short name T875
Test name
Test status
Simulation time 143841802860 ps
CPU time 69.55 seconds
Started Feb 25 01:38:43 PM PST 24
Finished Feb 25 01:39:53 PM PST 24
Peak memory 199588 kb
Host smart-576f8ef1-7078-460d-b36c-843aca2e7c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934452942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2934452942
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.349052209
Short name T279
Test name
Test status
Simulation time 132057135941 ps
CPU time 305.59 seconds
Started Feb 25 01:38:40 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 199704 kb
Host smart-b4dd3c1a-bfea-45be-b03b-9e22a7f1245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349052209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.349052209
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1257530697
Short name T134
Test name
Test status
Simulation time 22673438007 ps
CPU time 35.63 seconds
Started Feb 25 01:38:40 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 199512 kb
Host smart-e3f86449-c0a3-4308-841a-cad1414e2b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257530697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1257530697
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1557760734
Short name T1013
Test name
Test status
Simulation time 276000426931 ps
CPU time 57.67 seconds
Started Feb 25 01:38:42 PM PST 24
Finished Feb 25 01:39:39 PM PST 24
Peak memory 199532 kb
Host smart-85b8c442-58bc-4627-baf8-8b6d4004cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557760734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1557760734
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.387737944
Short name T1074
Test name
Test status
Simulation time 115469748092 ps
CPU time 324.89 seconds
Started Feb 25 01:38:43 PM PST 24
Finished Feb 25 01:44:08 PM PST 24
Peak memory 216324 kb
Host smart-8dc945fb-0ff8-411c-b93f-dadfc3773fd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387737944 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.387737944
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2427534390
Short name T939
Test name
Test status
Simulation time 50984030435 ps
CPU time 26.01 seconds
Started Feb 25 01:38:45 PM PST 24
Finished Feb 25 01:39:11 PM PST 24
Peak memory 199608 kb
Host smart-3e67096c-4021-42b8-af9d-1e33d663fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427534390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2427534390
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1802720026
Short name T494
Test name
Test status
Simulation time 11884179 ps
CPU time 0.56 seconds
Started Feb 25 01:33:01 PM PST 24
Finished Feb 25 01:33:02 PM PST 24
Peak memory 195092 kb
Host smart-957f9162-65ca-4ac2-8b75-c2e16ff65301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802720026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1802720026
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3786752239
Short name T388
Test name
Test status
Simulation time 130472222247 ps
CPU time 49.99 seconds
Started Feb 25 01:33:08 PM PST 24
Finished Feb 25 01:34:00 PM PST 24
Peak memory 199600 kb
Host smart-65937434-521b-4390-90c2-63f0b7fef006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786752239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3786752239
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3753665207
Short name T648
Test name
Test status
Simulation time 66689963116 ps
CPU time 25.18 seconds
Started Feb 25 01:33:01 PM PST 24
Finished Feb 25 01:33:27 PM PST 24
Peak memory 199696 kb
Host smart-c195b1a4-09cc-4b52-a173-5652551fdbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753665207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3753665207
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1718896418
Short name T198
Test name
Test status
Simulation time 30011022657 ps
CPU time 9.49 seconds
Started Feb 25 01:33:03 PM PST 24
Finished Feb 25 01:33:13 PM PST 24
Peak memory 199256 kb
Host smart-881009e6-d09d-461e-9055-ea4b94830312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718896418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1718896418
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1328311549
Short name T1094
Test name
Test status
Simulation time 1295208867188 ps
CPU time 882.28 seconds
Started Feb 25 01:33:04 PM PST 24
Finished Feb 25 01:47:47 PM PST 24
Peak memory 199720 kb
Host smart-66821476-8c0c-4529-9364-bac01a25d430
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328311549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1328311549
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.1973249962
Short name T504
Test name
Test status
Simulation time 563628877 ps
CPU time 0.82 seconds
Started Feb 25 01:33:08 PM PST 24
Finished Feb 25 01:33:09 PM PST 24
Peak memory 195024 kb
Host smart-c0bb7c49-ba94-4b58-99dd-5ee96b928758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973249962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1973249962
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.200296971
Short name T879
Test name
Test status
Simulation time 222160618890 ps
CPU time 46.96 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:49 PM PST 24
Peak memory 207984 kb
Host smart-0b4c43fd-2ec8-4212-aa6a-edecc866596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200296971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.200296971
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2199913532
Short name T419
Test name
Test status
Simulation time 19652438966 ps
CPU time 293.44 seconds
Started Feb 25 01:33:04 PM PST 24
Finished Feb 25 01:37:58 PM PST 24
Peak memory 199616 kb
Host smart-f4cef86d-7a34-4473-9c23-913492a7ceec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199913532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2199913532
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2518435209
Short name T729
Test name
Test status
Simulation time 2326313394 ps
CPU time 15.33 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:18 PM PST 24
Peak memory 197736 kb
Host smart-96c31301-9663-4f85-89e3-f9df1f1621ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518435209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2518435209
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3015737484
Short name T920
Test name
Test status
Simulation time 118864683384 ps
CPU time 74.39 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:34:17 PM PST 24
Peak memory 199624 kb
Host smart-99a09148-f0db-4f11-bf6f-d3340295e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015737484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3015737484
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2561440194
Short name T699
Test name
Test status
Simulation time 36680680451 ps
CPU time 55.41 seconds
Started Feb 25 01:33:04 PM PST 24
Finished Feb 25 01:34:00 PM PST 24
Peak memory 195176 kb
Host smart-d738de7c-7b98-422b-8682-f743beb9d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561440194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2561440194
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.170709037
Short name T1
Test name
Test status
Simulation time 5718499989 ps
CPU time 11.28 seconds
Started Feb 25 01:33:05 PM PST 24
Finished Feb 25 01:33:16 PM PST 24
Peak memory 199508 kb
Host smart-b2374951-56d4-4454-880e-d426fc63a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170709037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.170709037
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4051681109
Short name T395
Test name
Test status
Simulation time 998104535311 ps
CPU time 286.88 seconds
Started Feb 25 01:33:05 PM PST 24
Finished Feb 25 01:37:52 PM PST 24
Peak memory 199608 kb
Host smart-060249e3-4f99-4f50-985e-1223b2fd9153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051681109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4051681109
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4278404526
Short name T508
Test name
Test status
Simulation time 1016295608 ps
CPU time 3.48 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:06 PM PST 24
Peak memory 198228 kb
Host smart-60c4f443-0167-46b4-a09a-5aeb5019e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278404526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4278404526
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2975260142
Short name T210
Test name
Test status
Simulation time 42872119087 ps
CPU time 74.8 seconds
Started Feb 25 01:33:01 PM PST 24
Finished Feb 25 01:34:16 PM PST 24
Peak memory 199540 kb
Host smart-b54fab5b-255e-4be3-a47f-cecc47b33107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975260142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2975260142
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2549543651
Short name T1027
Test name
Test status
Simulation time 16421994622 ps
CPU time 22.66 seconds
Started Feb 25 01:38:42 PM PST 24
Finished Feb 25 01:39:05 PM PST 24
Peak memory 199632 kb
Host smart-4a220f1b-b40e-456f-b16c-2649e11c0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549543651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2549543651
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2665000665
Short name T912
Test name
Test status
Simulation time 36589302838 ps
CPU time 17.74 seconds
Started Feb 25 01:38:43 PM PST 24
Finished Feb 25 01:39:01 PM PST 24
Peak memory 199144 kb
Host smart-d9b37626-266a-4af0-9ca4-270469865f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665000665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2665000665
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2947480012
Short name T242
Test name
Test status
Simulation time 23298736039 ps
CPU time 33.1 seconds
Started Feb 25 01:38:43 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 199244 kb
Host smart-a3a3e5e3-e962-45d1-b836-f37c406c7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947480012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2947480012
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1373356548
Short name T234
Test name
Test status
Simulation time 83349991191 ps
CPU time 40.53 seconds
Started Feb 25 01:38:42 PM PST 24
Finished Feb 25 01:39:22 PM PST 24
Peak memory 199636 kb
Host smart-322bb3d7-dd12-47f5-9f94-33e653cfd17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373356548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1373356548
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3176039853
Short name T474
Test name
Test status
Simulation time 47557777547 ps
CPU time 297.91 seconds
Started Feb 25 01:38:44 PM PST 24
Finished Feb 25 01:43:42 PM PST 24
Peak memory 215296 kb
Host smart-0bea2c89-7841-4d80-bb04-36d83bb5c87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176039853 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3176039853
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2826861097
Short name T1008
Test name
Test status
Simulation time 26239175880 ps
CPU time 43.17 seconds
Started Feb 25 01:38:41 PM PST 24
Finished Feb 25 01:39:24 PM PST 24
Peak memory 199576 kb
Host smart-f0525f17-599a-4047-a75a-8fea49a3ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826861097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2826861097
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.743808861
Short name T274
Test name
Test status
Simulation time 89004000042 ps
CPU time 34.55 seconds
Started Feb 25 01:38:42 PM PST 24
Finished Feb 25 01:39:17 PM PST 24
Peak memory 199612 kb
Host smart-195583c2-121e-41e2-8989-e85f028a6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743808861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.743808861
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.893190586
Short name T231
Test name
Test status
Simulation time 82100539021 ps
CPU time 32.25 seconds
Started Feb 25 01:38:58 PM PST 24
Finished Feb 25 01:39:31 PM PST 24
Peak memory 199648 kb
Host smart-df796397-2d7c-4fb4-a6aa-3098ce689832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893190586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.893190586
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1768152599
Short name T69
Test name
Test status
Simulation time 122706144835 ps
CPU time 358.33 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:44:58 PM PST 24
Peak memory 215564 kb
Host smart-3b781b41-8a2c-45ae-9cdb-dc569783ee35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768152599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1768152599
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3330686262
Short name T66
Test name
Test status
Simulation time 125502055531 ps
CPU time 56.34 seconds
Started Feb 25 01:39:04 PM PST 24
Finished Feb 25 01:40:01 PM PST 24
Peak memory 199616 kb
Host smart-99b7b98d-1353-43e8-a963-e75192779b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330686262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3330686262
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.244276557
Short name T261
Test name
Test status
Simulation time 76673780788 ps
CPU time 28.66 seconds
Started Feb 25 01:39:01 PM PST 24
Finished Feb 25 01:39:30 PM PST 24
Peak memory 198280 kb
Host smart-394fb338-bb5e-44b0-bc67-4daa708f418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244276557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.244276557
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1894386711
Short name T566
Test name
Test status
Simulation time 34019499 ps
CPU time 0.56 seconds
Started Feb 25 01:33:15 PM PST 24
Finished Feb 25 01:33:16 PM PST 24
Peak memory 195036 kb
Host smart-9b85adc3-e096-4d70-8d7e-f86a582dc2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894386711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1894386711
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3230220545
Short name T747
Test name
Test status
Simulation time 86678143837 ps
CPU time 47.99 seconds
Started Feb 25 01:33:03 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 199704 kb
Host smart-ee887d7b-fb8a-47db-af31-fbe612a1c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230220545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3230220545
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4116415087
Short name T716
Test name
Test status
Simulation time 221347144556 ps
CPU time 51.88 seconds
Started Feb 25 01:33:09 PM PST 24
Finished Feb 25 01:34:02 PM PST 24
Peak memory 198788 kb
Host smart-f0957446-e126-4f9a-8275-ad5409f41f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116415087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4116415087
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1799870907
Short name T270
Test name
Test status
Simulation time 90186320020 ps
CPU time 68.23 seconds
Started Feb 25 01:33:01 PM PST 24
Finished Feb 25 01:34:10 PM PST 24
Peak memory 199604 kb
Host smart-de6ac30a-b041-4bda-bdf9-0f9dc82e72f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799870907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1799870907
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.857396673
Short name T695
Test name
Test status
Simulation time 1178230547787 ps
CPU time 873.35 seconds
Started Feb 25 01:33:10 PM PST 24
Finished Feb 25 01:47:44 PM PST 24
Peak memory 199416 kb
Host smart-4f21882c-3577-48a2-a552-859874b1852a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857396673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.857396673
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3652939922
Short name T584
Test name
Test status
Simulation time 68435694201 ps
CPU time 119.82 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:35:12 PM PST 24
Peak memory 199620 kb
Host smart-482dc99d-5bb2-4a0c-bbc5-4a7360653bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652939922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3652939922
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2746177994
Short name T1106
Test name
Test status
Simulation time 4348961733 ps
CPU time 3.67 seconds
Started Feb 25 01:33:12 PM PST 24
Finished Feb 25 01:33:15 PM PST 24
Peak memory 197932 kb
Host smart-7df19c71-2b84-4b75-ac23-848a1e3fb353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746177994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2746177994
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2424830685
Short name T554
Test name
Test status
Simulation time 87983926097 ps
CPU time 177.2 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:35:59 PM PST 24
Peak memory 199840 kb
Host smart-d2eaccb1-66d0-4de2-bc14-af5e3eaec3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424830685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2424830685
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3516961282
Short name T199
Test name
Test status
Simulation time 17321513695 ps
CPU time 782 seconds
Started Feb 25 01:33:11 PM PST 24
Finished Feb 25 01:46:14 PM PST 24
Peak memory 199696 kb
Host smart-f2ebc0b8-1563-4053-8995-d6f7837c66bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516961282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3516961282
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3594515879
Short name T758
Test name
Test status
Simulation time 3324835335 ps
CPU time 22.6 seconds
Started Feb 25 01:33:03 PM PST 24
Finished Feb 25 01:33:26 PM PST 24
Peak memory 198056 kb
Host smart-d2d39b73-bae6-40d1-a89e-43be8fb6eac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594515879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3594515879
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.762259809
Short name T359
Test name
Test status
Simulation time 17225225738 ps
CPU time 13.12 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:15 PM PST 24
Peak memory 198792 kb
Host smart-82cd3d80-ed8b-4414-8c45-d052c9b50bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762259809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.762259809
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2020095722
Short name T43
Test name
Test status
Simulation time 4295736209 ps
CPU time 3.91 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:06 PM PST 24
Peak memory 195352 kb
Host smart-a4860b99-37ff-4ea9-b812-ff88c6e1f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020095722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2020095722
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3419674386
Short name T702
Test name
Test status
Simulation time 311113943 ps
CPU time 1.7 seconds
Started Feb 25 01:33:04 PM PST 24
Finished Feb 25 01:33:06 PM PST 24
Peak memory 197716 kb
Host smart-d920c6d3-b83c-498a-879d-1f0d85645546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419674386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3419674386
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.275981637
Short name T792
Test name
Test status
Simulation time 327304753468 ps
CPU time 1110.71 seconds
Started Feb 25 01:33:16 PM PST 24
Finished Feb 25 01:51:46 PM PST 24
Peak memory 199764 kb
Host smart-7437d863-2de7-4b42-a3be-1d015d0b42fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275981637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.275981637
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3532997796
Short name T24
Test name
Test status
Simulation time 968011898 ps
CPU time 3.17 seconds
Started Feb 25 01:33:05 PM PST 24
Finished Feb 25 01:33:08 PM PST 24
Peak memory 197624 kb
Host smart-9c87955f-0941-4fc9-a09b-1e42004bb833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532997796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3532997796
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3756202260
Short name T602
Test name
Test status
Simulation time 6770388718 ps
CPU time 8.09 seconds
Started Feb 25 01:33:02 PM PST 24
Finished Feb 25 01:33:11 PM PST 24
Peak memory 197040 kb
Host smart-cfc928c0-90b6-4d6e-a976-840805660efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756202260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3756202260
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2021059923
Short name T147
Test name
Test status
Simulation time 25954456340 ps
CPU time 10.4 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:39:11 PM PST 24
Peak memory 199600 kb
Host smart-803a8784-110c-4058-a243-db492bf112ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021059923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2021059923
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1115094719
Short name T167
Test name
Test status
Simulation time 69359081097 ps
CPU time 56.96 seconds
Started Feb 25 01:38:58 PM PST 24
Finished Feb 25 01:39:56 PM PST 24
Peak memory 199544 kb
Host smart-6cc3d739-e720-4e5a-8717-896b1e5c418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115094719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1115094719
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3737732120
Short name T683
Test name
Test status
Simulation time 77461474967 ps
CPU time 324.82 seconds
Started Feb 25 01:38:59 PM PST 24
Finished Feb 25 01:44:24 PM PST 24
Peak memory 216140 kb
Host smart-a992584d-53f2-4713-9080-c42cf5a90ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737732120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3737732120
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3944696105
Short name T1047
Test name
Test status
Simulation time 82887672057 ps
CPU time 128.65 seconds
Started Feb 25 01:38:58 PM PST 24
Finished Feb 25 01:41:08 PM PST 24
Peak memory 199600 kb
Host smart-9c154ffc-5a53-4de1-9043-bb1cf9c69a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944696105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3944696105
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.468145794
Short name T1071
Test name
Test status
Simulation time 46178093918 ps
CPU time 71.27 seconds
Started Feb 25 01:38:56 PM PST 24
Finished Feb 25 01:40:08 PM PST 24
Peak memory 199568 kb
Host smart-738f50d3-8e70-4753-86c6-1058dc25fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468145794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.468145794
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4220506110
Short name T308
Test name
Test status
Simulation time 13336150959 ps
CPU time 18.99 seconds
Started Feb 25 01:39:05 PM PST 24
Finished Feb 25 01:39:24 PM PST 24
Peak memory 199604 kb
Host smart-52c6c150-4a98-49ff-b741-eed49a756113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220506110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4220506110
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4001801598
Short name T117
Test name
Test status
Simulation time 48681302502 ps
CPU time 514.44 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:47:34 PM PST 24
Peak memory 207984 kb
Host smart-1be84979-5468-4e32-a3f0-b931828fb9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001801598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4001801598
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.130202537
Short name T735
Test name
Test status
Simulation time 143157939276 ps
CPU time 115.95 seconds
Started Feb 25 01:38:54 PM PST 24
Finished Feb 25 01:40:52 PM PST 24
Peak memory 199604 kb
Host smart-9599a41a-58f2-4823-9900-1e0e632695ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130202537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.130202537
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1573519051
Short name T251
Test name
Test status
Simulation time 19837927610 ps
CPU time 36.64 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:39:37 PM PST 24
Peak memory 199616 kb
Host smart-3fe41f75-7223-424f-924b-4b1c0983487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573519051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1573519051
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2955480865
Short name T849
Test name
Test status
Simulation time 86800245852 ps
CPU time 143.22 seconds
Started Feb 25 01:38:59 PM PST 24
Finished Feb 25 01:41:22 PM PST 24
Peak memory 199688 kb
Host smart-24b16572-1c43-4461-9fbe-fbea69b319de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955480865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2955480865
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3152889971
Short name T731
Test name
Test status
Simulation time 27976166262 ps
CPU time 345.99 seconds
Started Feb 25 01:38:58 PM PST 24
Finished Feb 25 01:44:45 PM PST 24
Peak memory 215028 kb
Host smart-956f6181-ef36-4b18-be9d-995c7d98ca77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152889971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3152889971
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2900953912
Short name T109
Test name
Test status
Simulation time 102853694740 ps
CPU time 173.95 seconds
Started Feb 25 01:38:59 PM PST 24
Finished Feb 25 01:41:53 PM PST 24
Peak memory 199660 kb
Host smart-06407e3f-1c50-46fb-ad2d-e1e18d1e44ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900953912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2900953912
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3914461051
Short name T57
Test name
Test status
Simulation time 61814876181 ps
CPU time 534.53 seconds
Started Feb 25 01:39:00 PM PST 24
Finished Feb 25 01:47:55 PM PST 24
Peak memory 215824 kb
Host smart-523cafe0-66be-48dc-9b76-6a6ec43ef12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914461051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3914461051
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3666654430
Short name T1051
Test name
Test status
Simulation time 44533243550 ps
CPU time 15.31 seconds
Started Feb 25 01:39:01 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 199256 kb
Host smart-3cfa4728-0de8-44d6-93be-7315de4443fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666654430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3666654430
Directory /workspace/99.uart_fifo_reset/latest
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