Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100847	1			T1	10		T2	230		T3	1
all_values[1]	100847	1			T1	10		T2	230		T3	1
all_values[2]	100847	1			T1	10		T2	230		T3	1
all_values[3]	100847	1			T1	10		T2	230		T3	1
all_values[4]	100847	1			T1	10		T2	230		T3	1
all_values[5]	100847	1			T1	10		T2	230		T3	1
all_values[6]	100847	1			T1	10		T2	230		T3	1
all_values[7]	100847	1			T1	10		T2	230		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

393842

1

T1

37

T2

858

T3

3

auto[1]

412934

1

T1

43

T2

982

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

792270

1

T1

68

T2

1813

T3

8

auto[1]

14506

1

T1

12

T2

27

T4

27

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	45979	1			T1	5		T2	33		T3	1
all_values[0]	auto[0]	auto[1]	2158	1			T2	4		T4	7		T5	1
all_values[0]	auto[1]	auto[0]	50612	1			T2	191		T4	42		T6	3
all_values[0]	auto[1]	auto[1]	2098	1			T1	5		T2	2		T4	7
all_values[1]	auto[0]	auto[0]	47943	1			T1	3		T2	85		T4	50
all_values[1]	auto[0]	auto[1]	2143	1			T4	4		T6	3		T8	9
all_values[1]	auto[1]	auto[0]	48847	1			T1	4		T2	142		T3	1
all_values[1]	auto[1]	auto[1]	1914	1			T1	3		T2	3		T7	1
all_values[2]	auto[0]	auto[0]	42830	1			T1	2		T4	58		T5	3
all_values[2]	auto[0]	auto[1]	2183	1			T1	3		T2	3		T4	5
all_values[2]	auto[1]	auto[0]	53906	1			T1	4		T2	212		T3	1
all_values[2]	auto[1]	auto[1]	1928	1			T1	1		T2	15		T4	4
all_values[3]	auto[0]	auto[0]	50521	1			T1	2		T2	226		T3	1
all_values[3]	auto[0]	auto[1]	149	1			T8	2		T13	1		T14	3
all_values[3]	auto[1]	auto[0]	50015	1			T1	8		T2	4		T4	45
all_values[3]	auto[1]	auto[1]	162	1			T13	6		T15	3		T75	1
all_values[4]	auto[0]	auto[0]	51698	1			T1	10		T2	122		T4	49
all_values[4]	auto[0]	auto[1]	412	1			T13	1		T16	5		T15	8
all_values[4]	auto[1]	auto[0]	48346	1			T2	108		T3	1		T4	47
all_values[4]	auto[1]	auto[1]	391	1			T8	4		T11	16		T13	11
all_values[5]	auto[0]	auto[0]	47054	1			T1	3		T2	191		T4	63
all_values[5]	auto[0]	auto[1]	98	1			T8	3		T15	1		T388	3
all_values[5]	auto[1]	auto[0]	53575	1			T1	7		T2	39		T3	1
all_values[5]	auto[1]	auto[1]	120	1			T8	1		T74	2		T28	1
all_values[6]	auto[0]	auto[0]	49725	1			T1	5		T2	2		T4	43
all_values[6]	auto[0]	auto[1]	99	1			T8	2		T15	2		T74	1
all_values[6]	auto[1]	auto[0]	50904	1			T1	5		T2	228		T3	1
all_values[6]	auto[1]	auto[1]	119	1			T8	1		T74	2		T28	2
all_values[7]	auto[0]	auto[0]	50593	1			T1	4		T2	192		T3	1
all_values[7]	auto[0]	auto[1]	257	1			T8	1		T9	1		T300	2
all_values[7]	auto[1]	auto[0]	49722	1			T1	6		T2	38		T4	62
all_values[7]	auto[1]	auto[1]	275	1			T8	3		T300	5		T307	2