Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2008

1

T1

1

T2

1

T3

1

auto[UartRx]

2008

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3887	1			T1	2		T2	2		T3	2
values[1]	26	1			T8	1		T11	2		T20	3
values[2]	9	1			T11	1		T20	1		T446	1
values[3]	13	1			T11	1		T28	1		T32	1
values[4]	9	1			T29	1		T31	1		T33	1
values[5]	12	1			T11	2		T29	2		T30	2
values[6]	11	1			T8	1		T29	3		T30	1
values[7]	11	1			T8	3		T33	1		T446	1
values[8]	7	1			T8	1		T96	1		T447	1
values[9]	10	1			T8	1		T28	1		T29	1
values[10]	14	1			T8	1		T20	1		T27	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1962	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	10	1			T8	1		T11	1		T20	1
auto[UartTx]	values[2]	3	1			T20	1		T96	1		T448	1
auto[UartTx]	values[3]	5	1			T28	1		T52	1		T447	1
auto[UartTx]	values[4]	3	1			T447	1		T449	1		T100	1
auto[UartTx]	values[5]	1	1			T450	1		-	-		-	-
auto[UartTx]	values[6]	4	1			T29	1		T30	1		T32	1
auto[UartTx]	values[7]	6	1			T8	2		T446	1		T184	1
auto[UartTx]	values[8]	2	1			T8	1		T451	1		-	-
auto[UartTx]	values[9]	3	1			T98	2		T452	1		-	-
auto[UartTx]	values[10]	7	1			T20	1		T28	1		T96	1
auto[UartRx]	values[0]	1925	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	16	1			T11	1		T20	2		T27	1
auto[UartRx]	values[2]	6	1			T11	1		T446	1		T184	1
auto[UartRx]	values[3]	8	1			T11	1		T32	1		T217	1
auto[UartRx]	values[4]	6	1			T29	1		T31	1		T33	1
auto[UartRx]	values[5]	11	1			T11	2		T29	2		T30	2
auto[UartRx]	values[6]	7	1			T8	1		T29	2		T32	1
auto[UartRx]	values[7]	5	1			T8	1		T33	1		T453	1
auto[UartRx]	values[8]	5	1			T96	1		T447	1		T99	1
auto[UartRx]	values[9]	7	1			T8	1		T28	1		T29	1
auto[UartRx]	values[10]	7	1			T8	1		T27	1		T446	1