Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1648	1			T2	3		T3	8		T4	6
auto[BaudRate115200]	1644	1			T1	1		T3	8		T6	2
auto[BaudRate230400]	1434	1			T2	3		T4	6		T6	3
auto[BaudRate128Kbps]	1493	1			T1	3		T6	1		T7	1
auto[BaudRate256Kbps]	1590	1			T1	1		T2	1		T4	4
auto[BaudRate1Mbps]	1454	1			T1	1		T2	1		T4	3
auto[BaudRate1p5Mbps]	1070	1			T2	2		T4	4		T7	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	928	1			T128	5		T408	2		T124	7
freqs[25]	975	1			T7	9		T38	8		T115	5
freqs[48]	559	1			T34	2		T12	10		T214	6
freqs[50]	473	1			T415	7		T428	2		T414	2
freqs[100]	1002	1			T3	16		T151	10		T40	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	118	1			T128	1		T124	1		T135	2
auto[BaudRate9600]	freqs[25]	173	1			T7	1		T38	2		T240	1
auto[BaudRate9600]	freqs[48]	78	1			T214	1		T325	1		T437	3
auto[BaudRate9600]	freqs[50]	60	1			T139	1		T162	1		T454	4
auto[BaudRate9600]	freqs[100]	157	1			T3	8		T455	3		T167	4
auto[BaudRate115200]	freqs[24]	154	1			T128	1		T124	2		T395	2
auto[BaudRate115200]	freqs[25]	200	1			T7	1		T38	1		T316	1
auto[BaudRate115200]	freqs[48]	72	1			T12	2		T214	2		T313	1
auto[BaudRate115200]	freqs[50]	78	1			T415	1		T119	2		T139	1
auto[BaudRate115200]	freqs[100]	154	1			T3	8		T151	1		T129	3
auto[BaudRate230400]	freqs[24]	128	1			T124	1		T395	1		T329	2
auto[BaudRate230400]	freqs[25]	95	1			T7	2		T412	1		T240	1
auto[BaudRate230400]	freqs[48]	76	1			T214	1		T313	3		T325	1
auto[BaudRate230400]	freqs[50]	76	1			T428	1		T143	3		T119	1
auto[BaudRate230400]	freqs[100]	126	1			T151	1		T455	9		T418	1
auto[BaudRate128Kbps]	freqs[24]	145	1			T128	1		T395	2		T329	3
auto[BaudRate128Kbps]	freqs[25]	135	1			T7	1		T38	2		T316	1
auto[BaudRate128Kbps]	freqs[48]	86	1			T12	3		T214	1		T313	1
auto[BaudRate128Kbps]	freqs[50]	54	1			T415	3		T414	1		T139	1
auto[BaudRate128Kbps]	freqs[100]	128	1			T151	2		T455	9		T16	1
auto[BaudRate256Kbps]	freqs[24]	148	1			T397	2		T395	1		T42	5
auto[BaudRate256Kbps]	freqs[25]	147	1			T7	3		T38	1		T115	2
auto[BaudRate256Kbps]	freqs[48]	87	1			T12	1		T402	1		T437	1
auto[BaudRate256Kbps]	freqs[50]	68	1			T415	1		T414	1		T119	1
auto[BaudRate256Kbps]	freqs[100]	140	1			T151	2		T40	1		T129	2
auto[BaudRate1Mbps]	freqs[24]	143	1			T128	1		T408	1		T124	1
auto[BaudRate1Mbps]	freqs[25]	153	1			T38	1		T115	3		T412	1
auto[BaudRate1Mbps]	freqs[48]	93	1			T34	1		T12	2		T214	1
auto[BaudRate1Mbps]	freqs[50]	66	1			T415	2		T162	2		T417	1
auto[BaudRate1Mbps]	freqs[100]	160	1			T151	1		T40	3		T129	2
auto[BaudRate1p5Mbps]	freqs[25]	72	1			T7	1		T38	1		T412	1
auto[BaudRate1p5Mbps]	freqs[48]	67	1			T34	1		T12	2		T325	1
auto[BaudRate1p5Mbps]	freqs[50]	71	1			T428	1		T143	2		T119	1
auto[BaudRate1p5Mbps]	freqs[100]	137	1			T151	3		T40	3		T129	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded