Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1746 1 T4 2 T7 1 T8 13
all_levels[1] 470 1 T1 3 T8 1 T11 2
all_levels[2] 326 1 T11 3 T147 1 T296 2
all_levels[3] 298 1 T2 3 T300 1 T296 2
all_levels[4] 356 1 T300 2 T147 2 T115 1
all_levels[5] 382 1 T296 4 T151 1 T329 2
all_levels[6] 304 1 T4 2 T147 1 T296 1
all_levels[7] 173 1 T6 3 T11 1 T124 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%