Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100847	1			T1	10		T2	230		T3	1
all_pins[1]	100847	1			T1	10		T2	230		T3	1
all_pins[2]	100847	1			T1	10		T2	230		T3	1
all_pins[3]	100847	1			T1	10		T2	230		T3	1
all_pins[4]	100847	1			T1	10		T2	230		T3	1
all_pins[5]	100847	1			T1	10		T2	230		T3	1
all_pins[6]	100847	1			T1	10		T2	230		T3	1
all_pins[7]	100847	1			T1	10		T2	230		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	799031	1			T1	71		T2	1817		T3	8
values[0x1]	7745	1			T1	9		T2	23		T4	11
transitions[0x0=>0x1]	7016	1			T1	5		T2	21		T4	11
transitions[0x1=>0x0]	7029	1			T1	5		T2	21		T4	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98697	1			T1	5		T2	227		T3	1
all_pins[0]	values[0x1]	2150	1			T1	5		T2	3		T4	7
all_pins[0]	transitions[0x0=>0x1]	1912	1			T1	2		T2	3		T4	7
all_pins[0]	transitions[0x1=>0x0]	1676	1			T2	3		T8	4		T11	13
all_pins[1]	values[0x0]	98933	1			T1	7		T2	227		T3	1
all_pins[1]	values[0x1]	1914	1			T1	3		T2	3		T7	1
all_pins[1]	transitions[0x0=>0x1]	1654	1			T1	2		T2	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	1742	1			T2	13		T4	4		T7	4
all_pins[2]	values[0x0]	98845	1			T1	9		T2	215		T3	1
all_pins[2]	values[0x1]	2002	1			T1	1		T2	15		T4	4
all_pins[2]	transitions[0x0=>0x1]	1972	1			T1	1		T2	15		T4	4
all_pins[2]	transitions[0x1=>0x0]	132	1			T13	6		T15	3		T75	1
all_pins[3]	values[0x0]	100685	1			T1	10		T2	230		T3	1
all_pins[3]	values[0x1]	162	1			T13	6		T15	3		T75	1
all_pins[3]	transitions[0x0=>0x1]	130	1			T13	6		T15	3		T75	1
all_pins[3]	transitions[0x1=>0x0]	359	1			T8	4		T11	16		T13	11
all_pins[4]	values[0x0]	100456	1			T1	10		T2	230		T3	1
all_pins[4]	values[0x1]	391	1			T8	4		T11	16		T13	11
all_pins[4]	transitions[0x0=>0x1]	335	1			T8	3		T11	12		T13	10
all_pins[4]	transitions[0x1=>0x0]	119	1			T15	2		T74	1		T388	1
all_pins[5]	values[0x0]	100672	1			T1	10		T2	230		T3	1
all_pins[5]	values[0x1]	175	1			T8	1		T11	4		T13	1
all_pins[5]	transitions[0x0=>0x1]	143	1			T11	4		T13	1		T15	2
all_pins[5]	transitions[0x1=>0x0]	644	1			T2	2		T9	1		T11	5
all_pins[6]	values[0x0]	100171	1			T1	10		T2	228		T3	1
all_pins[6]	values[0x1]	676	1			T2	2		T8	1		T9	1
all_pins[6]	transitions[0x0=>0x1]	637	1			T2	2		T8	1		T9	1
all_pins[6]	transitions[0x1=>0x0]	236	1			T8	3		T300	5		T307	2
all_pins[7]	values[0x0]	100572	1			T1	10		T2	230		T3	1
all_pins[7]	values[0x1]	275	1			T8	3		T300	5		T307	2
all_pins[7]	transitions[0x0=>0x1]	233	1			T8	2		T300	5		T307	2
all_pins[7]	transitions[0x1=>0x0]	2121	1			T1	5		T2	3		T4	7