Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	441	1			T8	4		T15	4		T74	4
all_values[1]	441	1			T8	4		T15	4		T74	4
all_values[2]	441	1			T8	4		T15	4		T74	4
all_values[3]	441	1			T8	4		T15	4		T74	4
all_values[4]	441	1			T8	4		T15	4		T74	4
all_values[5]	441	1			T8	4		T15	4		T74	4
all_values[6]	441	1			T8	4		T15	4		T74	4
all_values[7]	441	1			T8	4		T15	4		T74	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1922

1

T8

19

T15

23

T74

22

auto[1]

1606

1

T8

13

T15

9

T74

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1407

1

T8

6

T15

18

T74

10

auto[1]

2121

1

T8

26

T15

14

T74

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2094

1

T8

16

T15

22

T74

17

auto[1]

1434

1

T8

16

T15

10

T74

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	101	1			T8	1		T15	1		T28	1
all_values[0]	auto[0]	auto[0]	auto[1]	48	1			T8	1		T15	2		T74	2
all_values[0]	auto[0]	auto[1]	auto[0]	72	1			T388	5		T29	1		T31	2
all_values[0]	auto[0]	auto[1]	auto[1]	35	1			T74	1		T28	2		T31	1
all_values[0]	auto[1]	auto[0]	auto[1]	116	1			T8	1		T74	1		T31	3
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T8	1		T15	1		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	90	1			T74	2		T388	2		T29	2
all_values[1]	auto[0]	auto[0]	auto[1]	52	1			T388	1		T29	1		T32	3
all_values[1]	auto[0]	auto[1]	auto[0]	74	1			T15	2		T74	1		T28	1
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T8	2		T28	1		T388	2
all_values[1]	auto[1]	auto[0]	auto[1]	103	1			T8	1		T15	1		T74	1
all_values[1]	auto[1]	auto[1]	auto[1]	78	1			T8	1		T15	1		T28	1
all_values[2]	auto[0]	auto[0]	auto[0]	92	1			T8	2		T15	1		T74	3
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T28	1		T32	1		T389	1
all_values[2]	auto[0]	auto[1]	auto[0]	95	1			T15	3		T388	2		T29	2
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T8	1		T28	1		T388	1
all_values[2]	auto[1]	auto[0]	auto[1]	90	1			T74	1		T28	1		T388	2
all_values[2]	auto[1]	auto[1]	auto[1]	84	1			T8	1		T28	1		T388	1
all_values[3]	auto[0]	auto[0]	auto[0]	96	1			T8	1		T15	2		T74	1
all_values[3]	auto[0]	auto[0]	auto[1]	40	1			T8	1		T388	3		T32	1
all_values[3]	auto[0]	auto[1]	auto[0]	82	1			T8	1		T28	1		T388	1
all_values[3]	auto[0]	auto[1]	auto[1]	44	1			T74	1		T28	1		T32	2
all_values[3]	auto[1]	auto[0]	auto[1]	89	1			T8	1		T15	2		T74	1
all_values[3]	auto[1]	auto[1]	auto[1]	90	1			T74	1		T31	4		T32	4
all_values[4]	auto[0]	auto[0]	auto[0]	106	1			T15	3		T388	2		T29	1
all_values[4]	auto[0]	auto[0]	auto[1]	37	1			T388	1		T31	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	81	1			T28	2		T388	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[1]	47	1			T8	1		T74	1		T28	1
all_values[4]	auto[1]	auto[0]	auto[1]	94	1			T8	1		T15	1		T74	2
all_values[4]	auto[1]	auto[1]	auto[1]	76	1			T8	2		T74	1		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	94	1			T15	2		T74	1		T28	1
all_values[5]	auto[0]	auto[0]	auto[1]	40	1			T8	1		T388	1		T111	1
all_values[5]	auto[0]	auto[1]	auto[0]	69	1			T74	1		T28	1		T388	1
all_values[5]	auto[0]	auto[1]	auto[1]	43	1			T388	1		T29	2		T96	1
all_values[5]	auto[1]	auto[0]	auto[1]	104	1			T8	3		T15	2		T74	1
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T74	1		T28	2		T388	3
all_values[6]	auto[0]	auto[0]	auto[0]	98	1			T8	1		T15	1		T74	1
all_values[6]	auto[0]	auto[0]	auto[1]	41	1			T8	1		T15	1		T28	1
all_values[6]	auto[0]	auto[1]	auto[0]	68	1			T15	1		T32	3		T111	1
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T74	1		T28	1		T388	2
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T8	2		T15	1		T74	2
all_values[6]	auto[1]	auto[1]	auto[1]	80	1			T388	2		T31	5		T32	2
all_values[7]	auto[0]	auto[0]	auto[0]	104	1			T15	2		T31	3		T32	4
all_values[7]	auto[0]	auto[0]	auto[1]	36	1			T74	1		T31	1		T96	1
all_values[7]	auto[0]	auto[1]	auto[0]	85	1			T388	2		T29	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[1]	49	1			T8	2		T15	1		T28	2
all_values[7]	auto[1]	auto[0]	auto[1]	105	1			T8	1		T15	1		T74	2
all_values[7]	auto[1]	auto[1]	auto[1]	62	1			T8	1		T74	1		T28	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal