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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.79 98.45 100.00 99.76 100.00 97.59


Total test records in report: 1232
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T1044 /workspace/coverage/default/4.uart_intr.96389408 Feb 29 01:18:53 PM PST 24 Feb 29 01:29:31 PM PST 24 971766772254 ps
T86 /workspace/coverage/default/4.uart_sec_cm.289415042 Feb 29 01:18:56 PM PST 24 Feb 29 01:18:57 PM PST 24 148502750 ps
T1045 /workspace/coverage/default/46.uart_long_xfer_wo_dly.2313703465 Feb 29 01:22:43 PM PST 24 Feb 29 01:26:17 PM PST 24 68024953371 ps
T1046 /workspace/coverage/default/17.uart_fifo_overflow.4026302580 Feb 29 01:19:54 PM PST 24 Feb 29 01:20:50 PM PST 24 312624730503 ps
T1047 /workspace/coverage/default/25.uart_stress_all.636169036 Feb 29 01:20:44 PM PST 24 Feb 29 01:21:31 PM PST 24 21585479525 ps
T1048 /workspace/coverage/default/25.uart_intr.3315190419 Feb 29 01:20:31 PM PST 24 Feb 29 01:21:06 PM PST 24 22084396146 ps
T1049 /workspace/coverage/default/49.uart_noise_filter.2412856440 Feb 29 01:22:58 PM PST 24 Feb 29 01:23:28 PM PST 24 33122625715 ps
T180 /workspace/coverage/default/0.uart_fifo_overflow.3808077573 Feb 29 01:18:40 PM PST 24 Feb 29 01:19:52 PM PST 24 47674530741 ps
T1050 /workspace/coverage/default/29.uart_alert_test.2585887377 Feb 29 01:21:26 PM PST 24 Feb 29 01:21:27 PM PST 24 13357841 ps
T1051 /workspace/coverage/default/114.uart_fifo_reset.3520904919 Feb 29 01:23:38 PM PST 24 Feb 29 01:23:55 PM PST 24 5546436040 ps
T1052 /workspace/coverage/default/15.uart_smoke.1303359154 Feb 29 01:19:48 PM PST 24 Feb 29 01:19:49 PM PST 24 462447573 ps
T1053 /workspace/coverage/default/282.uart_fifo_reset.2299483395 Feb 29 01:24:51 PM PST 24 Feb 29 01:25:05 PM PST 24 32689701912 ps
T1054 /workspace/coverage/default/9.uart_noise_filter.854310646 Feb 29 01:19:26 PM PST 24 Feb 29 01:19:32 PM PST 24 2692266218 ps
T1055 /workspace/coverage/default/96.uart_fifo_reset.2047143008 Feb 29 01:23:36 PM PST 24 Feb 29 01:26:06 PM PST 24 180343304344 ps
T1056 /workspace/coverage/default/22.uart_fifo_overflow.3716182868 Feb 29 01:20:18 PM PST 24 Feb 29 01:21:40 PM PST 24 116390927150 ps
T1057 /workspace/coverage/default/30.uart_smoke.1801221645 Feb 29 01:21:21 PM PST 24 Feb 29 01:21:23 PM PST 24 430166183 ps
T1058 /workspace/coverage/default/252.uart_fifo_reset.4229801416 Feb 29 01:24:39 PM PST 24 Feb 29 01:29:28 PM PST 24 206143776618 ps
T1059 /workspace/coverage/default/15.uart_loopback.2129094202 Feb 29 01:19:43 PM PST 24 Feb 29 01:19:56 PM PST 24 5037246202 ps
T201 /workspace/coverage/default/162.uart_fifo_reset.3868420200 Feb 29 01:23:56 PM PST 24 Feb 29 01:24:17 PM PST 24 11854135814 ps
T383 /workspace/coverage/default/37.uart_fifo_full.3574857658 Feb 29 01:21:55 PM PST 24 Feb 29 01:22:04 PM PST 24 60688698569 ps
T1060 /workspace/coverage/default/44.uart_fifo_reset.2789848126 Feb 29 01:22:31 PM PST 24 Feb 29 01:25:27 PM PST 24 327674830023 ps
T1061 /workspace/coverage/default/27.uart_perf.1860761212 Feb 29 01:21:01 PM PST 24 Feb 29 01:23:18 PM PST 24 33376116006 ps
T1062 /workspace/coverage/default/48.uart_stress_all.1264858444 Feb 29 01:22:57 PM PST 24 Feb 29 01:26:14 PM PST 24 418004294973 ps
T1063 /workspace/coverage/default/4.uart_loopback.2607962654 Feb 29 01:18:54 PM PST 24 Feb 29 01:18:55 PM PST 24 243628665 ps
T1064 /workspace/coverage/default/81.uart_fifo_reset.3563450516 Feb 29 01:23:28 PM PST 24 Feb 29 01:25:31 PM PST 24 80981438448 ps
T1065 /workspace/coverage/default/37.uart_rx_start_bit_filter.2754302378 Feb 29 01:21:55 PM PST 24 Feb 29 01:22:13 PM PST 24 44113274489 ps
T1066 /workspace/coverage/default/23.uart_perf.1929646620 Feb 29 01:20:34 PM PST 24 Feb 29 01:24:11 PM PST 24 17086397593 ps
T1067 /workspace/coverage/default/20.uart_rx_parity_err.501522232 Feb 29 01:20:18 PM PST 24 Feb 29 01:22:12 PM PST 24 336870098550 ps
T1068 /workspace/coverage/default/60.uart_fifo_reset.3307136531 Feb 29 01:23:12 PM PST 24 Feb 29 01:23:58 PM PST 24 121418364060 ps
T1069 /workspace/coverage/default/0.uart_long_xfer_wo_dly.2795419852 Feb 29 01:18:43 PM PST 24 Feb 29 01:21:16 PM PST 24 43355909128 ps
T1070 /workspace/coverage/default/98.uart_fifo_reset.1835776551 Feb 29 01:23:38 PM PST 24 Feb 29 01:24:06 PM PST 24 76057515826 ps
T1071 /workspace/coverage/default/17.uart_perf.2554335853 Feb 29 01:19:59 PM PST 24 Feb 29 01:25:39 PM PST 24 11604367770 ps
T1072 /workspace/coverage/default/4.uart_perf.2982230354 Feb 29 01:18:53 PM PST 24 Feb 29 01:23:56 PM PST 24 5254409992 ps
T370 /workspace/coverage/default/32.uart_fifo_overflow.1017378795 Feb 29 01:21:26 PM PST 24 Feb 29 01:22:44 PM PST 24 97270246972 ps
T1073 /workspace/coverage/default/25.uart_tx_rx.1006845948 Feb 29 01:20:36 PM PST 24 Feb 29 01:22:10 PM PST 24 50696117490 ps
T1074 /workspace/coverage/default/236.uart_fifo_reset.2688539880 Feb 29 01:24:39 PM PST 24 Feb 29 01:26:03 PM PST 24 48384510619 ps
T1075 /workspace/coverage/default/17.uart_long_xfer_wo_dly.2270747832 Feb 29 01:19:56 PM PST 24 Feb 29 01:23:45 PM PST 24 119471262693 ps
T1076 /workspace/coverage/default/129.uart_fifo_reset.270060599 Feb 29 01:23:43 PM PST 24 Feb 29 01:23:54 PM PST 24 24922963184 ps
T1077 /workspace/coverage/default/214.uart_fifo_reset.2933446582 Feb 29 01:24:32 PM PST 24 Feb 29 01:26:02 PM PST 24 61741447189 ps
T1078 /workspace/coverage/default/7.uart_long_xfer_wo_dly.3267254956 Feb 29 01:19:10 PM PST 24 Feb 29 01:32:49 PM PST 24 112357777983 ps
T1079 /workspace/coverage/default/24.uart_alert_test.3408383574 Feb 29 01:20:31 PM PST 24 Feb 29 01:20:32 PM PST 24 14179113 ps
T1080 /workspace/coverage/default/32.uart_fifo_full.3517472815 Feb 29 01:21:24 PM PST 24 Feb 29 01:22:03 PM PST 24 90437190100 ps
T1081 /workspace/coverage/default/45.uart_tx_ovrd.2089393067 Feb 29 01:22:32 PM PST 24 Feb 29 01:22:34 PM PST 24 1036015786 ps
T1082 /workspace/coverage/default/22.uart_smoke.1706465627 Feb 29 01:20:18 PM PST 24 Feb 29 01:20:29 PM PST 24 6294135638 ps
T1083 /workspace/coverage/default/44.uart_intr.2119405215 Feb 29 01:22:32 PM PST 24 Feb 29 01:24:54 PM PST 24 1175520968626 ps
T1084 /workspace/coverage/default/16.uart_rx_oversample.1709808891 Feb 29 01:19:46 PM PST 24 Feb 29 01:20:08 PM PST 24 3640257590 ps
T1085 /workspace/coverage/default/226.uart_fifo_reset.3124142494 Feb 29 01:24:38 PM PST 24 Feb 29 01:27:52 PM PST 24 94332860780 ps
T1086 /workspace/coverage/default/43.uart_stress_all.3728505071 Feb 29 01:22:27 PM PST 24 Feb 29 01:25:12 PM PST 24 38594487353 ps
T1087 /workspace/coverage/default/276.uart_fifo_reset.3176958165 Feb 29 01:24:43 PM PST 24 Feb 29 01:25:30 PM PST 24 25322764309 ps
T1088 /workspace/coverage/default/33.uart_stress_all.2286588114 Feb 29 01:21:39 PM PST 24 Feb 29 01:22:11 PM PST 24 71155190618 ps
T335 /workspace/coverage/default/199.uart_fifo_reset.426501006 Feb 29 01:24:28 PM PST 24 Feb 29 01:24:53 PM PST 24 80510170184 ps
T1089 /workspace/coverage/default/35.uart_rx_start_bit_filter.1966288528 Feb 29 01:21:40 PM PST 24 Feb 29 01:22:12 PM PST 24 41192895435 ps
T452 /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1707965231 Feb 29 01:23:27 PM PST 24 Feb 29 01:34:36 PM PST 24 64888737284 ps
T1090 /workspace/coverage/default/41.uart_long_xfer_wo_dly.96949000 Feb 29 01:22:20 PM PST 24 Feb 29 01:29:17 PM PST 24 99651824180 ps
T1091 /workspace/coverage/default/48.uart_alert_test.2011409514 Feb 29 01:22:56 PM PST 24 Feb 29 01:22:58 PM PST 24 13073549 ps
T1092 /workspace/coverage/default/30.uart_long_xfer_wo_dly.2714333864 Feb 29 01:21:22 PM PST 24 Feb 29 01:26:55 PM PST 24 152520018374 ps
T1093 /workspace/coverage/default/268.uart_fifo_reset.889973513 Feb 29 01:24:43 PM PST 24 Feb 29 01:25:21 PM PST 24 45220492235 ps
T1094 /workspace/coverage/default/54.uart_fifo_reset.1973154280 Feb 29 01:23:08 PM PST 24 Feb 29 01:23:50 PM PST 24 106941497364 ps
T1095 /workspace/coverage/default/61.uart_fifo_reset.4262212658 Feb 29 01:23:09 PM PST 24 Feb 29 01:24:26 PM PST 24 193503690204 ps
T1096 /workspace/coverage/default/22.uart_perf.2929037000 Feb 29 01:20:19 PM PST 24 Feb 29 01:39:40 PM PST 24 20296487409 ps
T1097 /workspace/coverage/default/58.uart_fifo_reset.4090408538 Feb 29 01:23:11 PM PST 24 Feb 29 01:25:46 PM PST 24 97453448675 ps
T1098 /workspace/coverage/default/13.uart_fifo_reset.2214275539 Feb 29 01:19:32 PM PST 24 Feb 29 01:19:46 PM PST 24 33644304056 ps
T1099 /workspace/coverage/default/6.uart_noise_filter.3805675759 Feb 29 01:19:06 PM PST 24 Feb 29 01:20:28 PM PST 24 35955291768 ps
T1100 /workspace/coverage/default/281.uart_fifo_reset.29773539 Feb 29 01:24:51 PM PST 24 Feb 29 01:25:00 PM PST 24 17720383522 ps
T1101 /workspace/coverage/default/2.uart_long_xfer_wo_dly.2172880346 Feb 29 01:18:57 PM PST 24 Feb 29 01:29:46 PM PST 24 94835505884 ps
T100 /workspace/coverage/default/64.uart_stress_all_with_rand_reset.936911211 Feb 29 01:23:08 PM PST 24 Feb 29 01:26:23 PM PST 24 38814002568 ps
T1102 /workspace/coverage/default/157.uart_fifo_reset.3866132490 Feb 29 01:23:53 PM PST 24 Feb 29 01:24:24 PM PST 24 106934069968 ps
T66 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4203907558 Feb 29 12:46:23 PM PST 24 Feb 29 12:46:29 PM PST 24 32276181 ps
T67 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4033484065 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:17 PM PST 24 142945511 ps
T68 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1506748341 Feb 29 12:46:21 PM PST 24 Feb 29 12:46:22 PM PST 24 20147860 ps
T54 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3983112158 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:38 PM PST 24 12260791 ps
T69 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1741425658 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:31 PM PST 24 24368825 ps
T1103 /workspace/coverage/cover_reg_top/28.uart_intr_test.3404730596 Feb 29 12:46:31 PM PST 24 Feb 29 12:46:32 PM PST 24 43331073 ps
T1104 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2296701006 Feb 29 12:46:18 PM PST 24 Feb 29 12:46:26 PM PST 24 344755275 ps
T1105 /workspace/coverage/cover_reg_top/13.uart_intr_test.649377444 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:31 PM PST 24 26634668 ps
T1106 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1972947655 Feb 29 12:46:21 PM PST 24 Feb 29 12:46:22 PM PST 24 183742300 ps
T1107 /workspace/coverage/cover_reg_top/20.uart_intr_test.2472257336 Feb 29 12:46:28 PM PST 24 Feb 29 12:46:28 PM PST 24 67308240 ps
T1108 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2585779297 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:40 PM PST 24 27283376 ps
T70 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3780816226 Feb 29 12:46:24 PM PST 24 Feb 29 12:46:25 PM PST 24 30064131 ps
T76 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2113112209 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:40 PM PST 24 270947496 ps
T101 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3605474533 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:19 PM PST 24 118881812 ps
T71 /workspace/coverage/cover_reg_top/5.uart_csr_rw.136468375 Feb 29 12:46:09 PM PST 24 Feb 29 12:46:11 PM PST 24 33514710 ps
T55 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2762346107 Feb 29 12:46:41 PM PST 24 Feb 29 12:46:42 PM PST 24 39371799 ps
T113 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.718405316 Feb 29 12:46:52 PM PST 24 Feb 29 12:46:53 PM PST 24 18618054 ps
T1109 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3484964813 Feb 29 12:46:29 PM PST 24 Feb 29 12:46:29 PM PST 24 36040632 ps
T1110 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1103177827 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:07 PM PST 24 28858408 ps
T1111 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4166338352 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:19 PM PST 24 58610214 ps
T56 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2298201036 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:15 PM PST 24 31064910 ps
T72 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1623703481 Feb 29 12:46:24 PM PST 24 Feb 29 12:46:25 PM PST 24 58394003 ps
T1112 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1830744453 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:39 PM PST 24 36174253 ps
T1113 /workspace/coverage/cover_reg_top/0.uart_intr_test.4110302733 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:13 PM PST 24 14642413 ps
T1114 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.800895712 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:13 PM PST 24 103434881 ps
T1115 /workspace/coverage/cover_reg_top/49.uart_intr_test.1135475800 Feb 29 12:46:48 PM PST 24 Feb 29 12:46:48 PM PST 24 13125722 ps
T1116 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1358070582 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:49 PM PST 24 121562664 ps
T1117 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.578611162 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:14 PM PST 24 75376427 ps
T77 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2390420568 Feb 29 12:46:42 PM PST 24 Feb 29 12:46:44 PM PST 24 289445793 ps
T73 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1530791812 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:19 PM PST 24 31698657 ps
T78 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2358454432 Feb 29 12:46:28 PM PST 24 Feb 29 12:46:29 PM PST 24 125204086 ps
T384 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2185811576 Feb 29 12:46:27 PM PST 24 Feb 29 12:46:28 PM PST 24 534178072 ps
T1118 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2031582656 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:13 PM PST 24 20088308 ps
T1119 /workspace/coverage/cover_reg_top/48.uart_intr_test.1735506431 Feb 29 12:46:35 PM PST 24 Feb 29 12:46:35 PM PST 24 23581380 ps
T1120 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3556041032 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:17 PM PST 24 24117185 ps
T1121 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2475056443 Feb 29 12:45:59 PM PST 24 Feb 29 12:46:01 PM PST 24 55691435 ps
T1122 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1104866635 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:14 PM PST 24 54475851 ps
T1123 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.461006848 Feb 29 12:46:36 PM PST 24 Feb 29 12:46:37 PM PST 24 72580776 ps
T1124 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1864499134 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:07 PM PST 24 16604057 ps
T1125 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3077165239 Feb 29 12:46:32 PM PST 24 Feb 29 12:46:33 PM PST 24 195079925 ps
T60 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2999829143 Feb 29 12:46:04 PM PST 24 Feb 29 12:46:06 PM PST 24 62604099 ps
T79 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1562903324 Feb 29 12:45:55 PM PST 24 Feb 29 12:45:57 PM PST 24 204974348 ps
T1126 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1483272090 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:19 PM PST 24 571253733 ps
T1127 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1011777817 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:39 PM PST 24 56713794 ps
T1128 /workspace/coverage/cover_reg_top/42.uart_intr_test.1076903633 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:39 PM PST 24 33570726 ps
T57 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2555990728 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:39 PM PST 24 17611119 ps
T1129 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3419014690 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:17 PM PST 24 27640866 ps
T58 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2990720287 Feb 29 12:46:13 PM PST 24 Feb 29 12:46:16 PM PST 24 1034633082 ps
T1130 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2708656201 Feb 29 12:46:23 PM PST 24 Feb 29 12:46:25 PM PST 24 269276421 ps
T1131 /workspace/coverage/cover_reg_top/29.uart_intr_test.1361420550 Feb 29 12:46:40 PM PST 24 Feb 29 12:46:41 PM PST 24 44908056 ps
T1132 /workspace/coverage/cover_reg_top/4.uart_intr_test.2053749063 Feb 29 12:46:32 PM PST 24 Feb 29 12:46:33 PM PST 24 45827302 ps
T1133 /workspace/coverage/cover_reg_top/13.uart_tl_errors.199413788 Feb 29 12:46:20 PM PST 24 Feb 29 12:46:22 PM PST 24 153187251 ps
T1134 /workspace/coverage/cover_reg_top/17.uart_intr_test.710492665 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:46 PM PST 24 19175953 ps
T1135 /workspace/coverage/cover_reg_top/11.uart_intr_test.32184073 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:18 PM PST 24 14942192 ps
T1136 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1320459575 Feb 29 12:46:05 PM PST 24 Feb 29 12:46:06 PM PST 24 38473031 ps
T83 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3372781342 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:38 PM PST 24 141669750 ps
T1137 /workspace/coverage/cover_reg_top/45.uart_intr_test.1262196238 Feb 29 12:46:54 PM PST 24 Feb 29 12:47:00 PM PST 24 13272425 ps
T1138 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2506999328 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:26 PM PST 24 45297047 ps
T1139 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3830295909 Feb 29 12:45:58 PM PST 24 Feb 29 12:46:00 PM PST 24 79088581 ps
T1140 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4142258637 Feb 29 12:46:21 PM PST 24 Feb 29 12:46:22 PM PST 24 227651835 ps
T1141 /workspace/coverage/cover_reg_top/9.uart_intr_test.3282143737 Feb 29 12:46:36 PM PST 24 Feb 29 12:46:36 PM PST 24 26238911 ps
T1142 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1029309447 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:11 PM PST 24 319942611 ps
T59 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2575242433 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:04 PM PST 24 15263873 ps
T386 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3296627974 Feb 29 12:46:33 PM PST 24 Feb 29 12:46:34 PM PST 24 66809863 ps
T1143 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4018033354 Feb 29 12:46:14 PM PST 24 Feb 29 12:46:16 PM PST 24 58938351 ps
T387 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3492340817 Feb 29 12:46:14 PM PST 24 Feb 29 12:46:18 PM PST 24 175487462 ps
T1144 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2983026581 Feb 29 12:46:39 PM PST 24 Feb 29 12:46:40 PM PST 24 28636377 ps
T1145 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1322148694 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:49 PM PST 24 117955819 ps
T1146 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3150762630 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:18 PM PST 24 82308693 ps
T64 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3020301736 Feb 29 12:46:40 PM PST 24 Feb 29 12:46:41 PM PST 24 24947684 ps
T1147 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2537831296 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:21 PM PST 24 90363852 ps
T1148 /workspace/coverage/cover_reg_top/22.uart_intr_test.2816729220 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:47 PM PST 24 25804155 ps
T1149 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1704906455 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:28 PM PST 24 132501278 ps
T1150 /workspace/coverage/cover_reg_top/16.uart_intr_test.440491652 Feb 29 12:46:51 PM PST 24 Feb 29 12:46:52 PM PST 24 13188648 ps
T1151 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1248565350 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:39 PM PST 24 125460436 ps
T1152 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2515579442 Feb 29 12:46:27 PM PST 24 Feb 29 12:46:28 PM PST 24 28045764 ps
T1153 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1782707484 Feb 29 12:46:24 PM PST 24 Feb 29 12:46:24 PM PST 24 17660176 ps
T1154 /workspace/coverage/cover_reg_top/38.uart_intr_test.2556157639 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:35 PM PST 24 46723087 ps
T1155 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1481568701 Feb 29 12:46:28 PM PST 24 Feb 29 12:46:29 PM PST 24 22674273 ps
T1156 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1844790975 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:20 PM PST 24 25101928 ps
T1157 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3054263205 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:20 PM PST 24 345076488 ps
T1158 /workspace/coverage/cover_reg_top/25.uart_intr_test.410262523 Feb 29 12:46:40 PM PST 24 Feb 29 12:46:41 PM PST 24 27724251 ps
T1159 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.188282906 Feb 29 12:46:32 PM PST 24 Feb 29 12:46:33 PM PST 24 24602467 ps
T1160 /workspace/coverage/cover_reg_top/37.uart_intr_test.1291500345 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:31 PM PST 24 24282736 ps
T1161 /workspace/coverage/cover_reg_top/3.uart_intr_test.118757811 Feb 29 12:46:35 PM PST 24 Feb 29 12:46:36 PM PST 24 123269968 ps
T1162 /workspace/coverage/cover_reg_top/43.uart_intr_test.3095054310 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:38 PM PST 24 67201879 ps
T1163 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3155124615 Feb 29 12:46:29 PM PST 24 Feb 29 12:46:31 PM PST 24 179926759 ps
T1164 /workspace/coverage/cover_reg_top/33.uart_intr_test.3593140004 Feb 29 12:46:35 PM PST 24 Feb 29 12:46:36 PM PST 24 14088682 ps
T1165 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2616610534 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:35 PM PST 24 58441109 ps
T65 /workspace/coverage/cover_reg_top/16.uart_csr_rw.4038378087 Feb 29 12:46:25 PM PST 24 Feb 29 12:46:25 PM PST 24 16061430 ps
T1166 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1649738579 Feb 29 12:46:39 PM PST 24 Feb 29 12:46:41 PM PST 24 21720282 ps
T1167 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4201837482 Feb 29 12:46:18 PM PST 24 Feb 29 12:46:19 PM PST 24 241282091 ps
T1168 /workspace/coverage/cover_reg_top/21.uart_intr_test.1925954724 Feb 29 12:46:47 PM PST 24 Feb 29 12:46:48 PM PST 24 14798379 ps
T1169 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2207299256 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:38 PM PST 24 41338619 ps
T1170 /workspace/coverage/cover_reg_top/23.uart_intr_test.2382669869 Feb 29 12:46:41 PM PST 24 Feb 29 12:46:42 PM PST 24 91785908 ps
T1171 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1717339704 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:35 PM PST 24 33377871 ps
T1172 /workspace/coverage/cover_reg_top/8.uart_intr_test.3017852803 Feb 29 12:46:23 PM PST 24 Feb 29 12:46:23 PM PST 24 13794852 ps
T1173 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4150243880 Feb 29 12:46:48 PM PST 24 Feb 29 12:46:48 PM PST 24 37210809 ps
T1174 /workspace/coverage/cover_reg_top/14.uart_intr_test.3327779134 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:18 PM PST 24 12332016 ps
T1175 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2605287412 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:13 PM PST 24 82031852 ps
T1176 /workspace/coverage/cover_reg_top/47.uart_intr_test.174225719 Feb 29 12:46:33 PM PST 24 Feb 29 12:46:34 PM PST 24 16210417 ps
T1177 /workspace/coverage/cover_reg_top/24.uart_intr_test.1971674610 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:30 PM PST 24 38192771 ps
T1178 /workspace/coverage/cover_reg_top/15.uart_intr_test.2607380251 Feb 29 12:46:28 PM PST 24 Feb 29 12:46:28 PM PST 24 19227027 ps
T1179 /workspace/coverage/cover_reg_top/6.uart_intr_test.1075742276 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:15 PM PST 24 43508113 ps
T1180 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.97030444 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:27 PM PST 24 39151878 ps
T1181 /workspace/coverage/cover_reg_top/19.uart_intr_test.3083124520 Feb 29 12:46:24 PM PST 24 Feb 29 12:46:24 PM PST 24 53282846 ps
T1182 /workspace/coverage/cover_reg_top/12.uart_intr_test.3929932972 Feb 29 12:46:18 PM PST 24 Feb 29 12:46:19 PM PST 24 14746262 ps
T1183 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1228279465 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:31 PM PST 24 109294842 ps
T61 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3874519223 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:11 PM PST 24 46189122 ps
T1184 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3760121989 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:18 PM PST 24 64661306 ps
T1185 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2268407313 Feb 29 12:46:25 PM PST 24 Feb 29 12:46:25 PM PST 24 38188160 ps
T1186 /workspace/coverage/cover_reg_top/30.uart_intr_test.1092077567 Feb 29 12:46:27 PM PST 24 Feb 29 12:46:27 PM PST 24 13840010 ps
T1187 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3203540070 Feb 29 12:46:13 PM PST 24 Feb 29 12:46:16 PM PST 24 43363837 ps
T1188 /workspace/coverage/cover_reg_top/10.uart_intr_test.688906153 Feb 29 12:46:27 PM PST 24 Feb 29 12:46:28 PM PST 24 30970935 ps
T80 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3739868583 Feb 29 12:46:18 PM PST 24 Feb 29 12:46:20 PM PST 24 353852296 ps
T1189 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3202645677 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:11 PM PST 24 84653944 ps
T1190 /workspace/coverage/cover_reg_top/1.uart_intr_test.1298830649 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:04 PM PST 24 15113738 ps
T1191 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1424527838 Feb 29 12:46:15 PM PST 24 Feb 29 12:46:17 PM PST 24 39904769 ps
T1192 /workspace/coverage/cover_reg_top/41.uart_intr_test.392655986 Feb 29 12:46:24 PM PST 24 Feb 29 12:46:25 PM PST 24 15743143 ps
T1193 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2855535112 Feb 29 12:46:13 PM PST 24 Feb 29 12:46:15 PM PST 24 72876365 ps
T1194 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2136184038 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:39 PM PST 24 125941197 ps
T1195 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2849494352 Feb 29 12:46:33 PM PST 24 Feb 29 12:46:34 PM PST 24 17345514 ps
T1196 /workspace/coverage/cover_reg_top/4.uart_tl_errors.498348362 Feb 29 12:46:14 PM PST 24 Feb 29 12:46:18 PM PST 24 23424700 ps
T1197 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3416102318 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:14 PM PST 24 51454155 ps
T1198 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.481146081 Feb 29 12:46:33 PM PST 24 Feb 29 12:46:33 PM PST 24 17069180 ps
T385 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.366579166 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:28 PM PST 24 314381520 ps
T81 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3208500899 Feb 29 12:46:13 PM PST 24 Feb 29 12:46:16 PM PST 24 629156187 ps
T1199 /workspace/coverage/cover_reg_top/1.uart_csr_rw.4086582607 Feb 29 12:45:59 PM PST 24 Feb 29 12:46:00 PM PST 24 13988167 ps
T1200 /workspace/coverage/cover_reg_top/39.uart_intr_test.2685033429 Feb 29 12:46:44 PM PST 24 Feb 29 12:46:45 PM PST 24 10573077 ps
T1201 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2687452654 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:32 PM PST 24 104404754 ps
T1202 /workspace/coverage/cover_reg_top/46.uart_intr_test.2560658996 Feb 29 12:46:36 PM PST 24 Feb 29 12:46:37 PM PST 24 98615526 ps
T1203 /workspace/coverage/cover_reg_top/5.uart_intr_test.2447888818 Feb 29 12:46:09 PM PST 24 Feb 29 12:46:11 PM PST 24 43030037 ps
T1204 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2698026712 Feb 29 12:46:14 PM PST 24 Feb 29 12:46:16 PM PST 24 80546092 ps
T1205 /workspace/coverage/cover_reg_top/40.uart_intr_test.3186935897 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:31 PM PST 24 10726749 ps
T1206 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2697640510 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:18 PM PST 24 12053197 ps
T1207 /workspace/coverage/cover_reg_top/34.uart_intr_test.4089889849 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:47 PM PST 24 52025499 ps
T1208 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.484998788 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:27 PM PST 24 44731649 ps
T1209 /workspace/coverage/cover_reg_top/31.uart_intr_test.764630071 Feb 29 12:46:26 PM PST 24 Feb 29 12:46:27 PM PST 24 33795497 ps
T1210 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3109789514 Feb 29 12:46:31 PM PST 24 Feb 29 12:46:33 PM PST 24 225644226 ps
T84 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.884931366 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:36 PM PST 24 258964157 ps
T1211 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3589795147 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:35 PM PST 24 340983903 ps
T1212 /workspace/coverage/cover_reg_top/6.uart_tl_errors.411843033 Feb 29 12:46:30 PM PST 24 Feb 29 12:46:32 PM PST 24 106905925 ps
T1213 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2933612616 Feb 29 12:46:33 PM PST 24 Feb 29 12:46:34 PM PST 24 14424919 ps
T1214 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.838346680 Feb 29 12:46:08 PM PST 24 Feb 29 12:46:10 PM PST 24 283944283 ps
T1215 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1776942461 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:14 PM PST 24 14582007 ps
T1216 /workspace/coverage/cover_reg_top/27.uart_intr_test.1208361069 Feb 29 12:46:31 PM PST 24 Feb 29 12:46:31 PM PST 24 38701511 ps
T1217 /workspace/coverage/cover_reg_top/1.uart_tl_errors.928370372 Feb 29 12:46:18 PM PST 24 Feb 29 12:46:20 PM PST 24 119665884 ps
T1218 /workspace/coverage/cover_reg_top/2.uart_intr_test.132683628 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:13 PM PST 24 13402130 ps
T82 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1638827277 Feb 29 12:46:09 PM PST 24 Feb 29 12:46:11 PM PST 24 175434536 ps
T62 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2483165095 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:14 PM PST 24 24787436 ps
T1219 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.187764695 Feb 29 12:46:19 PM PST 24 Feb 29 12:46:21 PM PST 24 903057291 ps
T1220 /workspace/coverage/cover_reg_top/32.uart_intr_test.3770578902 Feb 29 12:46:40 PM PST 24 Feb 29 12:46:42 PM PST 24 30051714 ps
T1221 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1547668601 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:19 PM PST 24 479979658 ps
T1222 /workspace/coverage/cover_reg_top/26.uart_intr_test.2306661019 Feb 29 12:46:38 PM PST 24 Feb 29 12:46:38 PM PST 24 38966216 ps
T1223 /workspace/coverage/cover_reg_top/18.uart_intr_test.702310872 Feb 29 12:46:34 PM PST 24 Feb 29 12:46:34 PM PST 24 55018662 ps
T1224 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1971413131 Feb 29 12:46:16 PM PST 24 Feb 29 12:46:18 PM PST 24 131183630 ps
T1225 /workspace/coverage/cover_reg_top/35.uart_intr_test.420947972 Feb 29 12:46:45 PM PST 24 Feb 29 12:46:46 PM PST 24 19554964 ps
T1226 /workspace/coverage/cover_reg_top/36.uart_intr_test.3242635334 Feb 29 12:46:46 PM PST 24 Feb 29 12:46:46 PM PST 24 47656990 ps
T1227 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.805379859 Feb 29 12:46:07 PM PST 24 Feb 29 12:46:09 PM PST 24 415783810 ps
T63 /workspace/coverage/cover_reg_top/12.uart_csr_rw.734747540 Feb 29 12:46:32 PM PST 24 Feb 29 12:46:33 PM PST 24 21056205 ps
T1228 /workspace/coverage/cover_reg_top/7.uart_intr_test.4072460231 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:12 PM PST 24 16733141 ps
T1229 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4155253528 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:14 PM PST 24 102313960 ps
T1230 /workspace/coverage/cover_reg_top/44.uart_intr_test.338189406 Feb 29 12:46:37 PM PST 24 Feb 29 12:46:38 PM PST 24 125303465 ps
T1231 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2056471297 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:14 PM PST 24 114340197 ps
T1232 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2590924445 Feb 29 12:46:17 PM PST 24 Feb 29 12:46:18 PM PST 24 50185002 ps

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4230963751
Short name T8
Test name
Test status
Simulation time 62254708997 ps
CPU time 1383.8 seconds
Started Feb 29 01:23:08 PM PST 24
Finished Feb 29 01:46:13 PM PST 24
Peak memory 224440 kb
Host smart-2189caa4-9da9-4d40-b093-141b8694b489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230963751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4230963751
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all.2030704962
Short name T296
Test name
Test status
Simulation time 442251511933 ps
CPU time 1119.88 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 199572 kb
Host smart-8b04d215-1257-4444-9232-72a7ec8dc2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030704962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2030704962
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.1893377636
Short name T15
Test name
Test status
Simulation time 1380695605561 ps
CPU time 2538.66 seconds
Started Feb 29 01:22:24 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 199640 kb
Host smart-aacccec5-8a75-429f-843e-b1e1687d7758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893377636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1893377636
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2934006103
Short name T1
Test name
Test status
Simulation time 36839844199 ps
CPU time 36.8 seconds
Started Feb 29 01:23:30 PM PST 24
Finished Feb 29 01:24:07 PM PST 24
Peak memory 199460 kb
Host smart-56fbddde-a995-4d27-8abb-afbb5bc35139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934006103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2934006103
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3568475489
Short name T29
Test name
Test status
Simulation time 544771304852 ps
CPU time 1133.27 seconds
Started Feb 29 01:23:29 PM PST 24
Finished Feb 29 01:42:23 PM PST 24
Peak memory 224352 kb
Host smart-de99db65-4ab6-4a28-8c6f-7c89272cb2c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568475489 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3568475489
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.492965423
Short name T167
Test name
Test status
Simulation time 339513227499 ps
CPU time 940.13 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:35:08 PM PST 24
Peak memory 215652 kb
Host smart-2abfba9d-36f4-459e-a5ca-2641d9afc8a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492965423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.492965423
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2904869501
Short name T42
Test name
Test status
Simulation time 188043794847 ps
CPU time 532.8 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:28:21 PM PST 24
Peak memory 199816 kb
Host smart-75c40d59-5871-4589-8cc8-a48caa91dcf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904869501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2904869501
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2051028260
Short name T53
Test name
Test status
Simulation time 162465492439 ps
CPU time 765.25 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:34:31 PM PST 24
Peak memory 216252 kb
Host smart-43b0e4bc-c0e6-4f61-9c76-e5abc90a5bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051028260 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2051028260
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2543540226
Short name T233
Test name
Test status
Simulation time 246376345618 ps
CPU time 153.72 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:24:56 PM PST 24
Peak memory 199560 kb
Host smart-e4e220d1-9a1b-4355-88cc-338621c5af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543540226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2543540226
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_intr.3583331910
Short name T16
Test name
Test status
Simulation time 57398664480 ps
CPU time 102.22 seconds
Started Feb 29 01:20:50 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 199528 kb
Host smart-95ad680a-55e4-4438-8708-1cf2f8ec4e37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583331910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3583331910
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/0.uart_sec_cm.678936090
Short name T24
Test name
Test status
Simulation time 59219690 ps
CPU time 0.85 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:44 PM PST 24
Peak memory 217120 kb
Host smart-220c4d1a-f43c-40d2-9716-cf12c3ec0c38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678936090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.678936090
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2635613651
Short name T390
Test name
Test status
Simulation time 133880117928 ps
CPU time 215.35 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:22:28 PM PST 24
Peak memory 199768 kb
Host smart-35e09fcb-9a2b-43da-a0a0-14ce9b702c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635613651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2635613651
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_alert_test.842004969
Short name T470
Test name
Test status
Simulation time 44505450 ps
CPU time 0.57 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:32 PM PST 24
Peak memory 194064 kb
Host smart-0cc4b9cf-5f0c-4a00-a0d2-7c6abc3a6884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842004969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.842004969
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2757673074
Short name T2
Test name
Test status
Simulation time 216847455590 ps
CPU time 360.75 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:25:11 PM PST 24
Peak memory 199504 kb
Host smart-d3564b08-9822-4805-b0bb-fab8debb3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757673074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2757673074
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_stress_all.692680333
Short name T147
Test name
Test status
Simulation time 274642412490 ps
CPU time 126.51 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:21:16 PM PST 24
Peak memory 215872 kb
Host smart-e523c3d8-0267-4b02-a939-9eac7c21089b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692680333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.692680333
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.449652017
Short name T144
Test name
Test status
Simulation time 91871757857 ps
CPU time 150.21 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:24:16 PM PST 24
Peak memory 199572 kb
Host smart-bdfe6c91-9199-492e-b04e-b518ff0caa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449652017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.449652017
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2147733960
Short name T232
Test name
Test status
Simulation time 480780378500 ps
CPU time 87.16 seconds
Started Feb 29 01:22:44 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199564 kb
Host smart-eda28b56-573e-437a-bd0d-0025352bc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147733960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2147733960
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3739868583
Short name T80
Test name
Test status
Simulation time 353852296 ps
CPU time 1.31 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:46:20 PM PST 24
Peak memory 199120 kb
Host smart-4fe533e5-1bd8-4581-84e2-0849a31ee261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739868583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3739868583
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3653818085
Short name T401
Test name
Test status
Simulation time 88139283156 ps
CPU time 243.09 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:26:25 PM PST 24
Peak memory 199640 kb
Host smart-f9ba9123-0cf1-46c9-998f-d5f53ec5c979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653818085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3653818085
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_stress_all.2704590057
Short name T422
Test name
Test status
Simulation time 268507860725 ps
CPU time 160.2 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:22:10 PM PST 24
Peak memory 207960 kb
Host smart-8b6f3eb6-32b4-49e0-b9d0-6fb85f507dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704590057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2704590057
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2970736349
Short name T32
Test name
Test status
Simulation time 197365374429 ps
CPU time 1180.79 seconds
Started Feb 29 01:20:48 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 216664 kb
Host smart-78b6e72c-9043-4343-ad39-05768323d808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970736349 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2970736349
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1444523427
Short name T7
Test name
Test status
Simulation time 126220845072 ps
CPU time 52.47 seconds
Started Feb 29 01:23:41 PM PST 24
Finished Feb 29 01:24:34 PM PST 24
Peak memory 199524 kb
Host smart-daac497f-cd61-4200-8544-d7db5ced3140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444523427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1444523427
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3355986565
Short name T336
Test name
Test status
Simulation time 114060647367 ps
CPU time 17.83 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:18:59 PM PST 24
Peak memory 199592 kb
Host smart-c8725743-0d13-4bf6-ab96-7f5c91390799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355986565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3355986565
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_tx_rx.434882252
Short name T154
Test name
Test status
Simulation time 80630041326 ps
CPU time 41.07 seconds
Started Feb 29 01:18:40 PM PST 24
Finished Feb 29 01:19:21 PM PST 24
Peak memory 199604 kb
Host smart-c1809e0c-475b-4206-b37d-2d823032a729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434882252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.434882252
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.460300486
Short name T96
Test name
Test status
Simulation time 14615765973 ps
CPU time 67.85 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:23:18 PM PST 24
Peak memory 215076 kb
Host smart-241092a8-a7aa-48c6-94b9-74c0513d5589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460300486 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.460300486
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2990720287
Short name T58
Test name
Test status
Simulation time 1034633082 ps
CPU time 2.21 seconds
Started Feb 29 12:46:13 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 195420 kb
Host smart-a1fba18f-2ab5-465c-8e20-5ac0086b0216
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990720287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2990720287
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4033484065
Short name T67
Test name
Test status
Simulation time 142945511 ps
CPU time 0.75 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:17 PM PST 24
Peak memory 196904 kb
Host smart-6196aea9-9983-475a-b3d9-17fda303f437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033484065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4033484065
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3487912856
Short name T275
Test name
Test status
Simulation time 73573244815 ps
CPU time 32.91 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:24:16 PM PST 24
Peak memory 199612 kb
Host smart-282d2b8d-bb4f-4a74-a537-69367f88f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487912856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3487912856
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3458843539
Short name T43
Test name
Test status
Simulation time 29600787468 ps
CPU time 20.59 seconds
Started Feb 29 01:23:48 PM PST 24
Finished Feb 29 01:24:08 PM PST 24
Peak memory 199540 kb
Host smart-87d1d371-5ff4-43f9-b4fe-129e2d25d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458843539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3458843539
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3740787600
Short name T169
Test name
Test status
Simulation time 97174756906 ps
CPU time 161.37 seconds
Started Feb 29 01:21:06 PM PST 24
Finished Feb 29 01:23:47 PM PST 24
Peak memory 199544 kb
Host smart-636bf5f3-c6d9-49ce-860c-a7ec27fca1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740787600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3740787600
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3178327819
Short name T145
Test name
Test status
Simulation time 193934579970 ps
CPU time 45.37 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:24 PM PST 24
Peak memory 199520 kb
Host smart-594604aa-625c-4cc8-9a60-af76947b6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178327819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3178327819
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4272831049
Short name T238
Test name
Test status
Simulation time 86992291897 ps
CPU time 119.37 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:26:28 PM PST 24
Peak memory 199568 kb
Host smart-431bc47d-2b04-4757-a205-99a5d1f3fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272831049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4272831049
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.699515581
Short name T98
Test name
Test status
Simulation time 105347091465 ps
CPU time 254.06 seconds
Started Feb 29 01:23:17 PM PST 24
Finished Feb 29 01:27:31 PM PST 24
Peak memory 214484 kb
Host smart-5ec9dc8e-64a1-4566-a415-0c67f59f4861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699515581 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.699515581
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3108893508
Short name T159
Test name
Test status
Simulation time 135838628100 ps
CPU time 180.33 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:22:27 PM PST 24
Peak memory 199224 kb
Host smart-f3071b9c-b0a3-454e-a557-913746e854d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108893508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3108893508
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1042066908
Short name T176
Test name
Test status
Simulation time 162989351533 ps
CPU time 123.02 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:26:31 PM PST 24
Peak memory 199552 kb
Host smart-faa40a77-5d72-4503-9317-b5e361a2d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042066908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1042066908
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2398022502
Short name T119
Test name
Test status
Simulation time 24665960241 ps
CPU time 21.45 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:23:50 PM PST 24
Peak memory 199628 kb
Host smart-7410b21b-166c-4dce-b1f1-0b204bfa467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398022502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2398022502
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.884931366
Short name T84
Test name
Test status
Simulation time 258964157 ps
CPU time 1.23 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:36 PM PST 24
Peak memory 199140 kb
Host smart-370fde13-deeb-46ad-9fbd-0178be474bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884931366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.884931366
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.198634416
Short name T11
Test name
Test status
Simulation time 64554805193 ps
CPU time 839.32 seconds
Started Feb 29 01:22:27 PM PST 24
Finished Feb 29 01:36:27 PM PST 24
Peak memory 225240 kb
Host smart-9baabd77-2baa-40e0-a587-557b040285a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198634416 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.198634416
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2199125486
Short name T197
Test name
Test status
Simulation time 30462026871 ps
CPU time 45.6 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:24:14 PM PST 24
Peak memory 199240 kb
Host smart-52f17950-afb7-4bb9-a757-b008756d72a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199125486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2199125486
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2358454432
Short name T78
Test name
Test status
Simulation time 125204086 ps
CPU time 1.31 seconds
Started Feb 29 12:46:28 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 199284 kb
Host smart-078a5a21-ae45-43b4-a9a9-11531d72b0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358454432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2358454432
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3752512078
Short name T432
Test name
Test status
Simulation time 50854993976 ps
CPU time 49.8 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 199616 kb
Host smart-db84d334-340b-4552-9fe7-4f0a64756bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752512078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3752512078
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2802522954
Short name T178
Test name
Test status
Simulation time 26433571399 ps
CPU time 39.46 seconds
Started Feb 29 01:23:37 PM PST 24
Finished Feb 29 01:24:17 PM PST 24
Peak memory 199544 kb
Host smart-7a0a2f19-41ab-4e96-924d-7c22edfabad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802522954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2802522954
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1040599897
Short name T191
Test name
Test status
Simulation time 21101938858 ps
CPU time 17.59 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:24:01 PM PST 24
Peak memory 199296 kb
Host smart-fb65bda8-1891-4740-a7d5-3478e4935b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040599897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1040599897
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3251235500
Short name T245
Test name
Test status
Simulation time 20943616534 ps
CPU time 23.97 seconds
Started Feb 29 01:24:01 PM PST 24
Finished Feb 29 01:24:25 PM PST 24
Peak memory 199560 kb
Host smart-bf017e48-d5e0-4e6c-9069-5f9ee5dceb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251235500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3251235500
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.685708334
Short name T241
Test name
Test status
Simulation time 38058106419 ps
CPU time 16.19 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:45 PM PST 24
Peak memory 199588 kb
Host smart-4bc6c562-be90-4455-8336-19cf1244dcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685708334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.685708334
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2540266371
Short name T155
Test name
Test status
Simulation time 46194174474 ps
CPU time 60.63 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:40 PM PST 24
Peak memory 199628 kb
Host smart-5ef2c71e-c59d-4246-898c-40d4ce41d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540266371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2540266371
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.627086023
Short name T326
Test name
Test status
Simulation time 112692442836 ps
CPU time 186.52 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:27:59 PM PST 24
Peak memory 199564 kb
Host smart-68112f86-0cc1-46af-b322-a38e167c44c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627086023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.627086023
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1519802044
Short name T206
Test name
Test status
Simulation time 88519265758 ps
CPU time 135.52 seconds
Started Feb 29 01:23:45 PM PST 24
Finished Feb 29 01:26:01 PM PST 24
Peak memory 199560 kb
Host smart-60bf08e3-2241-4bcf-a08f-1182f9e791c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519802044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1519802044
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.139957612
Short name T265
Test name
Test status
Simulation time 95257967004 ps
CPU time 23.62 seconds
Started Feb 29 01:23:47 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199504 kb
Host smart-2cd63447-4b2b-4784-9dc5-ddfcb6069099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139957612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.139957612
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2981699671
Short name T122
Test name
Test status
Simulation time 32175359238 ps
CPU time 61.72 seconds
Started Feb 29 01:23:49 PM PST 24
Finished Feb 29 01:24:51 PM PST 24
Peak memory 199560 kb
Host smart-f0224a34-2573-485c-b807-33ea7bcdb319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981699671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2981699671
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1272517657
Short name T143
Test name
Test status
Simulation time 42805419774 ps
CPU time 38.07 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:19:19 PM PST 24
Peak memory 199028 kb
Host smart-061602de-0838-4db1-bcfc-017d6713f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272517657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1272517657
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1104626330
Short name T237
Test name
Test status
Simulation time 32425959703 ps
CPU time 53.68 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:33 PM PST 24
Peak memory 199472 kb
Host smart-2cfaaff7-5996-48a3-adee-1ab3ba3e6baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104626330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1104626330
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2736147064
Short name T347
Test name
Test status
Simulation time 65346181468 ps
CPU time 17.49 seconds
Started Feb 29 01:24:55 PM PST 24
Finished Feb 29 01:25:13 PM PST 24
Peak memory 199572 kb
Host smart-38dbd7d0-4746-417f-8d9c-0fc83de91aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736147064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2736147064
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1856208498
Short name T174
Test name
Test status
Simulation time 196410706259 ps
CPU time 112.83 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:25:46 PM PST 24
Peak memory 199416 kb
Host smart-6a4badeb-8e8d-4f3d-8755-b5a244857223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856208498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1856208498
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1165523898
Short name T358
Test name
Test status
Simulation time 20505183205 ps
CPU time 33.73 seconds
Started Feb 29 01:23:54 PM PST 24
Finished Feb 29 01:24:28 PM PST 24
Peak memory 199476 kb
Host smart-8b98c2f8-a944-44b0-9367-393a17fbfde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165523898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1165523898
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2242050560
Short name T288
Test name
Test status
Simulation time 3628117171 ps
CPU time 6.39 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:05 PM PST 24
Peak memory 198456 kb
Host smart-6184ff89-7918-4248-8181-7efd59e1ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242050560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2242050560
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3275185126
Short name T189
Test name
Test status
Simulation time 130147107187 ps
CPU time 55.84 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:25:24 PM PST 24
Peak memory 199544 kb
Host smart-c5f76eb5-20ac-435f-b63f-dae70f2d0573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275185126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3275185126
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2380866068
Short name T340
Test name
Test status
Simulation time 73813169262 ps
CPU time 43.27 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:25:26 PM PST 24
Peak memory 199652 kb
Host smart-e3370e53-f2ff-4657-9e36-7abc94c33541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380866068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2380866068
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2214652711
Short name T247
Test name
Test status
Simulation time 18460349524 ps
CPU time 27.22 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:49 PM PST 24
Peak memory 198664 kb
Host smart-dc89c899-67d4-4304-ae58-5e618f9ba573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214652711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2214652711
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1965088471
Short name T351
Test name
Test status
Simulation time 150299913756 ps
CPU time 206.95 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:27:05 PM PST 24
Peak memory 198692 kb
Host smart-e31c0793-b760-44d8-bb6a-1124507097fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965088471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1965088471
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2940996799
Short name T360
Test name
Test status
Simulation time 134051802293 ps
CPU time 18.22 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:47 PM PST 24
Peak memory 199592 kb
Host smart-3e9ead86-7196-42c9-a15e-9ee8edf7c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940996799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2940996799
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1991943727
Short name T568
Test name
Test status
Simulation time 77111166291 ps
CPU time 93.86 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:25:27 PM PST 24
Peak memory 199552 kb
Host smart-c8841d9a-1cc5-489e-a790-0ef1fcff0b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991943727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1991943727
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.44953971
Short name T211
Test name
Test status
Simulation time 90864757513 ps
CPU time 41.41 seconds
Started Feb 29 01:23:48 PM PST 24
Finished Feb 29 01:24:30 PM PST 24
Peak memory 199636 kb
Host smart-d2985cd9-19f7-43e5-b243-961552f05348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44953971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.44953971
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2068805736
Short name T115
Test name
Test status
Simulation time 8081044014 ps
CPU time 4.02 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:23:55 PM PST 24
Peak memory 199460 kb
Host smart-73b1df35-9599-469a-8540-b8b5abc6a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068805736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2068805736
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.520868621
Short name T342
Test name
Test status
Simulation time 9758456559 ps
CPU time 15.35 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:14 PM PST 24
Peak memory 199844 kb
Host smart-a12b2b07-2bf4-44ee-8fbe-b258cac70dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520868621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.520868621
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.901829497
Short name T170
Test name
Test status
Simulation time 16601427818 ps
CPU time 35.92 seconds
Started Feb 29 01:24:05 PM PST 24
Finished Feb 29 01:24:41 PM PST 24
Peak memory 199624 kb
Host smart-dfce96bc-8c4d-4a5d-bf8e-87fda96c12d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901829497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.901829497
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1301593131
Short name T36
Test name
Test status
Simulation time 63716195569 ps
CPU time 15.16 seconds
Started Feb 29 01:24:27 PM PST 24
Finished Feb 29 01:24:43 PM PST 24
Peak memory 199520 kb
Host smart-2484645e-f398-4ac5-84ba-36c4ccf1040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301593131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1301593131
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4078719393
Short name T235
Test name
Test status
Simulation time 62737447270 ps
CPU time 24.41 seconds
Started Feb 29 01:24:29 PM PST 24
Finished Feb 29 01:24:54 PM PST 24
Peak memory 199620 kb
Host smart-72179326-b85d-4f50-a8ee-e0435ffb171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078719393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4078719393
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1558499316
Short name T374
Test name
Test status
Simulation time 388701014617 ps
CPU time 163.53 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:21:25 PM PST 24
Peak memory 199612 kb
Host smart-95f1a139-262d-449c-b8f6-edef9c955e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558499316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1558499316
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.440644465
Short name T261
Test name
Test status
Simulation time 35549808231 ps
CPU time 52.34 seconds
Started Feb 29 01:24:32 PM PST 24
Finished Feb 29 01:25:25 PM PST 24
Peak memory 199564 kb
Host smart-b72cc066-9d3c-45cb-8505-4ff61dea2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440644465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.440644465
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2083243636
Short name T314
Test name
Test status
Simulation time 22279544427 ps
CPU time 11.72 seconds
Started Feb 29 01:20:21 PM PST 24
Finished Feb 29 01:20:33 PM PST 24
Peak memory 197788 kb
Host smart-adc3970a-1f29-4bdc-a38f-d05da148a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083243636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2083243636
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1903255366
Short name T363
Test name
Test status
Simulation time 265731358676 ps
CPU time 183.09 seconds
Started Feb 29 01:24:31 PM PST 24
Finished Feb 29 01:27:35 PM PST 24
Peak memory 199600 kb
Host smart-019bb143-479e-45f0-84fc-9c03bc714a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903255366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1903255366
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2658791064
Short name T312
Test name
Test status
Simulation time 161691630888 ps
CPU time 58.82 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:39 PM PST 24
Peak memory 199560 kb
Host smart-25d56cf7-ea4e-4552-8a8c-2e454cfbdfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658791064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2658791064
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1709318737
Short name T138
Test name
Test status
Simulation time 18782206767 ps
CPU time 17.56 seconds
Started Feb 29 01:24:44 PM PST 24
Finished Feb 29 01:25:02 PM PST 24
Peak memory 199536 kb
Host smart-80390152-a418-4940-a4ad-59305f1cac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709318737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1709318737
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.938910663
Short name T329
Test name
Test status
Simulation time 76146814968 ps
CPU time 29.13 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:22:49 PM PST 24
Peak memory 199412 kb
Host smart-3d49ed33-20b1-43e2-9335-adaeec5a46e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938910663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.938910663
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3540384342
Short name T355
Test name
Test status
Simulation time 40835107917 ps
CPU time 12.83 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 199632 kb
Host smart-b8218c24-2d5a-43ff-932a-b8a766343236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540384342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3540384342
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.750638149
Short name T339
Test name
Test status
Simulation time 78632460684 ps
CPU time 63.31 seconds
Started Feb 29 01:23:10 PM PST 24
Finished Feb 29 01:24:13 PM PST 24
Peak memory 199492 kb
Host smart-99c04452-50cf-4eb1-a4aa-53d8acff5663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750638149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.750638149
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2627300848
Short name T373
Test name
Test status
Simulation time 123841398472 ps
CPU time 43.4 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:19:27 PM PST 24
Peak memory 199064 kb
Host smart-1dc89372-a1ad-439c-a26b-8f97cc14b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627300848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2627300848
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_stress_all.2924247941
Short name T308
Test name
Test status
Simulation time 260235044809 ps
CPU time 572.61 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:28:16 PM PST 24
Peak memory 199568 kb
Host smart-108bc6d1-526f-43d7-b36a-18eb457105ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924247941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2924247941
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.3082724736
Short name T297
Test name
Test status
Simulation time 525682708793 ps
CPU time 2076.76 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:54:07 PM PST 24
Peak memory 199556 kb
Host smart-10801c3d-66c4-4dde-800a-5d9eacd9733e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082724736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3082724736
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.344461159
Short name T447
Test name
Test status
Simulation time 120228237057 ps
CPU time 1240.65 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 224880 kb
Host smart-ef39b5e7-0f5e-438c-ab74-da14d35cdfd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344461159 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.344461159
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1000500355
Short name T367
Test name
Test status
Simulation time 121738247466 ps
CPU time 24.69 seconds
Started Feb 29 01:19:30 PM PST 24
Finished Feb 29 01:19:55 PM PST 24
Peak memory 198560 kb
Host smart-8f781885-73c3-45d2-ade4-53abe603f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000500355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1000500355
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3401554834
Short name T184
Test name
Test status
Simulation time 38295852232 ps
CPU time 456.9 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:27:08 PM PST 24
Peak memory 216132 kb
Host smart-0d6dc3cb-aa7a-4dd9-93e8-f67603b3330c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401554834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3401554834
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1482323004
Short name T305
Test name
Test status
Simulation time 166645517323 ps
CPU time 269.8 seconds
Started Feb 29 01:23:40 PM PST 24
Finished Feb 29 01:28:10 PM PST 24
Peak memory 199544 kb
Host smart-5787dc77-3ba9-4df6-8b1c-b303406443f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482323004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1482323004
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2781663866
Short name T199
Test name
Test status
Simulation time 15822902773 ps
CPU time 21.71 seconds
Started Feb 29 01:23:40 PM PST 24
Finished Feb 29 01:24:02 PM PST 24
Peak memory 199724 kb
Host smart-a28292fc-8c08-4069-9bd2-287d28aa78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781663866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2781663866
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3599312072
Short name T321
Test name
Test status
Simulation time 306302392720 ps
CPU time 27.34 seconds
Started Feb 29 01:23:44 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199632 kb
Host smart-23c406b9-bf2f-484a-bb6e-8fd07268789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599312072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3599312072
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2612092483
Short name T269
Test name
Test status
Simulation time 9614789973 ps
CPU time 13.48 seconds
Started Feb 29 01:23:47 PM PST 24
Finished Feb 29 01:24:01 PM PST 24
Peak memory 199532 kb
Host smart-c5310d48-6bb3-4e72-9f48-408fbec27467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612092483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2612092483
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3765664057
Short name T378
Test name
Test status
Simulation time 358620679778 ps
CPU time 32.38 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:24:26 PM PST 24
Peak memory 199336 kb
Host smart-27b2f99d-d0b4-4b8f-81e5-409959cc385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765664057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3765664057
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.818458533
Short name T223
Test name
Test status
Simulation time 29544001746 ps
CPU time 26.08 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:24:19 PM PST 24
Peak memory 199496 kb
Host smart-4c20b0cb-2ee8-4506-8e1e-0e9d7f2c2766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818458533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.818458533
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2330993476
Short name T278
Test name
Test status
Simulation time 36523549512 ps
CPU time 55.67 seconds
Started Feb 29 01:19:44 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 199532 kb
Host smart-e1a6508c-3514-4dc3-b701-97dfd60d1df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330993476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2330993476
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.980945508
Short name T44
Test name
Test status
Simulation time 47340352932 ps
CPU time 33.89 seconds
Started Feb 29 01:19:45 PM PST 24
Finished Feb 29 01:20:19 PM PST 24
Peak memory 199620 kb
Host smart-8a3b3ce5-4359-4911-ab27-bbf30fd695fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980945508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.980945508
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.4086858112
Short name T6
Test name
Test status
Simulation time 82130541299 ps
CPU time 21.26 seconds
Started Feb 29 01:23:52 PM PST 24
Finished Feb 29 01:24:13 PM PST 24
Peak memory 199332 kb
Host smart-7de9f953-951e-4964-99e8-c7c233b3e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086858112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4086858112
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2144180556
Short name T286
Test name
Test status
Simulation time 74378389550 ps
CPU time 58.86 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:24:50 PM PST 24
Peak memory 199484 kb
Host smart-2d6272b1-00ac-4838-898b-1b5096c8adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144180556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2144180556
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2888597296
Short name T257
Test name
Test status
Simulation time 84396538009 ps
CPU time 34.64 seconds
Started Feb 29 01:20:00 PM PST 24
Finished Feb 29 01:20:34 PM PST 24
Peak memory 199552 kb
Host smart-0bcdc51a-eb2e-4326-9046-586039294d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888597296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2888597296
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.426501006
Short name T335
Test name
Test status
Simulation time 80510170184 ps
CPU time 24.85 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:53 PM PST 24
Peak memory 199484 kb
Host smart-5d14628e-2a08-4ed9-90ac-de29b19d434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426501006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.426501006
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.289861324
Short name T272
Test name
Test status
Simulation time 40421529659 ps
CPU time 72.64 seconds
Started Feb 29 01:20:14 PM PST 24
Finished Feb 29 01:21:26 PM PST 24
Peak memory 199172 kb
Host smart-dbd201d8-ff9d-490a-bbd2-561be94d5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289861324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.289861324
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4240542272
Short name T323
Test name
Test status
Simulation time 23815453626 ps
CPU time 22.33 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:51 PM PST 24
Peak memory 199828 kb
Host smart-a7c85b88-db22-47f4-9412-c2c87c1b99c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240542272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4240542272
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1249649196
Short name T294
Test name
Test status
Simulation time 26594484875 ps
CPU time 11.16 seconds
Started Feb 29 01:24:27 PM PST 24
Finished Feb 29 01:24:38 PM PST 24
Peak memory 199560 kb
Host smart-871295bb-c2ec-431e-96cf-5e1d4ca80415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249649196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1249649196
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3012563906
Short name T192
Test name
Test status
Simulation time 45915546212 ps
CPU time 82.13 seconds
Started Feb 29 01:24:32 PM PST 24
Finished Feb 29 01:25:55 PM PST 24
Peak memory 199564 kb
Host smart-8eb12477-4ee1-481f-9de9-300441f4ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012563906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3012563906
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.965546841
Short name T121
Test name
Test status
Simulation time 160412415702 ps
CPU time 26.86 seconds
Started Feb 29 01:24:31 PM PST 24
Finished Feb 29 01:24:58 PM PST 24
Peak memory 199596 kb
Host smart-ee58329e-5de2-4d45-ba5a-75e044069af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965546841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.965546841
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3618232000
Short name T375
Test name
Test status
Simulation time 126283869311 ps
CPU time 99.82 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:26:19 PM PST 24
Peak memory 199360 kb
Host smart-1bb166b5-f748-46ad-94a3-564d5180c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618232000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3618232000
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1831290566
Short name T346
Test name
Test status
Simulation time 60715116863 ps
CPU time 43.55 seconds
Started Feb 29 01:24:36 PM PST 24
Finished Feb 29 01:25:20 PM PST 24
Peak memory 199180 kb
Host smart-d7ed8b94-24a1-486f-96f8-840952761e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831290566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1831290566
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1571542175
Short name T204
Test name
Test status
Simulation time 67233310300 ps
CPU time 27.36 seconds
Started Feb 29 01:24:36 PM PST 24
Finished Feb 29 01:25:04 PM PST 24
Peak memory 199556 kb
Host smart-54fd9b58-2150-4bd0-b58a-b0053fa6c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571542175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1571542175
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4188349093
Short name T219
Test name
Test status
Simulation time 19893527679 ps
CPU time 37.31 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:17 PM PST 24
Peak memory 199472 kb
Host smart-015b5ddc-9497-4261-bccf-7a01272e9992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188349093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4188349093
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3660486577
Short name T134
Test name
Test status
Simulation time 126048421189 ps
CPU time 36.72 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:25:15 PM PST 24
Peak memory 199548 kb
Host smart-e727ae78-812f-4d9b-a3bf-5e3a62d5ff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660486577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3660486577
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.711106337
Short name T362
Test name
Test status
Simulation time 20701445840 ps
CPU time 30.87 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:21:21 PM PST 24
Peak memory 199524 kb
Host smart-a2e0c19a-9032-46bf-ae30-8c50c2d6d3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711106337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.711106337
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.157103645
Short name T285
Test name
Test status
Simulation time 25133198798 ps
CPU time 41.45 seconds
Started Feb 29 01:24:50 PM PST 24
Finished Feb 29 01:25:32 PM PST 24
Peak memory 199540 kb
Host smart-818360c1-0997-44ba-a4ae-3909cf13ee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157103645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.157103645
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2748786421
Short name T187
Test name
Test status
Simulation time 112011578932 ps
CPU time 233.85 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:28:46 PM PST 24
Peak memory 199624 kb
Host smart-014070d9-3f39-489b-95a3-3cf7fcbde8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748786421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2748786421
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_full.404346481
Short name T290
Test name
Test status
Simulation time 101760148491 ps
CPU time 83.72 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 199476 kb
Host smart-e23fe095-4eb5-4bb3-b1c8-c136d7592499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404346481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.404346481
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2440809602
Short name T293
Test name
Test status
Simulation time 22577155417 ps
CPU time 33.21 seconds
Started Feb 29 01:21:58 PM PST 24
Finished Feb 29 01:22:32 PM PST 24
Peak memory 199184 kb
Host smart-cfccae81-654b-48cb-975c-f98c70e13770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440809602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2440809602
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_stress_all.2707244023
Short name T382
Test name
Test status
Simulation time 254653491353 ps
CPU time 144.58 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:21:16 PM PST 24
Peak memory 199864 kb
Host smart-886d6786-0594-47b7-ba88-1d0e047d2e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707244023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2707244023
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1879223334
Short name T210
Test name
Test status
Simulation time 103639951792 ps
CPU time 41.58 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:23:00 PM PST 24
Peak memory 199496 kb
Host smart-2a5ac89b-387b-4641-9601-e61545af4ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879223334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1879223334
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.83166471
Short name T92
Test name
Test status
Simulation time 175539312291 ps
CPU time 628.88 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:33:12 PM PST 24
Peak memory 199552 kb
Host smart-6e649272-4f6d-43dc-8a6f-309f2356892a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83166471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.83166471
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3961295175
Short name T97
Test name
Test status
Simulation time 245518330864 ps
CPU time 896.2 seconds
Started Feb 29 01:23:08 PM PST 24
Finished Feb 29 01:38:05 PM PST 24
Peak memory 224984 kb
Host smart-99946cf8-6ac1-4849-9351-de69458b6e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961295175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3961295175
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.92309320
Short name T291
Test name
Test status
Simulation time 122803383828 ps
CPU time 497.86 seconds
Started Feb 29 01:19:07 PM PST 24
Finished Feb 29 01:27:25 PM PST 24
Peak memory 199664 kb
Host smart-530ddcf2-824d-48d1-ac59-8dd379605030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92309320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.92309320
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2465161493
Short name T319
Test name
Test status
Simulation time 39785169742 ps
CPU time 55.81 seconds
Started Feb 29 01:23:10 PM PST 24
Finished Feb 29 01:24:06 PM PST 24
Peak memory 199488 kb
Host smart-e88b1787-d528-4c74-bbf3-ad9ad4e4b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465161493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2465161493
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3422120785
Short name T450
Test name
Test status
Simulation time 23592545605 ps
CPU time 468.96 seconds
Started Feb 29 01:23:26 PM PST 24
Finished Feb 29 01:31:15 PM PST 24
Peak memory 215360 kb
Host smart-73c75c74-bf7e-4392-8f67-38f9cb5708be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422120785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3422120785
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.402188007
Short name T292
Test name
Test status
Simulation time 37585575530 ps
CPU time 41 seconds
Started Feb 29 01:23:29 PM PST 24
Finished Feb 29 01:24:10 PM PST 24
Peak memory 199680 kb
Host smart-f809353c-b340-4398-9203-4d17e88a3139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402188007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.402188007
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4018033354
Short name T1143
Test name
Test status
Simulation time 58938351 ps
CPU time 0.64 seconds
Started Feb 29 12:46:14 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 194844 kb
Host smart-f2565d32-4948-49ab-850e-664d4b43859b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018033354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4018033354
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.187764695
Short name T1219
Test name
Test status
Simulation time 903057291 ps
CPU time 2.45 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:21 PM PST 24
Peak memory 197808 kb
Host smart-29846826-0f44-4ed4-a944-0940277604e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187764695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.187764695
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2855535112
Short name T1193
Test name
Test status
Simulation time 72876365 ps
CPU time 0.78 seconds
Started Feb 29 12:46:13 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 199788 kb
Host smart-35e6768d-f439-441b-8d92-7d51b1a1dc8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855535112 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2855535112
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2031582656
Short name T1118
Test name
Test status
Simulation time 20088308 ps
CPU time 0.57 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 195416 kb
Host smart-f93cc9f2-807f-4152-9d45-6460e7a9a1bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031582656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2031582656
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4110302733
Short name T1113
Test name
Test status
Simulation time 14642413 ps
CPU time 0.55 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 194496 kb
Host smart-325576a8-24f4-4af3-b14a-0b44b6ce33cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110302733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4110302733
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3760121989
Short name T1184
Test name
Test status
Simulation time 64661306 ps
CPU time 1.55 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 200096 kb
Host smart-f2b2c397-3a2e-48e1-b274-15c0d57c4fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760121989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3760121989
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1562903324
Short name T79
Test name
Test status
Simulation time 204974348 ps
CPU time 1.37 seconds
Started Feb 29 12:45:55 PM PST 24
Finished Feb 29 12:45:57 PM PST 24
Peak memory 199516 kb
Host smart-e67801ff-a6d3-4b9f-93a9-b021e88c6a40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562903324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1562903324
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.578611162
Short name T1117
Test name
Test status
Simulation time 75376427 ps
CPU time 0.7 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 195416 kb
Host smart-038ae036-0165-46b8-b656-a713dcf93777
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578611162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.578611162
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2537831296
Short name T1147
Test name
Test status
Simulation time 90363852 ps
CPU time 1.5 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:21 PM PST 24
Peak memory 197772 kb
Host smart-2da5041f-4209-4ccc-8e56-875d881acf24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537831296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2537831296
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2575242433
Short name T59
Test name
Test status
Simulation time 15263873 ps
CPU time 0.62 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 195392 kb
Host smart-354a3efd-a153-478b-ae67-1c5c9cdbb8b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575242433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2575242433
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1844790975
Short name T1156
Test name
Test status
Simulation time 25101928 ps
CPU time 0.74 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:20 PM PST 24
Peak memory 198980 kb
Host smart-9b83ce90-d586-4761-846c-e338cdb1cc2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844790975 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1844790975
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4086582607
Short name T1199
Test name
Test status
Simulation time 13988167 ps
CPU time 0.59 seconds
Started Feb 29 12:45:59 PM PST 24
Finished Feb 29 12:46:00 PM PST 24
Peak memory 195432 kb
Host smart-cb7da3c7-3acc-423e-a061-ce32c775131e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086582607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4086582607
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1298830649
Short name T1190
Test name
Test status
Simulation time 15113738 ps
CPU time 0.55 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 194692 kb
Host smart-5deed413-14d4-4920-83b7-6ce39ceb3d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298830649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1298830649
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1424527838
Short name T1191
Test name
Test status
Simulation time 39904769 ps
CPU time 0.63 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:17 PM PST 24
Peak memory 195784 kb
Host smart-b8f31559-d276-4cee-9e20-ddecc567e583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424527838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1424527838
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.928370372
Short name T1217
Test name
Test status
Simulation time 119665884 ps
CPU time 2.39 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:46:20 PM PST 24
Peak memory 200088 kb
Host smart-0fe29ef0-f978-48f8-a6f9-9d7510ffa146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928370372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.928370372
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.838346680
Short name T1214
Test name
Test status
Simulation time 283944283 ps
CPU time 1.52 seconds
Started Feb 29 12:46:08 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 199260 kb
Host smart-4737de04-9fb2-47b2-ab52-f866848b4118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838346680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.838346680
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3556041032
Short name T1120
Test name
Test status
Simulation time 24117185 ps
CPU time 0.74 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:17 PM PST 24
Peak memory 198132 kb
Host smart-18793097-7242-4e84-9ab0-05ca13786d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556041032 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3556041032
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2555990728
Short name T57
Test name
Test status
Simulation time 17611119 ps
CPU time 0.61 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 195452 kb
Host smart-26deda57-127a-4a49-881f-efb7866e114a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555990728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2555990728
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.688906153
Short name T1188
Test name
Test status
Simulation time 30970935 ps
CPU time 0.58 seconds
Started Feb 29 12:46:27 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 185124 kb
Host smart-e2f135da-66cb-4551-8af1-41bab276eea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688906153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.688906153
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1623703481
Short name T72
Test name
Test status
Simulation time 58394003 ps
CPU time 0.7 seconds
Started Feb 29 12:46:24 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 196936 kb
Host smart-6c93bcc9-04cf-4207-bea2-49c7726ccae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623703481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1623703481
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3605474533
Short name T101
Test name
Test status
Simulation time 118881812 ps
CPU time 1.23 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 200364 kb
Host smart-0ffde0b9-6d9e-490b-a357-a7f47771ebc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605474533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3605474533
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3202645677
Short name T1189
Test name
Test status
Simulation time 84653944 ps
CPU time 1.06 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 200132 kb
Host smart-7e06f0cc-6e47-4062-84e9-2ca7732daee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202645677 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3202645677
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3780816226
Short name T70
Test name
Test status
Simulation time 30064131 ps
CPU time 0.63 seconds
Started Feb 29 12:46:24 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 195404 kb
Host smart-b9432860-f14e-49d2-b56d-a5cb49020956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780816226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3780816226
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.32184073
Short name T1135
Test name
Test status
Simulation time 14942192 ps
CPU time 0.55 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 185216 kb
Host smart-a1524f4c-ff5a-418d-89e6-17d5d735ed26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32184073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.32184073
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1530791812
Short name T73
Test name
Test status
Simulation time 31698657 ps
CPU time 0.75 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 197056 kb
Host smart-7e7a2c76-c899-4107-a8f4-953ce8ba69ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530791812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1530791812
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1704906455
Short name T1149
Test name
Test status
Simulation time 132501278 ps
CPU time 2.16 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 200188 kb
Host smart-fdd88761-ee1c-42a8-b664-3884e5f8cfa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704906455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1704906455
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4166338352
Short name T1111
Test name
Test status
Simulation time 58610214 ps
CPU time 0.64 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 197448 kb
Host smart-cfa9e6f9-457d-4859-a721-4d84aa5bf889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166338352 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4166338352
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.734747540
Short name T63
Test name
Test status
Simulation time 21056205 ps
CPU time 0.59 seconds
Started Feb 29 12:46:32 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 195440 kb
Host smart-5748f548-98c9-432e-9ca5-56d920bb5d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734747540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.734747540
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3929932972
Short name T1182
Test name
Test status
Simulation time 14746262 ps
CPU time 0.59 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 185140 kb
Host smart-4a1e7bdb-fa48-436f-aa51-46522ba8181a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929932972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3929932972
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2698026712
Short name T1204
Test name
Test status
Simulation time 80546092 ps
CPU time 0.64 seconds
Started Feb 29 12:46:14 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 195804 kb
Host smart-3dd99f39-2d29-423f-809f-b70622ea8022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698026712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2698026712
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1483272090
Short name T1126
Test name
Test status
Simulation time 571253733 ps
CPU time 1.68 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 200200 kb
Host smart-6d53f07c-dbce-4a82-b513-bdf5ebbc340a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483272090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1483272090
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3296627974
Short name T386
Test name
Test status
Simulation time 66809863 ps
CPU time 1.29 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 199372 kb
Host smart-24285f0b-3c5a-4e9a-9682-2d874acef3e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296627974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3296627974
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4142258637
Short name T1140
Test name
Test status
Simulation time 227651835 ps
CPU time 0.77 seconds
Started Feb 29 12:46:21 PM PST 24
Finished Feb 29 12:46:22 PM PST 24
Peak memory 197924 kb
Host smart-bac56b13-1874-4391-8dc6-fc93a39645d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142258637 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.4142258637
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1971413131
Short name T1224
Test name
Test status
Simulation time 131183630 ps
CPU time 0.66 seconds
Started Feb 29 12:46:16 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 195708 kb
Host smart-3d08191b-7877-4a90-aeca-1490ea87bac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971413131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1971413131
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.649377444
Short name T1105
Test name
Test status
Simulation time 26634668 ps
CPU time 0.54 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 194316 kb
Host smart-a985fbeb-1c39-4d5f-879b-71ad097ab783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649377444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.649377444
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3150762630
Short name T1146
Test name
Test status
Simulation time 82308693 ps
CPU time 0.69 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 195728 kb
Host smart-6f713652-f9e0-44e9-8eeb-fe01e96efc09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150762630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3150762630
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.199413788
Short name T1133
Test name
Test status
Simulation time 153187251 ps
CPU time 1.83 seconds
Started Feb 29 12:46:20 PM PST 24
Finished Feb 29 12:46:22 PM PST 24
Peak memory 200064 kb
Host smart-e1f42e82-91f7-4c61-8b82-4dc80d6fc7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199413788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.199413788
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2185811576
Short name T384
Test name
Test status
Simulation time 534178072 ps
CPU time 1.18 seconds
Started Feb 29 12:46:27 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 199220 kb
Host smart-cc3be777-21c1-4fc5-9ab0-aafd6d669fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185811576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2185811576
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4201837482
Short name T1167
Test name
Test status
Simulation time 241282091 ps
CPU time 0.67 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 196620 kb
Host smart-e5fd0d85-903b-497c-8ec1-482a03ad1103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201837482 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4201837482
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2933612616
Short name T1213
Test name
Test status
Simulation time 14424919 ps
CPU time 0.63 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 195392 kb
Host smart-77f93510-2457-4e40-af37-48f90e545c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933612616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2933612616
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3327779134
Short name T1174
Test name
Test status
Simulation time 12332016 ps
CPU time 0.57 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 194504 kb
Host smart-1c0be70d-f787-4350-a0c4-99c399d4b60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327779134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3327779134
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.481146081
Short name T1198
Test name
Test status
Simulation time 17069180 ps
CPU time 0.65 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 195616 kb
Host smart-36e476ef-e122-40fa-87f1-6eb1fd57f969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481146081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.481146081
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3109789514
Short name T1210
Test name
Test status
Simulation time 225644226 ps
CPU time 2.06 seconds
Started Feb 29 12:46:31 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 200288 kb
Host smart-f44ea3ee-73d7-4994-9484-7dabfd441195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109789514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3109789514
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1481568701
Short name T1155
Test name
Test status
Simulation time 22674273 ps
CPU time 0.74 seconds
Started Feb 29 12:46:28 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 197220 kb
Host smart-f4518d60-beaf-450d-bf15-b94649ff1aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481568701 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1481568701
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3874519223
Short name T61
Test name
Test status
Simulation time 46189122 ps
CPU time 0.61 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 195516 kb
Host smart-21b6601e-55ef-4aa1-9cdb-58fda18450b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874519223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3874519223
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2607380251
Short name T1178
Test name
Test status
Simulation time 19227027 ps
CPU time 0.58 seconds
Started Feb 29 12:46:28 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 194420 kb
Host smart-6d59055a-d9a5-48e6-9531-edbde15e94aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607380251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2607380251
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2515579442
Short name T1152
Test name
Test status
Simulation time 28045764 ps
CPU time 0.73 seconds
Started Feb 29 12:46:27 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 196920 kb
Host smart-7fe4d8d1-8fa4-4d46-af5f-5003108ce897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515579442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2515579442
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1248565350
Short name T1151
Test name
Test status
Simulation time 125460436 ps
CPU time 1.35 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200244 kb
Host smart-24e9a659-cc45-4dbf-b18b-405b4276550b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248565350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1248565350
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.484998788
Short name T1208
Test name
Test status
Simulation time 44731649 ps
CPU time 0.93 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:27 PM PST 24
Peak memory 198448 kb
Host smart-8aa956e5-3af5-48e9-b431-857500f3cf15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484998788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.484998788
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2849494352
Short name T1195
Test name
Test status
Simulation time 17345514 ps
CPU time 0.75 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 197360 kb
Host smart-c5b9052e-9c8a-4411-8984-dea5306a23fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849494352 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2849494352
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4038378087
Short name T65
Test name
Test status
Simulation time 16061430 ps
CPU time 0.59 seconds
Started Feb 29 12:46:25 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 195480 kb
Host smart-6e4ca90e-2b0b-4e4a-9d61-ca71fcf5dc30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038378087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4038378087
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.440491652
Short name T1150
Test name
Test status
Simulation time 13188648 ps
CPU time 0.54 seconds
Started Feb 29 12:46:51 PM PST 24
Finished Feb 29 12:46:52 PM PST 24
Peak memory 194444 kb
Host smart-6cb1a1c7-ce82-47e4-8aea-65889a2b5851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440491652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.440491652
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1011777817
Short name T1127
Test name
Test status
Simulation time 56713794 ps
CPU time 0.68 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 195764 kb
Host smart-d2b683f6-c8fd-4fd4-84f8-75db83c2b354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011777817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1011777817
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1322148694
Short name T1145
Test name
Test status
Simulation time 117955819 ps
CPU time 2.06 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 200292 kb
Host smart-b851e80c-b968-4e51-8e41-5d0f4b3d2656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322148694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1322148694
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3208500899
Short name T81
Test name
Test status
Simulation time 629156187 ps
CPU time 0.92 seconds
Started Feb 29 12:46:13 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 198904 kb
Host smart-664c6a38-e28d-4503-a99d-a8523ca35d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208500899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3208500899
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.188282906
Short name T1159
Test name
Test status
Simulation time 24602467 ps
CPU time 0.64 seconds
Started Feb 29 12:46:32 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 196592 kb
Host smart-bb5bd107-4776-4e59-8788-9bad8c5b345c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188282906 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.188282906
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3484964813
Short name T1109
Test name
Test status
Simulation time 36040632 ps
CPU time 0.57 seconds
Started Feb 29 12:46:29 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 195412 kb
Host smart-55c02f70-d01c-4d7e-9dbf-a4396ad844fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484964813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3484964813
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.710492665
Short name T1134
Test name
Test status
Simulation time 19175953 ps
CPU time 0.56 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 194508 kb
Host smart-eed376b3-1b0f-4f5b-945e-51189d543054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710492665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.710492665
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4150243880
Short name T1173
Test name
Test status
Simulation time 37210809 ps
CPU time 0.64 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 195572 kb
Host smart-3f1bf7e3-5e00-4196-afb1-9b8182c76390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150243880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4150243880
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1358070582
Short name T1116
Test name
Test status
Simulation time 121562664 ps
CPU time 2.46 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 200184 kb
Host smart-d457854d-c0df-4483-8ad0-5e1f73f07bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358070582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1358070582
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3372781342
Short name T83
Test name
Test status
Simulation time 141669750 ps
CPU time 0.91 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 198912 kb
Host smart-c1ed179c-1cca-465e-aed9-16599632804d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372781342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3372781342
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.718405316
Short name T113
Test name
Test status
Simulation time 18618054 ps
CPU time 0.72 seconds
Started Feb 29 12:46:52 PM PST 24
Finished Feb 29 12:46:53 PM PST 24
Peak memory 198064 kb
Host smart-d26ec1d7-3c2c-427c-9e1c-d60561ad61ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718405316 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.718405316
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1506748341
Short name T68
Test name
Test status
Simulation time 20147860 ps
CPU time 0.55 seconds
Started Feb 29 12:46:21 PM PST 24
Finished Feb 29 12:46:22 PM PST 24
Peak memory 195548 kb
Host smart-47c0ab65-3eb3-4123-9db2-99d22630afa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506748341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1506748341
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.702310872
Short name T1223
Test name
Test status
Simulation time 55018662 ps
CPU time 0.56 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 185196 kb
Host smart-f78eb7dc-63a9-436b-8f00-072f988985a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702310872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.702310872
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2983026581
Short name T1144
Test name
Test status
Simulation time 28636377 ps
CPU time 0.79 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 197156 kb
Host smart-a5add05b-717c-4682-ac47-194632e91c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983026581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2983026581
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2207299256
Short name T1169
Test name
Test status
Simulation time 41338619 ps
CPU time 1.1 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 200020 kb
Host smart-92b02195-08ec-4197-b0af-2bb422d40d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207299256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2207299256
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2390420568
Short name T77
Test name
Test status
Simulation time 289445793 ps
CPU time 1.57 seconds
Started Feb 29 12:46:42 PM PST 24
Finished Feb 29 12:46:44 PM PST 24
Peak memory 199124 kb
Host smart-42c91a1e-b0eb-4c00-be54-701c4ad55070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390420568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2390420568
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3589795147
Short name T1211
Test name
Test status
Simulation time 340983903 ps
CPU time 0.8 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:35 PM PST 24
Peak memory 199200 kb
Host smart-866252b1-2f6a-49b3-885e-cf2f5c877895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589795147 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3589795147
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3983112158
Short name T54
Test name
Test status
Simulation time 12260791 ps
CPU time 0.59 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 195496 kb
Host smart-4b91ceab-711f-48d9-8eb0-803df139f9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983112158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3983112158
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3083124520
Short name T1181
Test name
Test status
Simulation time 53282846 ps
CPU time 0.56 seconds
Started Feb 29 12:46:24 PM PST 24
Finished Feb 29 12:46:24 PM PST 24
Peak memory 185304 kb
Host smart-e0c38001-7b35-468e-a79f-55a1d0eda2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083124520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3083124520
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.461006848
Short name T1123
Test name
Test status
Simulation time 72580776 ps
CPU time 0.67 seconds
Started Feb 29 12:46:36 PM PST 24
Finished Feb 29 12:46:37 PM PST 24
Peak memory 195516 kb
Host smart-988a8be7-3ae5-48d4-bd56-fface2466c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461006848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.461006848
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1972947655
Short name T1106
Test name
Test status
Simulation time 183742300 ps
CPU time 1.28 seconds
Started Feb 29 12:46:21 PM PST 24
Finished Feb 29 12:46:22 PM PST 24
Peak memory 200168 kb
Host smart-468184c1-69f6-47b3-b1bc-f24f8fd04df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972947655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1972947655
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2113112209
Short name T76
Test name
Test status
Simulation time 270947496 ps
CPU time 1.28 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 199180 kb
Host smart-ad7bcf81-26d5-41d6-8d3f-aaa8acbea8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113112209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2113112209
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2298201036
Short name T56
Test name
Test status
Simulation time 31064910 ps
CPU time 0.83 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 196728 kb
Host smart-1d474f8a-5090-494d-80f2-9bc7e5f0ad4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298201036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2298201036
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3155124615
Short name T1163
Test name
Test status
Simulation time 179926759 ps
CPU time 1.54 seconds
Started Feb 29 12:46:29 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 198176 kb
Host smart-83076159-ba87-4cc0-a53e-c1dfe71dc84f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155124615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3155124615
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1320459575
Short name T1136
Test name
Test status
Simulation time 38473031 ps
CPU time 0.65 seconds
Started Feb 29 12:46:05 PM PST 24
Finished Feb 29 12:46:06 PM PST 24
Peak memory 195452 kb
Host smart-ec82ad3a-83f4-4976-af42-42a8b2a60fcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320459575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1320459575
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2605287412
Short name T1175
Test name
Test status
Simulation time 82031852 ps
CPU time 0.75 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 198176 kb
Host smart-5dc3eb89-6ea1-4ad8-a56c-430634717d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605287412 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2605287412
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2483165095
Short name T62
Test name
Test status
Simulation time 24787436 ps
CPU time 0.66 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 195592 kb
Host smart-9cbc5bf7-05b9-4103-b5e8-32c6eeebc096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483165095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2483165095
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.132683628
Short name T1218
Test name
Test status
Simulation time 13402130 ps
CPU time 0.57 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 194468 kb
Host smart-888a26ff-ceb0-4d22-bd01-acc2248253ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132683628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.132683628
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1029309447
Short name T1142
Test name
Test status
Simulation time 319942611 ps
CPU time 0.74 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 197256 kb
Host smart-a44fad4a-5aca-4d60-8ba7-ad85004dc12d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029309447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1029309447
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2708656201
Short name T1130
Test name
Test status
Simulation time 269276421 ps
CPU time 1.62 seconds
Started Feb 29 12:46:23 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 200248 kb
Host smart-cd3b7b50-9fc7-4823-873d-d53868ba143a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708656201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2708656201
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.805379859
Short name T1227
Test name
Test status
Simulation time 415783810 ps
CPU time 1.33 seconds
Started Feb 29 12:46:07 PM PST 24
Finished Feb 29 12:46:09 PM PST 24
Peak memory 199380 kb
Host smart-a3c0bdaf-6acb-42df-83a1-c515508480eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805379859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.805379859
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2472257336
Short name T1107
Test name
Test status
Simulation time 67308240 ps
CPU time 0.54 seconds
Started Feb 29 12:46:28 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 185096 kb
Host smart-5cbb81da-8f0b-4e95-b1ed-677dc12d408f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472257336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2472257336
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1925954724
Short name T1168
Test name
Test status
Simulation time 14798379 ps
CPU time 0.57 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 185096 kb
Host smart-18947967-04aa-48ba-a191-4a8d3704c5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925954724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1925954724
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2816729220
Short name T1148
Test name
Test status
Simulation time 25804155 ps
CPU time 0.55 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 185288 kb
Host smart-530a0c3b-a30b-4bcc-a02e-c03997a69a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816729220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2816729220
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2382669869
Short name T1170
Test name
Test status
Simulation time 91785908 ps
CPU time 0.55 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 185288 kb
Host smart-1d062fab-3f2c-4201-8abd-fe2345289f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382669869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2382669869
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1971674610
Short name T1177
Test name
Test status
Simulation time 38192771 ps
CPU time 0.55 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:30 PM PST 24
Peak memory 185164 kb
Host smart-1bb4d2da-b0e5-452e-b0ad-b4309e742c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971674610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1971674610
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.410262523
Short name T1158
Test name
Test status
Simulation time 27724251 ps
CPU time 0.56 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 185276 kb
Host smart-f6573c72-5dea-44c6-ba3d-57b7638432cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410262523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.410262523
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2306661019
Short name T1222
Test name
Test status
Simulation time 38966216 ps
CPU time 0.56 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 194424 kb
Host smart-69ce46ec-3ef4-4b9c-97fb-751a0e676b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306661019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2306661019
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1208361069
Short name T1216
Test name
Test status
Simulation time 38701511 ps
CPU time 0.53 seconds
Started Feb 29 12:46:31 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 185096 kb
Host smart-874560da-8981-4e1a-ae19-d10bdf0446ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208361069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1208361069
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3404730596
Short name T1103
Test name
Test status
Simulation time 43331073 ps
CPU time 0.56 seconds
Started Feb 29 12:46:31 PM PST 24
Finished Feb 29 12:46:32 PM PST 24
Peak memory 194388 kb
Host smart-83c6adc9-8e16-4bc8-abd1-e03564ff5921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404730596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3404730596
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1361420550
Short name T1131
Test name
Test status
Simulation time 44908056 ps
CPU time 0.57 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 185188 kb
Host smart-d7bf3548-1aa6-427b-8a41-16919297cfad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361420550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1361420550
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3020301736
Short name T64
Test name
Test status
Simulation time 24947684 ps
CPU time 0.8 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 196268 kb
Host smart-eb35cbd9-eca6-422d-aed6-524899ab6cd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020301736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3020301736
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2999829143
Short name T60
Test name
Test status
Simulation time 62604099 ps
CPU time 1.43 seconds
Started Feb 29 12:46:04 PM PST 24
Finished Feb 29 12:46:06 PM PST 24
Peak memory 197776 kb
Host smart-b673ae8b-6744-44de-ae30-9002d4886b84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999829143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2999829143
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2697640510
Short name T1206
Test name
Test status
Simulation time 12053197 ps
CPU time 0.58 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 195724 kb
Host smart-174a93a8-fcdc-4571-b214-be85c85f6625
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697640510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2697640510
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.97030444
Short name T1180
Test name
Test status
Simulation time 39151878 ps
CPU time 0.73 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:27 PM PST 24
Peak memory 196772 kb
Host smart-91e99c7a-bba8-4b83-9c9d-3411e22d31e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97030444 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.97030444
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1776942461
Short name T1215
Test name
Test status
Simulation time 14582007 ps
CPU time 0.6 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 195720 kb
Host smart-2101b3bb-63f2-40b8-985c-4da9b576a156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776942461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1776942461
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.118757811
Short name T1161
Test name
Test status
Simulation time 123269968 ps
CPU time 0.54 seconds
Started Feb 29 12:46:35 PM PST 24
Finished Feb 29 12:46:36 PM PST 24
Peak memory 185196 kb
Host smart-f8d55ef0-cc19-44b3-b8c5-652a8a6f0227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118757811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.118757811
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2475056443
Short name T1121
Test name
Test status
Simulation time 55691435 ps
CPU time 0.66 seconds
Started Feb 29 12:45:59 PM PST 24
Finished Feb 29 12:46:01 PM PST 24
Peak memory 195720 kb
Host smart-a7dcaa43-84c9-42e2-8593-56cd853e309e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475056443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2475056443
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2056471297
Short name T1231
Test name
Test status
Simulation time 114340197 ps
CPU time 1.54 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 200080 kb
Host smart-8fa5ee37-19d7-4305-96ee-34c1535b9100
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056471297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2056471297
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3054263205
Short name T1157
Test name
Test status
Simulation time 345076488 ps
CPU time 1.32 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:46:20 PM PST 24
Peak memory 199488 kb
Host smart-9d497b0e-bada-410c-a7f9-cdc79a8d4808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054263205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3054263205
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1092077567
Short name T1186
Test name
Test status
Simulation time 13840010 ps
CPU time 0.54 seconds
Started Feb 29 12:46:27 PM PST 24
Finished Feb 29 12:46:27 PM PST 24
Peak memory 194400 kb
Host smart-fa9e48f9-efa2-4fa9-afbb-e0ddf472dd8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092077567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1092077567
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.764630071
Short name T1209
Test name
Test status
Simulation time 33795497 ps
CPU time 0.54 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:27 PM PST 24
Peak memory 194396 kb
Host smart-1fbb54a4-accb-4a4a-894f-0f6476ab8560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764630071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.764630071
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3770578902
Short name T1220
Test name
Test status
Simulation time 30051714 ps
CPU time 0.57 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 194428 kb
Host smart-1539f019-6371-4e59-bc54-86ed10e36883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770578902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3770578902
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3593140004
Short name T1164
Test name
Test status
Simulation time 14088682 ps
CPU time 0.57 seconds
Started Feb 29 12:46:35 PM PST 24
Finished Feb 29 12:46:36 PM PST 24
Peak memory 194436 kb
Host smart-1d11d366-e0c2-4c8a-bc24-9f20b8bd7892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593140004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3593140004
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4089889849
Short name T1207
Test name
Test status
Simulation time 52025499 ps
CPU time 0.57 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 185192 kb
Host smart-f2e3b216-2b6e-408f-9dbe-6a30638a0db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089889849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4089889849
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.420947972
Short name T1225
Test name
Test status
Simulation time 19554964 ps
CPU time 0.51 seconds
Started Feb 29 12:46:45 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 185160 kb
Host smart-11656a76-2124-4bd6-a6a4-fd172ed6293f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420947972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.420947972
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3242635334
Short name T1226
Test name
Test status
Simulation time 47656990 ps
CPU time 0.58 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 194416 kb
Host smart-edb1966a-ca99-4d49-8b49-10779174d912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242635334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3242635334
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1291500345
Short name T1160
Test name
Test status
Simulation time 24282736 ps
CPU time 0.59 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 194332 kb
Host smart-abe0e8a8-8918-457a-ad5e-cf700a4d061c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291500345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1291500345
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2556157639
Short name T1154
Test name
Test status
Simulation time 46723087 ps
CPU time 0.53 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:35 PM PST 24
Peak memory 194400 kb
Host smart-44963ee7-f9c6-4794-bace-d68fb2cb8e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556157639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2556157639
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2685033429
Short name T1200
Test name
Test status
Simulation time 10573077 ps
CPU time 0.57 seconds
Started Feb 29 12:46:44 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 194428 kb
Host smart-ff9f70db-5b06-49b7-beee-822c1c8aefa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685033429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2685033429
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.800895712
Short name T1114
Test name
Test status
Simulation time 103434881 ps
CPU time 0.8 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 196268 kb
Host smart-870709d3-00f7-4fb4-94a3-1a29539cb9bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800895712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.800895712
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2296701006
Short name T1104
Test name
Test status
Simulation time 344755275 ps
CPU time 2.56 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:46:26 PM PST 24
Peak memory 197888 kb
Host smart-15a57246-2a81-4c3a-9995-ef733f1d57d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296701006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2296701006
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1717339704
Short name T1171
Test name
Test status
Simulation time 33377871 ps
CPU time 0.56 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:35 PM PST 24
Peak memory 195364 kb
Host smart-e9651654-4979-4754-bef6-a7f66d15af72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717339704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1717339704
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3830295909
Short name T1139
Test name
Test status
Simulation time 79088581 ps
CPU time 0.72 seconds
Started Feb 29 12:45:58 PM PST 24
Finished Feb 29 12:46:00 PM PST 24
Peak memory 197496 kb
Host smart-afc88aee-5d9c-42bc-b582-2555458b3540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830295909 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3830295909
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1864499134
Short name T1124
Test name
Test status
Simulation time 16604057 ps
CPU time 0.64 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 195424 kb
Host smart-71c9b15b-6512-43e8-a109-f6d88d02d76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864499134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1864499134
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2053749063
Short name T1132
Test name
Test status
Simulation time 45827302 ps
CPU time 0.59 seconds
Started Feb 29 12:46:32 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 185244 kb
Host smart-0ba7b478-8a5d-49bb-9f5e-798dec430f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053749063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2053749063
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4155253528
Short name T1229
Test name
Test status
Simulation time 102313960 ps
CPU time 0.75 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 196948 kb
Host smart-a0eec184-6dad-4caf-877f-016c4234f99d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155253528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4155253528
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.498348362
Short name T1196
Test name
Test status
Simulation time 23424700 ps
CPU time 1.24 seconds
Started Feb 29 12:46:14 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 200460 kb
Host smart-235e3468-c6d4-49b8-bdc8-4d5033a385e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498348362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.498348362
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3492340817
Short name T387
Test name
Test status
Simulation time 175487462 ps
CPU time 1.28 seconds
Started Feb 29 12:46:14 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 199348 kb
Host smart-8acd9737-288f-4977-8dde-bb396bc85f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492340817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3492340817
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3186935897
Short name T1205
Test name
Test status
Simulation time 10726749 ps
CPU time 0.56 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 185096 kb
Host smart-5072fd45-1ab0-4e7a-86ef-3c9d4867732a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186935897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3186935897
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.392655986
Short name T1192
Test name
Test status
Simulation time 15743143 ps
CPU time 0.6 seconds
Started Feb 29 12:46:24 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 185216 kb
Host smart-99366e6d-abea-4127-8c4a-26875eb831cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392655986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.392655986
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1076903633
Short name T1128
Test name
Test status
Simulation time 33570726 ps
CPU time 0.55 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 185264 kb
Host smart-654ddb49-5c00-4218-a5ac-f10bdd6ac8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076903633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1076903633
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3095054310
Short name T1162
Test name
Test status
Simulation time 67201879 ps
CPU time 0.59 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 185192 kb
Host smart-c41944a3-bfc8-41ae-b1b4-11ac5fc67dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095054310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3095054310
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.338189406
Short name T1230
Test name
Test status
Simulation time 125303465 ps
CPU time 0.57 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:38 PM PST 24
Peak memory 194412 kb
Host smart-f11b28ef-8a66-4b0f-8184-f886093070ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338189406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.338189406
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1262196238
Short name T1137
Test name
Test status
Simulation time 13272425 ps
CPU time 0.55 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:47:00 PM PST 24
Peak memory 194512 kb
Host smart-a14eff72-bfa9-406e-bb08-cb184150c980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262196238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1262196238
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2560658996
Short name T1202
Test name
Test status
Simulation time 98615526 ps
CPU time 0.57 seconds
Started Feb 29 12:46:36 PM PST 24
Finished Feb 29 12:46:37 PM PST 24
Peak memory 194444 kb
Host smart-fa36b432-639c-4298-9582-cf43cbe98369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560658996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2560658996
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.174225719
Short name T1176
Test name
Test status
Simulation time 16210417 ps
CPU time 0.56 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 185444 kb
Host smart-64993945-11d5-4c4c-b8f6-d47ffd20af8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174225719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.174225719
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1735506431
Short name T1119
Test name
Test status
Simulation time 23581380 ps
CPU time 0.56 seconds
Started Feb 29 12:46:35 PM PST 24
Finished Feb 29 12:46:35 PM PST 24
Peak memory 185276 kb
Host smart-06979abb-cebd-4b21-a00e-bf6e7b0fcd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735506431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1735506431
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1135475800
Short name T1115
Test name
Test status
Simulation time 13125722 ps
CPU time 0.62 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 185268 kb
Host smart-66a2d6b5-1ecc-4fff-94f8-25880b036543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135475800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1135475800
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3419014690
Short name T1129
Test name
Test status
Simulation time 27640866 ps
CPU time 0.77 seconds
Started Feb 29 12:46:15 PM PST 24
Finished Feb 29 12:46:17 PM PST 24
Peak memory 198584 kb
Host smart-0e6ba5da-07c9-4a23-8c3c-dc0a05ca5338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419014690 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3419014690
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.136468375
Short name T71
Test name
Test status
Simulation time 33514710 ps
CPU time 0.61 seconds
Started Feb 29 12:46:09 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 195452 kb
Host smart-7bb80ef7-a3f0-4909-ba48-3baf86171628
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136468375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.136468375
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2447888818
Short name T1203
Test name
Test status
Simulation time 43030037 ps
CPU time 0.61 seconds
Started Feb 29 12:46:09 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 185196 kb
Host smart-2113c327-83e7-4d5b-9680-3124d24b9359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447888818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2447888818
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2616610534
Short name T1165
Test name
Test status
Simulation time 58441109 ps
CPU time 0.63 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:35 PM PST 24
Peak memory 195784 kb
Host smart-2abf7166-b368-40bb-8a7e-bb8d769b12b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616610534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2616610534
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1104866635
Short name T1122
Test name
Test status
Simulation time 54475851 ps
CPU time 1.49 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 200184 kb
Host smart-c75bf55d-187a-40ca-b53f-4df632ad4bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104866635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1104866635
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2590924445
Short name T1232
Test name
Test status
Simulation time 50185002 ps
CPU time 1 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 199256 kb
Host smart-36d77a17-5649-4ebb-be57-6c4e0a0011d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590924445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2590924445
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1103177827
Short name T1110
Test name
Test status
Simulation time 28858408 ps
CPU time 0.83 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 197676 kb
Host smart-33edbce7-9478-4057-a6c1-93267865ce87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103177827 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1103177827
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2506999328
Short name T1138
Test name
Test status
Simulation time 45297047 ps
CPU time 0.61 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:26 PM PST 24
Peak memory 195468 kb
Host smart-47db0b7e-e24c-42c3-aa85-5cb844467961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506999328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2506999328
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1075742276
Short name T1179
Test name
Test status
Simulation time 43508113 ps
CPU time 0.54 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 185156 kb
Host smart-77323c5a-f866-4b02-8e72-5295c6105599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075742276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1075742276
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1741425658
Short name T69
Test name
Test status
Simulation time 24368825 ps
CPU time 0.69 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 196816 kb
Host smart-e0ffdbab-a53b-4081-afac-0a12c9e97e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741425658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1741425658
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.411843033
Short name T1212
Test name
Test status
Simulation time 106905925 ps
CPU time 1.95 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:32 PM PST 24
Peak memory 200184 kb
Host smart-94ac1e2a-906f-4fae-9331-36933a5315f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411843033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.411843033
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1547668601
Short name T1221
Test name
Test status
Simulation time 479979658 ps
CPU time 1.38 seconds
Started Feb 29 12:46:17 PM PST 24
Finished Feb 29 12:46:19 PM PST 24
Peak memory 199672 kb
Host smart-e441be23-c850-473b-a7b8-ebade7abb2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547668601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1547668601
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3203540070
Short name T1187
Test name
Test status
Simulation time 43363837 ps
CPU time 0.76 seconds
Started Feb 29 12:46:13 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 199996 kb
Host smart-af319a75-84a3-4185-9216-a8e558a6ac86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203540070 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3203540070
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2762346107
Short name T55
Test name
Test status
Simulation time 39371799 ps
CPU time 0.68 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 195508 kb
Host smart-e3f17f10-035d-4f3a-83ca-6c6df17bae25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762346107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2762346107
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4072460231
Short name T1228
Test name
Test status
Simulation time 16733141 ps
CPU time 0.57 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:12 PM PST 24
Peak memory 194372 kb
Host smart-1cb8d30a-1ed3-43ee-93d2-90597dae4c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072460231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4072460231
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1228279465
Short name T1183
Test name
Test status
Simulation time 109294842 ps
CPU time 0.74 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 197784 kb
Host smart-b1f1e303-3b73-47bb-90a9-d65d49001cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228279465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1228279465
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2136184038
Short name T1194
Test name
Test status
Simulation time 125941197 ps
CPU time 1.43 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200232 kb
Host smart-4108f93b-5373-431d-9a32-dbf0337ce7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136184038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2136184038
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2687452654
Short name T1201
Test name
Test status
Simulation time 104404754 ps
CPU time 1.29 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:32 PM PST 24
Peak memory 199300 kb
Host smart-aa186ce5-228f-4d7b-88a5-576bd9a0e10e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687452654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2687452654
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3416102318
Short name T1197
Test name
Test status
Simulation time 51454155 ps
CPU time 0.79 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 198572 kb
Host smart-168b7038-6f1c-4ac0-a4a0-4813cb9b4d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416102318 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3416102318
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2268407313
Short name T1185
Test name
Test status
Simulation time 38188160 ps
CPU time 0.61 seconds
Started Feb 29 12:46:25 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 195408 kb
Host smart-6442c8a5-3333-45e3-8406-f741929f92a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268407313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2268407313
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3017852803
Short name T1172
Test name
Test status
Simulation time 13794852 ps
CPU time 0.55 seconds
Started Feb 29 12:46:23 PM PST 24
Finished Feb 29 12:46:23 PM PST 24
Peak memory 185156 kb
Host smart-7ab8a426-64d1-4fd1-a9ad-0292b791e511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017852803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3017852803
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1649738579
Short name T1166
Test name
Test status
Simulation time 21720282 ps
CPU time 0.68 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 195904 kb
Host smart-a98c368a-1881-4d2d-b1b3-488f32efe552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649738579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1649738579
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1830744453
Short name T1112
Test name
Test status
Simulation time 36174253 ps
CPU time 1.66 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200116 kb
Host smart-d2a4893f-bed0-4f5b-bf14-44eb8edfcde1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830744453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1830744453
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.366579166
Short name T385
Test name
Test status
Simulation time 314381520 ps
CPU time 1.35 seconds
Started Feb 29 12:46:26 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 199224 kb
Host smart-234488e0-583c-43b9-9c38-f721e3011435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366579166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.366579166
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2585779297
Short name T1108
Test name
Test status
Simulation time 27283376 ps
CPU time 1.32 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 200176 kb
Host smart-1d79ba13-9a4b-4090-b6e5-087c4c2e2da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585779297 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2585779297
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1782707484
Short name T1153
Test name
Test status
Simulation time 17660176 ps
CPU time 0.62 seconds
Started Feb 29 12:46:24 PM PST 24
Finished Feb 29 12:46:24 PM PST 24
Peak memory 195468 kb
Host smart-a62dd268-f95b-4bea-b691-8e2d8d03283c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782707484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1782707484
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3282143737
Short name T1141
Test name
Test status
Simulation time 26238911 ps
CPU time 0.56 seconds
Started Feb 29 12:46:36 PM PST 24
Finished Feb 29 12:46:36 PM PST 24
Peak memory 185272 kb
Host smart-0bfb8b00-0126-42f1-8ce2-0a2225ab5f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282143737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3282143737
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4203907558
Short name T66
Test name
Test status
Simulation time 32276181 ps
CPU time 0.69 seconds
Started Feb 29 12:46:23 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 196568 kb
Host smart-22395af6-fe23-4453-a414-b7be337975fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203907558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4203907558
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3077165239
Short name T1125
Test name
Test status
Simulation time 195079925 ps
CPU time 1.37 seconds
Started Feb 29 12:46:32 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 200120 kb
Host smart-75328e19-2db3-4280-9165-9f7f395af7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077165239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3077165239
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1638827277
Short name T82
Test name
Test status
Simulation time 175434536 ps
CPU time 1.29 seconds
Started Feb 29 12:46:09 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 199232 kb
Host smart-f9779e15-958a-41f1-a78d-5d89622206fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638827277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1638827277
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2613593583
Short name T767
Test name
Test status
Simulation time 25506339 ps
CPU time 0.57 seconds
Started Feb 29 01:18:40 PM PST 24
Finished Feb 29 01:18:41 PM PST 24
Peak memory 195056 kb
Host smart-6cf6dc19-7ea7-416f-baf9-775b019989a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613593583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2613593583
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.603030286
Short name T524
Test name
Test status
Simulation time 143434665812 ps
CPU time 236.22 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:22:39 PM PST 24
Peak memory 199484 kb
Host smart-fedc6e07-1843-436c-968f-0c66943ad359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603030286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.603030286
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3808077573
Short name T180
Test name
Test status
Simulation time 47674530741 ps
CPU time 71.89 seconds
Started Feb 29 01:18:40 PM PST 24
Finished Feb 29 01:19:52 PM PST 24
Peak memory 199636 kb
Host smart-22dd4155-c65e-4779-b65a-197a470ea171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808077573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3808077573
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1298436147
Short name T181
Test name
Test status
Simulation time 22444844816 ps
CPU time 41.12 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 199236 kb
Host smart-6e187354-9476-4f74-b513-9dfa7603ff99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298436147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1298436147
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2976420270
Short name T544
Test name
Test status
Simulation time 120614393644 ps
CPU time 49.25 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 198112 kb
Host smart-c17621be-c20a-4bb8-a558-9ca517033f87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976420270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2976420270
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2795419852
Short name T1069
Test name
Test status
Simulation time 43355909128 ps
CPU time 152.47 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:21:16 PM PST 24
Peak memory 199420 kb
Host smart-482bce0c-059e-4490-aad9-42a337703d6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795419852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2795419852
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3622976772
Short name T922
Test name
Test status
Simulation time 2478527863 ps
CPU time 5.26 seconds
Started Feb 29 01:18:44 PM PST 24
Finished Feb 29 01:18:49 PM PST 24
Peak memory 197796 kb
Host smart-fcc790e8-ed12-4be7-9c34-30d1b4a7b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622976772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3622976772
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1504849726
Short name T634
Test name
Test status
Simulation time 32013652282 ps
CPU time 12.73 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 198544 kb
Host smart-e4d99875-7ecd-4ad6-ae4e-6bbf6863a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504849726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1504849726
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1564268163
Short name T797
Test name
Test status
Simulation time 26074454418 ps
CPU time 354.44 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:24:36 PM PST 24
Peak memory 199572 kb
Host smart-16541aab-8f87-46e2-b914-96b6127cf961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564268163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1564268163
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1180657372
Short name T964
Test name
Test status
Simulation time 3709767896 ps
CPU time 24.72 seconds
Started Feb 29 01:18:40 PM PST 24
Finished Feb 29 01:19:05 PM PST 24
Peak memory 198480 kb
Host smart-8dfc2da2-eb5e-4e06-bd5d-313192e291af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180657372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1180657372
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.734381547
Short name T841
Test name
Test status
Simulation time 499061874 ps
CPU time 0.97 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:18:42 PM PST 24
Peak memory 195036 kb
Host smart-7ab5f953-ef0a-4ae3-9b74-0e0dbc2952f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734381547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.734381547
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.856824953
Short name T557
Test name
Test status
Simulation time 739821144 ps
CPU time 1.88 seconds
Started Feb 29 01:18:39 PM PST 24
Finished Feb 29 01:18:41 PM PST 24
Peak memory 197508 kb
Host smart-d7b05fe1-47fa-4213-a84c-8d7bf7597041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856824953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.856824953
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.42593037
Short name T648
Test name
Test status
Simulation time 892191906701 ps
CPU time 1743.16 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:47:46 PM PST 24
Peak memory 208216 kb
Host smart-6e3f1ca0-9cda-469c-8834-9992fe8cdb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.42593037
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.266511605
Short name T30
Test name
Test status
Simulation time 49598416794 ps
CPU time 521.48 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:27:25 PM PST 24
Peak memory 215252 kb
Host smart-a080bcd2-10fb-40e0-a267-4cb2a8655316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266511605 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.266511605
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3978784295
Short name T46
Test name
Test status
Simulation time 273294300 ps
CPU time 1.33 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:18:43 PM PST 24
Peak memory 196936 kb
Host smart-08a957cd-3adb-4286-af70-a0c5f1ebbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978784295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3978784295
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2737173018
Short name T125
Test name
Test status
Simulation time 37024270999 ps
CPU time 29.53 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 199308 kb
Host smart-0ba5469a-a1e1-487d-8c91-738cabd842f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737173018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2737173018
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2695427075
Short name T789
Test name
Test status
Simulation time 43399348 ps
CPU time 0.54 seconds
Started Feb 29 01:18:45 PM PST 24
Finished Feb 29 01:18:45 PM PST 24
Peak memory 193860 kb
Host smart-58e9d05e-9378-41be-80bb-bb02c232d0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695427075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2695427075
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1362483192
Short name T728
Test name
Test status
Simulation time 151906444340 ps
CPU time 36.97 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:19:20 PM PST 24
Peak memory 199464 kb
Host smart-35d98c89-5289-4fc8-b624-8a65837cd3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362483192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1362483192
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2195700874
Short name T1042
Test name
Test status
Simulation time 78702811789 ps
CPU time 65.08 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:19:47 PM PST 24
Peak memory 199608 kb
Host smart-547fa756-7db4-4d72-acad-6f1742668e3e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195700874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2195700874
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3703334945
Short name T1007
Test name
Test status
Simulation time 90782790161 ps
CPU time 388.05 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:25:11 PM PST 24
Peak memory 199576 kb
Host smart-6f4337d2-ec9c-4125-9b89-f16561b217b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703334945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3703334945
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.954367494
Short name T671
Test name
Test status
Simulation time 8963322079 ps
CPU time 9.21 seconds
Started Feb 29 01:18:44 PM PST 24
Finished Feb 29 01:18:53 PM PST 24
Peak memory 198632 kb
Host smart-b5975d21-2f01-456f-9882-64efc9aea639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954367494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.954367494
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1397056227
Short name T755
Test name
Test status
Simulation time 17371625504 ps
CPU time 29.11 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 197612 kb
Host smart-8ae80778-0663-4b9e-a2ab-34c7f4d3846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397056227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1397056227
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3048256963
Short name T737
Test name
Test status
Simulation time 21490174903 ps
CPU time 268.81 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:23:11 PM PST 24
Peak memory 199496 kb
Host smart-61337f79-32f5-41aa-b693-71e5ac7f8af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048256963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3048256963
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2119622556
Short name T585
Test name
Test status
Simulation time 1655210180 ps
CPU time 1.19 seconds
Started Feb 29 01:18:40 PM PST 24
Finished Feb 29 01:18:42 PM PST 24
Peak memory 197592 kb
Host smart-28e92364-77c0-440f-8a14-36a7998a6f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119622556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2119622556
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1971563031
Short name T391
Test name
Test status
Simulation time 89671739412 ps
CPU time 82.21 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:20:05 PM PST 24
Peak memory 199560 kb
Host smart-84c8d865-9367-4748-a26e-28533562898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971563031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1971563031
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.266413609
Short name T675
Test name
Test status
Simulation time 4298129085 ps
CPU time 7.4 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:18:49 PM PST 24
Peak memory 195368 kb
Host smart-d63e6a78-f62f-4a71-bd86-5f7b0ed49011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266413609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.266413609
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.177176471
Short name T25
Test name
Test status
Simulation time 134532592 ps
CPU time 0.77 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:44 PM PST 24
Peak memory 217028 kb
Host smart-5c174ce7-4bfc-4208-9904-c95799e2d592
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177176471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.177176471
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3700666596
Short name T553
Test name
Test status
Simulation time 896653100 ps
CPU time 2.75 seconds
Started Feb 29 01:18:44 PM PST 24
Finished Feb 29 01:18:47 PM PST 24
Peak memory 197500 kb
Host smart-67d02b64-2032-4c38-bc7b-e9d0c3eb5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700666596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3700666596
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3978690714
Short name T461
Test name
Test status
Simulation time 1423940890 ps
CPU time 2.3 seconds
Started Feb 29 01:18:41 PM PST 24
Finished Feb 29 01:18:43 PM PST 24
Peak memory 197540 kb
Host smart-6d0f02c1-e401-4a37-8c0f-98e4df9b8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978690714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3978690714
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_alert_test.1024895120
Short name T977
Test name
Test status
Simulation time 42566896 ps
CPU time 0.55 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:19:28 PM PST 24
Peak memory 194084 kb
Host smart-4b0d54fe-3dfc-4164-bc05-e492109aacf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024895120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1024895120
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.12210215
Short name T985
Test name
Test status
Simulation time 47509830230 ps
CPU time 72.57 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 199508 kb
Host smart-164abaaf-a5ea-4314-8f1a-4c410ad1d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12210215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.12210215
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2174463467
Short name T674
Test name
Test status
Simulation time 209817807504 ps
CPU time 76.26 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:20:46 PM PST 24
Peak memory 198876 kb
Host smart-700504b6-5127-40a8-ac1f-8880589f6b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174463467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2174463467
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1669489903
Short name T127
Test name
Test status
Simulation time 27479417119 ps
CPU time 47.5 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:20:16 PM PST 24
Peak memory 199292 kb
Host smart-7661d233-686f-4c11-b76c-94f56c0585dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669489903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1669489903
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2549590380
Short name T527
Test name
Test status
Simulation time 392697941034 ps
CPU time 116.87 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:21:28 PM PST 24
Peak memory 198620 kb
Host smart-a54b750d-9f85-4dba-9496-7f7ad8f3320f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549590380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2549590380
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2560333867
Short name T559
Test name
Test status
Simulation time 122130571932 ps
CPU time 340.71 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:25:13 PM PST 24
Peak memory 199548 kb
Host smart-2faed957-9ee9-48cd-b825-09d201deb9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560333867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2560333867
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.739981156
Short name T481
Test name
Test status
Simulation time 1329010640 ps
CPU time 1.3 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:33 PM PST 24
Peak memory 195968 kb
Host smart-66cad813-8e86-4db2-a896-6595a9a89e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739981156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.739981156
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3865986555
Short name T838
Test name
Test status
Simulation time 49755727958 ps
CPU time 18.41 seconds
Started Feb 29 01:19:30 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 196784 kb
Host smart-1eba756b-b468-4672-8f0e-aa8aa99c1edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865986555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3865986555
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.521527762
Short name T753
Test name
Test status
Simulation time 7848208264 ps
CPU time 459.85 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:27:08 PM PST 24
Peak memory 199548 kb
Host smart-b5bf4482-17b2-4d57-a162-cd2b030925bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521527762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.521527762
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3411873157
Short name T536
Test name
Test status
Simulation time 4714181954 ps
CPU time 20.33 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:50 PM PST 24
Peak memory 198296 kb
Host smart-616a5d98-2817-40f3-8f41-f8eae1efaddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411873157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3411873157
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2841706977
Short name T392
Test name
Test status
Simulation time 99803023629 ps
CPU time 41.53 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:20:11 PM PST 24
Peak memory 199392 kb
Host smart-f2dbc737-d3c3-49c7-a668-a830e07c0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841706977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2841706977
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1937397273
Short name T968
Test name
Test status
Simulation time 1883091795 ps
CPU time 1.47 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:19:30 PM PST 24
Peak memory 194924 kb
Host smart-5c84edb0-4615-48ac-9307-16d4560ac632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937397273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1937397273
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.175114958
Short name T683
Test name
Test status
Simulation time 765234899 ps
CPU time 1.62 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:19:32 PM PST 24
Peak memory 198460 kb
Host smart-cbbb1ab5-6cc4-4f84-ba51-1b1d8bb3b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175114958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.175114958
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3154648497
Short name T474
Test name
Test status
Simulation time 847078757 ps
CPU time 1.5 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 197484 kb
Host smart-6cebe4b7-9e3d-43a3-a85f-fc51d24002dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154648497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3154648497
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.667283347
Short name T485
Test name
Test status
Simulation time 31403749898 ps
CPU time 11.67 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 197872 kb
Host smart-09a21559-810e-49e4-aebb-6e206764b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667283347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.667283347
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4001971199
Short name T934
Test name
Test status
Simulation time 101293277243 ps
CPU time 132.9 seconds
Started Feb 29 01:23:37 PM PST 24
Finished Feb 29 01:25:50 PM PST 24
Peak memory 199588 kb
Host smart-3f374a0e-edd5-4f4f-ac6b-5b6bb784b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001971199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4001971199
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1001874416
Short name T969
Test name
Test status
Simulation time 67810453674 ps
CPU time 19.8 seconds
Started Feb 29 01:23:39 PM PST 24
Finished Feb 29 01:23:59 PM PST 24
Peak memory 199328 kb
Host smart-5b5e486e-12dd-4043-88c4-22b1364dbc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001874416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1001874416
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3540494835
Short name T935
Test name
Test status
Simulation time 6377763403 ps
CPU time 10.33 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:23:49 PM PST 24
Peak memory 197716 kb
Host smart-c11dbe09-a4bd-4291-9dd8-bff7d8eef4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540494835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3540494835
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.542712414
Short name T718
Test name
Test status
Simulation time 151202201919 ps
CPU time 65.01 seconds
Started Feb 29 01:23:39 PM PST 24
Finished Feb 29 01:24:44 PM PST 24
Peak memory 198116 kb
Host smart-48fe089e-f28d-43c1-bef8-4501ea98c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542712414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.542712414
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2355958401
Short name T1033
Test name
Test status
Simulation time 17898889079 ps
CPU time 8.35 seconds
Started Feb 29 01:23:37 PM PST 24
Finished Feb 29 01:23:45 PM PST 24
Peak memory 199576 kb
Host smart-136c81ca-9af2-480c-bc74-5fccf9a4040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355958401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2355958401
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2791127452
Short name T899
Test name
Test status
Simulation time 63425687549 ps
CPU time 94.89 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:25:13 PM PST 24
Peak memory 199548 kb
Host smart-5f82a6b7-5977-479d-821e-52d531c61d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791127452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2791127452
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2386212907
Short name T273
Test name
Test status
Simulation time 21245971297 ps
CPU time 13.99 seconds
Started Feb 29 01:23:39 PM PST 24
Finished Feb 29 01:23:53 PM PST 24
Peak memory 199380 kb
Host smart-9db22a90-98b9-404c-ba34-b5298905a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386212907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2386212907
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2967638393
Short name T216
Test name
Test status
Simulation time 9034010342 ps
CPU time 13.44 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:23:52 PM PST 24
Peak memory 196508 kb
Host smart-b14484cc-29b3-4fec-9d4f-9ccab71371bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967638393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2967638393
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.584627069
Short name T214
Test name
Test status
Simulation time 71892047281 ps
CPU time 61.39 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:20:28 PM PST 24
Peak memory 199596 kb
Host smart-c693f925-0ab6-4330-b8f2-92387b0ca267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584627069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.584627069
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1178859773
Short name T433
Test name
Test status
Simulation time 114485408191 ps
CPU time 47.1 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:20:16 PM PST 24
Peak memory 199488 kb
Host smart-a8487294-5508-4072-bd9c-9da9390b98c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178859773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1178859773
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3211593184
Short name T166
Test name
Test status
Simulation time 45420204207 ps
CPU time 33.84 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:20:04 PM PST 24
Peak memory 199152 kb
Host smart-2a0c6f4a-5a98-4b7f-8b7f-95620d85f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211593184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3211593184
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.939902328
Short name T987
Test name
Test status
Simulation time 121750558613 ps
CPU time 69.28 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:20:41 PM PST 24
Peak memory 198228 kb
Host smart-017738c6-2b64-4a03-aadd-543af01e45af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939902328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.939902328
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.245407663
Short name T1018
Test name
Test status
Simulation time 271802483937 ps
CPU time 193.86 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:22:40 PM PST 24
Peak memory 199564 kb
Host smart-81af1968-51e2-4c6f-b2b0-534da5cf7d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245407663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.245407663
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.752892017
Short name T87
Test name
Test status
Simulation time 3916494211 ps
CPU time 5.85 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:19:38 PM PST 24
Peak memory 195112 kb
Host smart-d9628431-b84c-49d9-b72f-07dbc1840550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752892017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.752892017
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3447615553
Short name T650
Test name
Test status
Simulation time 208161958916 ps
CPU time 209.64 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:23:00 PM PST 24
Peak memory 207688 kb
Host smart-41b1ced0-8ee6-4197-b427-75a6400b2cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447615553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3447615553
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2272906285
Short name T434
Test name
Test status
Simulation time 7766816679 ps
CPU time 90.09 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:21:02 PM PST 24
Peak memory 199596 kb
Host smart-755bf875-1d28-4e10-b75e-1b33910b86fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272906285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2272906285
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2988707372
Short name T1020
Test name
Test status
Simulation time 2793570059 ps
CPU time 6.67 seconds
Started Feb 29 01:19:25 PM PST 24
Finished Feb 29 01:19:33 PM PST 24
Peak memory 197572 kb
Host smart-8484bb50-0ff3-41f2-bbbc-49448f7f1af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988707372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2988707372
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.340852957
Short name T409
Test name
Test status
Simulation time 37932436335 ps
CPU time 15.4 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 195296 kb
Host smart-284fc7e5-0c16-4eaa-8d16-fc5c40b191b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340852957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.340852957
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1710523309
Short name T500
Test name
Test status
Simulation time 5761656693 ps
CPU time 10.78 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:19:39 PM PST 24
Peak memory 198896 kb
Host smart-e58bb5d6-3686-4be6-95ff-44b776b7cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710523309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1710523309
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2580452484
Short name T834
Test name
Test status
Simulation time 6121640184 ps
CPU time 22.11 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:54 PM PST 24
Peak memory 199024 kb
Host smart-99c3c029-e84b-4c84-918f-da05323c69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580452484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2580452484
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3691478932
Short name T586
Test name
Test status
Simulation time 12772878039 ps
CPU time 29.47 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 199500 kb
Host smart-d1bb3c47-bd3e-4e80-8baf-d2a6ea3d2771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691478932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3691478932
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1172997930
Short name T246
Test name
Test status
Simulation time 165026706684 ps
CPU time 227.33 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:27:25 PM PST 24
Peak memory 199492 kb
Host smart-9defc8a6-0c2d-4693-9c39-e3d505581d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172997930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1172997930
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3149823534
Short name T341
Test name
Test status
Simulation time 83666725530 ps
CPU time 138.8 seconds
Started Feb 29 01:23:41 PM PST 24
Finished Feb 29 01:26:00 PM PST 24
Peak memory 199772 kb
Host smart-b3ac8a8a-b11e-485f-952c-4030189c9ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149823534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3149823534
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2480120087
Short name T126
Test name
Test status
Simulation time 81442530426 ps
CPU time 22.2 seconds
Started Feb 29 01:23:42 PM PST 24
Finished Feb 29 01:24:04 PM PST 24
Peak memory 198020 kb
Host smart-0b300453-a7cc-40ad-8f9c-c4166a80abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480120087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2480120087
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.405161604
Short name T161
Test name
Test status
Simulation time 111163768132 ps
CPU time 164.49 seconds
Started Feb 29 01:23:40 PM PST 24
Finished Feb 29 01:26:25 PM PST 24
Peak memory 199360 kb
Host smart-9c23045e-27d9-4a02-ac5a-a6ead99c3483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405161604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.405161604
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3520904919
Short name T1051
Test name
Test status
Simulation time 5546436040 ps
CPU time 16.01 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:23:55 PM PST 24
Peak memory 199552 kb
Host smart-3c8c5cea-23f0-4574-839d-92b8ce12d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520904919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3520904919
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4120904457
Short name T912
Test name
Test status
Simulation time 29883908823 ps
CPU time 23.51 seconds
Started Feb 29 01:23:39 PM PST 24
Finished Feb 29 01:24:03 PM PST 24
Peak memory 199608 kb
Host smart-e610cfae-6629-432a-8cf9-274e499f2187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120904457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4120904457
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2172944874
Short name T188
Test name
Test status
Simulation time 63813836461 ps
CPU time 111.53 seconds
Started Feb 29 01:23:42 PM PST 24
Finished Feb 29 01:25:34 PM PST 24
Peak memory 199544 kb
Host smart-ca5cae67-899a-4854-8d63-b3271e3edf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172944874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2172944874
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2148240655
Short name T304
Test name
Test status
Simulation time 16435621706 ps
CPU time 28.49 seconds
Started Feb 29 01:23:44 PM PST 24
Finished Feb 29 01:24:13 PM PST 24
Peak memory 199552 kb
Host smart-ea419036-1873-4dc8-bc03-27e27e4d673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148240655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2148240655
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2735975797
Short name T995
Test name
Test status
Simulation time 51861730 ps
CPU time 0.54 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:32 PM PST 24
Peak memory 195024 kb
Host smart-1d39afd9-8234-4bd8-a321-204615495c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735975797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2735975797
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1448247895
Short name T711
Test name
Test status
Simulation time 120658023575 ps
CPU time 185.62 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:22:36 PM PST 24
Peak memory 199628 kb
Host smart-22e4bd02-3a00-4338-9cf8-e5a417ca8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448247895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1448247895
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2595917715
Short name T1015
Test name
Test status
Simulation time 60506322987 ps
CPU time 104.79 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:21:16 PM PST 24
Peak memory 199836 kb
Host smart-589ac380-5a44-4eff-8a29-ca25d87f77b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595917715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2595917715
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1185628635
Short name T649
Test name
Test status
Simulation time 332313095487 ps
CPU time 119.78 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:21:34 PM PST 24
Peak memory 199280 kb
Host smart-67e3ae36-54bc-4d3a-a324-980d1dfb3cd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185628635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1185628635
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3557864198
Short name T890
Test name
Test status
Simulation time 26863232897 ps
CPU time 122.37 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:21:37 PM PST 24
Peak memory 199520 kb
Host smart-c812450f-09ab-4495-85d5-4bd3b61f8043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557864198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3557864198
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2592006643
Short name T937
Test name
Test status
Simulation time 1778775509 ps
CPU time 1.99 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:19:37 PM PST 24
Peak memory 197748 kb
Host smart-7118aaf7-6664-4498-a257-2c5912a1766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592006643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2592006643
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1402037555
Short name T826
Test name
Test status
Simulation time 68424527314 ps
CPU time 163.64 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 207968 kb
Host smart-cbf64e2f-8374-4dd2-af9b-5bee5925182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402037555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1402037555
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3872609667
Short name T12
Test name
Test status
Simulation time 45576525734 ps
CPU time 1036.88 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:36:51 PM PST 24
Peak memory 199676 kb
Host smart-597e9587-d86b-4038-952b-9e01183b2f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872609667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3872609667
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1100840824
Short name T698
Test name
Test status
Simulation time 1398163386 ps
CPU time 10.35 seconds
Started Feb 29 01:19:33 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 197300 kb
Host smart-0b5aaf40-65ce-4356-8f7c-99ef3fee8771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100840824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1100840824
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3344949773
Short name T417
Test name
Test status
Simulation time 70250355294 ps
CPU time 54.27 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:20:29 PM PST 24
Peak memory 199320 kb
Host smart-15176018-928e-4031-9e3f-2baea5b296e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344949773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3344949773
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3841816763
Short name T506
Test name
Test status
Simulation time 3421960678 ps
CPU time 3.4 seconds
Started Feb 29 01:19:29 PM PST 24
Finished Feb 29 01:19:33 PM PST 24
Peak memory 195384 kb
Host smart-1f733c38-3b18-4c38-b07a-a5248f97147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841816763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3841816763
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1956174979
Short name T800
Test name
Test status
Simulation time 734869421 ps
CPU time 3.18 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:35 PM PST 24
Peak memory 197344 kb
Host smart-9a467999-0fb4-42fe-a2cc-c122a3b135e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956174979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1956174979
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1460695942
Short name T1021
Test name
Test status
Simulation time 3603491058449 ps
CPU time 6778.23 seconds
Started Feb 29 01:19:33 PM PST 24
Finished Feb 29 03:12:32 PM PST 24
Peak memory 199852 kb
Host smart-cb7d7b6e-76a4-4b7a-ab78-b1be13f93439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460695942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1460695942
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.646272636
Short name T446
Test name
Test status
Simulation time 14552663596 ps
CPU time 172.24 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:22:27 PM PST 24
Peak memory 209068 kb
Host smart-0d1bcb8d-216d-4cf9-982b-9a21809c661a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646272636 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.646272636
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1841876769
Short name T693
Test name
Test status
Simulation time 2098031258 ps
CPU time 2.19 seconds
Started Feb 29 01:19:30 PM PST 24
Finished Feb 29 01:19:33 PM PST 24
Peak memory 197636 kb
Host smart-b43cc8ab-079a-4dad-9b68-96f9875a8eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841876769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1841876769
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3717989462
Short name T739
Test name
Test status
Simulation time 74338257957 ps
CPU time 57 seconds
Started Feb 29 01:19:33 PM PST 24
Finished Feb 29 01:20:30 PM PST 24
Peak memory 199596 kb
Host smart-11ef6dc7-7542-4ec5-8c6a-58f2b69368ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717989462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3717989462
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2385689794
Short name T116
Test name
Test status
Simulation time 137869563102 ps
CPU time 323.44 seconds
Started Feb 29 01:23:39 PM PST 24
Finished Feb 29 01:29:02 PM PST 24
Peak memory 199384 kb
Host smart-0918b6d1-bb43-46fb-92ef-76338b0f3103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385689794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2385689794
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.773619391
Short name T511
Test name
Test status
Simulation time 30816074809 ps
CPU time 50.73 seconds
Started Feb 29 01:23:40 PM PST 24
Finished Feb 29 01:24:31 PM PST 24
Peak memory 199192 kb
Host smart-cdc06aa8-85c9-4edb-b8d8-1bd4fa5b188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773619391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.773619391
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.734468599
Short name T267
Test name
Test status
Simulation time 46009443137 ps
CPU time 76.69 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 199600 kb
Host smart-cf48419d-adb8-4a1a-baae-ca3585e213ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734468599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.734468599
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4123130542
Short name T817
Test name
Test status
Simulation time 65696568080 ps
CPU time 39.38 seconds
Started Feb 29 01:23:44 PM PST 24
Finished Feb 29 01:24:23 PM PST 24
Peak memory 199520 kb
Host smart-79235054-fbda-42f9-abb1-bc7d03b9ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123130542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4123130542
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1329127511
Short name T303
Test name
Test status
Simulation time 174393555472 ps
CPU time 257.49 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:28:01 PM PST 24
Peak memory 199624 kb
Host smart-89158b6d-1943-4460-95e4-3a96fcbd7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329127511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1329127511
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2810269647
Short name T248
Test name
Test status
Simulation time 120332949855 ps
CPU time 201.59 seconds
Started Feb 29 01:23:42 PM PST 24
Finished Feb 29 01:27:04 PM PST 24
Peak memory 199560 kb
Host smart-88c02d46-adc1-41b0-bec8-ed4bee7e5708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810269647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2810269647
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.270060599
Short name T1076
Test name
Test status
Simulation time 24922963184 ps
CPU time 10.32 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:23:54 PM PST 24
Peak memory 199556 kb
Host smart-71ffbfe7-e219-4ea4-a605-d7bb130523a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270060599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.270060599
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.446575393
Short name T770
Test name
Test status
Simulation time 18914248 ps
CPU time 0.54 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:19:40 PM PST 24
Peak memory 194088 kb
Host smart-de0e9a0c-6622-4733-af20-5cc24569e7a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446575393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.446575393
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2778235646
Short name T149
Test name
Test status
Simulation time 95080691676 ps
CPU time 138.02 seconds
Started Feb 29 01:19:36 PM PST 24
Finished Feb 29 01:21:54 PM PST 24
Peak memory 199540 kb
Host smart-f539f960-a33a-44ab-a1f3-170f76d877af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778235646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2778235646
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.743779660
Short name T666
Test name
Test status
Simulation time 236773729698 ps
CPU time 76.89 seconds
Started Feb 29 01:19:37 PM PST 24
Finished Feb 29 01:20:54 PM PST 24
Peak memory 199160 kb
Host smart-a6485d52-26d7-4a4e-a92f-470838cf06d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743779660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.743779660
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2214275539
Short name T1098
Test name
Test status
Simulation time 33644304056 ps
CPU time 12.93 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:19:46 PM PST 24
Peak memory 199484 kb
Host smart-ab56ed40-b256-4d02-ba09-f7bf6bc89790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214275539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2214275539
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3105561751
Short name T14
Test name
Test status
Simulation time 675246928420 ps
CPU time 408.68 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:26:23 PM PST 24
Peak memory 198008 kb
Host smart-033e326b-31bc-457f-8914-8695c63cfe2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105561751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3105561751
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.49192950
Short name T626
Test name
Test status
Simulation time 297559771205 ps
CPU time 234.89 seconds
Started Feb 29 01:19:35 PM PST 24
Finished Feb 29 01:23:30 PM PST 24
Peak memory 199592 kb
Host smart-a6c8b354-0051-4832-8015-8b89bdb704ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49192950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.49192950
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3132549489
Short name T458
Test name
Test status
Simulation time 10299657003 ps
CPU time 22.73 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:20:02 PM PST 24
Peak memory 198212 kb
Host smart-24384c24-1acc-468d-bfeb-0d890760736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132549489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3132549489
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.783576654
Short name T748
Test name
Test status
Simulation time 25354472280 ps
CPU time 47.09 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:20:27 PM PST 24
Peak memory 197768 kb
Host smart-c89c4065-8c39-4c2a-a57f-881543dad3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783576654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.783576654
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3842574857
Short name T805
Test name
Test status
Simulation time 12114437996 ps
CPU time 609.74 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:29:44 PM PST 24
Peak memory 199572 kb
Host smart-623cef45-3d27-4eff-bbf0-4bc386d68fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842574857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3842574857
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.253751878
Short name T348
Test name
Test status
Simulation time 191757325962 ps
CPU time 263.85 seconds
Started Feb 29 01:19:40 PM PST 24
Finished Feb 29 01:24:05 PM PST 24
Peak memory 199496 kb
Host smart-f1e53d01-7123-4764-8407-be04ce9045a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253751878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.253751878
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3635832095
Short name T703
Test name
Test status
Simulation time 3659501960 ps
CPU time 5.85 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:19:39 PM PST 24
Peak memory 195148 kb
Host smart-e11f2295-dc42-407a-9940-9ea392f016fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635832095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3635832095
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1518692788
Short name T714
Test name
Test status
Simulation time 947708140 ps
CPU time 2.27 seconds
Started Feb 29 01:19:37 PM PST 24
Finished Feb 29 01:19:40 PM PST 24
Peak memory 197876 kb
Host smart-1e6aadbc-dc9d-4edf-8084-2d2e9fe4fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518692788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1518692788
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3548814740
Short name T111
Test name
Test status
Simulation time 80454587780 ps
CPU time 34.81 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:20:07 PM PST 24
Peak memory 199588 kb
Host smart-6285cb23-d779-462d-9193-20b22e8362f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548814740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3548814740
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1339520073
Short name T18
Test name
Test status
Simulation time 6578378814 ps
CPU time 36.56 seconds
Started Feb 29 01:19:34 PM PST 24
Finished Feb 29 01:20:11 PM PST 24
Peak memory 199012 kb
Host smart-dfb67f9e-7e78-4195-959c-8561e60298fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339520073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1339520073
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.731003438
Short name T963
Test name
Test status
Simulation time 120873652200 ps
CPU time 71.31 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:20:51 PM PST 24
Peak memory 199564 kb
Host smart-30bb0114-3fb4-47f2-b7df-11ecc7620011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731003438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.731003438
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.154092038
Short name T299
Test name
Test status
Simulation time 15859115908 ps
CPU time 26.39 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:24:10 PM PST 24
Peak memory 199556 kb
Host smart-059b75e2-4bc0-4102-8e07-053ac4d2e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154092038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.154092038
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.797771489
Short name T625
Test name
Test status
Simulation time 192185542630 ps
CPU time 28.32 seconds
Started Feb 29 01:23:43 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199536 kb
Host smart-ff48811d-eeab-487b-abf8-fb6512d48e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797771489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.797771489
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1934723632
Short name T200
Test name
Test status
Simulation time 56480322163 ps
CPU time 44.5 seconds
Started Feb 29 01:23:46 PM PST 24
Finished Feb 29 01:24:31 PM PST 24
Peak memory 199548 kb
Host smart-a8f3466b-6a5a-45e2-8fc8-699fc198a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934723632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1934723632
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3116956857
Short name T338
Test name
Test status
Simulation time 15535722494 ps
CPU time 37.65 seconds
Started Feb 29 01:23:46 PM PST 24
Finished Feb 29 01:24:24 PM PST 24
Peak memory 199516 kb
Host smart-c98a1c5f-552c-4b06-8131-d70b2b55589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116956857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3116956857
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2639155309
Short name T377
Test name
Test status
Simulation time 47472474233 ps
CPU time 27.81 seconds
Started Feb 29 01:23:47 PM PST 24
Finished Feb 29 01:24:16 PM PST 24
Peak memory 199540 kb
Host smart-76fc8cf2-80b6-49fa-9e0c-b6a57d78dbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639155309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2639155309
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3866143100
Short name T264
Test name
Test status
Simulation time 10540279150 ps
CPU time 15.59 seconds
Started Feb 29 01:23:49 PM PST 24
Finished Feb 29 01:24:05 PM PST 24
Peak memory 199272 kb
Host smart-f1ea8759-f938-4140-9544-8923dc882262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866143100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3866143100
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.397684933
Short name T23
Test name
Test status
Simulation time 15884718 ps
CPU time 0.57 seconds
Started Feb 29 01:19:41 PM PST 24
Finished Feb 29 01:19:42 PM PST 24
Peak memory 194960 kb
Host smart-11e610fa-70da-4767-8257-3ee009a9d9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397684933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.397684933
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.712746397
Short name T839
Test name
Test status
Simulation time 197385487725 ps
CPU time 39.47 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:20:19 PM PST 24
Peak memory 199600 kb
Host smart-c29e05c3-bd7b-410a-b110-d964324e73b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712746397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.712746397
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.539026510
Short name T1028
Test name
Test status
Simulation time 47725381522 ps
CPU time 21.6 seconds
Started Feb 29 01:19:38 PM PST 24
Finished Feb 29 01:20:00 PM PST 24
Peak memory 199640 kb
Host smart-33411c88-f483-4f79-aa6c-5bd97a527b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539026510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.539026510
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3705551783
Short name T198
Test name
Test status
Simulation time 8780779569 ps
CPU time 14.16 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:19:54 PM PST 24
Peak memory 199224 kb
Host smart-4b65188c-efc1-4432-9374-e9d49d589261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705551783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3705551783
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3626793956
Short name T75
Test name
Test status
Simulation time 548693949970 ps
CPU time 699.22 seconds
Started Feb 29 01:19:41 PM PST 24
Finished Feb 29 01:31:21 PM PST 24
Peak memory 199492 kb
Host smart-6557ac70-036f-451b-a693-f3343f988f7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626793956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3626793956
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1724412280
Short name T984
Test name
Test status
Simulation time 152139241469 ps
CPU time 657.98 seconds
Started Feb 29 01:19:41 PM PST 24
Finished Feb 29 01:30:39 PM PST 24
Peak memory 199648 kb
Host smart-4cfbe007-bdae-4e0c-8664-2689c2e60d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724412280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1724412280
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.233055287
Short name T577
Test name
Test status
Simulation time 8137122532 ps
CPU time 6.38 seconds
Started Feb 29 01:19:41 PM PST 24
Finished Feb 29 01:19:48 PM PST 24
Peak memory 198728 kb
Host smart-e15d4ad8-0d90-4eb6-8e85-66190c3fcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233055287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.233055287
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2305698288
Short name T173
Test name
Test status
Simulation time 57928795221 ps
CPU time 105.86 seconds
Started Feb 29 01:19:49 PM PST 24
Finished Feb 29 01:21:35 PM PST 24
Peak memory 199772 kb
Host smart-4617a41f-085e-4fbb-902c-96e102fbbe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305698288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2305698288
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3548429464
Short name T483
Test name
Test status
Simulation time 8844476752 ps
CPU time 475.03 seconds
Started Feb 29 01:19:38 PM PST 24
Finished Feb 29 01:27:34 PM PST 24
Peak memory 199516 kb
Host smart-61eb0c61-47d0-4347-b7a3-336fbf3475fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548429464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3548429464
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2668008898
Short name T523
Test name
Test status
Simulation time 1172193176 ps
CPU time 1.68 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:19:41 PM PST 24
Peak memory 195972 kb
Host smart-122e3825-6bd0-410d-be64-117208a75ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668008898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2668008898
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2236764786
Short name T519
Test name
Test status
Simulation time 73196007664 ps
CPU time 57.08 seconds
Started Feb 29 01:19:41 PM PST 24
Finished Feb 29 01:20:38 PM PST 24
Peak memory 199164 kb
Host smart-641b347c-146d-4776-a9b2-6cb329becf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236764786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2236764786
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.246841784
Short name T1036
Test name
Test status
Simulation time 522092363 ps
CPU time 1.43 seconds
Started Feb 29 01:19:38 PM PST 24
Finished Feb 29 01:19:39 PM PST 24
Peak memory 195028 kb
Host smart-17b78b25-8967-4984-97df-8d7fc27490c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246841784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.246841784
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1640399581
Short name T531
Test name
Test status
Simulation time 711855747 ps
CPU time 1.78 seconds
Started Feb 29 01:19:38 PM PST 24
Finished Feb 29 01:19:40 PM PST 24
Peak memory 197460 kb
Host smart-0c53a5dc-b7f4-43e7-bf0b-b2176aea5206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640399581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1640399581
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2382961500
Short name T505
Test name
Test status
Simulation time 152699586878 ps
CPU time 644.82 seconds
Started Feb 29 01:19:38 PM PST 24
Finished Feb 29 01:30:23 PM PST 24
Peak memory 199656 kb
Host smart-78887132-4fcc-4d95-b9ac-b463d53b236a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382961500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2382961500
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1931252269
Short name T451
Test name
Test status
Simulation time 374380773102 ps
CPU time 599.61 seconds
Started Feb 29 01:19:32 PM PST 24
Finished Feb 29 01:29:32 PM PST 24
Peak memory 216100 kb
Host smart-ce2dcc3f-b737-42a2-b813-da6c4e13febb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931252269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1931252269
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2008865237
Short name T750
Test name
Test status
Simulation time 2429716587 ps
CPU time 2.25 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:19:34 PM PST 24
Peak memory 197792 kb
Host smart-8bbe1b30-aebe-4b98-bc07-cefc241e5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008865237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2008865237
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.92345372
Short name T883
Test name
Test status
Simulation time 59096506218 ps
CPU time 24.98 seconds
Started Feb 29 01:19:39 PM PST 24
Finished Feb 29 01:20:04 PM PST 24
Peak memory 199624 kb
Host smart-9f0aef9d-26c8-4c37-8814-04f5382c6a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92345372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.92345372
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2589770875
Short name T172
Test name
Test status
Simulation time 95016493499 ps
CPU time 80.93 seconds
Started Feb 29 01:23:47 PM PST 24
Finished Feb 29 01:25:09 PM PST 24
Peak memory 199568 kb
Host smart-2f2145dc-c687-43af-b880-43144e8a2dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589770875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2589770875
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.639855747
Short name T691
Test name
Test status
Simulation time 40443341119 ps
CPU time 69.54 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 198888 kb
Host smart-a4b8a680-c715-4fc0-8619-2a352242d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639855747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.639855747
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1437894234
Short name T345
Test name
Test status
Simulation time 21069580920 ps
CPU time 32.61 seconds
Started Feb 29 01:23:50 PM PST 24
Finished Feb 29 01:24:23 PM PST 24
Peak memory 199572 kb
Host smart-a8f0ac51-437d-40d9-976b-8253735e62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437894234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1437894234
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.521701640
Short name T971
Test name
Test status
Simulation time 41612035922 ps
CPU time 18.11 seconds
Started Feb 29 01:23:50 PM PST 24
Finished Feb 29 01:24:08 PM PST 24
Peak memory 198236 kb
Host smart-411d056c-539e-4c5a-924b-3a864595e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521701640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.521701640
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.257868093
Short name T333
Test name
Test status
Simulation time 117260583512 ps
CPU time 167.16 seconds
Started Feb 29 01:23:49 PM PST 24
Finished Feb 29 01:26:37 PM PST 24
Peak memory 199228 kb
Host smart-eb7e08e6-b6bd-4fb0-92c9-e753a103e896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257868093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.257868093
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.561633213
Short name T413
Test name
Test status
Simulation time 51331374318 ps
CPU time 38.73 seconds
Started Feb 29 01:23:47 PM PST 24
Finished Feb 29 01:24:26 PM PST 24
Peak memory 199528 kb
Host smart-1b0d3445-5a93-4a09-a61f-adde1b374825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561633213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.561633213
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.129446911
Short name T469
Test name
Test status
Simulation time 19789181 ps
CPU time 0.52 seconds
Started Feb 29 01:19:43 PM PST 24
Finished Feb 29 01:19:44 PM PST 24
Peak memory 195020 kb
Host smart-cfe86bab-2ab4-4386-a0b0-c3098851932b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129446911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.129446911
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.124131321
Short name T727
Test name
Test status
Simulation time 26877463092 ps
CPU time 17.12 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:20:05 PM PST 24
Peak memory 199556 kb
Host smart-1013a3d9-cd6c-411f-941d-accaa9bf10a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124131321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.124131321
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2191499038
Short name T331
Test name
Test status
Simulation time 115531670825 ps
CPU time 176.19 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:22:43 PM PST 24
Peak memory 199592 kb
Host smart-fd287ffe-460f-4813-9e7f-e23e341fa831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191499038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2191499038
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3390746080
Short name T139
Test name
Test status
Simulation time 95524899857 ps
CPU time 87.56 seconds
Started Feb 29 01:19:45 PM PST 24
Finished Feb 29 01:21:13 PM PST 24
Peak memory 199356 kb
Host smart-195c83be-9263-49f5-bb56-dcf755b54e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390746080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3390746080
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1537871078
Short name T862
Test name
Test status
Simulation time 848186544577 ps
CPU time 1207.76 seconds
Started Feb 29 01:19:45 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 198660 kb
Host smart-b03dd749-1be2-4a0a-8d29-ee7d9d3da4cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537871078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1537871078
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.190284281
Short name T967
Test name
Test status
Simulation time 222129891939 ps
CPU time 385.34 seconds
Started Feb 29 01:19:45 PM PST 24
Finished Feb 29 01:26:10 PM PST 24
Peak memory 199624 kb
Host smart-20876c1c-c00a-4314-8aeb-03378477dcbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190284281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.190284281
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2129094202
Short name T1059
Test name
Test status
Simulation time 5037246202 ps
CPU time 12.97 seconds
Started Feb 29 01:19:43 PM PST 24
Finished Feb 29 01:19:56 PM PST 24
Peak memory 198864 kb
Host smart-57ef6861-1eca-4808-a000-67c4c8c24a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129094202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2129094202
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2015557424
Short name T792
Test name
Test status
Simulation time 12444176231 ps
CPU time 20.89 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 197240 kb
Host smart-c023b4ee-db09-44de-9edb-82a87fb44d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015557424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2015557424
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.364945233
Short name T868
Test name
Test status
Simulation time 8581160296 ps
CPU time 105.13 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:21:33 PM PST 24
Peak memory 199576 kb
Host smart-c8365b28-4843-48c8-b434-b923adf19518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364945233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.364945233
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.901589008
Short name T477
Test name
Test status
Simulation time 2010604298 ps
CPU time 5.51 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:19:53 PM PST 24
Peak memory 197720 kb
Host smart-bdffcfb4-cee2-41fd-95c1-8c088eceaf21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901589008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.901589008
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.680582084
Short name T999
Test name
Test status
Simulation time 136417728416 ps
CPU time 63.78 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:20:52 PM PST 24
Peak memory 198808 kb
Host smart-16367aea-4f3a-43ac-b2de-736c43f5d110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680582084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.680582084
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.183721454
Short name T893
Test name
Test status
Simulation time 4685983048 ps
CPU time 1.23 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 195276 kb
Host smart-672dee8d-a374-4c41-8f87-baf15f3c3d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183721454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.183721454
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1303359154
Short name T1052
Test name
Test status
Simulation time 462447573 ps
CPU time 1.03 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 197592 kb
Host smart-f08a50e4-fbe5-47dc-8300-09d4d89cdfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303359154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1303359154
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2060884347
Short name T112
Test name
Test status
Simulation time 137237679558 ps
CPU time 96.29 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 199620 kb
Host smart-d073f971-b453-4cb1-bfce-cfacae69b279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060884347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2060884347
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3339419192
Short name T848
Test name
Test status
Simulation time 6551309343 ps
CPU time 36.04 seconds
Started Feb 29 01:19:44 PM PST 24
Finished Feb 29 01:20:20 PM PST 24
Peak memory 199560 kb
Host smart-f27347aa-a1b6-4875-9fc1-b9bbc0b03d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339419192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3339419192
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1995138459
Short name T966
Test name
Test status
Simulation time 175130341852 ps
CPU time 68.57 seconds
Started Feb 29 01:20:40 PM PST 24
Finished Feb 29 01:21:49 PM PST 24
Peak memory 199552 kb
Host smart-93a85910-4a9c-440c-aa84-d16be886b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995138459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1995138459
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2784548517
Short name T283
Test name
Test status
Simulation time 31064108836 ps
CPU time 13.97 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:24:07 PM PST 24
Peak memory 198928 kb
Host smart-0bcbd234-9b46-442b-8ec1-045ac45e14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784548517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2784548517
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2180145439
Short name T991
Test name
Test status
Simulation time 131497473627 ps
CPU time 118.02 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:25:51 PM PST 24
Peak memory 198968 kb
Host smart-16a1eb23-8729-408e-a240-698e14017b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180145439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2180145439
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1938413671
Short name T840
Test name
Test status
Simulation time 29047179991 ps
CPU time 49.04 seconds
Started Feb 29 01:23:50 PM PST 24
Finished Feb 29 01:24:39 PM PST 24
Peak memory 199648 kb
Host smart-5a4573f9-2bd6-410b-a070-0bbd0d1d79c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938413671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1938413671
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3113411134
Short name T320
Test name
Test status
Simulation time 54967809838 ps
CPU time 21.06 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:24:13 PM PST 24
Peak memory 199644 kb
Host smart-9917baaa-bb51-4e76-ad84-7ca75448e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113411134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3113411134
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2988232077
Short name T654
Test name
Test status
Simulation time 29785868195 ps
CPU time 46.5 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:24:37 PM PST 24
Peak memory 198628 kb
Host smart-c2d19594-78a2-4dbf-889f-6c697ae196c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988232077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2988232077
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2881783090
Short name T1012
Test name
Test status
Simulation time 132021709316 ps
CPU time 154.91 seconds
Started Feb 29 01:23:51 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 199572 kb
Host smart-1c04237f-0c08-4a10-8cdc-48182c4f35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881783090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2881783090
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3866132490
Short name T1102
Test name
Test status
Simulation time 106934069968 ps
CPU time 30.88 seconds
Started Feb 29 01:23:53 PM PST 24
Finished Feb 29 01:24:24 PM PST 24
Peak memory 199436 kb
Host smart-d701453e-bdc0-47be-9e67-ce821a864c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866132490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3866132490
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1202969701
Short name T925
Test name
Test status
Simulation time 102926217537 ps
CPU time 155.48 seconds
Started Feb 29 01:23:49 PM PST 24
Finished Feb 29 01:26:25 PM PST 24
Peak memory 199544 kb
Host smart-64357497-052a-4e4b-88e7-94ef53ce4b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202969701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1202969701
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3747377360
Short name T957
Test name
Test status
Simulation time 12765120 ps
CPU time 0.53 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:19:59 PM PST 24
Peak memory 193944 kb
Host smart-cccce20a-b696-4b28-bfba-9e337aa3437c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747377360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3747377360
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1068815385
Short name T629
Test name
Test status
Simulation time 39074265227 ps
CPU time 29.84 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:20:18 PM PST 24
Peak memory 199544 kb
Host smart-9af76960-3e30-48da-9127-f3c7d76eeccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068815385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1068815385
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_intr.3127373981
Short name T845
Test name
Test status
Simulation time 709584554018 ps
CPU time 1113.3 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:38:20 PM PST 24
Peak memory 199464 kb
Host smart-f3d41f54-61ca-4c2f-823d-ebcead690908
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127373981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3127373981
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2454773069
Short name T558
Test name
Test status
Simulation time 118410142822 ps
CPU time 140.72 seconds
Started Feb 29 01:19:44 PM PST 24
Finished Feb 29 01:22:05 PM PST 24
Peak memory 199592 kb
Host smart-f1f28d59-93c3-4bb6-ac14-73570aecd8f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454773069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2454773069
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.944075610
Short name T697
Test name
Test status
Simulation time 8553538300 ps
CPU time 9.86 seconds
Started Feb 29 01:20:00 PM PST 24
Finished Feb 29 01:20:10 PM PST 24
Peak memory 198764 kb
Host smart-f974ee7f-0811-40d0-92e0-b3facf096002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944075610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.944075610
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2486778225
Short name T510
Test name
Test status
Simulation time 107991646455 ps
CPU time 52.62 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 198304 kb
Host smart-628ae86f-7fe5-4070-80b7-981d9e30fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486778225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2486778225
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2234903953
Short name T657
Test name
Test status
Simulation time 10484768605 ps
CPU time 107.29 seconds
Started Feb 29 01:19:44 PM PST 24
Finished Feb 29 01:21:32 PM PST 24
Peak memory 199624 kb
Host smart-130868d2-1a29-4f2f-8a69-1fe4cad52d4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234903953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2234903953
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1709808891
Short name T1084
Test name
Test status
Simulation time 3640257590 ps
CPU time 21.78 seconds
Started Feb 29 01:19:46 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 197872 kb
Host smart-88f5f4e8-b88d-4356-a119-0a4d183fcae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709808891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1709808891
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.232945237
Short name T35
Test name
Test status
Simulation time 67884661401 ps
CPU time 35.47 seconds
Started Feb 29 01:19:47 PM PST 24
Finished Feb 29 01:20:23 PM PST 24
Peak memory 199540 kb
Host smart-ffcaa1f3-c099-4a5a-bc92-0450d760fa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232945237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.232945237
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3834140444
Short name T593
Test name
Test status
Simulation time 608140285 ps
CPU time 1.63 seconds
Started Feb 29 01:20:01 PM PST 24
Finished Feb 29 01:20:03 PM PST 24
Peak memory 194952 kb
Host smart-71a87b5f-c150-401b-9217-224b521ffa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834140444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3834140444
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1532625199
Short name T917
Test name
Test status
Simulation time 474034640 ps
CPU time 1.53 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 197932 kb
Host smart-0464ef65-46fc-4a83-9662-2965b949c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532625199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1532625199
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.78323644
Short name T884
Test name
Test status
Simulation time 655751968244 ps
CPU time 477.12 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:27:54 PM PST 24
Peak memory 207996 kb
Host smart-8e791588-cdd2-4bc9-a7fb-a54895e5b55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78323644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.78323644
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.638540330
Short name T642
Test name
Test status
Simulation time 7752674996 ps
CPU time 11.48 seconds
Started Feb 29 01:19:48 PM PST 24
Finished Feb 29 01:20:00 PM PST 24
Peak memory 198892 kb
Host smart-742506dd-12f3-47c8-8966-f2f62d17317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638540330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.638540330
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1120337064
Short name T777
Test name
Test status
Simulation time 60862411453 ps
CPU time 28.99 seconds
Started Feb 29 01:19:45 PM PST 24
Finished Feb 29 01:20:14 PM PST 24
Peak memory 199604 kb
Host smart-cc979ec0-cd59-4e6b-a4c8-3fc47f238691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120337064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1120337064
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3868420200
Short name T201
Test name
Test status
Simulation time 11854135814 ps
CPU time 20.97 seconds
Started Feb 29 01:23:56 PM PST 24
Finished Feb 29 01:24:17 PM PST 24
Peak memory 199396 kb
Host smart-2a30b045-d6e2-413c-8f69-0b5417ce686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868420200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3868420200
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3485955629
Short name T298
Test name
Test status
Simulation time 37633040592 ps
CPU time 48.92 seconds
Started Feb 29 01:23:50 PM PST 24
Finished Feb 29 01:24:39 PM PST 24
Peak memory 199444 kb
Host smart-d9cc56a4-dabe-4b4a-ab1d-52d4f3173d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485955629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3485955629
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.518173543
Short name T208
Test name
Test status
Simulation time 72679357292 ps
CPU time 17.6 seconds
Started Feb 29 01:23:56 PM PST 24
Finished Feb 29 01:24:13 PM PST 24
Peak memory 199472 kb
Host smart-e78fb030-2fa1-4bcd-b535-e6dcf3167479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518173543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.518173543
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2719787172
Short name T757
Test name
Test status
Simulation time 26251195279 ps
CPU time 37.86 seconds
Started Feb 29 01:23:56 PM PST 24
Finished Feb 29 01:24:34 PM PST 24
Peak memory 199496 kb
Host smart-57b1f06d-fd59-417f-957b-7e6784bd7a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719787172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2719787172
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.495496999
Short name T324
Test name
Test status
Simulation time 34885298015 ps
CPU time 55.18 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:53 PM PST 24
Peak memory 199580 kb
Host smart-1949f4d0-827a-4d81-b455-643fd8643dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495496999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.495496999
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1004638553
Short name T540
Test name
Test status
Simulation time 48308634 ps
CPU time 0.55 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:19:59 PM PST 24
Peak memory 195024 kb
Host smart-47f17375-23e0-4076-84c0-0ac1ca2fec4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004638553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1004638553
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3674727771
Short name T756
Test name
Test status
Simulation time 69315261948 ps
CPU time 48.21 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:20:42 PM PST 24
Peak memory 199560 kb
Host smart-fa2f5718-cec9-4d20-9d31-e30b5626ba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674727771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3674727771
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.4026302580
Short name T1046
Test name
Test status
Simulation time 312624730503 ps
CPU time 55.8 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:20:50 PM PST 24
Peak memory 199528 kb
Host smart-75cbf8cd-d008-4e2e-88ef-07ffcc911167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026302580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4026302580
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1455291597
Short name T929
Test name
Test status
Simulation time 52894955465 ps
CPU time 29.12 seconds
Started Feb 29 01:19:55 PM PST 24
Finished Feb 29 01:20:24 PM PST 24
Peak memory 198960 kb
Host smart-4596f90c-999e-4a01-b218-79b7176a318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455291597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1455291597
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3961034617
Short name T653
Test name
Test status
Simulation time 189843140005 ps
CPU time 121.12 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:22:00 PM PST 24
Peak memory 198276 kb
Host smart-d156ee58-c1bf-47ca-a9ca-cac392a4dd9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961034617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3961034617
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2270747832
Short name T1075
Test name
Test status
Simulation time 119471262693 ps
CPU time 228.27 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:23:45 PM PST 24
Peak memory 199508 kb
Host smart-2d792904-3aea-471d-8547-932f8d995338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270747832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2270747832
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2572606817
Short name T715
Test name
Test status
Simulation time 7032303901 ps
CPU time 11.01 seconds
Started Feb 29 01:20:27 PM PST 24
Finished Feb 29 01:20:39 PM PST 24
Peak memory 197152 kb
Host smart-ccab18b1-bf64-4ba4-aee5-9de4e11a9df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572606817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2572606817
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.174198607
Short name T617
Test name
Test status
Simulation time 19989716913 ps
CPU time 17.87 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:20:14 PM PST 24
Peak memory 196988 kb
Host smart-cbfe9188-2bcb-45c3-8f08-c033d9853ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174198607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.174198607
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2554335853
Short name T1071
Test name
Test status
Simulation time 11604367770 ps
CPU time 339.27 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:25:39 PM PST 24
Peak memory 199584 kb
Host smart-7c846088-7c55-428d-9169-2ff88581bdd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554335853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2554335853
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2656083008
Short name T313
Test name
Test status
Simulation time 20046190421 ps
CPU time 18.01 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:20:12 PM PST 24
Peak memory 198984 kb
Host smart-07fb93de-427d-4aa2-abe0-d5703aee5105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656083008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2656083008
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2309632660
Short name T916
Test name
Test status
Simulation time 626050408 ps
CPU time 0.87 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:19:57 PM PST 24
Peak memory 194972 kb
Host smart-c56d54de-cbda-4172-b572-864c5fc9b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309632660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2309632660
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2279926542
Short name T911
Test name
Test status
Simulation time 6073812968 ps
CPU time 5.16 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:20:01 PM PST 24
Peak memory 199008 kb
Host smart-b4a25881-97f8-44f6-84ec-5cfff59f72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279926542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2279926542
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1704166639
Short name T903
Test name
Test status
Simulation time 121446082513 ps
CPU time 103.8 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:21:38 PM PST 24
Peak memory 199640 kb
Host smart-cbe6f420-15bf-46c3-be2b-31aaab1c3a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704166639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1704166639
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3340275090
Short name T468
Test name
Test status
Simulation time 1330176932 ps
CPU time 2.15 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:19:59 PM PST 24
Peak memory 198388 kb
Host smart-56e60e07-56b1-42b3-b999-58e89a1b48cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340275090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3340275090
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.713419734
Short name T525
Test name
Test status
Simulation time 159824391405 ps
CPU time 39.74 seconds
Started Feb 29 01:19:53 PM PST 24
Finished Feb 29 01:20:33 PM PST 24
Peak memory 199644 kb
Host smart-9a85f4a9-da0c-4681-af34-068d619b8fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713419734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.713419734
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.271155999
Short name T151
Test name
Test status
Simulation time 21328594524 ps
CPU time 39.69 seconds
Started Feb 29 01:24:07 PM PST 24
Finished Feb 29 01:24:46 PM PST 24
Peak memory 199456 kb
Host smart-23152c60-a537-4be6-9f45-c47578ba9079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271155999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.271155999
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2726421378
Short name T244
Test name
Test status
Simulation time 62381596539 ps
CPU time 29.23 seconds
Started Feb 29 01:24:06 PM PST 24
Finished Feb 29 01:24:35 PM PST 24
Peak memory 199084 kb
Host smart-7547f147-151f-4722-af61-e52018a1791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726421378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2726421378
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1986407364
Short name T148
Test name
Test status
Simulation time 36937471116 ps
CPU time 15.03 seconds
Started Feb 29 01:24:04 PM PST 24
Finished Feb 29 01:24:20 PM PST 24
Peak memory 199648 kb
Host smart-190103e5-cc59-4b9b-9a65-fbd750e72184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986407364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1986407364
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1572226553
Short name T194
Test name
Test status
Simulation time 132565644281 ps
CPU time 52.43 seconds
Started Feb 29 01:24:05 PM PST 24
Finished Feb 29 01:24:58 PM PST 24
Peak memory 199496 kb
Host smart-ed5b7a16-761a-438d-b8db-ff8a547506c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572226553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1572226553
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1339685479
Short name T117
Test name
Test status
Simulation time 41415121311 ps
CPU time 16.87 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:15 PM PST 24
Peak memory 199560 kb
Host smart-7ed99955-dc93-408c-8ab5-773d48bcb8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339685479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1339685479
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1128891560
Short name T672
Test name
Test status
Simulation time 74802415346 ps
CPU time 61.73 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 199552 kb
Host smart-6a4393ad-7c37-4a13-83fe-73eec9f99ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128891560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1128891560
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.478148966
Short name T133
Test name
Test status
Simulation time 138886147035 ps
CPU time 56.31 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:55 PM PST 24
Peak memory 199496 kb
Host smart-12616618-cdd8-4150-80d5-c7fbe9c8a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478148966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.478148966
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2261848995
Short name T280
Test name
Test status
Simulation time 115963005061 ps
CPU time 179.32 seconds
Started Feb 29 01:23:57 PM PST 24
Finished Feb 29 01:26:57 PM PST 24
Peak memory 199416 kb
Host smart-39461771-ce3e-4311-bb8c-d92eed02b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261848995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2261848995
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.790271991
Short name T877
Test name
Test status
Simulation time 33531763740 ps
CPU time 50.27 seconds
Started Feb 29 01:24:00 PM PST 24
Finished Feb 29 01:24:50 PM PST 24
Peak memory 199552 kb
Host smart-564c27fb-3315-49d7-90a2-7698cf8f57fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790271991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.790271991
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3954965208
Short name T633
Test name
Test status
Simulation time 25859344 ps
CPU time 0.55 seconds
Started Feb 29 01:20:14 PM PST 24
Finished Feb 29 01:20:14 PM PST 24
Peak memory 194928 kb
Host smart-f1cb931e-4082-4324-a467-3a9431573374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954965208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3954965208
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.332224944
Short name T437
Test name
Test status
Simulation time 133699100784 ps
CPU time 92.37 seconds
Started Feb 29 01:19:55 PM PST 24
Finished Feb 29 01:21:28 PM PST 24
Peak memory 199580 kb
Host smart-7189569c-6439-4db8-b8fa-cbce8b3842b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332224944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.332224944
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2525121538
Short name T835
Test name
Test status
Simulation time 180241098027 ps
CPU time 295.5 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:24:50 PM PST 24
Peak memory 199640 kb
Host smart-3a8b9df4-39f5-45e6-b9c2-3f5dbd3b7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525121538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2525121538
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.154354478
Short name T1034
Test name
Test status
Simulation time 3852872588 ps
CPU time 6.03 seconds
Started Feb 29 01:19:57 PM PST 24
Finished Feb 29 01:20:04 PM PST 24
Peak memory 195252 kb
Host smart-318a7807-8e88-4759-8b4c-e352425ec18b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154354478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.154354478
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3500500504
Short name T520
Test name
Test status
Simulation time 73136826439 ps
CPU time 547.61 seconds
Started Feb 29 01:20:27 PM PST 24
Finished Feb 29 01:29:35 PM PST 24
Peak memory 199496 kb
Host smart-b353d74a-5d56-431c-8178-eed800d81c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500500504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3500500504
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1982193738
Short name T945
Test name
Test status
Simulation time 9048080001 ps
CPU time 7.27 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:20:01 PM PST 24
Peak memory 197588 kb
Host smart-94a9eeee-a995-44c1-a945-a55704640fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982193738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1982193738
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3008360160
Short name T602
Test name
Test status
Simulation time 38924513916 ps
CPU time 32.81 seconds
Started Feb 29 01:20:28 PM PST 24
Finished Feb 29 01:21:00 PM PST 24
Peak memory 198500 kb
Host smart-e6e2cbff-c49a-4b7d-9373-c8a759f59fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008360160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3008360160
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1724974991
Short name T427
Test name
Test status
Simulation time 8750098760 ps
CPU time 374.35 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:26:09 PM PST 24
Peak memory 199572 kb
Host smart-8e789481-5bc9-432c-a17a-de51e63b77ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724974991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1724974991
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2070192121
Short name T1013
Test name
Test status
Simulation time 2954303114 ps
CPU time 19.76 seconds
Started Feb 29 01:19:58 PM PST 24
Finished Feb 29 01:20:18 PM PST 24
Peak memory 197996 kb
Host smart-e940d047-7e62-4f71-98b1-ba0a74d76ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070192121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2070192121
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1141501874
Short name T316
Test name
Test status
Simulation time 115028187726 ps
CPU time 49.19 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:20:45 PM PST 24
Peak memory 198780 kb
Host smart-5446f184-c9cd-44ab-9ecf-ba639dd372b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141501874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1141501874
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.58631969
Short name T556
Test name
Test status
Simulation time 34361545943 ps
CPU time 56.06 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:20:56 PM PST 24
Peak memory 195232 kb
Host smart-cf8167d5-1fbe-4bed-9f03-2a143662fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58631969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.58631969
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2514059369
Short name T431
Test name
Test status
Simulation time 647937752 ps
CPU time 3.03 seconds
Started Feb 29 01:19:59 PM PST 24
Finished Feb 29 01:20:02 PM PST 24
Peak memory 197892 kb
Host smart-9137d001-2507-4f18-8886-a49065af1b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514059369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2514059369
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1141207997
Short name T418
Test name
Test status
Simulation time 6442645260 ps
CPU time 11.65 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 198916 kb
Host smart-df9ee1ce-4cf2-4909-826b-46515c230efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141207997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1141207997
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2299956240
Short name T465
Test name
Test status
Simulation time 900728989 ps
CPU time 3.32 seconds
Started Feb 29 01:19:54 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 198836 kb
Host smart-bf6f4771-a4a1-42e8-bbe9-ad71e8e67f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299956240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2299956240
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2618824967
Short name T956
Test name
Test status
Simulation time 19393559847 ps
CPU time 34.92 seconds
Started Feb 29 01:19:56 PM PST 24
Finished Feb 29 01:20:31 PM PST 24
Peak memory 199568 kb
Host smart-c25bf8b3-ee92-43db-81ec-2003291d48dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618824967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2618824967
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3318740331
Short name T747
Test name
Test status
Simulation time 148966839089 ps
CPU time 67.69 seconds
Started Feb 29 01:24:00 PM PST 24
Finished Feb 29 01:25:07 PM PST 24
Peak memory 199560 kb
Host smart-13661749-c9de-4649-9270-719b2e870fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318740331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3318740331
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.939203960
Short name T136
Test name
Test status
Simulation time 29908250978 ps
CPU time 15.7 seconds
Started Feb 29 01:24:06 PM PST 24
Finished Feb 29 01:24:22 PM PST 24
Peak memory 199456 kb
Host smart-8805ca0d-6fdd-4709-b736-0decb6f77d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939203960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.939203960
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1405329839
Short name T732
Test name
Test status
Simulation time 109144930832 ps
CPU time 92.39 seconds
Started Feb 29 01:24:05 PM PST 24
Finished Feb 29 01:25:37 PM PST 24
Peak memory 199544 kb
Host smart-b53d8a29-d2a2-4a08-8894-5435db163238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405329839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1405329839
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3559108788
Short name T918
Test name
Test status
Simulation time 68578308714 ps
CPU time 27.2 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:25 PM PST 24
Peak memory 199544 kb
Host smart-8d1e4aa1-8c1d-4c05-a7a2-01782c84b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559108788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3559108788
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3647784057
Short name T135
Test name
Test status
Simulation time 112562915215 ps
CPU time 62.44 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:25:01 PM PST 24
Peak memory 199456 kb
Host smart-34d100b5-0499-41cd-99d1-623a128d77ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647784057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3647784057
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.820678853
Short name T784
Test name
Test status
Simulation time 188881851467 ps
CPU time 70.6 seconds
Started Feb 29 01:24:04 PM PST 24
Finished Feb 29 01:25:15 PM PST 24
Peak memory 199568 kb
Host smart-55fa3222-d54c-4417-bf74-f0bb9cc7907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820678853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.820678853
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.728348115
Short name T905
Test name
Test status
Simulation time 12167673842 ps
CPU time 21.26 seconds
Started Feb 29 01:23:59 PM PST 24
Finished Feb 29 01:24:21 PM PST 24
Peak memory 199528 kb
Host smart-41c5850b-624d-4e72-b4b4-ab058df82470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728348115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.728348115
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.986388129
Short name T608
Test name
Test status
Simulation time 66446783 ps
CPU time 0.6 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 195036 kb
Host smart-2ae9e7a3-6a49-4cf4-9689-d610b9f1e880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986388129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.986388129
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2826153278
Short name T919
Test name
Test status
Simulation time 152113215293 ps
CPU time 164.59 seconds
Started Feb 29 01:20:13 PM PST 24
Finished Feb 29 01:22:58 PM PST 24
Peak memory 199588 kb
Host smart-b6af9150-a02d-42ec-8099-cca95690d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826153278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2826153278
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2707962943
Short name T926
Test name
Test status
Simulation time 32453784443 ps
CPU time 25.15 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:20:32 PM PST 24
Peak memory 199264 kb
Host smart-ae714487-a98c-49dd-b6c9-6d550f85f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707962943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2707962943
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3447144864
Short name T221
Test name
Test status
Simulation time 131866778807 ps
CPU time 205.87 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:23:33 PM PST 24
Peak memory 199540 kb
Host smart-e95a524b-aabc-499a-a4d0-2c70fd7380ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447144864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3447144864
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.430460809
Short name T631
Test name
Test status
Simulation time 1958788953408 ps
CPU time 3081.75 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 02:11:29 PM PST 24
Peak memory 199568 kb
Host smart-15c7e371-a780-4c7f-9cb0-0b40a18f56c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430460809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.430460809
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4188819031
Short name T766
Test name
Test status
Simulation time 87130251767 ps
CPU time 796.16 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:33:23 PM PST 24
Peak memory 199628 kb
Host smart-8bb89efb-3ce2-440e-8454-a638ec5b85d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188819031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4188819031
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1319860227
Short name T459
Test name
Test status
Simulation time 152708865 ps
CPU time 0.92 seconds
Started Feb 29 01:20:14 PM PST 24
Finished Feb 29 01:20:16 PM PST 24
Peak memory 195980 kb
Host smart-f821a4a8-cc3d-4fb1-992b-67ce5739d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319860227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1319860227
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2834344821
Short name T1027
Test name
Test status
Simulation time 143877779086 ps
CPU time 20.85 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:20:28 PM PST 24
Peak memory 196828 kb
Host smart-3f8ac27d-8727-4bff-8ac0-97dacfaaa8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834344821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2834344821
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1491798766
Short name T707
Test name
Test status
Simulation time 11933500131 ps
CPU time 188.54 seconds
Started Feb 29 01:20:08 PM PST 24
Finished Feb 29 01:23:16 PM PST 24
Peak memory 199432 kb
Host smart-603068eb-a241-4668-b522-32a00d029be3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491798766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1491798766
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2277525606
Short name T611
Test name
Test status
Simulation time 103193489250 ps
CPU time 173.45 seconds
Started Feb 29 01:20:08 PM PST 24
Finished Feb 29 01:23:02 PM PST 24
Peak memory 199552 kb
Host smart-7444f381-8e5e-404a-a2d6-a5aad7986fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277525606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2277525606
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1185355127
Short name T861
Test name
Test status
Simulation time 32004057166 ps
CPU time 22.65 seconds
Started Feb 29 01:20:08 PM PST 24
Finished Feb 29 01:20:30 PM PST 24
Peak memory 195016 kb
Host smart-f398252b-8de6-4fd6-85f8-c5f45f31919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185355127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1185355127
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2175856520
Short name T745
Test name
Test status
Simulation time 5814308513 ps
CPU time 6.92 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:20:25 PM PST 24
Peak memory 199004 kb
Host smart-1f54d661-0fbf-40be-90a9-d6fdeb20a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175856520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2175856520
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3794535739
Short name T389
Test name
Test status
Simulation time 94209531285 ps
CPU time 66.83 seconds
Started Feb 29 01:20:13 PM PST 24
Finished Feb 29 01:21:20 PM PST 24
Peak memory 199488 kb
Host smart-f2a77518-d02d-4459-ab9c-95ce77accf4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794535739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3794535739
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.311287563
Short name T562
Test name
Test status
Simulation time 778649562 ps
CPU time 2.38 seconds
Started Feb 29 01:20:12 PM PST 24
Finished Feb 29 01:20:14 PM PST 24
Peak memory 197528 kb
Host smart-cc2c65b4-f8f9-4509-940f-e64d98b3a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311287563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.311287563
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3237729018
Short name T639
Test name
Test status
Simulation time 110702590447 ps
CPU time 62.54 seconds
Started Feb 29 01:20:09 PM PST 24
Finished Feb 29 01:21:12 PM PST 24
Peak memory 199532 kb
Host smart-7a3d226b-5695-4750-8420-47b3b436ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237729018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3237729018
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.436755482
Short name T933
Test name
Test status
Simulation time 12656788920 ps
CPU time 11.76 seconds
Started Feb 29 01:23:58 PM PST 24
Finished Feb 29 01:24:10 PM PST 24
Peak memory 198404 kb
Host smart-e0ac01fe-52da-4cbc-8e96-45b5d5f414d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436755482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.436755482
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.629110838
Short name T252
Test name
Test status
Simulation time 27693389070 ps
CPU time 22.84 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:51 PM PST 24
Peak memory 199576 kb
Host smart-0feb9d46-4fb4-4d0f-801d-0ce43a514ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629110838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.629110838
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.604742672
Short name T160
Test name
Test status
Simulation time 115211079512 ps
CPU time 168.76 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:27:17 PM PST 24
Peak memory 199536 kb
Host smart-44de13dd-683f-44e7-bcc4-a540b238471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604742672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.604742672
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1253089676
Short name T205
Test name
Test status
Simulation time 92971655559 ps
CPU time 85.08 seconds
Started Feb 29 01:24:29 PM PST 24
Finished Feb 29 01:25:54 PM PST 24
Peak memory 199464 kb
Host smart-04562eda-146a-4882-85b6-f421efe74ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253089676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1253089676
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3538064417
Short name T818
Test name
Test status
Simulation time 15508453533 ps
CPU time 24.62 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:53 PM PST 24
Peak memory 199584 kb
Host smart-ca6ba0f3-bda8-46e9-a293-57edd4761334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538064417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3538064417
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1231868529
Short name T301
Test name
Test status
Simulation time 116562877936 ps
CPU time 194.25 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:27:43 PM PST 24
Peak memory 199536 kb
Host smart-2b29e28e-22e8-455c-9f0e-15673f2f763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231868529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1231868529
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.682637853
Short name T597
Test name
Test status
Simulation time 22866038 ps
CPU time 0.55 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:18:55 PM PST 24
Peak memory 193968 kb
Host smart-32e5fe5d-f59e-4f63-8c5e-00359652639d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682637853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.682637853
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1916848491
Short name T372
Test name
Test status
Simulation time 192673925943 ps
CPU time 73.5 seconds
Started Feb 29 01:18:45 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 198832 kb
Host smart-60f5f161-8d38-4316-ace0-e60832175ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916848491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1916848491
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.1567359683
Short name T994
Test name
Test status
Simulation time 438919625381 ps
CPU time 589.69 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:28:33 PM PST 24
Peak memory 199540 kb
Host smart-37607c69-7068-4d6d-b72f-17ed88045792
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567359683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1567359683
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2172880346
Short name T1101
Test name
Test status
Simulation time 94835505884 ps
CPU time 648.76 seconds
Started Feb 29 01:18:57 PM PST 24
Finished Feb 29 01:29:46 PM PST 24
Peak memory 199548 kb
Host smart-1de02531-6ed0-47cd-96b1-98ba0dda863d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172880346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2172880346
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.730535092
Short name T578
Test name
Test status
Simulation time 1681382486 ps
CPU time 4.96 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:18:47 PM PST 24
Peak memory 197856 kb
Host smart-aa274938-2bb3-497c-a0f5-44d4f4748fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730535092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.730535092
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3420901
Short name T48
Test name
Test status
Simulation time 33808491861 ps
CPU time 29.01 seconds
Started Feb 29 01:18:45 PM PST 24
Finished Feb 29 01:19:14 PM PST 24
Peak memory 198296 kb
Host smart-ed79b410-0b4a-419e-8085-a3160a2fc762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3420901
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3131381715
Short name T415
Test name
Test status
Simulation time 14194752754 ps
CPU time 413.39 seconds
Started Feb 29 01:18:50 PM PST 24
Finished Feb 29 01:25:44 PM PST 24
Peak memory 199532 kb
Host smart-5bcbaac1-19f1-4d1d-8958-0ccebcad6613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131381715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3131381715
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.630716061
Short name T694
Test name
Test status
Simulation time 2403167779 ps
CPU time 6.01 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:49 PM PST 24
Peak memory 198028 kb
Host smart-da3c01d0-afcc-4b11-8df2-5c0c88546a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630716061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.630716061
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3302519861
Short name T353
Test name
Test status
Simulation time 125475792347 ps
CPU time 31.92 seconds
Started Feb 29 01:18:42 PM PST 24
Finished Feb 29 01:19:13 PM PST 24
Peak memory 198892 kb
Host smart-bdbcceb2-afa5-449c-9d00-488d7af37942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302519861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3302519861
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3503043949
Short name T542
Test name
Test status
Simulation time 3075624866 ps
CPU time 1.77 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:45 PM PST 24
Peak memory 194944 kb
Host smart-48dbcdd1-db7b-44e9-92b4-f53069fffaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503043949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3503043949
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4029259311
Short name T85
Test name
Test status
Simulation time 35545333 ps
CPU time 0.75 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:18:52 PM PST 24
Peak memory 217076 kb
Host smart-175fdcaf-695a-47ae-a835-50e16236b44f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029259311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4029259311
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3745136300
Short name T492
Test name
Test status
Simulation time 510272965 ps
CPU time 1.08 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:45 PM PST 24
Peak memory 197496 kb
Host smart-76e3ffd5-760f-4a1e-9239-7beb8a60ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745136300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3745136300
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1534740233
Short name T74
Test name
Test status
Simulation time 295813953692 ps
CPU time 418.41 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:25:55 PM PST 24
Peak memory 207992 kb
Host smart-c87682bc-ac8a-4f0c-916d-21a447ae5035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534740233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1534740233
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1128497966
Short name T561
Test name
Test status
Simulation time 535282617 ps
CPU time 2.05 seconds
Started Feb 29 01:18:45 PM PST 24
Finished Feb 29 01:18:47 PM PST 24
Peak memory 197968 kb
Host smart-83dc6acf-dd43-4b64-8270-6598a2ce432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128497966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1128497966
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4056821436
Short name T992
Test name
Test status
Simulation time 3807014524 ps
CPU time 12.88 seconds
Started Feb 29 01:18:43 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 199432 kb
Host smart-c3138c73-7653-486f-a57c-c308384e7b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056821436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4056821436
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3435344564
Short name T89
Test name
Test status
Simulation time 41979635 ps
CPU time 0.54 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:20:18 PM PST 24
Peak memory 194964 kb
Host smart-bd1b51f7-ee9c-4467-8cb8-6cfa9567c109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435344564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3435344564
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.930715866
Short name T369
Test name
Test status
Simulation time 47274272556 ps
CPU time 55 seconds
Started Feb 29 01:20:16 PM PST 24
Finished Feb 29 01:21:11 PM PST 24
Peak memory 199552 kb
Host smart-146a50ff-dba1-4977-9f6b-063b2283bef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930715866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.930715866
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3054443640
Short name T380
Test name
Test status
Simulation time 187122494734 ps
CPU time 79.9 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:21:38 PM PST 24
Peak memory 199380 kb
Host smart-a8ec094a-8ddd-4fa7-8c5b-994e5dc3ea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054443640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3054443640
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.1821131133
Short name T729
Test name
Test status
Simulation time 469376203585 ps
CPU time 380.34 seconds
Started Feb 29 01:20:06 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 199492 kb
Host smart-77fb9306-b3c6-4993-ba43-f614598161d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821131133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1821131133
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1362233923
Short name T482
Test name
Test status
Simulation time 50573512360 ps
CPU time 169.15 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:23:07 PM PST 24
Peak memory 199564 kb
Host smart-d301c20c-e56c-4d09-b1f9-b7451dc5c124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362233923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1362233923
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1628965291
Short name T831
Test name
Test status
Simulation time 10534163313 ps
CPU time 4.11 seconds
Started Feb 29 01:20:21 PM PST 24
Finished Feb 29 01:20:25 PM PST 24
Peak memory 198260 kb
Host smart-d8353c43-e5f2-4e1a-9080-d410c795b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628965291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1628965291
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3574122064
Short name T849
Test name
Test status
Simulation time 26870826102 ps
CPU time 10.92 seconds
Started Feb 29 01:20:15 PM PST 24
Finished Feb 29 01:20:26 PM PST 24
Peak memory 197152 kb
Host smart-12537f26-27bf-45cd-b5bf-69cd70eea71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574122064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3574122064
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1476005228
Short name T628
Test name
Test status
Simulation time 22256333951 ps
CPU time 286.36 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:25:07 PM PST 24
Peak memory 199560 kb
Host smart-b26c51d7-3891-46cd-a1e6-9d05cba8a74a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476005228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1476005228
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.501522232
Short name T1067
Test name
Test status
Simulation time 336870098550 ps
CPU time 113.75 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:22:12 PM PST 24
Peak memory 199620 kb
Host smart-39e79dab-3fe7-4d70-925f-36437a9bd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501522232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.501522232
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2123045951
Short name T94
Test name
Test status
Simulation time 4266267980 ps
CPU time 1.59 seconds
Started Feb 29 01:20:07 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 195604 kb
Host smart-231ca894-fdf7-4b45-ae3e-44ef83e95ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123045951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2123045951
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4198346262
Short name T702
Test name
Test status
Simulation time 571772055 ps
CPU time 1.48 seconds
Started Feb 29 01:20:08 PM PST 24
Finished Feb 29 01:20:10 PM PST 24
Peak memory 197788 kb
Host smart-fef20374-2b9b-452c-8de3-6a1a93d3788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198346262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4198346262
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1769994911
Short name T1043
Test name
Test status
Simulation time 162819289564 ps
CPU time 127.06 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:22:27 PM PST 24
Peak memory 199564 kb
Host smart-a43ae37f-7f26-424c-b409-166da6416502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769994911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1769994911
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.174389653
Short name T582
Test name
Test status
Simulation time 12321051745 ps
CPU time 17.83 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:38 PM PST 24
Peak memory 199340 kb
Host smart-002622eb-fd79-4405-a8a7-a54063d001fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174389653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.174389653
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2699019930
Short name T579
Test name
Test status
Simulation time 49556786497 ps
CPU time 87.49 seconds
Started Feb 29 01:20:09 PM PST 24
Finished Feb 29 01:21:36 PM PST 24
Peak memory 199648 kb
Host smart-863f5468-08ca-4e98-81c8-1cf6ae4d8171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699019930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2699019930
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3751944330
Short name T871
Test name
Test status
Simulation time 36843511910 ps
CPU time 18.25 seconds
Started Feb 29 01:24:26 PM PST 24
Finished Feb 29 01:24:45 PM PST 24
Peak memory 199128 kb
Host smart-5a130911-8d3a-4182-a5db-58374d8ad34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751944330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3751944330
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1300290720
Short name T311
Test name
Test status
Simulation time 13853139823 ps
CPU time 6.38 seconds
Started Feb 29 01:24:35 PM PST 24
Finished Feb 29 01:24:42 PM PST 24
Peak memory 196472 kb
Host smart-9e83740b-beca-4e6f-b83e-3b91e3e3cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300290720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1300290720
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1931117847
Short name T51
Test name
Test status
Simulation time 87287278914 ps
CPU time 117.07 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 199560 kb
Host smart-195f5369-b60f-4b1c-a494-b9a360e70a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931117847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1931117847
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2207326632
Short name T310
Test name
Test status
Simulation time 75791261056 ps
CPU time 29.82 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:24:58 PM PST 24
Peak memory 199620 kb
Host smart-7a1c9ab9-b279-4e35-9427-0ff5bbe1de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207326632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2207326632
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1004979228
Short name T924
Test name
Test status
Simulation time 153948959687 ps
CPU time 233.93 seconds
Started Feb 29 01:24:28 PM PST 24
Finished Feb 29 01:28:22 PM PST 24
Peak memory 199544 kb
Host smart-062f00c9-1aee-42b0-8bbe-ea9a1b9ed07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004979228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1004979228
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3788731531
Short name T162
Test name
Test status
Simulation time 15897292087 ps
CPU time 14.05 seconds
Started Feb 29 01:24:27 PM PST 24
Finished Feb 29 01:24:42 PM PST 24
Peak memory 199312 kb
Host smart-8e423c46-e95c-47a6-9baa-722cf799ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788731531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3788731531
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3147626683
Short name T894
Test name
Test status
Simulation time 39260912 ps
CPU time 0.62 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:21 PM PST 24
Peak memory 195040 kb
Host smart-93f290b0-2c2a-4054-a563-c65c0b6ad200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147626683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3147626683
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1299468860
Short name T158
Test name
Test status
Simulation time 98883503668 ps
CPU time 35.02 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:55 PM PST 24
Peak memory 199560 kb
Host smart-2bc5a768-563f-457c-ba3f-23a536a67893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299468860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1299468860
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3956776027
Short name T892
Test name
Test status
Simulation time 79620933753 ps
CPU time 136.4 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:22:35 PM PST 24
Peak memory 199500 kb
Host smart-4ce5348b-212b-411c-badb-3d7393471810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956776027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3956776027
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2816947863
Short name T168
Test name
Test status
Simulation time 23124395151 ps
CPU time 37.82 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:58 PM PST 24
Peak memory 199612 kb
Host smart-cd4e34a4-d04a-475f-99a0-3a40aaec63c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816947863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2816947863
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3532332928
Short name T913
Test name
Test status
Simulation time 619251089671 ps
CPU time 245.28 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:24:25 PM PST 24
Peak memory 199492 kb
Host smart-4b8eb547-a099-40f4-91f2-02b2b6884343
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532332928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3532332928
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1635039329
Short name T402
Test name
Test status
Simulation time 36218761125 ps
CPU time 102.27 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:22:03 PM PST 24
Peak memory 199580 kb
Host smart-96b034de-01d9-4ebc-b790-3dc0f88e40f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635039329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1635039329
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3866484602
Short name T1024
Test name
Test status
Simulation time 1966539540 ps
CPU time 5.02 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:24 PM PST 24
Peak memory 197604 kb
Host smart-e5b1e83b-0b67-4e44-9b55-fafdd86af835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866484602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3866484602
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2394395916
Short name T596
Test name
Test status
Simulation time 111818059822 ps
CPU time 180.76 seconds
Started Feb 29 01:20:41 PM PST 24
Finished Feb 29 01:23:42 PM PST 24
Peak memory 199756 kb
Host smart-cdbd61b1-027a-4946-b2e4-1e900691162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394395916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2394395916
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3291245474
Short name T867
Test name
Test status
Simulation time 19201786312 ps
CPU time 77.28 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:21:36 PM PST 24
Peak memory 199500 kb
Host smart-c2a815b3-e7e1-4626-9c59-877ce00e60cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291245474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3291245474
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1448679499
Short name T637
Test name
Test status
Simulation time 1261284004 ps
CPU time 3.38 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:23 PM PST 24
Peak memory 197560 kb
Host smart-dab5edbb-e73a-4fb7-9f79-03df898fdc5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448679499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1448679499
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.871627445
Short name T307
Test name
Test status
Simulation time 37999969257 ps
CPU time 55.18 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:21:15 PM PST 24
Peak memory 199564 kb
Host smart-0deeffae-5a8e-452a-99f7-669160dbc791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871627445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.871627445
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3663564464
Short name T407
Test name
Test status
Simulation time 1654411866 ps
CPU time 1.03 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:20:20 PM PST 24
Peak memory 194952 kb
Host smart-f02f923f-6adb-48b8-aa10-cfeaa60e9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663564464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3663564464
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.4014268217
Short name T565
Test name
Test status
Simulation time 128821803 ps
CPU time 0.8 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:20:19 PM PST 24
Peak memory 196204 kb
Host smart-ded65311-66db-49c8-9514-98afb9ea073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014268217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4014268217
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1666530149
Short name T719
Test name
Test status
Simulation time 11786126937 ps
CPU time 26.16 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:45 PM PST 24
Peak memory 199428 kb
Host smart-b050c378-b207-4cef-8513-76bccd7efc08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666530149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1666530149
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1345996025
Short name T217
Test name
Test status
Simulation time 38024661516 ps
CPU time 933.4 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:35:54 PM PST 24
Peak memory 207976 kb
Host smart-324f5a9c-d991-4757-9690-94096cc818f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345996025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1345996025
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2441863038
Short name T546
Test name
Test status
Simulation time 815086366 ps
CPU time 2.72 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:23 PM PST 24
Peak memory 197968 kb
Host smart-a153b24f-2235-4016-9c46-9f8fc638c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441863038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2441863038
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4152464817
Short name T944
Test name
Test status
Simulation time 12787931753 ps
CPU time 21.33 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:20:39 PM PST 24
Peak memory 199780 kb
Host smart-3f76b9ed-1b76-4c5c-b8d4-84fb69287dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152464817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4152464817
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3966148265
Short name T279
Test name
Test status
Simulation time 27650643206 ps
CPU time 66.47 seconds
Started Feb 29 01:24:27 PM PST 24
Finished Feb 29 01:25:34 PM PST 24
Peak memory 199632 kb
Host smart-0943f275-12d0-40c8-ab54-94adb788b2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966148265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3966148265
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2559416395
Short name T309
Test name
Test status
Simulation time 33047325902 ps
CPU time 27.56 seconds
Started Feb 29 01:24:30 PM PST 24
Finished Feb 29 01:24:58 PM PST 24
Peak memory 198188 kb
Host smart-4f2711f4-52db-429f-ac63-9c59a3afc9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559416395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2559416395
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4195413352
Short name T123
Test name
Test status
Simulation time 26657675813 ps
CPU time 50 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:29 PM PST 24
Peak memory 199340 kb
Host smart-c8722fc6-c00d-4cee-af4c-e33a5d119790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195413352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4195413352
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2933446582
Short name T1077
Test name
Test status
Simulation time 61741447189 ps
CPU time 89.56 seconds
Started Feb 29 01:24:32 PM PST 24
Finished Feb 29 01:26:02 PM PST 24
Peak memory 199596 kb
Host smart-febb412e-0c32-4054-8129-308c9216913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933446582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2933446582
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1061833172
Short name T591
Test name
Test status
Simulation time 42146131267 ps
CPU time 50.53 seconds
Started Feb 29 01:24:31 PM PST 24
Finished Feb 29 01:25:21 PM PST 24
Peak memory 199632 kb
Host smart-5f109061-864f-4d65-a2f1-d83d29878b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061833172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1061833172
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2651492328
Short name T146
Test name
Test status
Simulation time 177422580052 ps
CPU time 124.33 seconds
Started Feb 29 01:24:31 PM PST 24
Finished Feb 29 01:26:35 PM PST 24
Peak memory 199560 kb
Host smart-9c19a68a-eaa7-4aa7-ad65-e805e2a13e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651492328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2651492328
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3816001353
Short name T258
Test name
Test status
Simulation time 34242260972 ps
CPU time 18.43 seconds
Started Feb 29 01:24:30 PM PST 24
Finished Feb 29 01:24:49 PM PST 24
Peak memory 199568 kb
Host smart-8499cfd7-fb77-4172-9706-051cee51ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816001353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3816001353
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4056985636
Short name T998
Test name
Test status
Simulation time 158619112 ps
CPU time 0.55 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:20:19 PM PST 24
Peak memory 195024 kb
Host smart-6fa97322-d7a0-4996-8875-01c6a17d2349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056985636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4056985636
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3096353496
Short name T581
Test name
Test status
Simulation time 175274072990 ps
CPU time 34.82 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:56 PM PST 24
Peak memory 199604 kb
Host smart-943b508b-61f1-4153-bf28-e6e860ece835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096353496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3096353496
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3716182868
Short name T1056
Test name
Test status
Simulation time 116390927150 ps
CPU time 81.32 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:21:40 PM PST 24
Peak memory 199456 kb
Host smart-6138acdf-2a0f-4f43-a72a-20d383795e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716182868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3716182868
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.3736329777
Short name T440
Test name
Test status
Simulation time 1232511611717 ps
CPU time 2505.03 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 02:02:04 PM PST 24
Peak memory 199636 kb
Host smart-eb29a885-7a79-49ff-969f-1d131d0d9f52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736329777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3736329777
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3025922738
Short name T550
Test name
Test status
Simulation time 277996383014 ps
CPU time 199.87 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:23:37 PM PST 24
Peak memory 199536 kb
Host smart-d45d11ac-62b4-4a1f-b325-f173fee5bb96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025922738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3025922738
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3545679511
Short name T688
Test name
Test status
Simulation time 3172740926 ps
CPU time 3.51 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:20:22 PM PST 24
Peak memory 198272 kb
Host smart-84b6950c-3b6e-4bdb-b226-25b0f63baea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545679511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3545679511
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2881542427
Short name T928
Test name
Test status
Simulation time 71413718711 ps
CPU time 30.99 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:51 PM PST 24
Peak memory 199756 kb
Host smart-fd315364-fce6-47ae-965f-286fea91815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881542427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2881542427
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2929037000
Short name T1096
Test name
Test status
Simulation time 20296487409 ps
CPU time 1160.4 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:39:40 PM PST 24
Peak memory 199652 kb
Host smart-07f5c015-a2d7-4abf-aa76-c5de9698cb2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929037000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2929037000
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.776381730
Short name T457
Test name
Test status
Simulation time 242584941 ps
CPU time 1 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:20 PM PST 24
Peak memory 197436 kb
Host smart-5f8e6b25-aac3-47c9-a25e-7cbb73c7048e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776381730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.776381730
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3315015929
Short name T667
Test name
Test status
Simulation time 129649169908 ps
CPU time 218.93 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:23:59 PM PST 24
Peak memory 199544 kb
Host smart-c4332d5c-3bbe-4f41-b19a-bf20f700f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315015929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3315015929
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2865371012
Short name T603
Test name
Test status
Simulation time 741632884 ps
CPU time 1.73 seconds
Started Feb 29 01:20:20 PM PST 24
Finished Feb 29 01:20:22 PM PST 24
Peak memory 194972 kb
Host smart-ef5db405-1a89-434d-86e0-6f698ada1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865371012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2865371012
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1706465627
Short name T1082
Test name
Test status
Simulation time 6294135638 ps
CPU time 10.4 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:20:29 PM PST 24
Peak memory 199056 kb
Host smart-29594cb1-d865-42ce-94df-fac0220a6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706465627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1706465627
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3264661791
Short name T645
Test name
Test status
Simulation time 258698569433 ps
CPU time 816.31 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:33:56 PM PST 24
Peak memory 199660 kb
Host smart-43008892-a195-447c-b071-888880375499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264661791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3264661791
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.957867210
Short name T869
Test name
Test status
Simulation time 426631116 ps
CPU time 1.51 seconds
Started Feb 29 01:20:19 PM PST 24
Finished Feb 29 01:20:21 PM PST 24
Peak memory 197012 kb
Host smart-b62ef966-1d02-47ab-a214-52edb72134d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957867210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.957867210
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3917588826
Short name T762
Test name
Test status
Simulation time 78792230389 ps
CPU time 69.98 seconds
Started Feb 29 01:20:16 PM PST 24
Finished Feb 29 01:21:27 PM PST 24
Peak memory 199568 kb
Host smart-7d8146af-b34e-48f0-95a7-b9084106a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917588826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3917588826
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3687125320
Short name T91
Test name
Test status
Simulation time 41329930025 ps
CPU time 71.63 seconds
Started Feb 29 01:24:30 PM PST 24
Finished Feb 29 01:25:42 PM PST 24
Peak memory 199420 kb
Host smart-3544ec80-b633-4c5f-9e49-d073ca8a2cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687125320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3687125320
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2419238859
Short name T157
Test name
Test status
Simulation time 33454675852 ps
CPU time 58.83 seconds
Started Feb 29 01:24:30 PM PST 24
Finished Feb 29 01:25:29 PM PST 24
Peak memory 199544 kb
Host smart-ab10e83c-be0d-4b70-9c64-17ef95edd30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419238859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2419238859
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3991811248
Short name T220
Test name
Test status
Simulation time 14246488018 ps
CPU time 23.55 seconds
Started Feb 29 01:24:32 PM PST 24
Finished Feb 29 01:24:56 PM PST 24
Peak memory 198868 kb
Host smart-6dc12d20-809a-4237-83ae-9e51ab008257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991811248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3991811248
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3061980137
Short name T140
Test name
Test status
Simulation time 56265124859 ps
CPU time 24.43 seconds
Started Feb 29 01:24:32 PM PST 24
Finished Feb 29 01:24:57 PM PST 24
Peak memory 199532 kb
Host smart-83b6eb9c-25a7-4378-a286-2670359fd69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061980137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3061980137
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3124142494
Short name T1085
Test name
Test status
Simulation time 94332860780 ps
CPU time 193.62 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:27:52 PM PST 24
Peak memory 199592 kb
Host smart-07bdf805-fd9f-4de6-802e-0e873f963dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124142494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3124142494
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4109590159
Short name T376
Test name
Test status
Simulation time 8446454868 ps
CPU time 6.4 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:24:45 PM PST 24
Peak memory 198804 kb
Host smart-a99fab5e-d668-4859-b6e9-0d356c0a9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109590159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4109590159
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.244473405
Short name T668
Test name
Test status
Simulation time 29078204488 ps
CPU time 11.87 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:24:50 PM PST 24
Peak memory 199520 kb
Host smart-3b2336a5-d19d-40a9-b25e-dd81937e77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244473405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.244473405
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2262227886
Short name T652
Test name
Test status
Simulation time 12439351 ps
CPU time 0.52 seconds
Started Feb 29 01:20:34 PM PST 24
Finished Feb 29 01:20:35 PM PST 24
Peak memory 194032 kb
Host smart-1e050d39-1801-4e00-a87a-4bc421435f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262227886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2262227886
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.593995582
Short name T1017
Test name
Test status
Simulation time 110382601253 ps
CPU time 166.77 seconds
Started Feb 29 01:20:21 PM PST 24
Finished Feb 29 01:23:08 PM PST 24
Peak memory 199568 kb
Host smart-406cdd80-f322-4133-b87f-458f89483182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593995582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.593995582
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4099458963
Short name T1009
Test name
Test status
Simulation time 215682091252 ps
CPU time 159.98 seconds
Started Feb 29 01:20:36 PM PST 24
Finished Feb 29 01:23:16 PM PST 24
Peak memory 198780 kb
Host smart-238a476b-c341-4bb7-bca7-5416bba51114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099458963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4099458963
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3984942391
Short name T259
Test name
Test status
Simulation time 43156936934 ps
CPU time 21.68 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:20:53 PM PST 24
Peak memory 199564 kb
Host smart-ec280ddc-4214-4a3a-b1c0-4407ece6eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984942391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3984942391
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.364919720
Short name T915
Test name
Test status
Simulation time 245958098910 ps
CPU time 195.78 seconds
Started Feb 29 01:20:35 PM PST 24
Finished Feb 29 01:23:50 PM PST 24
Peak memory 199556 kb
Host smart-95e19ecb-b973-47d6-a3c4-e0be46f5b56d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364919720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.364919720
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1350523950
Short name T630
Test name
Test status
Simulation time 112322968045 ps
CPU time 151.06 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:23:03 PM PST 24
Peak memory 199636 kb
Host smart-b4329ac2-fb07-42d6-91fe-e130f1715e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350523950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1350523950
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_noise_filter.91376076
Short name T38
Test name
Test status
Simulation time 77067613299 ps
CPU time 37.14 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:21:08 PM PST 24
Peak memory 199812 kb
Host smart-bae6fc6b-50fe-43f6-bdb0-6f4c60b732c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91376076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.91376076
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1929646620
Short name T1066
Test name
Test status
Simulation time 17086397593 ps
CPU time 216.08 seconds
Started Feb 29 01:20:34 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199564 kb
Host smart-fb73511a-097c-41f8-a141-63898fbc3243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929646620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1929646620
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1071367889
Short name T955
Test name
Test status
Simulation time 21467974817 ps
CPU time 32.94 seconds
Started Feb 29 01:20:35 PM PST 24
Finished Feb 29 01:21:08 PM PST 24
Peak memory 199560 kb
Host smart-e47547b7-6d5f-49b5-b086-b33177116d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071367889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1071367889
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.41989390
Short name T507
Test name
Test status
Simulation time 44284803797 ps
CPU time 30.18 seconds
Started Feb 29 01:20:29 PM PST 24
Finished Feb 29 01:21:00 PM PST 24
Peak memory 195084 kb
Host smart-3563f74b-d2e7-4245-a4e8-43a69070e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41989390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.41989390
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1267476271
Short name T825
Test name
Test status
Simulation time 5390989119 ps
CPU time 12.71 seconds
Started Feb 29 01:20:18 PM PST 24
Finished Feb 29 01:20:31 PM PST 24
Peak memory 198388 kb
Host smart-2d83acd0-b532-4632-9acc-79417479791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267476271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1267476271
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2084971716
Short name T368
Test name
Test status
Simulation time 331498013478 ps
CPU time 1402.85 seconds
Started Feb 29 01:20:29 PM PST 24
Finished Feb 29 01:43:52 PM PST 24
Peak memory 199552 kb
Host smart-8f752947-f439-4e71-9d20-94f604c4b761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084971716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2084971716
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1141416265
Short name T476
Test name
Test status
Simulation time 2121388008 ps
CPU time 1.66 seconds
Started Feb 29 01:20:41 PM PST 24
Finished Feb 29 01:20:43 PM PST 24
Peak memory 197336 kb
Host smart-41edfa3d-7b77-4198-852b-2314c6e6c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141416265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1141416265
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1603895438
Short name T436
Test name
Test status
Simulation time 260066661231 ps
CPU time 198.01 seconds
Started Feb 29 01:20:17 PM PST 24
Finished Feb 29 01:23:36 PM PST 24
Peak memory 199508 kb
Host smart-2d122d0c-6407-4fb7-a1fc-e5d2bf3ef345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603895438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1603895438
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1499504380
Short name T751
Test name
Test status
Simulation time 76669236080 ps
CPU time 63.72 seconds
Started Feb 29 01:24:37 PM PST 24
Finished Feb 29 01:25:41 PM PST 24
Peak memory 199504 kb
Host smart-1c55f261-f758-4afc-aa7d-3b1d84ae1912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499504380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1499504380
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1364404582
Short name T218
Test name
Test status
Simulation time 42535808640 ps
CPU time 29.76 seconds
Started Feb 29 01:24:37 PM PST 24
Finished Feb 29 01:25:07 PM PST 24
Peak memory 199348 kb
Host smart-572c2861-f527-46ab-98a0-e02fc055f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364404582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1364404582
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3652206724
Short name T263
Test name
Test status
Simulation time 39850547201 ps
CPU time 33.99 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:13 PM PST 24
Peak memory 199464 kb
Host smart-156a6cd0-fe0f-4069-a22b-655011464705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652206724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3652206724
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1411119591
Short name T250
Test name
Test status
Simulation time 18518671840 ps
CPU time 29.16 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:09 PM PST 24
Peak memory 199560 kb
Host smart-93809da6-e5a9-49ba-979f-7e23c17ba831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411119591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1411119591
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3865209866
Short name T552
Test name
Test status
Simulation time 197285823356 ps
CPU time 32.62 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:12 PM PST 24
Peak memory 199548 kb
Host smart-add4d7d6-3aae-4d95-a2a4-5a5b915800c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865209866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3865209866
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2948884675
Short name T108
Test name
Test status
Simulation time 173523395863 ps
CPU time 238.33 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:28:36 PM PST 24
Peak memory 199428 kb
Host smart-6f1d3799-0d37-4b14-ac46-3abf7d962552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948884675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2948884675
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2688539880
Short name T1074
Test name
Test status
Simulation time 48384510619 ps
CPU time 83.67 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:26:03 PM PST 24
Peak memory 199308 kb
Host smart-dea5add8-6c11-4378-a25b-98a9f4e7d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688539880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2688539880
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1093243309
Short name T850
Test name
Test status
Simulation time 56114333037 ps
CPU time 11.28 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:24:49 PM PST 24
Peak memory 199636 kb
Host smart-2f49bdeb-e19c-4fd8-bee9-c52df63fb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093243309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1093243309
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.163990987
Short name T106
Test name
Test status
Simulation time 283476486703 ps
CPU time 50.28 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:25:30 PM PST 24
Peak memory 199200 kb
Host smart-d92ec11a-31a9-45ad-a803-38c1653e9af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163990987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.163990987
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3408383574
Short name T1079
Test name
Test status
Simulation time 14179113 ps
CPU time 0.53 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:20:32 PM PST 24
Peak memory 195020 kb
Host smart-ef6b1aad-e8b5-413a-83bb-79e5a37d5ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408383574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3408383574
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1037187609
Short name T541
Test name
Test status
Simulation time 22611287959 ps
CPU time 34.65 seconds
Started Feb 29 01:20:36 PM PST 24
Finished Feb 29 01:21:11 PM PST 24
Peak memory 199380 kb
Host smart-0c0f6b10-a7a1-4211-84b4-22643b58edb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037187609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1037187609
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.27649728
Short name T640
Test name
Test status
Simulation time 160423408439 ps
CPU time 53.05 seconds
Started Feb 29 01:20:35 PM PST 24
Finished Feb 29 01:21:28 PM PST 24
Peak memory 199532 kb
Host smart-bd9e88d3-3425-4f68-8f81-f4fbd45476e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27649728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.27649728
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2918945575
Short name T411
Test name
Test status
Simulation time 89157083474 ps
CPU time 39.46 seconds
Started Feb 29 01:20:29 PM PST 24
Finished Feb 29 01:21:08 PM PST 24
Peak memory 199564 kb
Host smart-0dda5cfc-d261-4e0d-b204-d2e00d618ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918945575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2918945575
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4153115063
Short name T708
Test name
Test status
Simulation time 1402931383079 ps
CPU time 2302.91 seconds
Started Feb 29 01:20:32 PM PST 24
Finished Feb 29 01:58:55 PM PST 24
Peak memory 199128 kb
Host smart-39512383-4607-4eba-aacd-c4399aacab4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153115063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4153115063
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3624977814
Short name T787
Test name
Test status
Simulation time 109580172585 ps
CPU time 216.15 seconds
Started Feb 29 01:20:34 PM PST 24
Finished Feb 29 01:24:10 PM PST 24
Peak memory 199584 kb
Host smart-822b8e68-90f9-4fb4-aa53-58dbbf204af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624977814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3624977814
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2699469752
Short name T102
Test name
Test status
Simulation time 69329931260 ps
CPU time 137.44 seconds
Started Feb 29 01:20:29 PM PST 24
Finished Feb 29 01:22:47 PM PST 24
Peak memory 197984 kb
Host smart-72aa3d01-202a-4110-a189-96d507bf129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699469752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2699469752
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.289394967
Short name T904
Test name
Test status
Simulation time 12062265623 ps
CPU time 672.49 seconds
Started Feb 29 01:20:56 PM PST 24
Finished Feb 29 01:32:09 PM PST 24
Peak memory 199544 kb
Host smart-9373c52f-1559-480c-aa7c-51a08a71a3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289394967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.289394967
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1357551655
Short name T941
Test name
Test status
Simulation time 159533447 ps
CPU time 1.13 seconds
Started Feb 29 01:20:34 PM PST 24
Finished Feb 29 01:20:35 PM PST 24
Peak memory 197492 kb
Host smart-a5f261de-1891-41ef-8b4e-642a96bcb813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357551655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1357551655
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3068702826
Short name T673
Test name
Test status
Simulation time 242817675961 ps
CPU time 407.29 seconds
Started Feb 29 01:20:28 PM PST 24
Finished Feb 29 01:27:16 PM PST 24
Peak memory 199564 kb
Host smart-37e96d4a-8cc2-4946-ada2-d6bb4dfacc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068702826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3068702826
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1211645744
Short name T10
Test name
Test status
Simulation time 3169389148 ps
CPU time 5.31 seconds
Started Feb 29 01:20:35 PM PST 24
Finished Feb 29 01:20:41 PM PST 24
Peak memory 195000 kb
Host smart-0b38e2f5-6ba7-45b0-9176-7c32c0d447bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211645744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1211645744
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.142999588
Short name T775
Test name
Test status
Simulation time 568460460 ps
CPU time 1.61 seconds
Started Feb 29 01:20:35 PM PST 24
Finished Feb 29 01:20:36 PM PST 24
Peak memory 197952 kb
Host smart-c9a13dbd-4df3-4c43-833a-9991a03dee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142999588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.142999588
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3077431868
Short name T295
Test name
Test status
Simulation time 287468864411 ps
CPU time 87.55 seconds
Started Feb 29 01:20:33 PM PST 24
Finished Feb 29 01:22:01 PM PST 24
Peak memory 199652 kb
Host smart-f5c9cc79-562f-4acf-b79d-ab9f0ded5244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077431868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3077431868
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2893227833
Short name T975
Test name
Test status
Simulation time 7334483546 ps
CPU time 8.81 seconds
Started Feb 29 01:20:37 PM PST 24
Finished Feb 29 01:20:45 PM PST 24
Peak memory 198940 kb
Host smart-0dfd5795-11be-41b9-a427-99761f38c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893227833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2893227833
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1286948197
Short name T635
Test name
Test status
Simulation time 166772521397 ps
CPU time 89.71 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:22:01 PM PST 24
Peak memory 199648 kb
Host smart-5d520bc4-cdb5-494c-88a6-aa2b17edaf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286948197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1286948197
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.265379044
Short name T215
Test name
Test status
Simulation time 135480880781 ps
CPU time 111.18 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:26:29 PM PST 24
Peak memory 199600 kb
Host smart-17961f4f-6895-43a6-8149-d88c257c2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265379044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.265379044
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4062608979
Short name T365
Test name
Test status
Simulation time 134651980809 ps
CPU time 118.32 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:26:38 PM PST 24
Peak memory 199384 kb
Host smart-31cb27d5-f31b-416b-b307-d0b761869d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062608979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4062608979
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4127203464
Short name T171
Test name
Test status
Simulation time 63905316562 ps
CPU time 25.37 seconds
Started Feb 29 01:24:35 PM PST 24
Finished Feb 29 01:25:01 PM PST 24
Peak memory 199572 kb
Host smart-2b446f04-18fe-417c-9129-d6341220a7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127203464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4127203464
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4189721136
Short name T230
Test name
Test status
Simulation time 16498994123 ps
CPU time 13.89 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:24:53 PM PST 24
Peak memory 199564 kb
Host smart-e0383212-3955-4c6f-8b0a-7471ae70fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189721136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4189721136
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3676175569
Short name T843
Test name
Test status
Simulation time 21106079 ps
CPU time 0.52 seconds
Started Feb 29 01:20:50 PM PST 24
Finished Feb 29 01:20:52 PM PST 24
Peak memory 194024 kb
Host smart-713c8f33-21de-4e50-a064-ad717f4fabbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676175569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3676175569
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1038417639
Short name T343
Test name
Test status
Simulation time 79883925566 ps
CPU time 14.43 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:20:45 PM PST 24
Peak memory 199328 kb
Host smart-18a528da-8b4c-4ba1-a7f5-b333d94974b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038417639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1038417639
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1151846705
Short name T1040
Test name
Test status
Simulation time 277682218020 ps
CPU time 107.83 seconds
Started Feb 29 01:20:33 PM PST 24
Finished Feb 29 01:22:21 PM PST 24
Peak memory 199528 kb
Host smart-f9a2b997-2999-4a8e-a6d0-70eb47cbf0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151846705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1151846705
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3402325237
Short name T354
Test name
Test status
Simulation time 22288303897 ps
CPU time 32.77 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:21:04 PM PST 24
Peak memory 199348 kb
Host smart-c693270e-4134-4465-8d8e-d5fab9bdf481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402325237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3402325237
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3315190419
Short name T1048
Test name
Test status
Simulation time 22084396146 ps
CPU time 34.91 seconds
Started Feb 29 01:20:31 PM PST 24
Finished Feb 29 01:21:06 PM PST 24
Peak memory 199000 kb
Host smart-0e8404e0-8550-4af3-9b5c-bf8317cae716
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315190419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3315190419
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.531365953
Short name T1032
Test name
Test status
Simulation time 137781062189 ps
CPU time 472.9 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:28:38 PM PST 24
Peak memory 199580 kb
Host smart-b919610b-cc19-4838-a8fd-8bd111481679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531365953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.531365953
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2080918859
Short name T676
Test name
Test status
Simulation time 13837101811 ps
CPU time 23.98 seconds
Started Feb 29 01:20:47 PM PST 24
Finished Feb 29 01:21:12 PM PST 24
Peak memory 196720 kb
Host smart-b2d3a917-cf80-4429-a56d-39faa5d293dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080918859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2080918859
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2716858696
Short name T754
Test name
Test status
Simulation time 11221055184 ps
CPU time 148.29 seconds
Started Feb 29 01:20:46 PM PST 24
Finished Feb 29 01:23:15 PM PST 24
Peak memory 199624 kb
Host smart-d8a2f908-8143-4c3a-8bb8-0f927e0370ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716858696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2716858696
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4138583207
Short name T497
Test name
Test status
Simulation time 4039656568 ps
CPU time 8.64 seconds
Started Feb 29 01:20:32 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 198060 kb
Host smart-22352d5a-2f1f-426f-91ec-95322fc11557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138583207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4138583207
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3796810464
Short name T421
Test name
Test status
Simulation time 192786344865 ps
CPU time 371.24 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:26:56 PM PST 24
Peak memory 199524 kb
Host smart-3269df07-308b-4334-98d6-9311a00a890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796810464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3796810464
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4208261534
Short name T891
Test name
Test status
Simulation time 4167219032 ps
CPU time 4.08 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:20:49 PM PST 24
Peak memory 195304 kb
Host smart-3ccdab3d-19fb-4cb7-8e53-374129f85695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208261534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4208261534
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2263132154
Short name T423
Test name
Test status
Simulation time 845317972 ps
CPU time 3.35 seconds
Started Feb 29 01:20:33 PM PST 24
Finished Feb 29 01:20:37 PM PST 24
Peak memory 198140 kb
Host smart-08419fe2-6dd1-40eb-abe7-6449a9c4e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263132154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2263132154
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.636169036
Short name T1047
Test name
Test status
Simulation time 21585479525 ps
CPU time 46.56 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:21:31 PM PST 24
Peak memory 199548 kb
Host smart-4b7b1e46-4e8b-4781-87fc-5ad8685449d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636169036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.636169036
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.205501864
Short name T598
Test name
Test status
Simulation time 7124208731 ps
CPU time 22.74 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:21:09 PM PST 24
Peak memory 199040 kb
Host smart-01d0f954-a7c5-4d17-8c72-72dde1193bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205501864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.205501864
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1006845948
Short name T1073
Test name
Test status
Simulation time 50696117490 ps
CPU time 94.71 seconds
Started Feb 29 01:20:36 PM PST 24
Finished Feb 29 01:22:10 PM PST 24
Peak memory 199544 kb
Host smart-d9a2bea7-6d36-48e1-8898-a5d156a95df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006845948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1006845948
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3269215006
Short name T786
Test name
Test status
Simulation time 112447367163 ps
CPU time 159.37 seconds
Started Feb 29 01:24:38 PM PST 24
Finished Feb 29 01:27:17 PM PST 24
Peak memory 199544 kb
Host smart-33fc34e5-a179-4abe-869b-bab1d0b38c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269215006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3269215006
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1061992421
Short name T150
Test name
Test status
Simulation time 16047363193 ps
CPU time 23.55 seconds
Started Feb 29 01:24:36 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 199220 kb
Host smart-58ba9dd8-1fbe-4735-8793-ff52186d6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061992421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1061992421
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4229801416
Short name T1058
Test name
Test status
Simulation time 206143776618 ps
CPU time 288.54 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:29:28 PM PST 24
Peak memory 199580 kb
Host smart-8e894fdb-4440-4ddd-8925-50ff82735e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229801416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4229801416
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1743479694
Short name T213
Test name
Test status
Simulation time 193642705291 ps
CPU time 77.79 seconds
Started Feb 29 01:24:44 PM PST 24
Finished Feb 29 01:26:02 PM PST 24
Peak memory 199208 kb
Host smart-1ae3ebed-3618-4181-98fd-7f30c5e91cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743479694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1743479694
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3915022145
Short name T1001
Test name
Test status
Simulation time 18946558382 ps
CPU time 38.82 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:19 PM PST 24
Peak memory 199344 kb
Host smart-a2bb5552-3aad-4780-8152-ecdfdfe0b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915022145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3915022145
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1872523932
Short name T349
Test name
Test status
Simulation time 66193885847 ps
CPU time 26.57 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:25:10 PM PST 24
Peak memory 199352 kb
Host smart-adc56209-fc14-4006-851c-1032c1d2137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872523932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1872523932
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4023251473
Short name T704
Test name
Test status
Simulation time 18029193775 ps
CPU time 15.57 seconds
Started Feb 29 01:24:42 PM PST 24
Finished Feb 29 01:24:58 PM PST 24
Peak memory 199104 kb
Host smart-67cac204-313c-4531-9e01-314f3ac896da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023251473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4023251473
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.837565496
Short name T949
Test name
Test status
Simulation time 49038366759 ps
CPU time 24.17 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:16 PM PST 24
Peak memory 199456 kb
Host smart-a59e2d2c-b182-4ba3-aced-20d3d97eff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837565496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.837565496
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1145014210
Short name T224
Test name
Test status
Simulation time 9398266910 ps
CPU time 14.48 seconds
Started Feb 29 01:24:39 PM PST 24
Finished Feb 29 01:24:54 PM PST 24
Peak memory 199164 kb
Host smart-3df3d34b-8190-4f43-af62-463f427de2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145014210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1145014210
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4157692837
Short name T799
Test name
Test status
Simulation time 60179492 ps
CPU time 0.54 seconds
Started Feb 29 01:20:46 PM PST 24
Finished Feb 29 01:20:47 PM PST 24
Peak memory 195044 kb
Host smart-f46d47e8-dfd2-4016-a0fa-8776e66bcf84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157692837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4157692837
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3162494000
Short name T948
Test name
Test status
Simulation time 18428866456 ps
CPU time 8.51 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:20:53 PM PST 24
Peak memory 199564 kb
Host smart-6c5a1de2-cb4d-404b-b93b-91fc753ddd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162494000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3162494000
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3696276547
Short name T350
Test name
Test status
Simulation time 23355382768 ps
CPU time 10.73 seconds
Started Feb 29 01:20:47 PM PST 24
Finished Feb 29 01:20:59 PM PST 24
Peak memory 198952 kb
Host smart-45288b3f-97b4-4442-9bfb-f912186cc367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696276547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3696276547
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.23872076
Short name T1000
Test name
Test status
Simulation time 9509494371 ps
CPU time 13.46 seconds
Started Feb 29 01:20:45 PM PST 24
Finished Feb 29 01:20:59 PM PST 24
Peak memory 199768 kb
Host smart-ce554c22-e8b3-4688-ba19-fd083c7a805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23872076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.23872076
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4150879557
Short name T833
Test name
Test status
Simulation time 1773717626239 ps
CPU time 633.02 seconds
Started Feb 29 01:20:47 PM PST 24
Finished Feb 29 01:31:21 PM PST 24
Peak memory 199284 kb
Host smart-480e8e1a-7d53-4df0-a203-0a1b38ffa8b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150879557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4150879557
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3368355306
Short name T692
Test name
Test status
Simulation time 99535636605 ps
CPU time 469.65 seconds
Started Feb 29 01:20:45 PM PST 24
Finished Feb 29 01:28:35 PM PST 24
Peak memory 199636 kb
Host smart-b7e1ac9b-8df4-42a9-8169-7c946eb0ff7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368355306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3368355306
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3303962030
Short name T1002
Test name
Test status
Simulation time 3286536844 ps
CPU time 6.98 seconds
Started Feb 29 01:20:43 PM PST 24
Finished Feb 29 01:20:51 PM PST 24
Peak memory 198744 kb
Host smart-41833fca-cd2a-4362-a13e-9848bf75760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303962030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3303962030
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1678722777
Short name T1037
Test name
Test status
Simulation time 82560735601 ps
CPU time 54.84 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:21:41 PM PST 24
Peak memory 197340 kb
Host smart-11b292ff-cd97-4c50-8285-8a0bd164e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678722777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1678722777
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3952474959
Short name T110
Test name
Test status
Simulation time 5284224556 ps
CPU time 219.69 seconds
Started Feb 29 01:20:46 PM PST 24
Finished Feb 29 01:24:26 PM PST 24
Peak memory 199772 kb
Host smart-6103308f-7112-4d5e-afe5-34aa1184d760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952474959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3952474959
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3795026744
Short name T473
Test name
Test status
Simulation time 2731320812 ps
CPU time 29.6 seconds
Started Feb 29 01:20:46 PM PST 24
Finished Feb 29 01:21:16 PM PST 24
Peak memory 198080 kb
Host smart-0fbb81bc-5adb-49c0-8101-b24fb3f8ac3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795026744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3795026744
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1411216855
Short name T979
Test name
Test status
Simulation time 184930619003 ps
CPU time 89 seconds
Started Feb 29 01:20:45 PM PST 24
Finished Feb 29 01:22:15 PM PST 24
Peak memory 198888 kb
Host smart-fbb74874-764c-4c50-a697-6085d66cc8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411216855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1411216855
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1404761274
Short name T815
Test name
Test status
Simulation time 2291391078 ps
CPU time 4.13 seconds
Started Feb 29 01:20:47 PM PST 24
Finished Feb 29 01:20:52 PM PST 24
Peak memory 195020 kb
Host smart-05a3b14f-421d-41b6-b0f1-ed6451808506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404761274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1404761274
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1311785188
Short name T560
Test name
Test status
Simulation time 129029906 ps
CPU time 1.1 seconds
Started Feb 29 01:20:44 PM PST 24
Finished Feb 29 01:20:47 PM PST 24
Peak memory 197644 kb
Host smart-1319529c-5327-4aff-9766-0318bd09dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311785188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1311785188
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2636527926
Short name T456
Test name
Test status
Simulation time 410001975931 ps
CPU time 187.21 seconds
Started Feb 29 01:20:46 PM PST 24
Finished Feb 29 01:23:54 PM PST 24
Peak memory 199668 kb
Host smart-988c3bc1-10bf-42ec-a685-0a2abb218238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636527926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2636527926
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3625249968
Short name T679
Test name
Test status
Simulation time 5784026489 ps
CPU time 2.09 seconds
Started Feb 29 01:20:45 PM PST 24
Finished Feb 29 01:20:49 PM PST 24
Peak memory 198584 kb
Host smart-bdb732de-2960-4c0d-a966-2d9f2cc9ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625249968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3625249968
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.668500957
Short name T590
Test name
Test status
Simulation time 26501456554 ps
CPU time 74.02 seconds
Started Feb 29 01:20:45 PM PST 24
Finished Feb 29 01:22:00 PM PST 24
Peak memory 199520 kb
Host smart-b3e19dc3-d667-4073-8dfb-680a6ebb04f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668500957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.668500957
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1273879580
Short name T124
Test name
Test status
Simulation time 25155875156 ps
CPU time 12.25 seconds
Started Feb 29 01:24:41 PM PST 24
Finished Feb 29 01:24:54 PM PST 24
Peak memory 199560 kb
Host smart-47f5969d-c40a-49e9-b787-7389115af462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273879580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1273879580
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.64367374
Short name T118
Test name
Test status
Simulation time 386730429747 ps
CPU time 117.74 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:26:41 PM PST 24
Peak memory 198776 kb
Host smart-d4211537-31c9-47c3-ae74-fd335f3de326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64367374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.64367374
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2750286837
Short name T225
Test name
Test status
Simulation time 50138546426 ps
CPU time 46.08 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:27 PM PST 24
Peak memory 199816 kb
Host smart-4bc2930d-9fbf-4167-ae68-54dae258ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750286837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2750286837
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.885961847
Short name T997
Test name
Test status
Simulation time 120984753631 ps
CPU time 49.88 seconds
Started Feb 29 01:24:41 PM PST 24
Finished Feb 29 01:25:32 PM PST 24
Peak memory 197960 kb
Host smart-db36fa17-5822-4b94-98ed-47e121b7a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885961847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.885961847
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1372895520
Short name T713
Test name
Test status
Simulation time 201101671019 ps
CPU time 44.78 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:25 PM PST 24
Peak memory 199536 kb
Host smart-06976591-30fc-4b8a-a1f9-0eee4c2f7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372895520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1372895520
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2505326876
Short name T276
Test name
Test status
Simulation time 70251711405 ps
CPU time 53.62 seconds
Started Feb 29 01:24:47 PM PST 24
Finished Feb 29 01:25:42 PM PST 24
Peak memory 199156 kb
Host smart-70368db1-c9d0-4834-9a8a-895e13e8d6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505326876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2505326876
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1091699390
Short name T251
Test name
Test status
Simulation time 68085853635 ps
CPU time 108.52 seconds
Started Feb 29 01:24:49 PM PST 24
Finished Feb 29 01:26:37 PM PST 24
Peak memory 199228 kb
Host smart-1b2a895f-eecb-4665-9956-bafce96ac146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091699390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1091699390
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.889973513
Short name T1093
Test name
Test status
Simulation time 45220492235 ps
CPU time 37.7 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:25:21 PM PST 24
Peak memory 199216 kb
Host smart-97dc1918-8b0d-4233-9469-d3b617c94795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889973513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.889973513
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3553582908
Short name T239
Test name
Test status
Simulation time 69655898070 ps
CPU time 29.54 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:09 PM PST 24
Peak memory 199540 kb
Host smart-4539b779-0a4e-49d3-a7cd-dbb51c1082c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553582908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3553582908
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4179028960
Short name T993
Test name
Test status
Simulation time 40377036 ps
CPU time 0.53 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:01 PM PST 24
Peak memory 195040 kb
Host smart-3b4fbf8e-1b07-43c1-be2d-1474ac54a3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179028960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4179028960
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2289660796
Short name T722
Test name
Test status
Simulation time 28471488701 ps
CPU time 41.38 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:21:31 PM PST 24
Peak memory 199460 kb
Host smart-6b3f53ea-75da-4cd6-a0d0-8c2f15935374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289660796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2289660796
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4275168202
Short name T302
Test name
Test status
Simulation time 269467707930 ps
CPU time 37.72 seconds
Started Feb 29 01:20:48 PM PST 24
Finished Feb 29 01:21:27 PM PST 24
Peak memory 199552 kb
Host smart-03ce53d1-d225-4b51-a131-32414b490ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275168202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4275168202
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1918320521
Short name T499
Test name
Test status
Simulation time 122235575963 ps
CPU time 190.76 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:24:11 PM PST 24
Peak memory 199588 kb
Host smart-9580bcbc-c680-4dd8-b8e1-8a1ff6760574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918320521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1918320521
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2914842652
Short name T765
Test name
Test status
Simulation time 3439585823 ps
CPU time 3.95 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:20:53 PM PST 24
Peak memory 197828 kb
Host smart-3c1d371d-6ae2-4128-bdd1-d6d34116fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914842652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2914842652
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.810052389
Short name T266
Test name
Test status
Simulation time 240949179388 ps
CPU time 51.19 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:21:41 PM PST 24
Peak memory 198860 kb
Host smart-57d793af-a192-4b8d-8956-c1f79eeafa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810052389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.810052389
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1860761212
Short name T1061
Test name
Test status
Simulation time 33376116006 ps
CPU time 136.71 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:23:18 PM PST 24
Peak memory 199576 kb
Host smart-c755901f-a812-462e-a77f-ccfdac051df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860761212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1860761212
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1116538810
Short name T881
Test name
Test status
Simulation time 63900563755 ps
CPU time 60.72 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:21:50 PM PST 24
Peak memory 198036 kb
Host smart-eb4f76e7-2b5b-4d6d-bca4-c7f72d1fea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116538810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1116538810
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3385416109
Short name T533
Test name
Test status
Simulation time 44069523520 ps
CPU time 68.63 seconds
Started Feb 29 01:20:48 PM PST 24
Finished Feb 29 01:21:57 PM PST 24
Peak memory 195252 kb
Host smart-c020a3a4-e1e0-43da-9ca6-87ac1dea79dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385416109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3385416109
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.52336891
Short name T1029
Test name
Test status
Simulation time 290960050 ps
CPU time 1.49 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:20:53 PM PST 24
Peak memory 198396 kb
Host smart-55b886fd-b3c9-459c-b53c-54cdd7f64e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52336891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.52336891
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.454027541
Short name T388
Test name
Test status
Simulation time 63598146350 ps
CPU time 107.62 seconds
Started Feb 29 01:21:02 PM PST 24
Finished Feb 29 01:22:50 PM PST 24
Peak memory 199560 kb
Host smart-a271229a-e523-4be0-b50d-2eb2178d11dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454027541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.454027541
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.84047239
Short name T740
Test name
Test status
Simulation time 576463359 ps
CPU time 1.45 seconds
Started Feb 29 01:20:49 PM PST 24
Finished Feb 29 01:20:51 PM PST 24
Peak memory 198144 kb
Host smart-2dd6f145-2a23-411b-bb15-483346ed24f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84047239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.84047239
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.712595430
Short name T39
Test name
Test status
Simulation time 41947273569 ps
CPU time 61.19 seconds
Started Feb 29 01:20:48 PM PST 24
Finished Feb 29 01:21:50 PM PST 24
Peak memory 199608 kb
Host smart-8f26cad3-1e24-4ad9-bcbf-21997450a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712595430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.712595430
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1574647919
Short name T182
Test name
Test status
Simulation time 19949109210 ps
CPU time 33.66 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:13 PM PST 24
Peak memory 199612 kb
Host smart-1b5d0323-5e01-44d1-8146-7b2440b7c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574647919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1574647919
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1105138447
Short name T270
Test name
Test status
Simulation time 50256067786 ps
CPU time 21.7 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:25:05 PM PST 24
Peak memory 199628 kb
Host smart-b5ef1c95-5d01-40c4-9622-4c428c151ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105138447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1105138447
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.413312693
Short name T262
Test name
Test status
Simulation time 23334370114 ps
CPU time 11.01 seconds
Started Feb 29 01:24:41 PM PST 24
Finished Feb 29 01:24:52 PM PST 24
Peak memory 199576 kb
Host smart-a8ef73cd-9def-4f81-b73d-0d4fa9a80f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413312693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.413312693
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.697786718
Short name T990
Test name
Test status
Simulation time 40993773953 ps
CPU time 68.31 seconds
Started Feb 29 01:24:40 PM PST 24
Finished Feb 29 01:25:49 PM PST 24
Peak memory 199580 kb
Host smart-a6609dc0-ded3-4e4f-9f76-728a99616796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697786718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.697786718
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1737687686
Short name T914
Test name
Test status
Simulation time 134770522429 ps
CPU time 55.34 seconds
Started Feb 29 01:24:49 PM PST 24
Finished Feb 29 01:25:44 PM PST 24
Peak memory 199240 kb
Host smart-b2091727-460d-4fd8-b6b3-b5142fbac3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737687686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1737687686
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3176958165
Short name T1087
Test name
Test status
Simulation time 25322764309 ps
CPU time 46.26 seconds
Started Feb 29 01:24:43 PM PST 24
Finished Feb 29 01:25:30 PM PST 24
Peak memory 199524 kb
Host smart-d70a2485-56f3-40ae-aab8-64c24b6b5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176958165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3176958165
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.384934211
Short name T616
Test name
Test status
Simulation time 20330217576 ps
CPU time 15.42 seconds
Started Feb 29 01:24:47 PM PST 24
Finished Feb 29 01:25:03 PM PST 24
Peak memory 199496 kb
Host smart-36ee89e7-a7f1-497a-a7ac-7b37cee162a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384934211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.384934211
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.754432961
Short name T813
Test name
Test status
Simulation time 41572643572 ps
CPU time 31.36 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:24 PM PST 24
Peak memory 199052 kb
Host smart-c6181391-8e88-448f-9170-575288b8cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754432961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.754432961
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1919926682
Short name T479
Test name
Test status
Simulation time 12969426 ps
CPU time 0.55 seconds
Started Feb 29 01:20:59 PM PST 24
Finished Feb 29 01:20:59 PM PST 24
Peak memory 194888 kb
Host smart-ebc120da-ea91-4958-ace2-6ca89deaa710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919926682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1919926682
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.162303775
Short name T851
Test name
Test status
Simulation time 31319891776 ps
CPU time 51.71 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:21:55 PM PST 24
Peak memory 199504 kb
Host smart-919d3551-80cb-4c1a-ae84-fc04d7b52ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162303775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.162303775
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1553961604
Short name T761
Test name
Test status
Simulation time 154439330027 ps
CPU time 60.19 seconds
Started Feb 29 01:21:02 PM PST 24
Finished Feb 29 01:22:02 PM PST 24
Peak memory 199568 kb
Host smart-30747a52-fac5-4efb-b653-dfb91061edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553961604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1553961604
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2019521729
Short name T940
Test name
Test status
Simulation time 10707179510 ps
CPU time 11.15 seconds
Started Feb 29 01:21:03 PM PST 24
Finished Feb 29 01:21:14 PM PST 24
Peak memory 199516 kb
Host smart-dba974f2-3abb-434e-bcf9-ba0eb6c3f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019521729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2019521729
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2901503026
Short name T785
Test name
Test status
Simulation time 1059533194174 ps
CPU time 887.34 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:35:51 PM PST 24
Peak memory 198740 kb
Host smart-09f8ba60-0e9b-4f7d-9ef5-b4f22b3b8c7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901503026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2901503026
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.62508696
Short name T607
Test name
Test status
Simulation time 278657507998 ps
CPU time 546.25 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:30:11 PM PST 24
Peak memory 199556 kb
Host smart-00a40ee7-24cf-4760-a65e-6e85a8be08c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62508696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.62508696
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1377217090
Short name T764
Test name
Test status
Simulation time 1063683293 ps
CPU time 2.13 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:03 PM PST 24
Peak memory 194896 kb
Host smart-4c4e5aeb-52ae-4a4d-83e5-835686069c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377217090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1377217090
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3616583336
Short name T1023
Test name
Test status
Simulation time 103789184904 ps
CPU time 41.57 seconds
Started Feb 29 01:21:02 PM PST 24
Finished Feb 29 01:21:44 PM PST 24
Peak memory 199724 kb
Host smart-796e820c-b743-4f36-94dd-9b620a544b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616583336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3616583336
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1580737472
Short name T179
Test name
Test status
Simulation time 9122920020 ps
CPU time 95.83 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:22:40 PM PST 24
Peak memory 199612 kb
Host smart-07840de1-061a-4b74-b1fa-580c4deebe7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580737472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1580737472
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2334410744
Short name T852
Test name
Test status
Simulation time 2344555899 ps
CPU time 3.97 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:21:05 PM PST 24
Peak memory 197972 kb
Host smart-fece0bed-de65-471e-9b6f-125e901cdf2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334410744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2334410744
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3444716844
Short name T300
Test name
Test status
Simulation time 162476631937 ps
CPU time 36.71 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:36 PM PST 24
Peak memory 199044 kb
Host smart-d6a03f00-e166-4ee4-8dae-589ae3567e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444716844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3444716844
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2932867396
Short name T441
Test name
Test status
Simulation time 3740535511 ps
CPU time 2.21 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:21:06 PM PST 24
Peak memory 195292 kb
Host smart-5d1325b6-a1a8-46fc-8674-002b5d0fa8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932867396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2932867396
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1808106090
Short name T731
Test name
Test status
Simulation time 312622515 ps
CPU time 1.31 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:01 PM PST 24
Peak memory 198024 kb
Host smart-f42d2a88-f234-407b-85f2-5c9b6737f780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808106090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1808106090
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2354769362
Short name T669
Test name
Test status
Simulation time 199918580460 ps
CPU time 210.23 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:24:31 PM PST 24
Peak memory 207864 kb
Host smart-7ee6d731-8546-46c3-a214-8e5a134a8cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354769362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2354769362
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.208800987
Short name T858
Test name
Test status
Simulation time 1972538381 ps
CPU time 2.33 seconds
Started Feb 29 01:21:04 PM PST 24
Finished Feb 29 01:21:06 PM PST 24
Peak memory 197916 kb
Host smart-4d39e8c1-9eb9-4c92-995a-b3ab76c1af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208800987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.208800987
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3070617043
Short name T857
Test name
Test status
Simulation time 40440413403 ps
CPU time 88.94 seconds
Started Feb 29 01:21:02 PM PST 24
Finished Feb 29 01:22:31 PM PST 24
Peak memory 199628 kb
Host smart-f8e6d7d1-5e69-419b-a91c-95385b01ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070617043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3070617043
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2504131242
Short name T1030
Test name
Test status
Simulation time 43237139177 ps
CPU time 22.11 seconds
Started Feb 29 01:24:54 PM PST 24
Finished Feb 29 01:25:16 PM PST 24
Peak memory 198504 kb
Host smart-db7eca31-3eae-49f1-8727-4ea79dd63bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504131242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2504131242
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.29773539
Short name T1100
Test name
Test status
Simulation time 17720383522 ps
CPU time 8.5 seconds
Started Feb 29 01:24:51 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 199544 kb
Host smart-1dfaa32e-526b-41ec-9f2f-0b059b56583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29773539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.29773539
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2299483395
Short name T1053
Test name
Test status
Simulation time 32689701912 ps
CPU time 13.54 seconds
Started Feb 29 01:24:51 PM PST 24
Finished Feb 29 01:25:05 PM PST 24
Peak memory 199524 kb
Host smart-484113d3-c390-45b4-b936-affc8b0d2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299483395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2299483395
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3971375453
Short name T128
Test name
Test status
Simulation time 29982540106 ps
CPU time 12.82 seconds
Started Feb 29 01:24:53 PM PST 24
Finished Feb 29 01:25:06 PM PST 24
Peak memory 197032 kb
Host smart-b7111024-eebd-42cf-9714-fab95d2b3d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971375453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3971375453
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3914584980
Short name T974
Test name
Test status
Simulation time 20854748496 ps
CPU time 34.07 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:26 PM PST 24
Peak memory 199048 kb
Host smart-9d95eb1e-274a-4c0d-881a-f16758058bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914584980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3914584980
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1477813340
Short name T1010
Test name
Test status
Simulation time 53540688329 ps
CPU time 54.16 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:46 PM PST 24
Peak memory 199500 kb
Host smart-75bd5b65-7662-4b25-a26d-8bded896f75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477813340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1477813340
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2032244198
Short name T322
Test name
Test status
Simulation time 27653397784 ps
CPU time 44.69 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:37 PM PST 24
Peak memory 198972 kb
Host smart-08d4ace0-0704-4f35-9354-01daf90919bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032244198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2032244198
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2585887377
Short name T1050
Test name
Test status
Simulation time 13357841 ps
CPU time 0.56 seconds
Started Feb 29 01:21:26 PM PST 24
Finished Feb 29 01:21:27 PM PST 24
Peak memory 195028 kb
Host smart-55b9414c-e886-454d-a614-d0f4a1b8d685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585887377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2585887377
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3157635188
Short name T403
Test name
Test status
Simulation time 135967778380 ps
CPU time 47.82 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:48 PM PST 24
Peak memory 199532 kb
Host smart-098aaca1-6206-4907-a260-e6702628d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157635188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3157635188
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3472253868
Short name T395
Test name
Test status
Simulation time 34326168455 ps
CPU time 17.22 seconds
Started Feb 29 01:20:59 PM PST 24
Finished Feb 29 01:21:17 PM PST 24
Peak memory 199524 kb
Host smart-b071fae6-5c43-4274-afe5-28c74df41d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472253868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3472253868
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3351452378
Short name T665
Test name
Test status
Simulation time 14626805283 ps
CPU time 24.09 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 196468 kb
Host smart-e606e000-1385-4e76-8257-8a639039242a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351452378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3351452378
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3893704398
Short name T882
Test name
Test status
Simulation time 72779465368 ps
CPU time 143.45 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:23:24 PM PST 24
Peak memory 199468 kb
Host smart-0c4f6cb1-5201-4eb0-b460-5f37837111d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893704398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3893704398
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2022473181
Short name T853
Test name
Test status
Simulation time 9217575804 ps
CPU time 10.93 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:21:13 PM PST 24
Peak memory 199436 kb
Host smart-79e033a5-7e55-4ec5-8fc1-3b12d71bb775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022473181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2022473181
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1185079931
Short name T517
Test name
Test status
Simulation time 90933915342 ps
CPU time 39.68 seconds
Started Feb 29 01:21:03 PM PST 24
Finished Feb 29 01:21:43 PM PST 24
Peak memory 199376 kb
Host smart-3dafad58-419d-4e11-8ec5-7c53339bd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185079931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1185079931
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.457202277
Short name T45
Test name
Test status
Simulation time 6891074011 ps
CPU time 395.28 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:27:36 PM PST 24
Peak memory 199552 kb
Host smart-e1f00a62-23ca-46e9-ac5b-83143414704c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457202277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.457202277
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2168151918
Short name T3
Test name
Test status
Simulation time 3074223377 ps
CPU time 27.35 seconds
Started Feb 29 01:21:06 PM PST 24
Finished Feb 29 01:21:34 PM PST 24
Peak memory 197792 kb
Host smart-09709f60-f3ad-45b9-93d2-6bcd7447b158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168151918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2168151918
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2182694395
Short name T587
Test name
Test status
Simulation time 27762553550 ps
CPU time 45.26 seconds
Started Feb 29 01:21:01 PM PST 24
Finished Feb 29 01:21:47 PM PST 24
Peak memory 195004 kb
Host smart-111fbb84-6153-45ce-96a2-f2491ca026ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182694395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2182694395
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.441184092
Short name T896
Test name
Test status
Simulation time 5604787118 ps
CPU time 6.28 seconds
Started Feb 29 01:21:02 PM PST 24
Finished Feb 29 01:21:08 PM PST 24
Peak memory 199592 kb
Host smart-2e51298b-b7f5-48f6-b2c1-5c0fcd60e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441184092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.441184092
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.4118513001
Short name T643
Test name
Test status
Simulation time 118596709288 ps
CPU time 654.49 seconds
Started Feb 29 01:21:20 PM PST 24
Finished Feb 29 01:32:14 PM PST 24
Peak memory 199496 kb
Host smart-cbbe43bf-0de6-4168-93df-600a40fc0138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118513001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4118513001
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2900764842
Short name T103
Test name
Test status
Simulation time 12581071473 ps
CPU time 32.14 seconds
Started Feb 29 01:21:00 PM PST 24
Finished Feb 29 01:21:33 PM PST 24
Peak memory 199148 kb
Host smart-2ab96e8c-ff34-4257-9430-cd20cc615c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900764842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2900764842
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.175694220
Short name T721
Test name
Test status
Simulation time 43189790342 ps
CPU time 76.06 seconds
Started Feb 29 01:21:03 PM PST 24
Finished Feb 29 01:22:19 PM PST 24
Peak memory 199556 kb
Host smart-073fb8c5-984b-4948-a2eb-475534676405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175694220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.175694220
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.998082538
Short name T142
Test name
Test status
Simulation time 94222763154 ps
CPU time 73.43 seconds
Started Feb 29 01:24:51 PM PST 24
Finished Feb 29 01:26:05 PM PST 24
Peak memory 199556 kb
Host smart-f09c6d97-7ad6-4f68-aadc-62769c5f8d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998082538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.998082538
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.816496409
Short name T951
Test name
Test status
Simulation time 148084766323 ps
CPU time 295.5 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:29:48 PM PST 24
Peak memory 199564 kb
Host smart-e5aa7b62-78ae-4baa-ac39-0668836c97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816496409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.816496409
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2851206716
Short name T972
Test name
Test status
Simulation time 58954952266 ps
CPU time 35.86 seconds
Started Feb 29 01:24:54 PM PST 24
Finished Feb 29 01:25:30 PM PST 24
Peak memory 199548 kb
Host smart-9351dc3a-4999-4dee-b220-483c1f2e8fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851206716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2851206716
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2104716649
Short name T900
Test name
Test status
Simulation time 13063283604 ps
CPU time 22.26 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:15 PM PST 24
Peak memory 199580 kb
Host smart-ad8d869a-59dc-4496-9efd-2aa9b0c3c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104716649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2104716649
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.629108190
Short name T953
Test name
Test status
Simulation time 138103567595 ps
CPU time 114.81 seconds
Started Feb 29 01:24:53 PM PST 24
Finished Feb 29 01:26:48 PM PST 24
Peak memory 199580 kb
Host smart-90e60762-2cb5-4249-bf98-99c033eeb084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629108190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.629108190
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.633650431
Short name T357
Test name
Test status
Simulation time 227111922037 ps
CPU time 99.19 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:26:31 PM PST 24
Peak memory 199224 kb
Host smart-7ef43543-9797-46ad-a608-59802ab3a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633650431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.633650431
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1933650950
Short name T249
Test name
Test status
Simulation time 56560453335 ps
CPU time 22.41 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:15 PM PST 24
Peak memory 198624 kb
Host smart-5fb2b978-079b-47b3-8db2-61fc2405f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933650950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1933650950
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3597066393
Short name T281
Test name
Test status
Simulation time 151806236108 ps
CPU time 71.2 seconds
Started Feb 29 01:24:58 PM PST 24
Finished Feb 29 01:26:09 PM PST 24
Peak memory 199388 kb
Host smart-f8ed4cf8-35a1-4006-9f68-b442d008af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597066393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3597066393
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2455488472
Short name T610
Test name
Test status
Simulation time 32737439114 ps
CPU time 17.91 seconds
Started Feb 29 01:24:52 PM PST 24
Finished Feb 29 01:25:10 PM PST 24
Peak memory 199636 kb
Host smart-b31209da-df91-40e2-9254-25591311caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455488472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2455488472
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1386340327
Short name T566
Test name
Test status
Simulation time 11201677 ps
CPU time 0.54 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:18:53 PM PST 24
Peak memory 193968 kb
Host smart-07844581-e638-4449-a1ec-d5acb070d642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386340327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1386340327
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3736141851
Short name T549
Test name
Test status
Simulation time 147193299827 ps
CPU time 114.71 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:20:48 PM PST 24
Peak memory 199576 kb
Host smart-9463a3db-2311-4eb0-92d9-1397ac5f5cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736141851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3736141851
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1909284885
Short name T1026
Test name
Test status
Simulation time 137618559341 ps
CPU time 232.84 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 199356 kb
Host smart-f7a706b1-7f72-4f59-8fa6-efe9268acf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909284885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1909284885
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2265011077
Short name T515
Test name
Test status
Simulation time 62972936270 ps
CPU time 24.91 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:19:16 PM PST 24
Peak memory 199476 kb
Host smart-b2bb7d12-85dd-4dca-9307-abc421cd9b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265011077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2265011077
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1761732866
Short name T641
Test name
Test status
Simulation time 5746257117 ps
CPU time 8.28 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:19:04 PM PST 24
Peak memory 194956 kb
Host smart-584a0f31-169b-4721-9d27-71155a16f7ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761732866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1761732866
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2711560662
Short name T783
Test name
Test status
Simulation time 130070128813 ps
CPU time 1181.61 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:38:37 PM PST 24
Peak memory 199604 kb
Host smart-0480a3cf-028b-45d9-94ea-bdee37f08e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711560662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2711560662
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3067904623
Short name T551
Test name
Test status
Simulation time 6038479884 ps
CPU time 4.28 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:18:57 PM PST 24
Peak memory 198064 kb
Host smart-a69ca978-5898-4947-ad3b-72dc6743be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067904623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3067904623
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.4182240608
Short name T177
Test name
Test status
Simulation time 154204941022 ps
CPU time 178 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:21:52 PM PST 24
Peak memory 199756 kb
Host smart-ab185de8-d836-4294-8686-621faacc4afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182240608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4182240608
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2200498825
Short name T254
Test name
Test status
Simulation time 26852678668 ps
CPU time 957.27 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:34:50 PM PST 24
Peak memory 199544 kb
Host smart-6bf641eb-1341-411d-a6e5-a224f18260a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200498825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2200498825
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1327110750
Short name T17
Test name
Test status
Simulation time 1374140964 ps
CPU time 14.95 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:19:06 PM PST 24
Peak memory 197732 kb
Host smart-fc552070-a7d5-4fde-8420-f7693d009ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327110750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1327110750
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3689443303
Short name T277
Test name
Test status
Simulation time 186610112960 ps
CPU time 232.35 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 199812 kb
Host smart-c5b2c4ab-c067-4b58-8ff4-c5fbde8145d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689443303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3689443303
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1801190318
Short name T699
Test name
Test status
Simulation time 51410580546 ps
CPU time 20.38 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:19:13 PM PST 24
Peak memory 195344 kb
Host smart-ec48e980-70bb-4613-b7a6-670103ac83c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801190318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1801190318
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.255670894
Short name T26
Test name
Test status
Simulation time 61112825 ps
CPU time 0.81 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:18:52 PM PST 24
Peak memory 217132 kb
Host smart-4c2d68a4-f7dd-4c83-a09d-200616f5cf99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255670894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.255670894
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1506114320
Short name T942
Test name
Test status
Simulation time 336851390 ps
CPU time 1 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 197216 kb
Host smart-22cd6e97-95eb-46f9-8d4e-8ff26765b09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506114320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1506114320
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1616022055
Short name T564
Test name
Test status
Simulation time 459020523336 ps
CPU time 431.92 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:26:03 PM PST 24
Peak memory 210296 kb
Host smart-3f6adb28-3060-48d3-841b-4069a767aa95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616022055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1616022055
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.136972911
Short name T686
Test name
Test status
Simulation time 548385049 ps
CPU time 1.76 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 197784 kb
Host smart-24e9e10f-6e38-4119-afb4-eb30efb508a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136972911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.136972911
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.728085854
Short name T651
Test name
Test status
Simulation time 9302210195 ps
CPU time 2.15 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 196456 kb
Host smart-a343cb74-a772-44c7-8d5e-c326649f8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728085854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.728085854
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3349559688
Short name T471
Test name
Test status
Simulation time 35940950 ps
CPU time 0.55 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 195016 kb
Host smart-cb50879c-2798-4fc8-a115-598a3923f888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349559688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3349559688
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1084205789
Short name T1008
Test name
Test status
Simulation time 82357797373 ps
CPU time 36.27 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:58 PM PST 24
Peak memory 199380 kb
Host smart-0c5a1237-d315-4def-bd4e-bf89867bcc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084205789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1084205789
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2794717333
Short name T878
Test name
Test status
Simulation time 27168408768 ps
CPU time 12.61 seconds
Started Feb 29 01:21:20 PM PST 24
Finished Feb 29 01:21:32 PM PST 24
Peak memory 199108 kb
Host smart-cd6071b2-4cb9-4b5c-bba7-b3cc6d4215b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794717333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2794717333
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3928643217
Short name T352
Test name
Test status
Simulation time 56877632390 ps
CPU time 48.93 seconds
Started Feb 29 01:21:20 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 199544 kb
Host smart-afb70d36-bce4-4422-80ac-36cff072413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928643217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3928643217
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2354720659
Short name T514
Test name
Test status
Simulation time 586456234438 ps
CPU time 382.35 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:27:46 PM PST 24
Peak memory 199464 kb
Host smart-0b00d695-f914-4539-a3b1-0f0d53d6b159
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354720659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2354720659
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2714333864
Short name T1092
Test name
Test status
Simulation time 152520018374 ps
CPU time 333.27 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:26:55 PM PST 24
Peak memory 199640 kb
Host smart-0ba21748-a723-4f87-b334-580d198bca53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714333864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2714333864
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2591027192
Short name T599
Test name
Test status
Simulation time 9363168436 ps
CPU time 9.88 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:32 PM PST 24
Peak memory 198120 kb
Host smart-1ccc314b-6627-4456-ac72-1572fecb1e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591027192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2591027192
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1193602640
Short name T822
Test name
Test status
Simulation time 125900765766 ps
CPU time 203.42 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:24:44 PM PST 24
Peak memory 207976 kb
Host smart-0f611b6d-5260-4a69-aa01-08004ac184f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193602640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1193602640
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3279267684
Short name T419
Test name
Test status
Simulation time 12948355938 ps
CPU time 535.35 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:30:16 PM PST 24
Peak memory 199504 kb
Host smart-353d3363-1d2e-443c-a45e-a8c8724de48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279267684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3279267684
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1358539688
Short name T480
Test name
Test status
Simulation time 2041070365 ps
CPU time 8.02 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:31 PM PST 24
Peak memory 197664 kb
Host smart-510c6900-6c45-4fd7-803a-34911326247f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358539688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1358539688
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.4004060009
Short name T931
Test name
Test status
Simulation time 142155188101 ps
CPU time 30.41 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:52 PM PST 24
Peak memory 198636 kb
Host smart-bf955b2e-b0c4-4097-88a2-849a701aac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004060009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.4004060009
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2645965671
Short name T774
Test name
Test status
Simulation time 5368863736 ps
CPU time 2.2 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:21:23 PM PST 24
Peak memory 195300 kb
Host smart-fd83d181-a635-4417-8c6c-53cacb3ed773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645965671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2645965671
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1801221645
Short name T1057
Test name
Test status
Simulation time 430166183 ps
CPU time 1.17 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:21:23 PM PST 24
Peak memory 197376 kb
Host smart-d9539ee4-dc03-429e-8f1e-3fbb48f0138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801221645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1801221645
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.884216185
Short name T202
Test name
Test status
Simulation time 373378645814 ps
CPU time 742.51 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:33:45 PM PST 24
Peak memory 199644 kb
Host smart-e9b4a1cb-7406-43f7-ae27-060964c30f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884216185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.884216185
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3103212318
Short name T449
Test name
Test status
Simulation time 35838373066 ps
CPU time 208.78 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:24:54 PM PST 24
Peak memory 216284 kb
Host smart-8af0b850-d41b-46be-bb1e-24ea1d562fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103212318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3103212318
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.980299993
Short name T439
Test name
Test status
Simulation time 8164915855 ps
CPU time 6.61 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:30 PM PST 24
Peak memory 199104 kb
Host smart-f354d20d-97e4-42c4-a87e-864bea0f5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980299993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.980299993
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2969359260
Short name T490
Test name
Test status
Simulation time 20760995359 ps
CPU time 31.8 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:55 PM PST 24
Peak memory 199860 kb
Host smart-5b6a6df7-71a4-478d-ba8d-d071f81ed2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969359260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2969359260
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3815564875
Short name T1041
Test name
Test status
Simulation time 14372634 ps
CPU time 0.57 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:21:22 PM PST 24
Peak memory 195020 kb
Host smart-49fe25f0-26ed-4cff-b8cd-25d2ca793758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815564875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3815564875
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.77069830
Short name T416
Test name
Test status
Simulation time 40409794294 ps
CPU time 22.36 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:44 PM PST 24
Peak memory 199504 kb
Host smart-f560b074-8342-468d-b618-a063c6db4bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77069830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.77069830
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2514786497
Short name T684
Test name
Test status
Simulation time 76856979660 ps
CPU time 35.77 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:58 PM PST 24
Peak memory 199040 kb
Host smart-085a76d7-7720-4057-9311-30b17ef3e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514786497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2514786497
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1672156592
Short name T1019
Test name
Test status
Simulation time 141465256774 ps
CPU time 29.47 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:21:53 PM PST 24
Peak memory 199616 kb
Host smart-afa9f273-6a1e-442f-a176-3036478b6fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672156592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1672156592
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3918902269
Short name T959
Test name
Test status
Simulation time 2071021872440 ps
CPU time 486.94 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:29:28 PM PST 24
Peak memory 199632 kb
Host smart-16208146-7744-4fe4-bbd9-46958c1cc412
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918902269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3918902269
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3987614847
Short name T528
Test name
Test status
Simulation time 300314256607 ps
CPU time 136.38 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:23:40 PM PST 24
Peak memory 199624 kb
Host smart-7fc2da80-45df-48ad-86c2-45eed8d1dc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987614847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3987614847
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3412983871
Short name T806
Test name
Test status
Simulation time 1703094020 ps
CPU time 3.07 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:21:25 PM PST 24
Peak memory 194984 kb
Host smart-aa9c90df-b46d-42ae-baae-1ddca9274d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412983871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3412983871
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.414834797
Short name T529
Test name
Test status
Simulation time 77958592944 ps
CPU time 254.41 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:25:36 PM PST 24
Peak memory 208036 kb
Host smart-53bf1fcc-053e-4879-b97e-23b8aa19a650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414834797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.414834797
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1300497513
Short name T939
Test name
Test status
Simulation time 3545175830 ps
CPU time 95.45 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:23:00 PM PST 24
Peak memory 199552 kb
Host smart-42fc7c27-6cfe-474a-97b3-83884955c14e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300497513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1300497513
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3384125054
Short name T475
Test name
Test status
Simulation time 3079298613 ps
CPU time 3.76 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:21:28 PM PST 24
Peak memory 198180 kb
Host smart-43f4d5aa-90de-436e-aa1a-8cc3aa1b8871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384125054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3384125054
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.981183394
Short name T371
Test name
Test status
Simulation time 75615639652 ps
CPU time 75.55 seconds
Started Feb 29 01:21:21 PM PST 24
Finished Feb 29 01:22:37 PM PST 24
Peak memory 199504 kb
Host smart-41d5503b-b955-4766-8df4-6020504cd29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981183394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.981183394
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.842846744
Short name T636
Test name
Test status
Simulation time 2275570193 ps
CPU time 4.08 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:26 PM PST 24
Peak memory 195032 kb
Host smart-392959ae-41e0-4b80-b44f-cb908e11817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842846744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.842846744
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3484532891
Short name T501
Test name
Test status
Simulation time 460199469 ps
CPU time 1.89 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 197348 kb
Host smart-060bceb1-dc25-453a-a1e4-3f756769f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484532891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3484532891
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1200579019
Short name T889
Test name
Test status
Simulation time 395640137148 ps
CPU time 101.11 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 215132 kb
Host smart-cfe3b5d4-ec29-4857-bc9f-6e81d11622bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200579019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1200579019
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2137307060
Short name T724
Test name
Test status
Simulation time 1442769912 ps
CPU time 1.62 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:21:25 PM PST 24
Peak memory 197420 kb
Host smart-fe62c60b-d568-42a7-b370-ffdb85db42fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137307060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2137307060
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1901990954
Short name T229
Test name
Test status
Simulation time 49795283226 ps
CPU time 130.53 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:23:33 PM PST 24
Peak memory 199572 kb
Host smart-d6d55128-3713-4992-8659-05e72cb55fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901990954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1901990954
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1083377851
Short name T50
Test name
Test status
Simulation time 52777540 ps
CPU time 0.53 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:21:39 PM PST 24
Peak memory 194172 kb
Host smart-b6bd443c-5d4f-4980-9718-072c1c83ffa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083377851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1083377851
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3517472815
Short name T1080
Test name
Test status
Simulation time 90437190100 ps
CPU time 39.17 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:22:03 PM PST 24
Peak memory 199792 kb
Host smart-a5898f62-4a3f-495e-a753-4a7b1eff99ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517472815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3517472815
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1017378795
Short name T370
Test name
Test status
Simulation time 97270246972 ps
CPU time 77.82 seconds
Started Feb 29 01:21:26 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 199588 kb
Host smart-8806631d-46e2-4c0c-89bd-011a4100d434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017378795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1017378795
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1289240377
Short name T284
Test name
Test status
Simulation time 39485865622 ps
CPU time 59.62 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 199528 kb
Host smart-fe7a2ac5-9eb9-46ed-8f71-c128544fc1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289240377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1289240377
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1218402691
Short name T594
Test name
Test status
Simulation time 120258522226 ps
CPU time 17.45 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:41 PM PST 24
Peak memory 198992 kb
Host smart-f06472fc-7715-41d3-8901-809dd6274aa2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218402691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1218402691
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.421182542
Short name T705
Test name
Test status
Simulation time 69223451537 ps
CPU time 431.99 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:28:37 PM PST 24
Peak memory 199344 kb
Host smart-a4b51a38-a051-44ee-a3b2-021bfcdcde90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421182542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.421182542
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1011045814
Short name T662
Test name
Test status
Simulation time 6507381969 ps
CPU time 12.83 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:21:38 PM PST 24
Peak memory 198676 kb
Host smart-78413bf5-ab29-4dcd-99e3-4139a51eeedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011045814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1011045814
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.792468283
Short name T486
Test name
Test status
Simulation time 46270992753 ps
CPU time 81.03 seconds
Started Feb 29 01:21:24 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 199816 kb
Host smart-6be0a4b4-529c-432d-b39c-4fef6be9be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792468283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.792468283
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3382154523
Short name T227
Test name
Test status
Simulation time 23404915748 ps
CPU time 332.58 seconds
Started Feb 29 01:21:22 PM PST 24
Finished Feb 29 01:26:54 PM PST 24
Peak memory 199552 kb
Host smart-67a6a34a-1140-430b-a708-346a31af3634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382154523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3382154523
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.676229101
Short name T503
Test name
Test status
Simulation time 1195468306 ps
CPU time 4.15 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:21:29 PM PST 24
Peak memory 197436 kb
Host smart-cc1b2732-a586-4741-8f84-38ee5cc294dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676229101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.676229101
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3388577372
Short name T429
Test name
Test status
Simulation time 119488714205 ps
CPU time 25.63 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:21:51 PM PST 24
Peak memory 199528 kb
Host smart-8767515b-5816-443c-9129-9759f899d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388577372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3388577372
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2618737786
Short name T760
Test name
Test status
Simulation time 3355500896 ps
CPU time 1.89 seconds
Started Feb 29 01:21:25 PM PST 24
Finished Feb 29 01:21:27 PM PST 24
Peak memory 194972 kb
Host smart-ae4d975d-e96e-4eb9-9784-3eda567531c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618737786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2618737786
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.65230437
Short name T1004
Test name
Test status
Simulation time 467000240 ps
CPU time 1.39 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:25 PM PST 24
Peak memory 197340 kb
Host smart-e92093dd-66d7-4747-aa24-f7501444d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65230437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.65230437
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3329159822
Short name T576
Test name
Test status
Simulation time 51048735968 ps
CPU time 652.63 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:32:16 PM PST 24
Peak memory 199608 kb
Host smart-42dfe593-3b85-4461-875c-19616fc5e80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329159822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3329159822
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3900107684
Short name T794
Test name
Test status
Simulation time 7530042776 ps
CPU time 10.42 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:21:34 PM PST 24
Peak memory 198456 kb
Host smart-ac20384c-e45e-4b73-8bd9-75a88d72bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900107684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3900107684
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1324202872
Short name T406
Test name
Test status
Simulation time 58820035626 ps
CPU time 94.19 seconds
Started Feb 29 01:21:23 PM PST 24
Finished Feb 29 01:22:57 PM PST 24
Peak memory 199856 kb
Host smart-c2e3a002-426e-4510-aa32-07601e14c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324202872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1324202872
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3645877047
Short name T495
Test name
Test status
Simulation time 81838122 ps
CPU time 0.54 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:21:40 PM PST 24
Peak memory 195240 kb
Host smart-c347b5e1-0465-44db-8c35-08633608765e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645877047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3645877047
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2162267048
Short name T260
Test name
Test status
Simulation time 256197147535 ps
CPU time 214.46 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:25:14 PM PST 24
Peak memory 199616 kb
Host smart-f88c0148-9f13-413a-9250-141a0aa3e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162267048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2162267048
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4172210585
Short name T659
Test name
Test status
Simulation time 26866387232 ps
CPU time 38.27 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 199324 kb
Host smart-dfad3942-f898-4e20-87f9-1df817f833ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172210585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4172210585
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3779480198
Short name T175
Test name
Test status
Simulation time 156424424287 ps
CPU time 245.69 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:25:46 PM PST 24
Peak memory 199552 kb
Host smart-101f46bb-dc94-42fb-90d0-814d68e87cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779480198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3779480198
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.552788034
Short name T820
Test name
Test status
Simulation time 36762051289 ps
CPU time 15.43 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:21:59 PM PST 24
Peak memory 197344 kb
Host smart-1e3e091a-5f88-4e72-beb6-314a7e777b20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552788034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.552788034
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2640168392
Short name T866
Test name
Test status
Simulation time 123227765865 ps
CPU time 355.02 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:27:36 PM PST 24
Peak memory 199444 kb
Host smart-42f81cb8-911f-4c0f-95f2-2ee047bbaaee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640168392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2640168392
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1549002652
Short name T638
Test name
Test status
Simulation time 3028968162 ps
CPU time 8.38 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:21:51 PM PST 24
Peak memory 198724 kb
Host smart-efd6afaa-6858-4253-b36e-065edf1c82bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549002652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1549002652
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2153442729
Short name T936
Test name
Test status
Simulation time 59921413329 ps
CPU time 139.95 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:24:00 PM PST 24
Peak memory 199604 kb
Host smart-d860b680-9e4a-4f09-b43f-23b000dd087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153442729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2153442729
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3686155469
Short name T231
Test name
Test status
Simulation time 10180708823 ps
CPU time 556.21 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:30:55 PM PST 24
Peak memory 199552 kb
Host smart-b559d283-3b47-4c94-9564-f4977f315216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686155469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3686155469
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3300359272
Short name T864
Test name
Test status
Simulation time 667908337 ps
CPU time 7.46 seconds
Started Feb 29 01:21:37 PM PST 24
Finished Feb 29 01:21:45 PM PST 24
Peak memory 197764 kb
Host smart-30b4b07d-0716-4ae8-88ea-a41f7b3f1fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300359272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3300359272
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3091777582
Short name T242
Test name
Test status
Simulation time 32462327370 ps
CPU time 51.74 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:22:32 PM PST 24
Peak memory 199584 kb
Host smart-71142207-fa71-4877-a38c-a29a7246c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091777582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3091777582
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1800844653
Short name T670
Test name
Test status
Simulation time 3878171125 ps
CPU time 1.5 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:21:44 PM PST 24
Peak memory 195396 kb
Host smart-1b6198cb-c361-4f14-9a39-34918bb4db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800844653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1800844653
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3080920934
Short name T771
Test name
Test status
Simulation time 527613874 ps
CPU time 1.17 seconds
Started Feb 29 01:21:38 PM PST 24
Finished Feb 29 01:21:39 PM PST 24
Peak memory 198436 kb
Host smart-3092df27-8ef2-4bd3-a9ed-60d1aef5ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080920934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3080920934
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2286588114
Short name T1088
Test name
Test status
Simulation time 71155190618 ps
CPU time 31.41 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:22:11 PM PST 24
Peak memory 198772 kb
Host smart-f82e5b4f-853f-442d-a84a-34a46a2f5a6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286588114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2286588114
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.823239705
Short name T453
Test name
Test status
Simulation time 59454757160 ps
CPU time 364.62 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:27:44 PM PST 24
Peak memory 216200 kb
Host smart-ee3ce86c-cc5b-4534-acd6-efaa3d463068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823239705 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.823239705
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1138114262
Short name T701
Test name
Test status
Simulation time 726182225 ps
CPU time 1.38 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:21:42 PM PST 24
Peak memory 197804 kb
Host smart-ae9521a7-f28c-448c-932a-43ee15d3ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138114262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1138114262
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.104430645
Short name T563
Test name
Test status
Simulation time 67420661488 ps
CPU time 30.01 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 199532 kb
Host smart-5f1f53d2-5470-410a-8711-3d5a1297c478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104430645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.104430645
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1589419540
Short name T21
Test name
Test status
Simulation time 33708579 ps
CPU time 0.54 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:21:47 PM PST 24
Peak memory 194084 kb
Host smart-6b650db3-0179-4970-b937-d0e7b05d6c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589419540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1589419540
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3318644966
Short name T364
Test name
Test status
Simulation time 229958475091 ps
CPU time 20.5 seconds
Started Feb 29 01:21:37 PM PST 24
Finished Feb 29 01:21:58 PM PST 24
Peak memory 199628 kb
Host smart-4e5e9675-ff6a-4752-8bbd-fcc24d0fabdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318644966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3318644966
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3712809447
Short name T927
Test name
Test status
Simulation time 180094474550 ps
CPU time 181.42 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:24:44 PM PST 24
Peak memory 199600 kb
Host smart-d990f66e-81ef-4cd7-9100-6300e56b378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712809447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3712809447
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1397115033
Short name T334
Test name
Test status
Simulation time 37409194147 ps
CPU time 15 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:21:56 PM PST 24
Peak memory 199524 kb
Host smart-c942f473-48ff-4bcc-8a6f-648faf748e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397115033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1397115033
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.678229222
Short name T1035
Test name
Test status
Simulation time 665005192296 ps
CPU time 1390.26 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:44:50 PM PST 24
Peak memory 199548 kb
Host smart-24e7a0e7-9988-4fe2-89b5-55a082792dcc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678229222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.678229222
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2871897539
Short name T399
Test name
Test status
Simulation time 61906178828 ps
CPU time 163.37 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:24:24 PM PST 24
Peak memory 199580 kb
Host smart-924a37c4-2015-4352-9425-91271089904c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871897539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2871897539
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2179522475
Short name T709
Test name
Test status
Simulation time 9127329493 ps
CPU time 9.28 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:21:49 PM PST 24
Peak memory 198504 kb
Host smart-59796c6d-2ec7-466e-ad7a-c260c204e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179522475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2179522475
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3681029647
Short name T398
Test name
Test status
Simulation time 28180331599 ps
CPU time 45.18 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 198748 kb
Host smart-2786454a-72e0-46f8-a858-ce85693b663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681029647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3681029647
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.514304595
Short name T442
Test name
Test status
Simulation time 7768739403 ps
CPU time 459.71 seconds
Started Feb 29 01:21:39 PM PST 24
Finished Feb 29 01:29:19 PM PST 24
Peak memory 199276 kb
Host smart-9c51aa1e-1354-4dc7-aa7e-8aa6a59c5895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514304595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.514304595
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3729298890
Short name T522
Test name
Test status
Simulation time 2230783081 ps
CPU time 24.11 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:22:06 PM PST 24
Peak memory 197684 kb
Host smart-c3204be7-b244-4187-88f7-58f690877a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729298890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3729298890
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1990434117
Short name T746
Test name
Test status
Simulation time 183721718017 ps
CPU time 47.64 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:22:29 PM PST 24
Peak memory 199356 kb
Host smart-b65fcb95-761a-4045-8847-9c994ce8f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990434117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1990434117
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2638954959
Short name T404
Test name
Test status
Simulation time 4784810493 ps
CPU time 1.31 seconds
Started Feb 29 01:21:38 PM PST 24
Finished Feb 29 01:21:40 PM PST 24
Peak memory 195336 kb
Host smart-0ec541db-7a9e-4ee7-9464-9f982ff5066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638954959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2638954959
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3424987552
Short name T801
Test name
Test status
Simulation time 6098242555 ps
CPU time 7.18 seconds
Started Feb 29 01:21:38 PM PST 24
Finished Feb 29 01:21:45 PM PST 24
Peak memory 198892 kb
Host smart-a51f5a82-c56d-4d4b-bee9-3967416269e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424987552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3424987552
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.602874890
Short name T622
Test name
Test status
Simulation time 574357204999 ps
CPU time 424.99 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:28:51 PM PST 24
Peak memory 199508 kb
Host smart-fe661d56-e836-40b2-8e90-16681e1ccad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602874890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.602874890
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1375616875
Short name T664
Test name
Test status
Simulation time 8453125081 ps
CPU time 1.77 seconds
Started Feb 29 01:21:44 PM PST 24
Finished Feb 29 01:21:46 PM PST 24
Peak memory 198376 kb
Host smart-50fa4e69-f6f4-4a7a-914c-85f7c669bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375616875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1375616875
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3966162744
Short name T623
Test name
Test status
Simulation time 10054521766 ps
CPU time 14.69 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:22:01 PM PST 24
Peak memory 195392 kb
Host smart-ca09d083-9de7-458d-b4c7-204a3e6d9a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966162744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3966162744
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3701844420
Short name T706
Test name
Test status
Simulation time 22733382 ps
CPU time 0.54 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:21:44 PM PST 24
Peak memory 194036 kb
Host smart-c7fe778e-8cbe-4f96-86db-f9010c519cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701844420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3701844420
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2947744945
Short name T589
Test name
Test status
Simulation time 26248918813 ps
CPU time 40.04 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:22:22 PM PST 24
Peak memory 199848 kb
Host smart-986a7a95-6c0f-4b9b-95e0-e725fcd9a858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947744945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2947744945
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.611658186
Short name T379
Test name
Test status
Simulation time 50663588579 ps
CPU time 91.28 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:23:18 PM PST 24
Peak memory 199464 kb
Host smart-b2743b2b-1674-4f37-98cc-0cac80d3b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611658186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.611658186
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3720255681
Short name T795
Test name
Test status
Simulation time 34331208851 ps
CPU time 28.59 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:22:12 PM PST 24
Peak memory 199576 kb
Host smart-02eb866b-f4fb-4e89-b089-82c8d5ba498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720255681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3720255681
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3786396882
Short name T572
Test name
Test status
Simulation time 674248025581 ps
CPU time 272.66 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:26:19 PM PST 24
Peak memory 199408 kb
Host smart-70a3d138-57a3-4824-906b-f7d2fc20911d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786396882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3786396882
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3288392746
Short name T816
Test name
Test status
Simulation time 111542505694 ps
CPU time 364.08 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:27:50 PM PST 24
Peak memory 199516 kb
Host smart-fd1b8bba-f498-45df-b757-5f47aacd24e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288392746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3288392746
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.4286513783
Short name T621
Test name
Test status
Simulation time 12971585380 ps
CPU time 13.31 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:22:00 PM PST 24
Peak memory 199156 kb
Host smart-ce8cc80b-bc7f-417e-ad2a-46f4b9b8ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286513783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4286513783
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3405516545
Short name T960
Test name
Test status
Simulation time 104976717024 ps
CPU time 78.34 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:23:05 PM PST 24
Peak memory 207628 kb
Host smart-b94d89ff-2d92-4338-8f15-907f9adb34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405516545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3405516545
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1956019620
Short name T282
Test name
Test status
Simulation time 14080742913 ps
CPU time 350.93 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:27:31 PM PST 24
Peak memory 199516 kb
Host smart-2ea3dadb-aa5a-4e8a-b4aa-cab8515ec885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956019620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1956019620
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.466586687
Short name T632
Test name
Test status
Simulation time 2644837050 ps
CPU time 13.89 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:21:54 PM PST 24
Peak memory 198000 kb
Host smart-446aa485-b044-44d2-9bea-63debbe8327c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466586687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.466586687
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1486100483
Short name T606
Test name
Test status
Simulation time 71790868059 ps
CPU time 39.46 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 199420 kb
Host smart-2d21a736-1590-436c-b0a4-416e93300717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486100483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1486100483
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1966288528
Short name T1089
Test name
Test status
Simulation time 41192895435 ps
CPU time 31.65 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:22:12 PM PST 24
Peak memory 195028 kb
Host smart-74a4bd88-a0e9-4749-8a14-8567db804dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966288528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1966288528
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3693900785
Short name T978
Test name
Test status
Simulation time 475068891 ps
CPU time 2.06 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:21:43 PM PST 24
Peak memory 198576 kb
Host smart-df18ce19-755e-44c7-b658-01f0bc918795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693900785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3693900785
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.4269567181
Short name T234
Test name
Test status
Simulation time 162275211728 ps
CPU time 751.47 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:34:13 PM PST 24
Peak memory 199584 kb
Host smart-c9578e39-af25-43a7-80b3-3d905f91a024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269567181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.4269567181
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.309107949
Short name T863
Test name
Test status
Simulation time 1215198135 ps
CPU time 1.81 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:21:43 PM PST 24
Peak memory 197924 kb
Host smart-e801b201-d007-47fb-b5de-735f86837636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309107949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.309107949
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.489573038
Short name T152
Test name
Test status
Simulation time 58192109103 ps
CPU time 121.43 seconds
Started Feb 29 01:21:44 PM PST 24
Finished Feb 29 01:23:46 PM PST 24
Peak memory 199520 kb
Host smart-c202c64a-7f43-4a61-9068-e0980953e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489573038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.489573038
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3465255288
Short name T472
Test name
Test status
Simulation time 14495521 ps
CPU time 0.54 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:21:54 PM PST 24
Peak memory 193924 kb
Host smart-0f22035d-c6d6-4f2e-8ad6-26ba1e4d4a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465255288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3465255288
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.679678166
Short name T958
Test name
Test status
Simulation time 157597775489 ps
CPU time 221.51 seconds
Started Feb 29 01:21:40 PM PST 24
Finished Feb 29 01:25:22 PM PST 24
Peak memory 199504 kb
Host smart-5cf18cee-6794-40a2-aedb-1faa9ed0861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679678166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.679678166
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3198948060
Short name T592
Test name
Test status
Simulation time 130129772715 ps
CPU time 130.41 seconds
Started Feb 29 01:21:41 PM PST 24
Finished Feb 29 01:23:51 PM PST 24
Peak memory 199548 kb
Host smart-6adda5b1-1d5d-4940-a09e-8836f466be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198948060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3198948060
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.6455097
Short name T502
Test name
Test status
Simulation time 104930355978 ps
CPU time 928.54 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:37:24 PM PST 24
Peak memory 199568 kb
Host smart-fbbc902f-b879-4c28-aee2-94acb2ef6c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6455097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.6455097
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.902261459
Short name T776
Test name
Test status
Simulation time 13068981411 ps
CPU time 14.24 seconds
Started Feb 29 01:21:54 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 197968 kb
Host smart-2a0f00cd-f506-4fe5-903f-4b42a94fb282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902261459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.902261459
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3103174690
Short name T624
Test name
Test status
Simulation time 79794691644 ps
CPU time 37.98 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 197892 kb
Host smart-a5dc5406-9891-4ec7-88e5-b1651494e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103174690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3103174690
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.485448827
Short name T658
Test name
Test status
Simulation time 22769889050 ps
CPU time 312.15 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:27:07 PM PST 24
Peak memory 199868 kb
Host smart-cd13a36e-dff0-47f1-8a9d-7cab2b247745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485448827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.485448827
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3337955523
Short name T454
Test name
Test status
Simulation time 2492122095 ps
CPU time 8.25 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:21:52 PM PST 24
Peak memory 197868 kb
Host smart-1585113e-c0a5-4c11-801e-abeaf931f84b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337955523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3337955523
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2114580720
Short name T901
Test name
Test status
Simulation time 97767538140 ps
CPU time 71.25 seconds
Started Feb 29 01:21:45 PM PST 24
Finished Feb 29 01:22:57 PM PST 24
Peak memory 199308 kb
Host smart-34303a61-a8a8-4fd4-92b8-4e636a3930dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114580720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2114580720
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1730624382
Short name T424
Test name
Test status
Simulation time 3562476596 ps
CPU time 2.94 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:21:46 PM PST 24
Peak memory 195252 kb
Host smart-d327526a-5f8e-46e5-b7ad-6baca78395c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730624382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1730624382
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3958375627
Short name T879
Test name
Test status
Simulation time 669190756 ps
CPU time 3.29 seconds
Started Feb 29 01:21:42 PM PST 24
Finished Feb 29 01:21:46 PM PST 24
Peak memory 197932 kb
Host smart-15b0f7b4-0e99-4984-b5b6-ed2c46ecf891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958375627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3958375627
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3931420227
Short name T49
Test name
Test status
Simulation time 130739083646 ps
CPU time 147.92 seconds
Started Feb 29 01:21:57 PM PST 24
Finished Feb 29 01:24:25 PM PST 24
Peak memory 199500 kb
Host smart-802083e1-bb94-4c03-aee0-9cf490fb6c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931420227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3931420227
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3325364219
Short name T735
Test name
Test status
Simulation time 12941664084 ps
CPU time 18.51 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:22:01 PM PST 24
Peak memory 199336 kb
Host smart-c5146093-5d11-4bfe-8656-38af045ebb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325364219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3325364219
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1938114959
Short name T655
Test name
Test status
Simulation time 25426211241 ps
CPU time 49.79 seconds
Started Feb 29 01:21:43 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 199592 kb
Host smart-f6393904-4acd-43ca-8ab3-6a6a339e8bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938114959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1938114959
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3655439096
Short name T902
Test name
Test status
Simulation time 31291827 ps
CPU time 0.54 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:21:54 PM PST 24
Peak memory 193940 kb
Host smart-d300a38c-8f42-40f9-a249-8e6b51151742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655439096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3655439096
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3574857658
Short name T383
Test name
Test status
Simulation time 60688698569 ps
CPU time 8.77 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:22:04 PM PST 24
Peak memory 199588 kb
Host smart-e87c4c24-6f08-4ef2-b44e-4fc9d61b0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574857658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3574857658
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3081743421
Short name T332
Test name
Test status
Simulation time 102149325989 ps
CPU time 31.37 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:22:27 PM PST 24
Peak memory 198920 kb
Host smart-dff15f1b-b09b-4635-8139-93b45b55dfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081743421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3081743421
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.911067075
Short name T163
Test name
Test status
Simulation time 50168150232 ps
CPU time 19.42 seconds
Started Feb 29 01:21:54 PM PST 24
Finished Feb 29 01:22:13 PM PST 24
Peak memory 199308 kb
Host smart-d6402faf-d9d6-4541-9b88-2b9418331c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911067075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.911067075
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.570999914
Short name T738
Test name
Test status
Simulation time 1024750717480 ps
CPU time 455.87 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:29:31 PM PST 24
Peak memory 199520 kb
Host smart-a851d9fa-1403-49b1-b375-d97edc64e3fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570999914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.570999914
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.150908976
Short name T420
Test name
Test status
Simulation time 88849997266 ps
CPU time 743.5 seconds
Started Feb 29 01:21:54 PM PST 24
Finished Feb 29 01:34:18 PM PST 24
Peak memory 199636 kb
Host smart-b98c0d18-eeee-4cc5-afc2-b0ea62213a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150908976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.150908976
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4126597287
Short name T537
Test name
Test status
Simulation time 3584996980 ps
CPU time 5.26 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:22:01 PM PST 24
Peak memory 197992 kb
Host smart-58dd661c-3b66-41e4-b265-3baa28216b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126597287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4126597287
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2303224024
Short name T243
Test name
Test status
Simulation time 34342212457 ps
CPU time 14.89 seconds
Started Feb 29 01:21:59 PM PST 24
Finished Feb 29 01:22:16 PM PST 24
Peak memory 198452 kb
Host smart-d302b744-cfb4-4b13-aa79-ab52217a0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303224024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2303224024
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1700655653
Short name T548
Test name
Test status
Simulation time 15086287763 ps
CPU time 169.06 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:24:44 PM PST 24
Peak memory 199608 kb
Host smart-decd8c21-3c28-4f8b-8cd0-20d68025498b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700655653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1700655653
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1900391594
Short name T460
Test name
Test status
Simulation time 368948403 ps
CPU time 3.01 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:21:59 PM PST 24
Peak memory 197748 kb
Host smart-7d6df0e5-908a-4ec6-8f68-7d9208071063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900391594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1900391594
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2668079858
Short name T226
Test name
Test status
Simulation time 8694054146 ps
CPU time 5.51 seconds
Started Feb 29 01:22:00 PM PST 24
Finished Feb 29 01:22:07 PM PST 24
Peak memory 199532 kb
Host smart-d7de8e7c-2fca-4b7e-8de1-67263915f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668079858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2668079858
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2754302378
Short name T1065
Test name
Test status
Simulation time 44113274489 ps
CPU time 17.74 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:22:13 PM PST 24
Peak memory 195372 kb
Host smart-ecdc6d59-70da-40f8-bf0b-9426b5b9e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754302378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2754302378
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2756034352
Short name T744
Test name
Test status
Simulation time 5374206734 ps
CPU time 9.1 seconds
Started Feb 29 01:22:00 PM PST 24
Finished Feb 29 01:22:11 PM PST 24
Peak memory 198976 kb
Host smart-589cf03d-29b0-4a24-b34a-f39e85d390ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756034352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2756034352
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3621830080
Short name T687
Test name
Test status
Simulation time 17791249262 ps
CPU time 31.76 seconds
Started Feb 29 01:21:54 PM PST 24
Finished Feb 29 01:22:26 PM PST 24
Peak memory 199432 kb
Host smart-cd0b9755-979d-4564-9b19-a5fae35268e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621830080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3621830080
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3011474171
Short name T752
Test name
Test status
Simulation time 7620323177 ps
CPU time 8.3 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:22:02 PM PST 24
Peak memory 198592 kb
Host smart-47096401-049e-403a-a53d-785af56232c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011474171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3011474171
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4008431267
Short name T410
Test name
Test status
Simulation time 59025042355 ps
CPU time 106.82 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:23:40 PM PST 24
Peak memory 199584 kb
Host smart-d3c4bc22-b530-4779-83df-c84e5a869d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008431267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4008431267
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1844379811
Short name T22
Test name
Test status
Simulation time 10562886 ps
CPU time 0.51 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:21:56 PM PST 24
Peak memory 194120 kb
Host smart-f8e1544f-5c2d-4c1e-94bb-5da5a4ad914d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844379811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1844379811
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.989428225
Short name T920
Test name
Test status
Simulation time 27294929793 ps
CPU time 12.2 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:22:05 PM PST 24
Peak memory 198732 kb
Host smart-c36ef75a-1452-4393-a6d2-139bc49cc70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989428225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.989428225
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1717537766
Short name T209
Test name
Test status
Simulation time 262732244703 ps
CPU time 30.68 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 199520 kb
Host smart-fc35a59e-291e-41ba-8543-b1009d3653be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717537766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1717537766
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.666675988
Short name T791
Test name
Test status
Simulation time 2268919904777 ps
CPU time 1671.92 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:49:46 PM PST 24
Peak memory 199496 kb
Host smart-cedec738-d6c6-45b2-9737-4010021bea4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666675988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.666675988
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2326651157
Short name T583
Test name
Test status
Simulation time 158339383959 ps
CPU time 1397.01 seconds
Started Feb 29 01:21:57 PM PST 24
Finished Feb 29 01:45:15 PM PST 24
Peak memory 199564 kb
Host smart-d57389f0-0774-4af4-b05d-de2118ec9e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326651157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2326651157
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1837210588
Short name T988
Test name
Test status
Simulation time 2830990890 ps
CPU time 1.98 seconds
Started Feb 29 01:22:00 PM PST 24
Finished Feb 29 01:22:03 PM PST 24
Peak memory 197656 kb
Host smart-8fabd1bc-e0d2-4564-85cc-4b09597997ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837210588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1837210588
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.955372878
Short name T842
Test name
Test status
Simulation time 195801553200 ps
CPU time 24.47 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 199140 kb
Host smart-aee667c8-8356-49d6-9c92-718d5caa42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955372878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.955372878
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1872426203
Short name T921
Test name
Test status
Simulation time 31785318962 ps
CPU time 1657.1 seconds
Started Feb 29 01:21:54 PM PST 24
Finished Feb 29 01:49:31 PM PST 24
Peak memory 199612 kb
Host smart-257a52db-d514-44b4-a51b-22531ec179c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872426203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1872426203
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2632450514
Short name T612
Test name
Test status
Simulation time 4045893304 ps
CPU time 12.39 seconds
Started Feb 29 01:21:52 PM PST 24
Finished Feb 29 01:22:05 PM PST 24
Peak memory 197992 kb
Host smart-5f943ccc-5836-4746-ac8d-530a40cc1024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632450514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2632450514
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1779425200
Short name T854
Test name
Test status
Simulation time 67266660758 ps
CPU time 103.02 seconds
Started Feb 29 01:21:59 PM PST 24
Finished Feb 29 01:23:44 PM PST 24
Peak memory 198652 kb
Host smart-f4f3c463-1b3a-4e84-a0e8-977c54c1f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779425200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1779425200
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3775710553
Short name T808
Test name
Test status
Simulation time 29913142259 ps
CPU time 19.62 seconds
Started Feb 29 01:22:00 PM PST 24
Finished Feb 29 01:22:21 PM PST 24
Peak memory 195316 kb
Host smart-c105fd35-b1ce-43a7-8455-a038e028a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775710553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3775710553
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3987208315
Short name T830
Test name
Test status
Simulation time 932642253 ps
CPU time 2.56 seconds
Started Feb 29 01:21:53 PM PST 24
Finished Feb 29 01:21:56 PM PST 24
Peak memory 197980 kb
Host smart-29ab4acf-7316-4d43-a066-b820ae42fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987208315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3987208315
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1793055679
Short name T961
Test name
Test status
Simulation time 754422405725 ps
CPU time 1159.17 seconds
Started Feb 29 01:21:59 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 199532 kb
Host smart-40599874-5484-4ea4-a517-455c69b854b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793055679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1793055679
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.41830302
Short name T696
Test name
Test status
Simulation time 4587666569 ps
CPU time 1.3 seconds
Started Feb 29 01:21:55 PM PST 24
Finished Feb 29 01:21:57 PM PST 24
Peak memory 197992 kb
Host smart-ac80bd0e-9567-4a62-941c-f49b29a5e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41830302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.41830302
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.92147166
Short name T571
Test name
Test status
Simulation time 64718666492 ps
CPU time 30.01 seconds
Started Feb 29 01:21:57 PM PST 24
Finished Feb 29 01:22:28 PM PST 24
Peak memory 199504 kb
Host smart-9ada091d-b651-4972-a006-e740bec86f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92147166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.92147166
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3088599679
Short name T682
Test name
Test status
Simulation time 39606347 ps
CPU time 0.52 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 193924 kb
Host smart-7a215ce0-f6f1-4332-9ded-42a5464f3dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088599679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3088599679
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2178886150
Short name T720
Test name
Test status
Simulation time 39824455802 ps
CPU time 32.9 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:22:40 PM PST 24
Peak memory 199480 kb
Host smart-3fadb4ca-51f7-4a39-9db1-2b3f816295cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178886150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2178886150
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3653038696
Short name T105
Test name
Test status
Simulation time 38636843999 ps
CPU time 16.7 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 198272 kb
Host smart-2ded42fd-6316-405f-a3d7-72335f2a92fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653038696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3653038696
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.4097270435
Short name T186
Test name
Test status
Simulation time 12429811664 ps
CPU time 16.58 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:22:26 PM PST 24
Peak memory 199612 kb
Host smart-4f8d20ea-3e85-459b-bf74-6de7fdf05965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097270435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.4097270435
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2395284855
Short name T780
Test name
Test status
Simulation time 538141094195 ps
CPU time 798.65 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:35:26 PM PST 24
Peak memory 198852 kb
Host smart-dfa9962c-5bc8-49a3-ac84-303f85db86a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395284855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2395284855
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2629580096
Short name T685
Test name
Test status
Simulation time 75198983087 ps
CPU time 394.42 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:28:42 PM PST 24
Peak memory 199780 kb
Host smart-b926d5aa-9376-4b1c-8bac-492775fb1c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629580096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2629580096
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3426561948
Short name T455
Test name
Test status
Simulation time 4019189841 ps
CPU time 8.02 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 199500 kb
Host smart-d4226d1d-b1f9-40ce-8ff8-5b340270dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426561948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3426561948
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.3577866271
Short name T947
Test name
Test status
Simulation time 14100064093 ps
CPU time 119.42 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:24:07 PM PST 24
Peak memory 199552 kb
Host smart-dc4f97ea-57ba-4244-b510-fe364d44d92c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577866271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3577866271
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.995751104
Short name T588
Test name
Test status
Simulation time 2067797278 ps
CPU time 10.6 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:22:19 PM PST 24
Peak memory 197884 kb
Host smart-21ca3527-db25-40fd-8be4-cd13cc450830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995751104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.995751104
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2836574142
Short name T356
Test name
Test status
Simulation time 112248294303 ps
CPU time 38.93 seconds
Started Feb 29 01:22:06 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 199412 kb
Host smart-d35bedf3-9791-49d0-aebb-0e4852fb8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836574142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2836574142
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.914454521
Short name T570
Test name
Test status
Simulation time 4309207550 ps
CPU time 5.75 seconds
Started Feb 29 01:22:16 PM PST 24
Finished Feb 29 01:22:22 PM PST 24
Peak memory 195368 kb
Host smart-d099c790-41f9-471a-9afc-75018e0d80ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914454521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.914454521
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1179682076
Short name T1022
Test name
Test status
Simulation time 651211559 ps
CPU time 2.54 seconds
Started Feb 29 01:21:59 PM PST 24
Finished Feb 29 01:22:03 PM PST 24
Peak memory 198920 kb
Host smart-802211ec-3429-4d84-85b8-034bb4a0162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179682076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1179682076
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3309535514
Short name T749
Test name
Test status
Simulation time 308958674586 ps
CPU time 455.56 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:29:44 PM PST 24
Peak memory 199556 kb
Host smart-ec3db4b9-99e7-435c-9009-8043667aa965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309535514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3309535514
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2555724591
Short name T414
Test name
Test status
Simulation time 972836586 ps
CPU time 2.49 seconds
Started Feb 29 01:22:06 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 198024 kb
Host smart-1816d4d3-0c0d-4625-8c44-11b2dd22d53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555724591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2555724591
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2852806545
Short name T712
Test name
Test status
Simulation time 45262830047 ps
CPU time 85.07 seconds
Started Feb 29 01:21:58 PM PST 24
Finished Feb 29 01:23:24 PM PST 24
Peak memory 199632 kb
Host smart-63b82d44-eda4-45a3-89b8-c4e7c80a6b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852806545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2852806545
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.290301679
Short name T535
Test name
Test status
Simulation time 14532675 ps
CPU time 0.57 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 194984 kb
Host smart-662fe669-2230-48ab-8bac-15abacef3b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290301679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.290301679
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1602585375
Short name T812
Test name
Test status
Simulation time 52088771759 ps
CPU time 87.31 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:20:25 PM PST 24
Peak memory 199480 kb
Host smart-4b76f3e2-4743-424f-a8f3-206aa8fac8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602585375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1602585375
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1163278142
Short name T938
Test name
Test status
Simulation time 138297342309 ps
CPU time 104.62 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:20:39 PM PST 24
Peak memory 199628 kb
Host smart-3192e7b5-8d73-47f2-9fff-43b8f97f93db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163278142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1163278142
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1809239724
Short name T1006
Test name
Test status
Simulation time 24153980199 ps
CPU time 40.81 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:19:34 PM PST 24
Peak memory 199588 kb
Host smart-99714a25-992f-4f85-af00-6ac92e1190a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809239724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1809239724
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.96389408
Short name T1044
Test name
Test status
Simulation time 971766772254 ps
CPU time 637.49 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:29:31 PM PST 24
Peak memory 199552 kb
Host smart-db0bbfbd-4da1-4ecc-8080-32eaa3e109a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96389408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.96389408
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1838228226
Short name T40
Test name
Test status
Simulation time 72172185228 ps
CPU time 556.77 seconds
Started Feb 29 01:18:51 PM PST 24
Finished Feb 29 01:28:08 PM PST 24
Peak memory 199564 kb
Host smart-28b3df4f-f390-49e4-b6b7-99451e5ab5c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838228226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1838228226
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2607962654
Short name T1063
Test name
Test status
Simulation time 243628665 ps
CPU time 0.76 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:18:55 PM PST 24
Peak memory 194952 kb
Host smart-820800da-ce2b-4d47-b359-673d81fbec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607962654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2607962654
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.2982230354
Short name T1072
Test name
Test status
Simulation time 5254409992 ps
CPU time 302.23 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:23:56 PM PST 24
Peak memory 199560 kb
Host smart-b890919a-b60c-438c-b2d6-f118f8deefae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982230354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2982230354
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2514914769
Short name T569
Test name
Test status
Simulation time 2472525847 ps
CPU time 7.55 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:19:01 PM PST 24
Peak memory 197608 kb
Host smart-b1a186a5-d548-45c7-8310-a874014a282e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514914769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2514914769
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2690410194
Short name T512
Test name
Test status
Simulation time 32030509702 ps
CPU time 14.93 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 197512 kb
Host smart-8aef90d1-123a-4bbf-967b-ca092ab772ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690410194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2690410194
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1205316640
Short name T107
Test name
Test status
Simulation time 6797920446 ps
CPU time 1.24 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:18:57 PM PST 24
Peak memory 195284 kb
Host smart-88be6139-e77b-446e-ae4e-23baef495019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205316640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1205316640
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.289415042
Short name T86
Test name
Test status
Simulation time 148502750 ps
CPU time 0.88 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:18:57 PM PST 24
Peak memory 217076 kb
Host smart-57825ea7-6df5-48d3-8829-9131c49feb6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289415042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.289415042
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3816484707
Short name T443
Test name
Test status
Simulation time 853449283 ps
CPU time 1.9 seconds
Started Feb 29 01:18:52 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 198780 kb
Host smart-854fed4e-a44c-4f9f-ac11-8afac9140241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816484707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3816484707
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2729510316
Short name T829
Test name
Test status
Simulation time 3263715383 ps
CPU time 1.88 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:18:58 PM PST 24
Peak memory 197908 kb
Host smart-075850bb-3493-48fc-99c0-a11b860c20ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729510316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2729510316
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.459699262
Short name T986
Test name
Test status
Simulation time 48917751806 ps
CPU time 19.79 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:19:15 PM PST 24
Peak memory 199616 kb
Host smart-401756fc-0f61-4d95-b853-94589fc42c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459699262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.459699262
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.312631061
Short name T464
Test name
Test status
Simulation time 24990870 ps
CPU time 0.58 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:22:10 PM PST 24
Peak memory 195008 kb
Host smart-f5657142-8c30-4ae6-b9f7-4f697bf1eba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312631061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.312631061
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.560003416
Short name T769
Test name
Test status
Simulation time 71977134538 ps
CPU time 96.86 seconds
Started Feb 29 01:22:06 PM PST 24
Finished Feb 29 01:23:43 PM PST 24
Peak memory 199484 kb
Host smart-825c74e2-6fda-47bf-a872-4842f55ec560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560003416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.560003416
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3758968965
Short name T595
Test name
Test status
Simulation time 120903474053 ps
CPU time 279.51 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:26:48 PM PST 24
Peak memory 199552 kb
Host smart-be4509b5-f063-45cc-9dd3-30dad3f8c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758968965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3758968965
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1956144861
Short name T859
Test name
Test status
Simulation time 103861266100 ps
CPU time 168.94 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:24:56 PM PST 24
Peak memory 199564 kb
Host smart-cf96382f-a543-4d2d-ba9e-d507b128e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956144861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1956144861
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3753130470
Short name T888
Test name
Test status
Simulation time 64117530910 ps
CPU time 103.03 seconds
Started Feb 29 01:22:16 PM PST 24
Finished Feb 29 01:23:59 PM PST 24
Peak memory 197296 kb
Host smart-01d47cb1-806f-4a13-afc2-42103d8ee48b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753130470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3753130470
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2596052325
Short name T798
Test name
Test status
Simulation time 125879819514 ps
CPU time 498.45 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:30:27 PM PST 24
Peak memory 199592 kb
Host smart-6035fefd-6776-4ce0-b0ef-99c1021ede4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596052325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2596052325
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1788573498
Short name T982
Test name
Test status
Simulation time 5098255895 ps
CPU time 9.65 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 198440 kb
Host smart-286c49a1-282a-464d-9416-a6447ae084cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788573498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1788573498
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1780010406
Short name T554
Test name
Test status
Simulation time 257009865979 ps
CPU time 64.48 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:23:13 PM PST 24
Peak memory 208140 kb
Host smart-f0e71b2c-cb2d-4706-9581-795b8ecf0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780010406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1780010406
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.619401158
Short name T923
Test name
Test status
Simulation time 18633712547 ps
CPU time 257.89 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:26:28 PM PST 24
Peak memory 199408 kb
Host smart-6775c11e-e879-4e20-a762-2f652c48df74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619401158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.619401158
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1003153363
Short name T493
Test name
Test status
Simulation time 4240781741 ps
CPU time 9.22 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 198260 kb
Host smart-67e84e01-636c-402c-8a2f-13a94623c9c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003153363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1003153363
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3229535651
Short name T489
Test name
Test status
Simulation time 24756461913 ps
CPU time 37.75 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 199640 kb
Host smart-61761141-4786-4eb1-bafe-5b59390cd00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229535651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3229535651
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1096187266
Short name T438
Test name
Test status
Simulation time 2666916921 ps
CPU time 1.4 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:22:09 PM PST 24
Peak memory 195008 kb
Host smart-3923891c-025e-4a24-ad65-21114fe2774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096187266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1096187266
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3496774672
Short name T782
Test name
Test status
Simulation time 6238074406 ps
CPU time 10.77 seconds
Started Feb 29 01:22:07 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 198268 kb
Host smart-1de3920d-8bfd-4c57-a821-d3d26fa255d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496774672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3496774672
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3417346307
Short name T644
Test name
Test status
Simulation time 241320872734 ps
CPU time 692.86 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:33:43 PM PST 24
Peak memory 199620 kb
Host smart-64e0e61b-83b4-4703-9025-935c20cc729b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417346307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3417346307
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1640070908
Short name T677
Test name
Test status
Simulation time 9192710459 ps
CPU time 5.25 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:13 PM PST 24
Peak memory 199468 kb
Host smart-4ef8e6a7-6ca5-4e98-8fee-55b10493939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640070908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1640070908
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3693592099
Short name T130
Test name
Test status
Simulation time 18324675934 ps
CPU time 25.77 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:22:36 PM PST 24
Peak memory 198428 kb
Host smart-3724683e-5e0f-4d75-a580-98ece4ea7bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693592099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3693592099
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1264098487
Short name T950
Test name
Test status
Simulation time 43179569 ps
CPU time 0.55 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 195040 kb
Host smart-4eed198f-599d-48d6-8ea4-c348a619825e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264098487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1264098487
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2986561198
Short name T824
Test name
Test status
Simulation time 283003880929 ps
CPU time 158.74 seconds
Started Feb 29 01:22:09 PM PST 24
Finished Feb 29 01:24:48 PM PST 24
Peak memory 199484 kb
Host smart-b3409dfc-abef-469d-b6e5-abbf3c0f2ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986561198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2986561198
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3149432717
Short name T837
Test name
Test status
Simulation time 11384811218 ps
CPU time 14.4 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:22 PM PST 24
Peak memory 199524 kb
Host smart-d31df147-da61-4bd3-9412-a260def92206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149432717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3149432717
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2071055681
Short name T327
Test name
Test status
Simulation time 53716316640 ps
CPU time 9.92 seconds
Started Feb 29 01:22:13 PM PST 24
Finished Feb 29 01:22:23 PM PST 24
Peak memory 198496 kb
Host smart-416a0f5c-f19f-4b62-9170-7d201a9381cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071055681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2071055681
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2799267247
Short name T952
Test name
Test status
Simulation time 30154275486 ps
CPU time 35.61 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 198704 kb
Host smart-f9023f55-627f-423d-872f-76562beef9df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799267247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2799267247
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.96949000
Short name T1090
Test name
Test status
Simulation time 99651824180 ps
CPU time 416.63 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:29:17 PM PST 24
Peak memory 199464 kb
Host smart-7d30bc98-2c4a-4a47-aab4-ce50e8bb35ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96949000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.96949000
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2213736799
Short name T898
Test name
Test status
Simulation time 10213106366 ps
CPU time 6.24 seconds
Started Feb 29 01:22:24 PM PST 24
Finished Feb 29 01:22:30 PM PST 24
Peak memory 198028 kb
Host smart-a8afc46b-9501-4a8b-bbeb-25a213b1f375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213736799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2213736799
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1619471946
Short name T619
Test name
Test status
Simulation time 197147778169 ps
CPU time 104.78 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:24:04 PM PST 24
Peak memory 208216 kb
Host smart-a6ab68e7-c481-4a9d-982c-35d68464389a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619471946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1619471946
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.94605342
Short name T880
Test name
Test status
Simulation time 18680041636 ps
CPU time 48.43 seconds
Started Feb 29 01:22:18 PM PST 24
Finished Feb 29 01:23:07 PM PST 24
Peak memory 199556 kb
Host smart-3bb2e450-6f3f-4210-8ffd-1b910232c7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94605342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.94605342
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3519345121
Short name T781
Test name
Test status
Simulation time 2701282867 ps
CPU time 5.03 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:13 PM PST 24
Peak memory 198128 kb
Host smart-f6184c75-6456-492f-97cd-65b80f8656eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519345121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3519345121
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2733895184
Short name T504
Test name
Test status
Simulation time 3303330686 ps
CPU time 3.24 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:23 PM PST 24
Peak memory 195124 kb
Host smart-1b12a74d-29ea-4b67-992e-a7e09ffe3d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733895184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2733895184
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2245635316
Short name T909
Test name
Test status
Simulation time 123537508 ps
CPU time 1.19 seconds
Started Feb 29 01:22:10 PM PST 24
Finished Feb 29 01:22:11 PM PST 24
Peak memory 198396 kb
Host smart-9666971e-f5cd-4254-9036-5168e1bf62a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245635316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2245635316
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.348476315
Short name T580
Test name
Test status
Simulation time 498355940189 ps
CPU time 51.18 seconds
Started Feb 29 01:22:27 PM PST 24
Finished Feb 29 01:23:19 PM PST 24
Peak memory 199796 kb
Host smart-43a754ff-2c60-45da-ba0f-2aefb2caf526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348476315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.348476315
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2457528373
Short name T526
Test name
Test status
Simulation time 739394865 ps
CPU time 2.91 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 198052 kb
Host smart-17560aaf-2578-4a85-a303-bd4d9540d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457528373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2457528373
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.797893603
Short name T5
Test name
Test status
Simulation time 15511662184 ps
CPU time 24.63 seconds
Started Feb 29 01:22:08 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 196436 kb
Host smart-b254df85-94aa-40b2-b539-dceac2c8c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797893603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.797893603
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2759267174
Short name T793
Test name
Test status
Simulation time 39015734 ps
CPU time 0.55 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 195032 kb
Host smart-ef094478-5e7a-4a43-bd77-18516c680d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759267174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2759267174
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.20446213
Short name T734
Test name
Test status
Simulation time 92563250095 ps
CPU time 133.12 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:24:32 PM PST 24
Peak memory 199876 kb
Host smart-c414aadb-9db5-4dd3-9237-2f39afc8b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20446213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.20446213
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2851049412
Short name T306
Test name
Test status
Simulation time 83730254751 ps
CPU time 37.78 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:23:12 PM PST 24
Peak memory 199612 kb
Host smart-f0a4a460-75b0-4cf5-a2de-04061d122769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851049412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2851049412
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.618662396
Short name T1039
Test name
Test status
Simulation time 19508893929 ps
CPU time 10.58 seconds
Started Feb 29 01:22:18 PM PST 24
Finished Feb 29 01:22:29 PM PST 24
Peak memory 195120 kb
Host smart-c36bbacf-eba5-4e6d-9979-05a759dfd4ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618662396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.618662396
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_loopback.62418752
Short name T847
Test name
Test status
Simulation time 2051856371 ps
CPU time 2.49 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:22 PM PST 24
Peak memory 198276 kb
Host smart-21cdbf1d-e3aa-420a-9488-613dc8d1e6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62418752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.62418752
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1218084535
Short name T555
Test name
Test status
Simulation time 170988126236 ps
CPU time 84.16 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:23:46 PM PST 24
Peak memory 199740 kb
Host smart-4bcd40eb-d2bd-4763-8e9b-cc056d460ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218084535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1218084535
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3790976746
Short name T809
Test name
Test status
Simulation time 13130171182 ps
CPU time 137.25 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:24:52 PM PST 24
Peak memory 199628 kb
Host smart-c5ada15a-71eb-45cf-b715-fc508c5b4b03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790976746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3790976746
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4284181466
Short name T932
Test name
Test status
Simulation time 2891203070 ps
CPU time 24.74 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:47 PM PST 24
Peak memory 198196 kb
Host smart-872d810e-08f2-4217-b677-54dda5f5e53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284181466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4284181466
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2970549831
Short name T396
Test name
Test status
Simulation time 41123592502 ps
CPU time 32.7 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:22:53 PM PST 24
Peak memory 199556 kb
Host smart-c56b24f6-834b-42e3-8bfa-c4426587bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970549831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2970549831
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3047808781
Short name T435
Test name
Test status
Simulation time 4051762642 ps
CPU time 2.67 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 195252 kb
Host smart-8773eae9-58df-4c39-857b-852c56b22ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047808781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3047808781
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1635695102
Short name T970
Test name
Test status
Simulation time 758883832 ps
CPU time 1.45 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 197888 kb
Host smart-e40fb5d2-d806-49e8-b2ad-0f9a1937ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635695102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1635695102
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.96101501
Short name T601
Test name
Test status
Simulation time 734571404 ps
CPU time 2.18 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 197468 kb
Host smart-5f2a9721-8d7b-443a-b41b-b7098aea1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96101501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.96101501
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2137383707
Short name T543
Test name
Test status
Simulation time 17504949039 ps
CPU time 13.98 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:22:36 PM PST 24
Peak memory 197832 kb
Host smart-c5f7971d-b924-450f-928c-a0d1d2777b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137383707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2137383707
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2410357468
Short name T88
Test name
Test status
Simulation time 12852436 ps
CPU time 0.54 seconds
Started Feb 29 01:22:23 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 195020 kb
Host smart-9a4f7c31-fe53-4da0-9b50-b6c0d585feaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410357468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2410357468
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3525252515
Short name T412
Test name
Test status
Simulation time 26454558242 ps
CPU time 10.74 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:22:31 PM PST 24
Peak memory 199192 kb
Host smart-be594ffc-ef5c-4cb1-ae1f-ae4908230fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525252515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3525252515
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3273534839
Short name T965
Test name
Test status
Simulation time 29523823771 ps
CPU time 48.36 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:23:10 PM PST 24
Peak memory 198852 kb
Host smart-c0af3817-1d46-49dd-b146-c5731d5e70e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273534839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3273534839
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1718531356
Short name T989
Test name
Test status
Simulation time 206604659763 ps
CPU time 454.76 seconds
Started Feb 29 01:22:24 PM PST 24
Finished Feb 29 01:29:58 PM PST 24
Peak memory 199548 kb
Host smart-fd974f6a-6ce4-4ca5-b217-1129cfa07013
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718531356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1718531356
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.127380925
Short name T462
Test name
Test status
Simulation time 1471541440 ps
CPU time 3.46 seconds
Started Feb 29 01:22:16 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 198092 kb
Host smart-fbe95187-2701-4da2-a915-cab6013abd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127380925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.127380925
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1686976799
Short name T768
Test name
Test status
Simulation time 102271098210 ps
CPU time 134.75 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:24:35 PM PST 24
Peak memory 207864 kb
Host smart-4d491b9b-a866-4639-adb7-6419a8897773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686976799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1686976799
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2753788038
Short name T855
Test name
Test status
Simulation time 20300695145 ps
CPU time 273.96 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:27:08 PM PST 24
Peak memory 199440 kb
Host smart-e4372624-af7f-47c6-a8c9-25355b655de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753788038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2753788038
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1271732109
Short name T823
Test name
Test status
Simulation time 2720401839 ps
CPU time 27.89 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:23:02 PM PST 24
Peak memory 198088 kb
Host smart-a1857730-ba56-4973-bf2f-b9cdc21cbd8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271732109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1271732109
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2909093807
Short name T9
Test name
Test status
Simulation time 83045043242 ps
CPU time 23.07 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:45 PM PST 24
Peak memory 197488 kb
Host smart-3a0494a5-82b4-4506-b938-3b681e294835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909093807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2909093807
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1103576453
Short name T983
Test name
Test status
Simulation time 1527989462 ps
CPU time 2.92 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 194988 kb
Host smart-78d455f7-d767-46b9-a1a9-af23860deab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103576453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1103576453
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3886335696
Short name T1038
Test name
Test status
Simulation time 5874972324 ps
CPU time 11.22 seconds
Started Feb 29 01:22:20 PM PST 24
Finished Feb 29 01:22:32 PM PST 24
Peak memory 198888 kb
Host smart-0c41f244-9070-4cb0-a38d-1a623dbc6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886335696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3886335696
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3728505071
Short name T1086
Test name
Test status
Simulation time 38594487353 ps
CPU time 164.24 seconds
Started Feb 29 01:22:27 PM PST 24
Finished Feb 29 01:25:12 PM PST 24
Peak memory 199572 kb
Host smart-c8f6c2e8-ba54-4d9f-9dcd-fd0c75ca2c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728505071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3728505071
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.267965158
Short name T532
Test name
Test status
Simulation time 276801959 ps
CPU time 1.21 seconds
Started Feb 29 01:22:22 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 197400 kb
Host smart-efc224b9-e23b-4cda-9a9e-2884b5b73fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267965158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.267965158
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1815159406
Short name T109
Test name
Test status
Simulation time 80895272926 ps
CPU time 63.56 seconds
Started Feb 29 01:22:21 PM PST 24
Finished Feb 29 01:23:26 PM PST 24
Peak memory 199556 kb
Host smart-2aa2d024-f4b4-4239-8fa9-125de3fb0dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815159406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1815159406
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.647029030
Short name T743
Test name
Test status
Simulation time 117869226 ps
CPU time 0.59 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:22:34 PM PST 24
Peak memory 195020 kb
Host smart-dc12931a-1dfb-4cd4-80e9-5ea79a29cac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647029030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.647029030
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.9792910
Short name T488
Test name
Test status
Simulation time 132222845407 ps
CPU time 157.48 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:25:12 PM PST 24
Peak memory 199380 kb
Host smart-e5f4a7ea-30e7-46e1-9b46-3db0b125905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9792910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.9792910
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.568502691
Short name T661
Test name
Test status
Simulation time 59694508521 ps
CPU time 31.99 seconds
Started Feb 29 01:22:19 PM PST 24
Finished Feb 29 01:22:51 PM PST 24
Peak memory 199728 kb
Host smart-5211b0d7-bec9-48db-a622-cc4b3c2da8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568502691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.568502691
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2789848126
Short name T1060
Test name
Test status
Simulation time 327674830023 ps
CPU time 176.06 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:25:27 PM PST 24
Peak memory 199616 kb
Host smart-528e7ebe-5580-46b6-aa16-ad083a0eb029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789848126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2789848126
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2119405215
Short name T1083
Test name
Test status
Simulation time 1175520968626 ps
CPU time 141.63 seconds
Started Feb 29 01:22:32 PM PST 24
Finished Feb 29 01:24:54 PM PST 24
Peak memory 199560 kb
Host smart-e93c6f72-691e-484d-9919-79721b4c3b5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119405215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2119405215
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2305894749
Short name T509
Test name
Test status
Simulation time 61689202159 ps
CPU time 187.36 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:25:38 PM PST 24
Peak memory 199576 kb
Host smart-1659fae8-41d5-4de2-8ac2-a335859fa59c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305894749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2305894749
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1239609223
Short name T678
Test name
Test status
Simulation time 2752027327 ps
CPU time 3.07 seconds
Started Feb 29 01:22:35 PM PST 24
Finished Feb 29 01:22:38 PM PST 24
Peak memory 195184 kb
Host smart-a35c0303-f256-4d6a-ad35-9dfe2e4fab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239609223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1239609223
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2792176587
Short name T976
Test name
Test status
Simulation time 44679644576 ps
CPU time 19.18 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:22:51 PM PST 24
Peak memory 196412 kb
Host smart-b03e18ac-2f09-48e6-8fa7-4a3b52a8d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792176587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2792176587
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2560772978
Short name T256
Test name
Test status
Simulation time 10827986673 ps
CPU time 158.56 seconds
Started Feb 29 01:22:32 PM PST 24
Finished Feb 29 01:25:11 PM PST 24
Peak memory 199632 kb
Host smart-41c1d9cf-071a-4ec6-b76d-fcb3cc58482c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560772978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2560772978
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3944285944
Short name T614
Test name
Test status
Simulation time 127301527 ps
CPU time 0.91 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:22:32 PM PST 24
Peak memory 197240 kb
Host smart-06450d17-9598-4f98-bb7c-cc4faa5a7a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944285944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3944285944
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2084351128
Short name T689
Test name
Test status
Simulation time 26533872451 ps
CPU time 22.42 seconds
Started Feb 29 01:22:32 PM PST 24
Finished Feb 29 01:22:54 PM PST 24
Peak memory 199284 kb
Host smart-1f4b103c-cb13-4b41-9446-858b35c05fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084351128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2084351128
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1528890024
Short name T870
Test name
Test status
Simulation time 4340671040 ps
CPU time 2.15 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 195428 kb
Host smart-247674c9-41af-4046-8446-4f4b57dd6090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528890024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1528890024
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.425060724
Short name T759
Test name
Test status
Simulation time 690357984 ps
CPU time 2.89 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:22:37 PM PST 24
Peak memory 197664 kb
Host smart-e97e097c-bfa1-4093-8e88-364b653a182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425060724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.425060724
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1175185568
Short name T516
Test name
Test status
Simulation time 2018890025 ps
CPU time 2.19 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:22:35 PM PST 24
Peak memory 198032 kb
Host smart-a27ab019-7daa-452e-be6d-33d1825a7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175185568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1175185568
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.803335163
Short name T141
Test name
Test status
Simulation time 30552857903 ps
CPU time 49.69 seconds
Started Feb 29 01:22:23 PM PST 24
Finished Feb 29 01:23:13 PM PST 24
Peak memory 199540 kb
Host smart-3744a1c7-5712-49aa-9fd8-aba7ab80a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803335163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.803335163
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.361677046
Short name T887
Test name
Test status
Simulation time 18997898 ps
CPU time 0.53 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 194072 kb
Host smart-95905c24-4079-4bd6-86b5-77d324c239e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361677046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.361677046
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.4193827876
Short name T330
Test name
Test status
Simulation time 137866374695 ps
CPU time 180.39 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:25:32 PM PST 24
Peak memory 199628 kb
Host smart-5d3fa6d5-c35e-4426-b60a-ac60e15ca2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193827876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.4193827876
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3565119757
Short name T885
Test name
Test status
Simulation time 25685943129 ps
CPU time 38.56 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:23:11 PM PST 24
Peak memory 199644 kb
Host smart-ae84f52b-b2a7-4ccf-98a2-05c3a39fd4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565119757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3565119757
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.3624017446
Short name T695
Test name
Test status
Simulation time 1145409193892 ps
CPU time 537.6 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:31:31 PM PST 24
Peak memory 199316 kb
Host smart-dc5da1ae-9257-42d0-905b-a0747b626989
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624017446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3624017446
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3911567340
Short name T716
Test name
Test status
Simulation time 58466211722 ps
CPU time 102.46 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:24:14 PM PST 24
Peak memory 199584 kb
Host smart-65c8e32c-f46e-41af-a49d-a0de8daf9425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911567340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3911567340
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2975782898
Short name T498
Test name
Test status
Simulation time 8264434725 ps
CPU time 5.51 seconds
Started Feb 29 01:22:34 PM PST 24
Finished Feb 29 01:22:39 PM PST 24
Peak memory 199068 kb
Host smart-b30e861a-052a-4788-a298-0c938b5716e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975782898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2975782898
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4298682
Short name T496
Test name
Test status
Simulation time 23939796129 ps
CPU time 11.34 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:22:42 PM PST 24
Peak memory 194124 kb
Host smart-2d5403c2-e5f8-486d-b6f0-373886ac3bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4298682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4298682
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1043428857
Short name T832
Test name
Test status
Simulation time 8618241490 ps
CPU time 214.8 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:26:05 PM PST 24
Peak memory 199560 kb
Host smart-111f8d4a-130f-4443-867d-bdd2b22b6d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043428857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1043428857
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2612804445
Short name T725
Test name
Test status
Simulation time 2033188423 ps
CPU time 8.84 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:22:42 PM PST 24
Peak memory 197280 kb
Host smart-f8039b1d-7197-4001-b87a-3db796aafa06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612804445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2612804445
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1754871583
Short name T620
Test name
Test status
Simulation time 440425140788 ps
CPU time 92.23 seconds
Started Feb 29 01:22:33 PM PST 24
Finished Feb 29 01:24:06 PM PST 24
Peak memory 199536 kb
Host smart-fd2b3d4f-a80f-43c8-afe7-3e78615f89d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754871583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1754871583
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3975028946
Short name T425
Test name
Test status
Simulation time 41603705594 ps
CPU time 16.54 seconds
Started Feb 29 01:22:36 PM PST 24
Finished Feb 29 01:22:52 PM PST 24
Peak memory 195092 kb
Host smart-c921340b-b680-49d6-b747-59cea0d9e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975028946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3975028946
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2717813245
Short name T426
Test name
Test status
Simulation time 867392079 ps
CPU time 2.41 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:22:33 PM PST 24
Peak memory 198980 kb
Host smart-eb90c4f8-2009-4523-bae9-3fc42c1261f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717813245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2717813245
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4287798045
Short name T359
Test name
Test status
Simulation time 419546294099 ps
CPU time 265.43 seconds
Started Feb 29 01:22:31 PM PST 24
Finished Feb 29 01:26:57 PM PST 24
Peak memory 207940 kb
Host smart-bef41e33-54f3-4f23-881a-a73ffd76db74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287798045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4287798045
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2089393067
Short name T1081
Test name
Test status
Simulation time 1036015786 ps
CPU time 2.37 seconds
Started Feb 29 01:22:32 PM PST 24
Finished Feb 29 01:22:34 PM PST 24
Peak memory 198044 kb
Host smart-8f57616b-f59e-4615-aed3-01d100875079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089393067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2089393067
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1427792213
Short name T394
Test name
Test status
Simulation time 45607995824 ps
CPU time 18.48 seconds
Started Feb 29 01:22:30 PM PST 24
Finished Feb 29 01:22:49 PM PST 24
Peak memory 199396 kb
Host smart-d29096f6-d3fc-4625-ae0b-b7bcc2c2ab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427792213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1427792213
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1879239480
Short name T821
Test name
Test status
Simulation time 53262773 ps
CPU time 0.54 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 195028 kb
Host smart-54b4e5e9-585b-4eee-accd-58ed76eb9ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879239480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1879239480
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1747707642
Short name T946
Test name
Test status
Simulation time 82471827929 ps
CPU time 127.91 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:24:51 PM PST 24
Peak memory 199528 kb
Host smart-0f30a998-0aea-4429-8233-2a9d036bdc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747707642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1747707642
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3751428565
Short name T930
Test name
Test status
Simulation time 188954922654 ps
CPU time 223.08 seconds
Started Feb 29 01:22:46 PM PST 24
Finished Feb 29 01:26:29 PM PST 24
Peak memory 199572 kb
Host smart-73d98e96-5858-4f5a-8f26-189ab1d55bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751428565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3751428565
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3541741208
Short name T268
Test name
Test status
Simulation time 119155760097 ps
CPU time 16.07 seconds
Started Feb 29 01:22:41 PM PST 24
Finished Feb 29 01:22:57 PM PST 24
Peak memory 198824 kb
Host smart-4c728467-6657-4a92-8089-2b66667072cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541741208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3541741208
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3190730180
Short name T802
Test name
Test status
Simulation time 12532375704 ps
CPU time 11.77 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:22:54 PM PST 24
Peak memory 196240 kb
Host smart-4974614e-6823-460e-a5e3-3ea671ad8ec1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190730180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3190730180
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2313703465
Short name T1045
Test name
Test status
Simulation time 68024953371 ps
CPU time 213.13 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:26:17 PM PST 24
Peak memory 199520 kb
Host smart-81dc2d7c-e3d5-47fb-952e-1afe71fe813b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313703465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2313703465
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3218440283
Short name T494
Test name
Test status
Simulation time 5064864815 ps
CPU time 3.8 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 197848 kb
Host smart-a08805d0-d3d0-4557-bca6-0a5a1098b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218440283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3218440283
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4150671464
Short name T484
Test name
Test status
Simulation time 12480755947 ps
CPU time 2.5 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 194236 kb
Host smart-1053d12f-c364-472f-813b-fb64f2fbd2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150671464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4150671464
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3662393367
Short name T207
Test name
Test status
Simulation time 12277146865 ps
CPU time 149.74 seconds
Started Feb 29 01:22:40 PM PST 24
Finished Feb 29 01:25:10 PM PST 24
Peak memory 199556 kb
Host smart-50601c1d-df3b-4d73-9039-b7d18b9aae16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662393367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3662393367
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3202834563
Short name T538
Test name
Test status
Simulation time 1506557463 ps
CPU time 3.43 seconds
Started Feb 29 01:22:47 PM PST 24
Finished Feb 29 01:22:51 PM PST 24
Peak memory 197748 kb
Host smart-9f8a9c10-3b8b-42e0-b9f7-f16bd156a22b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202834563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3202834563
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1286952272
Short name T491
Test name
Test status
Simulation time 43955469419 ps
CPU time 18.55 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:23:01 PM PST 24
Peak memory 195308 kb
Host smart-23715d73-6a83-47ea-b9db-5560e60adb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286952272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1286952272
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.472707947
Short name T807
Test name
Test status
Simulation time 6200505749 ps
CPU time 13.04 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:22:55 PM PST 24
Peak memory 198936 kb
Host smart-57aca0a6-b9f5-4c13-ae58-de077488f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472707947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.472707947
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.639144590
Short name T690
Test name
Test status
Simulation time 98930301951 ps
CPU time 152.84 seconds
Started Feb 29 01:22:47 PM PST 24
Finished Feb 29 01:25:20 PM PST 24
Peak memory 215216 kb
Host smart-588c723f-52e9-4eb4-9a10-afeecf4ddc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639144590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.639144590
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3622612074
Short name T796
Test name
Test status
Simulation time 7258104864 ps
CPU time 21.75 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 199052 kb
Host smart-287b2e1a-c23e-42d5-88fe-b7bf64e091b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622612074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3622612074
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3847146858
Short name T430
Test name
Test status
Simulation time 71533853194 ps
CPU time 102.16 seconds
Started Feb 29 01:22:44 PM PST 24
Finished Feb 29 01:24:26 PM PST 24
Peak memory 199560 kb
Host smart-3c47640a-a28d-48fc-b7fb-e1a80bcd8ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847146858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3847146858
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2268583120
Short name T463
Test name
Test status
Simulation time 15828831 ps
CPU time 0.57 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:22:44 PM PST 24
Peak memory 195016 kb
Host smart-251acdad-a7cc-422a-81ab-f9fecded156a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268583120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2268583120
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2905402391
Short name T344
Test name
Test status
Simulation time 210121721107 ps
CPU time 172.14 seconds
Started Feb 29 01:22:41 PM PST 24
Finished Feb 29 01:25:34 PM PST 24
Peak memory 199552 kb
Host smart-e5ff0503-7e5b-4ae8-a16e-4d8281df03c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905402391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2905402391
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1251445200
Short name T906
Test name
Test status
Simulation time 269827441972 ps
CPU time 341.79 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:28:27 PM PST 24
Peak memory 199516 kb
Host smart-e3f26efa-dd08-4aad-8508-bca9134144ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251445200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1251445200
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2605271024
Short name T196
Test name
Test status
Simulation time 183175387947 ps
CPU time 59.02 seconds
Started Feb 29 01:22:52 PM PST 24
Finished Feb 29 01:23:51 PM PST 24
Peak memory 199540 kb
Host smart-86e38226-3504-436b-a8ab-d96eafab43bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605271024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2605271024
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_loopback.2142178583
Short name T790
Test name
Test status
Simulation time 1251140352 ps
CPU time 1.39 seconds
Started Feb 29 01:22:47 PM PST 24
Finished Feb 29 01:22:48 PM PST 24
Peak memory 195184 kb
Host smart-8fac7954-fd7e-41c2-825d-febc764107f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142178583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2142178583
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2213923098
Short name T656
Test name
Test status
Simulation time 124142437390 ps
CPU time 42.34 seconds
Started Feb 29 01:22:46 PM PST 24
Finished Feb 29 01:23:28 PM PST 24
Peak memory 196476 kb
Host smart-fdd80dff-7c64-47df-968f-bde7d53fd6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213923098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2213923098
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2311751052
Short name T973
Test name
Test status
Simulation time 16544599422 ps
CPU time 780.8 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:35:46 PM PST 24
Peak memory 199552 kb
Host smart-2acaca00-bf17-4ac5-ab7a-bacff3393b67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311751052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2311751052
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1084212970
Short name T742
Test name
Test status
Simulation time 905860492 ps
CPU time 9.19 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:22:55 PM PST 24
Peak memory 197768 kb
Host smart-51ca678d-7638-46fb-8567-8fabc674426d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084212970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1084212970
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1815004963
Short name T361
Test name
Test status
Simulation time 33142765679 ps
CPU time 46.12 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:23:31 PM PST 24
Peak memory 199572 kb
Host smart-14558e91-d777-4fd8-8199-896840413289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815004963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1815004963
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1989942591
Short name T897
Test name
Test status
Simulation time 4177187735 ps
CPU time 3.94 seconds
Started Feb 29 01:22:41 PM PST 24
Finished Feb 29 01:22:45 PM PST 24
Peak memory 195308 kb
Host smart-2fe0c207-dca5-47bc-9662-5eea6a0c78db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989942591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1989942591
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4167976671
Short name T405
Test name
Test status
Simulation time 5389695863 ps
CPU time 32.33 seconds
Started Feb 29 01:22:43 PM PST 24
Finished Feb 29 01:23:16 PM PST 24
Peak memory 199484 kb
Host smart-2d642f60-f266-4254-b7f2-a9d7bd91b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167976671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4167976671
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3977572011
Short name T710
Test name
Test status
Simulation time 953382276011 ps
CPU time 514.71 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:31:20 PM PST 24
Peak memory 199664 kb
Host smart-9597eb92-3333-4bd2-acae-7fa0dbd88e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977572011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3977572011
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1190714220
Short name T467
Test name
Test status
Simulation time 1035171789 ps
CPU time 2.13 seconds
Started Feb 29 01:22:41 PM PST 24
Finished Feb 29 01:22:43 PM PST 24
Peak memory 198552 kb
Host smart-c19f355c-4573-40a2-8901-52e901efe50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190714220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1190714220
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.573133071
Short name T865
Test name
Test status
Simulation time 63169085543 ps
CPU time 21.76 seconds
Started Feb 29 01:22:42 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 199768 kb
Host smart-d961e866-cb42-4972-806c-48dffc76c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573133071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.573133071
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2011409514
Short name T1091
Test name
Test status
Simulation time 13073549 ps
CPU time 0.56 seconds
Started Feb 29 01:22:56 PM PST 24
Finished Feb 29 01:22:58 PM PST 24
Peak memory 194928 kb
Host smart-1f9e65a0-d3fd-4577-b9b1-071730a26906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011409514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2011409514
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2180368529
Short name T1031
Test name
Test status
Simulation time 107903289310 ps
CPU time 62.01 seconds
Started Feb 29 01:22:44 PM PST 24
Finished Feb 29 01:23:46 PM PST 24
Peak memory 199540 kb
Host smart-e19a6b5b-4520-4b2b-8c4e-e1464a91fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180368529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2180368529
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.13900705
Short name T222
Test name
Test status
Simulation time 21189454532 ps
CPU time 35.3 seconds
Started Feb 29 01:22:57 PM PST 24
Finished Feb 29 01:23:33 PM PST 24
Peak memory 199620 kb
Host smart-594a7145-5833-419a-8da0-919ce7826adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13900705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.13900705
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.627638007
Short name T1003
Test name
Test status
Simulation time 51092345905 ps
CPU time 85.21 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:24:24 PM PST 24
Peak memory 199508 kb
Host smart-971c9b23-22ce-422b-a32d-1232494c5750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627638007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.627638007
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2047423549
Short name T444
Test name
Test status
Simulation time 220006191510 ps
CPU time 365.44 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:29:05 PM PST 24
Peak memory 199548 kb
Host smart-68e495bc-3b0e-4fc3-b91a-c1dde28f3e7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047423549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2047423549
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3163365019
Short name T615
Test name
Test status
Simulation time 100961138642 ps
CPU time 229.82 seconds
Started Feb 29 01:22:56 PM PST 24
Finished Feb 29 01:26:47 PM PST 24
Peak memory 199588 kb
Host smart-c4eeac6c-c392-4f58-953d-6dd9d02a615b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163365019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3163365019
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1916383221
Short name T90
Test name
Test status
Simulation time 909862662 ps
CPU time 1.95 seconds
Started Feb 29 01:22:55 PM PST 24
Finished Feb 29 01:22:57 PM PST 24
Peak memory 194952 kb
Host smart-16689af3-0554-4e9b-b95c-2ab382b41565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916383221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1916383221
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.269419160
Short name T165
Test name
Test status
Simulation time 24055038072 ps
CPU time 40.61 seconds
Started Feb 29 01:22:57 PM PST 24
Finished Feb 29 01:23:38 PM PST 24
Peak memory 196672 kb
Host smart-bbdae743-e83f-46cd-a31e-2b29292cb55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269419160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.269419160
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2974526255
Short name T810
Test name
Test status
Simulation time 11453479999 ps
CPU time 321.33 seconds
Started Feb 29 01:22:56 PM PST 24
Finished Feb 29 01:28:17 PM PST 24
Peak memory 199532 kb
Host smart-3295859f-5ca4-4fbc-a5b3-2871c769db3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974526255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2974526255
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2725134617
Short name T530
Test name
Test status
Simulation time 4077639928 ps
CPU time 32.56 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:23:31 PM PST 24
Peak memory 198316 kb
Host smart-67d190ab-902c-4f1c-b29b-06650709bad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725134617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2725134617
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4010466665
Short name T547
Test name
Test status
Simulation time 34281131388 ps
CPU time 24.58 seconds
Started Feb 29 01:23:00 PM PST 24
Finished Feb 29 01:23:25 PM PST 24
Peak memory 198572 kb
Host smart-cd100bc3-4f1c-4ee7-9a36-732dadaa321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010466665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4010466665
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2131288248
Short name T93
Test name
Test status
Simulation time 7214100918 ps
CPU time 2.48 seconds
Started Feb 29 01:22:56 PM PST 24
Finished Feb 29 01:22:59 PM PST 24
Peak memory 195292 kb
Host smart-445644ea-e1ca-45f1-a891-a7fbb9b794b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131288248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2131288248
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2707288214
Short name T466
Test name
Test status
Simulation time 427579780 ps
CPU time 2.09 seconds
Started Feb 29 01:22:44 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 197348 kb
Host smart-aa654ee4-f335-431e-8d84-f9e979b3fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707288214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2707288214
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1264858444
Short name T1062
Test name
Test status
Simulation time 418004294973 ps
CPU time 197.02 seconds
Started Feb 29 01:22:57 PM PST 24
Finished Feb 29 01:26:14 PM PST 24
Peak memory 199584 kb
Host smart-8858618b-d3cd-4d7d-a487-8ef21f7ecd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264858444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1264858444
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1060287558
Short name T819
Test name
Test status
Simulation time 1146142341 ps
CPU time 1.56 seconds
Started Feb 29 01:22:56 PM PST 24
Finished Feb 29 01:22:59 PM PST 24
Peak memory 197844 kb
Host smart-2a33541b-85ae-4054-9eb7-64dcc3391aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060287558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1060287558
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2258010040
Short name T539
Test name
Test status
Simulation time 3199851655 ps
CPU time 2.78 seconds
Started Feb 29 01:22:45 PM PST 24
Finished Feb 29 01:22:47 PM PST 24
Peak memory 196564 kb
Host smart-60d10213-582b-4a23-85b1-2eee9a8ed249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258010040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2258010040
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.242044081
Short name T723
Test name
Test status
Simulation time 32786685 ps
CPU time 0.56 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:22:58 PM PST 24
Peak memory 194080 kb
Host smart-161ce2c4-b77b-4ddb-9342-51578ba662f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242044081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.242044081
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2701848521
Short name T804
Test name
Test status
Simulation time 144127461499 ps
CPU time 35.15 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:23:34 PM PST 24
Peak memory 199612 kb
Host smart-8193e634-3127-4248-9dea-74fe8e9612a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701848521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2701848521
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3852219639
Short name T366
Test name
Test status
Simulation time 127947274524 ps
CPU time 200.2 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:26:19 PM PST 24
Peak memory 199616 kb
Host smart-a948301a-36a1-4c82-bf2a-2577858cd476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852219639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3852219639
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.372420394
Short name T613
Test name
Test status
Simulation time 120287693001 ps
CPU time 181.42 seconds
Started Feb 29 01:22:57 PM PST 24
Finished Feb 29 01:25:58 PM PST 24
Peak memory 199608 kb
Host smart-4a870c05-f32c-449c-ab78-21db80af6373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372420394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.372420394
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3811281368
Short name T827
Test name
Test status
Simulation time 441144161159 ps
CPU time 329.95 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:28:28 PM PST 24
Peak memory 199572 kb
Host smart-28e5a9c4-ef55-4c2b-9998-2687ab8d1e8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811281368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3811281368
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2799025716
Short name T41
Test name
Test status
Simulation time 281897215342 ps
CPU time 197.75 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:26:16 PM PST 24
Peak memory 199584 kb
Host smart-9a3a3901-ce63-4b84-ac0f-7c1aad667182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799025716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2799025716
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2412856440
Short name T1049
Test name
Test status
Simulation time 33122625715 ps
CPU time 29.33 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:23:28 PM PST 24
Peak memory 197960 kb
Host smart-0fcf0b30-4644-40f0-859c-d72f2611d306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412856440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2412856440
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.387333410
Short name T1011
Test name
Test status
Simulation time 17747820811 ps
CPU time 228.48 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:26:47 PM PST 24
Peak memory 199664 kb
Host smart-46f8468c-09e2-44e9-8d75-abcc2fef2898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387333410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.387333410
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3772133752
Short name T609
Test name
Test status
Simulation time 2215351454 ps
CPU time 7.26 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:23:05 PM PST 24
Peak memory 197852 kb
Host smart-baf75a7d-fb1a-40db-bd11-a3ba1ddb855e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772133752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3772133752
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1096177386
Short name T287
Test name
Test status
Simulation time 45754733053 ps
CPU time 77.26 seconds
Started Feb 29 01:22:55 PM PST 24
Finished Feb 29 01:24:12 PM PST 24
Peak memory 199592 kb
Host smart-b78fc2dc-8d98-4913-be40-b653431d564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096177386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1096177386
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.33233866
Short name T700
Test name
Test status
Simulation time 34927212503 ps
CPU time 56.88 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:23:54 PM PST 24
Peak memory 195384 kb
Host smart-81a54cdb-9201-43f4-9101-7e1943fcdb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33233866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.33233866
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.73949124
Short name T874
Test name
Test status
Simulation time 519699477 ps
CPU time 1.36 seconds
Started Feb 29 01:22:57 PM PST 24
Finished Feb 29 01:22:59 PM PST 24
Peak memory 197364 kb
Host smart-c2dd8065-8a1c-4a76-bee3-675ee72b135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73949124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.73949124
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1926522287
Short name T663
Test name
Test status
Simulation time 616259193129 ps
CPU time 248.4 seconds
Started Feb 29 01:22:55 PM PST 24
Finished Feb 29 01:27:04 PM PST 24
Peak memory 199512 kb
Host smart-682c7821-5c2f-42b2-af84-48c69e140795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926522287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1926522287
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.222356281
Short name T574
Test name
Test status
Simulation time 2394280521 ps
CPU time 1.88 seconds
Started Feb 29 01:22:59 PM PST 24
Finished Feb 29 01:23:01 PM PST 24
Peak memory 197908 kb
Host smart-1f072c40-8140-4b4f-89ba-f4f6078a18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222356281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.222356281
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1255699209
Short name T393
Test name
Test status
Simulation time 222964221685 ps
CPU time 68.22 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:24:06 PM PST 24
Peak memory 199552 kb
Host smart-6b5018fd-06c7-4fc6-a7a7-6aaa98c29029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255699209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1255699209
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.890685432
Short name T584
Test name
Test status
Simulation time 115368761 ps
CPU time 0.64 seconds
Started Feb 29 01:18:58 PM PST 24
Finished Feb 29 01:18:59 PM PST 24
Peak memory 194948 kb
Host smart-07661847-c1f1-46c4-ab54-925b5e86157a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890685432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.890685432
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3848704014
Short name T943
Test name
Test status
Simulation time 68298547306 ps
CPU time 71.22 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:20:04 PM PST 24
Peak memory 199396 kb
Host smart-f8f33713-8aa3-4e65-b089-39d77994f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848704014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3848704014
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.674192177
Short name T513
Test name
Test status
Simulation time 47456954158 ps
CPU time 78.63 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:20:15 PM PST 24
Peak memory 199364 kb
Host smart-e1b78340-9f13-4e60-96f2-6bb645e1ff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674192177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.674192177
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3148905021
Short name T836
Test name
Test status
Simulation time 81093417779 ps
CPU time 19.23 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:19:15 PM PST 24
Peak memory 199604 kb
Host smart-f10975cc-32e2-49ad-b0ff-d7c8d09b9a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148905021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3148905021
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.192231850
Short name T13
Test name
Test status
Simulation time 1886827856505 ps
CPU time 404.55 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:25:41 PM PST 24
Peak memory 199496 kb
Host smart-a24cb26d-4fb3-488e-b24c-1af76248271d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192231850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.192231850
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.797778177
Short name T397
Test name
Test status
Simulation time 99029875940 ps
CPU time 121.98 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:20:56 PM PST 24
Peak memory 199612 kb
Host smart-3aacb88e-4044-4da9-991d-9d37e6632480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797778177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.797778177
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1417213631
Short name T872
Test name
Test status
Simulation time 2415440984 ps
CPU time 5.05 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:19:01 PM PST 24
Peak memory 198576 kb
Host smart-189728b7-eda3-4474-af94-87bf2e3ff8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417213631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1417213631
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3739402146
Short name T521
Test name
Test status
Simulation time 24916035419 ps
CPU time 58.6 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:19:53 PM PST 24
Peak memory 198056 kb
Host smart-370472ec-490c-4a28-b027-71254938ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739402146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3739402146
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.864642033
Short name T908
Test name
Test status
Simulation time 6003831988 ps
CPU time 248.68 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:23:05 PM PST 24
Peak memory 199632 kb
Host smart-c1668ec9-67e4-42a2-8e02-1aab0d8cb669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864642033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.864642033
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2320543593
Short name T773
Test name
Test status
Simulation time 3566122979 ps
CPU time 32.34 seconds
Started Feb 29 01:18:57 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 197928 kb
Host smart-3f711238-96ad-47ea-9a3e-7a293bded4d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320543593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2320543593
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4085504684
Short name T508
Test name
Test status
Simulation time 68632910461 ps
CPU time 177.41 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:21:53 PM PST 24
Peak memory 199488 kb
Host smart-3ce819d4-2c7c-4067-a880-08d26fb68163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085504684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4085504684
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4202976457
Short name T600
Test name
Test status
Simulation time 4066329393 ps
CPU time 1.62 seconds
Started Feb 29 01:18:58 PM PST 24
Finished Feb 29 01:18:59 PM PST 24
Peak memory 195320 kb
Host smart-c8fdd883-257f-4a21-95c1-79367deb6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202976457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4202976457
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2352390171
Short name T758
Test name
Test status
Simulation time 297143374 ps
CPU time 1.05 seconds
Started Feb 29 01:18:54 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 197888 kb
Host smart-4886aa5a-13e5-42f1-85a5-0e52e08b76f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352390171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2352390171
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2886429713
Short name T962
Test name
Test status
Simulation time 228844321490 ps
CPU time 268.8 seconds
Started Feb 29 01:18:53 PM PST 24
Finished Feb 29 01:23:23 PM PST 24
Peak memory 199648 kb
Host smart-8be171be-76a6-43c8-8666-63e8b19ffe92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886429713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2886429713
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.96274281
Short name T534
Test name
Test status
Simulation time 9458188802 ps
CPU time 8.08 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:19:03 PM PST 24
Peak memory 199572 kb
Host smart-314ce0ba-8562-48d6-8eed-bfff4d8b9834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96274281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.96274281
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3464700080
Short name T408
Test name
Test status
Simulation time 33588421732 ps
CPU time 13.49 seconds
Started Feb 29 01:18:59 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 196488 kb
Host smart-09cf9446-e964-472b-aa7e-4a5130b3af94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464700080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3464700080
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3703331183
Short name T129
Test name
Test status
Simulation time 27010112683 ps
CPU time 43.29 seconds
Started Feb 29 01:22:58 PM PST 24
Finished Feb 29 01:23:41 PM PST 24
Peak memory 199548 kb
Host smart-6013d5b7-edd1-4076-9459-68e3499e315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703331183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3703331183
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2248820332
Short name T183
Test name
Test status
Simulation time 11402036234 ps
CPU time 11.79 seconds
Started Feb 29 01:23:09 PM PST 24
Finished Feb 29 01:23:22 PM PST 24
Peak memory 199088 kb
Host smart-2dc21aea-04f1-46be-95bf-09868ed99ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248820332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2248820332
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4068161516
Short name T195
Test name
Test status
Simulation time 154885042473 ps
CPU time 40.91 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:23:52 PM PST 24
Peak memory 199552 kb
Host smart-62db8f0e-aa2d-43b6-a2bc-41a9d6b544d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068161516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4068161516
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1030738868
Short name T156
Test name
Test status
Simulation time 7712155076 ps
CPU time 15.88 seconds
Started Feb 29 01:23:09 PM PST 24
Finished Feb 29 01:23:26 PM PST 24
Peak memory 199504 kb
Host smart-c0f327fd-abd5-4b80-adf0-6099b2a07acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030738868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1030738868
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1973154280
Short name T1094
Test name
Test status
Simulation time 106941497364 ps
CPU time 41.38 seconds
Started Feb 29 01:23:08 PM PST 24
Finished Feb 29 01:23:50 PM PST 24
Peak memory 199568 kb
Host smart-29c5ec42-110e-484b-bac2-38e630d282d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973154280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1973154280
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3553805121
Short name T212
Test name
Test status
Simulation time 134838547913 ps
CPU time 25.8 seconds
Started Feb 29 01:23:08 PM PST 24
Finished Feb 29 01:23:35 PM PST 24
Peak memory 199612 kb
Host smart-115c8a24-f7b0-47d8-b480-72609b38cad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553805121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3553805121
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2813248424
Short name T104
Test name
Test status
Simulation time 45479575435 ps
CPU time 38.24 seconds
Started Feb 29 01:23:09 PM PST 24
Finished Feb 29 01:23:47 PM PST 24
Peak memory 199764 kb
Host smart-c5a5a3bc-5eef-42f3-afc5-22b8414876e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813248424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2813248424
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.718554735
Short name T31
Test name
Test status
Simulation time 113371920551 ps
CPU time 324.67 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:28:36 PM PST 24
Peak memory 216260 kb
Host smart-5d0965e0-7a1e-4c67-b38a-65c52e12c9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718554735 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.718554735
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4181403080
Short name T814
Test name
Test status
Simulation time 25631944382 ps
CPU time 82.08 seconds
Started Feb 29 01:23:15 PM PST 24
Finished Feb 29 01:24:37 PM PST 24
Peak memory 199516 kb
Host smart-22bf85a8-db3b-4183-b7d6-9cb0b6351922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181403080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4181403080
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4090408538
Short name T1097
Test name
Test status
Simulation time 97453448675 ps
CPU time 155.09 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:25:46 PM PST 24
Peak memory 199540 kb
Host smart-1331c799-38e4-4c16-8898-d2c2d4f46732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090408538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4090408538
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1256230674
Short name T193
Test name
Test status
Simulation time 17925033178 ps
CPU time 15.01 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:23:26 PM PST 24
Peak memory 199648 kb
Host smart-c241c353-e243-419e-9eae-59b3f412b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256230674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1256230674
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1994504616
Short name T567
Test name
Test status
Simulation time 38273803 ps
CPU time 0.54 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 195024 kb
Host smart-42832174-469a-4cef-bb2e-f698824fa1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994504616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1994504616
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.429214142
Short name T627
Test name
Test status
Simulation time 70825120684 ps
CPU time 29.08 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:19:25 PM PST 24
Peak memory 199556 kb
Host smart-8b3951d6-dcb7-4f4a-b18f-d82e28adfa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429214142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.429214142
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4023395490
Short name T910
Test name
Test status
Simulation time 150102513996 ps
CPU time 46.39 seconds
Started Feb 29 01:19:14 PM PST 24
Finished Feb 29 01:20:01 PM PST 24
Peak memory 199564 kb
Host smart-2b2ba092-deab-448d-90a1-6afaa0f8028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023395490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4023395490
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1801626877
Short name T137
Test name
Test status
Simulation time 150293544807 ps
CPU time 21.29 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 199532 kb
Host smart-8213046e-0720-4a0f-8744-c1df9835d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801626877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1801626877
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.900480264
Short name T518
Test name
Test status
Simulation time 182188256837 ps
CPU time 287.72 seconds
Started Feb 29 01:19:08 PM PST 24
Finished Feb 29 01:23:57 PM PST 24
Peak memory 199536 kb
Host smart-691ac24a-9d28-4133-994e-db5fb7244774
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900480264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.900480264
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3805675759
Short name T1099
Test name
Test status
Simulation time 35955291768 ps
CPU time 81.65 seconds
Started Feb 29 01:19:06 PM PST 24
Finished Feb 29 01:20:28 PM PST 24
Peak memory 199776 kb
Host smart-379d517e-5379-4949-af5a-82f25ac5af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805675759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3805675759
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3381509690
Short name T907
Test name
Test status
Simulation time 20747120740 ps
CPU time 243.17 seconds
Started Feb 29 01:19:11 PM PST 24
Finished Feb 29 01:23:14 PM PST 24
Peak memory 199556 kb
Host smart-5ce6e37a-6385-41f8-b387-b0934a1e3fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381509690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3381509690
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3525327046
Short name T318
Test name
Test status
Simulation time 42875275401 ps
CPU time 33.67 seconds
Started Feb 29 01:19:11 PM PST 24
Finished Feb 29 01:19:44 PM PST 24
Peak memory 199616 kb
Host smart-763c9837-cda9-4f33-b9d1-076226ddbba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525327046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3525327046
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.186253802
Short name T34
Test name
Test status
Simulation time 557177911 ps
CPU time 1.07 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:11 PM PST 24
Peak memory 194860 kb
Host smart-209f8640-e954-45e7-8b58-2ef617f0f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186253802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.186253802
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2002607165
Short name T400
Test name
Test status
Simulation time 866394357 ps
CPU time 1.86 seconds
Started Feb 29 01:18:55 PM PST 24
Finished Feb 29 01:18:58 PM PST 24
Peak memory 198680 kb
Host smart-b9b1df53-6f6e-41c6-ba46-afbd5b002144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002607165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2002607165
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1571862172
Short name T27
Test name
Test status
Simulation time 116158083043 ps
CPU time 346.56 seconds
Started Feb 29 01:19:08 PM PST 24
Finished Feb 29 01:24:56 PM PST 24
Peak memory 216572 kb
Host smart-b5333cc1-4a48-431a-8a8f-9866159ebc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571862172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1571862172
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2787681022
Short name T19
Test name
Test status
Simulation time 1220413566 ps
CPU time 1.51 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 197216 kb
Host smart-bba95b8d-d339-48d5-b607-7a50fb08cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787681022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2787681022
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1485545882
Short name T131
Test name
Test status
Simulation time 4304056039 ps
CPU time 6.98 seconds
Started Feb 29 01:18:56 PM PST 24
Finished Feb 29 01:19:03 PM PST 24
Peak memory 195284 kb
Host smart-d9159766-06bd-4cd1-ae50-d47fb6f48fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485545882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1485545882
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3307136531
Short name T1068
Test name
Test status
Simulation time 121418364060 ps
CPU time 45.39 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:23:58 PM PST 24
Peak memory 199124 kb
Host smart-f5382649-735a-41bc-ba3a-f007e270f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307136531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3307136531
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4262212658
Short name T1095
Test name
Test status
Simulation time 193503690204 ps
CPU time 76.08 seconds
Started Feb 29 01:23:09 PM PST 24
Finished Feb 29 01:24:26 PM PST 24
Peak memory 199572 kb
Host smart-455bff55-5362-4c11-a4dd-38d037475993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262212658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4262212658
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3659108395
Short name T164
Test name
Test status
Simulation time 20294260728 ps
CPU time 21.17 seconds
Started Feb 29 01:23:07 PM PST 24
Finished Feb 29 01:23:29 PM PST 24
Peak memory 199768 kb
Host smart-57e6a991-b71d-4c71-b7a4-05468b86e7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659108395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3659108395
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4013469553
Short name T255
Test name
Test status
Simulation time 73520671884 ps
CPU time 117.11 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:25:09 PM PST 24
Peak memory 199584 kb
Host smart-7bf6b627-b660-492a-ab9d-999004f7b072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013469553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4013469553
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.936911211
Short name T100
Test name
Test status
Simulation time 38814002568 ps
CPU time 193.87 seconds
Started Feb 29 01:23:08 PM PST 24
Finished Feb 29 01:26:23 PM PST 24
Peak memory 216132 kb
Host smart-b14ace4b-585a-4bf1-b8a4-ab01629feb30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936911211 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.936911211
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3288212936
Short name T844
Test name
Test status
Simulation time 32472229135 ps
CPU time 76.31 seconds
Started Feb 29 01:23:16 PM PST 24
Finished Feb 29 01:24:32 PM PST 24
Peak memory 199608 kb
Host smart-e82e2804-208e-49b2-8cf1-cb38621609d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288212936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3288212936
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.691323194
Short name T99
Test name
Test status
Simulation time 263527949616 ps
CPU time 805.87 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:36:38 PM PST 24
Peak memory 216320 kb
Host smart-52c72eb8-158c-4395-b7c5-bb447f50930e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691323194 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.691323194
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2738109631
Short name T846
Test name
Test status
Simulation time 66325606786 ps
CPU time 27.89 seconds
Started Feb 29 01:23:10 PM PST 24
Finished Feb 29 01:23:39 PM PST 24
Peak memory 199540 kb
Host smart-3093d47d-2fe1-4cc9-9491-ce3e83b36b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738109631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2738109631
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.731159810
Short name T274
Test name
Test status
Simulation time 19218939485 ps
CPU time 15.65 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:23:27 PM PST 24
Peak memory 199552 kb
Host smart-3d3879d9-7a2f-4722-b6aa-71d6ed6b6f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731159810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.731159810
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2610148713
Short name T95
Test name
Test status
Simulation time 100398214364 ps
CPU time 83.19 seconds
Started Feb 29 01:23:10 PM PST 24
Finished Feb 29 01:24:34 PM PST 24
Peak memory 199348 kb
Host smart-e2b3943a-f194-4314-acec-622a3e08e23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610148713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2610148713
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3836069336
Short name T185
Test name
Test status
Simulation time 15483056847 ps
CPU time 31.56 seconds
Started Feb 29 01:23:12 PM PST 24
Finished Feb 29 01:23:44 PM PST 24
Peak memory 199616 kb
Host smart-e883f078-7f7e-4bbe-baf9-0ebcaecad5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836069336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3836069336
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3677988726
Short name T730
Test name
Test status
Simulation time 28189878 ps
CPU time 0.59 seconds
Started Feb 29 01:19:11 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 194968 kb
Host smart-ab777c1f-97cf-45b6-a0a6-016941ecb0b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677988726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3677988726
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1924745180
Short name T778
Test name
Test status
Simulation time 68479389814 ps
CPU time 34.09 seconds
Started Feb 29 01:19:08 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 199600 kb
Host smart-1ed5adbb-7e52-4f1b-b376-271757c18913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924745180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1924745180
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3366252701
Short name T271
Test name
Test status
Simulation time 19642370618 ps
CPU time 15.51 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:19:26 PM PST 24
Peak memory 198352 kb
Host smart-d0c55e70-9c96-4405-a363-15e356d0097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366252701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3366252701
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.985628512
Short name T203
Test name
Test status
Simulation time 53604043832 ps
CPU time 95.37 seconds
Started Feb 29 01:19:14 PM PST 24
Finished Feb 29 01:20:50 PM PST 24
Peak memory 199484 kb
Host smart-5b7524a9-9f45-4108-afd2-031eebd68fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985628512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.985628512
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2092266795
Short name T828
Test name
Test status
Simulation time 268392591417 ps
CPU time 150.04 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:21:40 PM PST 24
Peak memory 199384 kb
Host smart-dc75f6a3-1d4a-4b55-b7e8-0221c737e3a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092266795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2092266795
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3267254956
Short name T1078
Test name
Test status
Simulation time 112357777983 ps
CPU time 818.1 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:32:49 PM PST 24
Peak memory 199632 kb
Host smart-6d84418d-0b4d-47f1-a111-d011daf0f2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267254956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3267254956
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.617904649
Short name T788
Test name
Test status
Simulation time 13235627213 ps
CPU time 20.65 seconds
Started Feb 29 01:19:07 PM PST 24
Finished Feb 29 01:19:28 PM PST 24
Peak memory 197976 kb
Host smart-f6493ac1-9fcb-48d4-9e9f-f589b5e4d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617904649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.617904649
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2252797488
Short name T803
Test name
Test status
Simulation time 30944446893 ps
CPU time 12.97 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:19:24 PM PST 24
Peak memory 196644 kb
Host smart-e3ceb312-f5b3-4e1f-ade7-f83793fd093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252797488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2252797488
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3464313800
Short name T37
Test name
Test status
Simulation time 15813834308 ps
CPU time 460.9 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:26:51 PM PST 24
Peak memory 199612 kb
Host smart-1ba1720e-c55c-497d-a75d-73d80d68803c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464313800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3464313800
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2265755125
Short name T487
Test name
Test status
Simulation time 3696198983 ps
CPU time 28.23 seconds
Started Feb 29 01:19:08 PM PST 24
Finished Feb 29 01:19:36 PM PST 24
Peak memory 198144 kb
Host smart-12eb7464-e8f6-4ee5-8734-aedc99286f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265755125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2265755125
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4127135829
Short name T289
Test name
Test status
Simulation time 104849158850 ps
CPU time 141.54 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:21:31 PM PST 24
Peak memory 199536 kb
Host smart-1a4cc1e4-dcfc-4307-a96f-315abe40333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127135829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4127135829
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.825135282
Short name T573
Test name
Test status
Simulation time 76841786502 ps
CPU time 123.25 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:21:14 PM PST 24
Peak memory 195004 kb
Host smart-7a6243d6-e543-4f12-be46-435d71bf72b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825135282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.825135282
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3295051455
Short name T1014
Test name
Test status
Simulation time 512333687 ps
CPU time 1.21 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 199408 kb
Host smart-294758b0-4f66-41fa-9fed-6c6060654495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295051455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3295051455
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.205806945
Short name T4
Test name
Test status
Simulation time 209711036985 ps
CPU time 1353.84 seconds
Started Feb 29 01:19:07 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 199552 kb
Host smart-a62a0380-7568-495b-8728-af913f94101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205806945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.205806945
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.56309109
Short name T428
Test name
Test status
Simulation time 1460645027 ps
CPU time 2.18 seconds
Started Feb 29 01:19:07 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 197748 kb
Host smart-861f6738-c713-42ff-9c23-bba0234acf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56309109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.56309109
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1914790162
Short name T681
Test name
Test status
Simulation time 35508949764 ps
CPU time 52.66 seconds
Started Feb 29 01:19:08 PM PST 24
Finished Feb 29 01:20:01 PM PST 24
Peak memory 199504 kb
Host smart-c1ba78bb-5e1d-4b07-bb03-44b085794a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914790162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1914790162
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3072255039
Short name T381
Test name
Test status
Simulation time 34695886153 ps
CPU time 15.38 seconds
Started Feb 29 01:23:09 PM PST 24
Finished Feb 29 01:23:24 PM PST 24
Peak memory 199088 kb
Host smart-8dd776bb-eab3-4fe3-a730-8b83c31323e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072255039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3072255039
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3660744613
Short name T153
Test name
Test status
Simulation time 80174918109 ps
CPU time 194.72 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 199560 kb
Host smart-971ba863-7bfd-4bc2-88de-4ac3559ed8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660744613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3660744613
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1265094822
Short name T240
Test name
Test status
Simulation time 19918239334 ps
CPU time 8.72 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:23:20 PM PST 24
Peak memory 198852 kb
Host smart-4a8a302e-9412-4b3f-af4a-fd343b871a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265094822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1265094822
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3337181683
Short name T811
Test name
Test status
Simulation time 123666803107 ps
CPU time 203.2 seconds
Started Feb 29 01:23:16 PM PST 24
Finished Feb 29 01:26:40 PM PST 24
Peak memory 199512 kb
Host smart-712135cb-b0f8-4e72-9170-b5f2a67ed8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337181683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3337181683
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1006200770
Short name T772
Test name
Test status
Simulation time 76103348531 ps
CPU time 27.61 seconds
Started Feb 29 01:23:17 PM PST 24
Finished Feb 29 01:23:45 PM PST 24
Peak memory 199484 kb
Host smart-a30d5b86-d9c2-4ed5-a0d0-c1febc6c2168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006200770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1006200770
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.4122233999
Short name T895
Test name
Test status
Simulation time 88132174868 ps
CPU time 30.56 seconds
Started Feb 29 01:23:11 PM PST 24
Finished Feb 29 01:23:41 PM PST 24
Peak memory 199476 kb
Host smart-008b6171-9cfe-49bc-9031-f02153115b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122233999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.4122233999
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1773898208
Short name T120
Test name
Test status
Simulation time 114047284217 ps
CPU time 64.29 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:24:31 PM PST 24
Peak memory 199560 kb
Host smart-91a3ef7e-756d-4b21-91b1-74fdc94ca850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773898208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1773898208
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.186573833
Short name T52
Test name
Test status
Simulation time 180476141717 ps
CPU time 224.12 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:27:12 PM PST 24
Peak memory 216052 kb
Host smart-5b9933fd-2058-4c7e-8399-68b14a44ebdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186573833 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.186573833
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1573955814
Short name T253
Test name
Test status
Simulation time 68780489808 ps
CPU time 25.67 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:23:52 PM PST 24
Peak memory 199540 kb
Host smart-1187e33a-97e2-4f85-9168-4e63dedad333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573955814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1573955814
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1170476451
Short name T646
Test name
Test status
Simulation time 30889601201 ps
CPU time 44.79 seconds
Started Feb 29 01:23:30 PM PST 24
Finished Feb 29 01:24:15 PM PST 24
Peak memory 199124 kb
Host smart-74ac4576-3ace-451b-a0c2-19b278e4317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170476451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1170476451
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2038750809
Short name T736
Test name
Test status
Simulation time 24424443909 ps
CPU time 361.97 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:29:29 PM PST 24
Peak memory 215940 kb
Host smart-9325f997-f335-47f3-ae11-1e5646c927f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038750809 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2038750809
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1539698131
Short name T779
Test name
Test status
Simulation time 27608102 ps
CPU time 0.52 seconds
Started Feb 29 01:19:27 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 193924 kb
Host smart-ad9ca424-60d2-4bfb-998d-d87fe0778dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539698131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1539698131
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1086110841
Short name T228
Test name
Test status
Simulation time 19593985633 ps
CPU time 32.33 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 198772 kb
Host smart-759fb021-6b7e-4aa0-a9e4-eedee29d7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086110841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1086110841
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3392808813
Short name T996
Test name
Test status
Simulation time 36806339119 ps
CPU time 28.04 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:38 PM PST 24
Peak memory 199552 kb
Host smart-693ddf5c-b674-4e89-81a8-f6d8f2096446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392808813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3392808813
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3009416234
Short name T741
Test name
Test status
Simulation time 52088739819 ps
CPU time 83.96 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:20:34 PM PST 24
Peak memory 198408 kb
Host smart-94e07e3b-98e5-41f7-a9e7-107958328343
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009416234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3009416234
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1014309261
Short name T726
Test name
Test status
Simulation time 67483088124 ps
CPU time 371.14 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:25:22 PM PST 24
Peak memory 199500 kb
Host smart-63136db4-86de-494e-86b1-d95fd9c5675a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014309261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1014309261
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2305377375
Short name T875
Test name
Test status
Simulation time 7217017598 ps
CPU time 13.49 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 198164 kb
Host smart-55a70a65-82cf-499e-8111-0269ddee9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305377375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2305377375
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1904663466
Short name T980
Test name
Test status
Simulation time 131229146111 ps
CPU time 213 seconds
Started Feb 29 01:19:06 PM PST 24
Finished Feb 29 01:22:40 PM PST 24
Peak memory 199408 kb
Host smart-00c4ca74-fac7-41d6-9873-f7fdf35bff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904663466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1904663466
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3440357164
Short name T733
Test name
Test status
Simulation time 26850470972 ps
CPU time 1171.79 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:38:42 PM PST 24
Peak memory 199572 kb
Host smart-9fff3db3-5d95-45c9-8ac6-aeed4d3d88a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440357164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3440357164
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.894477443
Short name T873
Test name
Test status
Simulation time 3312428331 ps
CPU time 20.16 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:19:30 PM PST 24
Peak memory 198088 kb
Host smart-fd96dc2d-e24a-4d2a-a015-fc9729320a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894477443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.894477443
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3090215560
Short name T114
Test name
Test status
Simulation time 63277973600 ps
CPU time 146.93 seconds
Started Feb 29 01:19:09 PM PST 24
Finished Feb 29 01:21:37 PM PST 24
Peak memory 199420 kb
Host smart-56621719-4e39-4b63-9b53-949d329a2783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090215560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3090215560
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2530870969
Short name T618
Test name
Test status
Simulation time 4413610534 ps
CPU time 2.82 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:19:13 PM PST 24
Peak memory 195272 kb
Host smart-51500132-d29f-4cf3-a764-6cdae29fe0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530870969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2530870969
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.983746876
Short name T605
Test name
Test status
Simulation time 501202538 ps
CPU time 1.34 seconds
Started Feb 29 01:19:14 PM PST 24
Finished Feb 29 01:19:16 PM PST 24
Peak memory 197404 kb
Host smart-359c4d72-3133-4410-8dd1-b6e0aa0334f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983746876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.983746876
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.457613641
Short name T1025
Test name
Test status
Simulation time 571309404005 ps
CPU time 435.67 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 207620 kb
Host smart-8e0ed836-3263-47d4-a155-c379923a5146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457613641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.457613641
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2776968043
Short name T1016
Test name
Test status
Simulation time 7778544498 ps
CPU time 16.55 seconds
Started Feb 29 01:19:10 PM PST 24
Finished Feb 29 01:19:27 PM PST 24
Peak memory 199012 kb
Host smart-9fd7fda4-8a05-4b3e-9c4b-9c3bfc802397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776968043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2776968043
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2557532512
Short name T647
Test name
Test status
Simulation time 39205455671 ps
CPU time 14.42 seconds
Started Feb 29 01:19:07 PM PST 24
Finished Feb 29 01:19:22 PM PST 24
Peak memory 197600 kb
Host smart-d3ee3f91-6c67-4d79-b479-a0d9bb634d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557532512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2557532512
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1905899877
Short name T190
Test name
Test status
Simulation time 299795350395 ps
CPU time 114.52 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:25:21 PM PST 24
Peak memory 199548 kb
Host smart-5f33e67e-ef61-457c-a93a-6ff3b72b8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905899877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1905899877
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3563450516
Short name T1064
Test name
Test status
Simulation time 80981438448 ps
CPU time 122.76 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:25:31 PM PST 24
Peak memory 199548 kb
Host smart-0cfd047e-a65e-478f-8bb1-24e92904b0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563450516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3563450516
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2846858826
Short name T337
Test name
Test status
Simulation time 40430878809 ps
CPU time 61.83 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:24:30 PM PST 24
Peak memory 199488 kb
Host smart-33d7bcc9-68cf-406d-8984-4265a1841aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846858826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2846858826
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.638756076
Short name T604
Test name
Test status
Simulation time 10159284919 ps
CPU time 15.17 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:23:44 PM PST 24
Peak memory 199332 kb
Host smart-ebc35f83-749f-42a4-95cd-3f04e25e6f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638756076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.638756076
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1707965231
Short name T452
Test name
Test status
Simulation time 64888737284 ps
CPU time 668.89 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:34:36 PM PST 24
Peak memory 224696 kb
Host smart-86260f8f-76d3-41f2-a5ab-4c40c89c31fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707965231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1707965231
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3241283925
Short name T328
Test name
Test status
Simulation time 29641547585 ps
CPU time 56.52 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:24:25 PM PST 24
Peak memory 199484 kb
Host smart-a52bfa96-b752-4517-b532-4a7851ce1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241283925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3241283925
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.242617815
Short name T1005
Test name
Test status
Simulation time 13833063800 ps
CPU time 24.04 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:23:52 PM PST 24
Peak memory 199552 kb
Host smart-7d8e7114-8c22-4cc2-a7eb-580c4252ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242617815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.242617815
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.507924958
Short name T856
Test name
Test status
Simulation time 109010418677 ps
CPU time 175.37 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:26:24 PM PST 24
Peak memory 199600 kb
Host smart-ced388eb-a9f9-4b9a-b481-d08094c1c0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507924958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.507924958
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.712775066
Short name T132
Test name
Test status
Simulation time 16117588890 ps
CPU time 28.95 seconds
Started Feb 29 01:23:30 PM PST 24
Finished Feb 29 01:23:59 PM PST 24
Peak memory 199548 kb
Host smart-c847569d-228f-415f-a1b0-1dfc1a612965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712775066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.712775066
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3064001668
Short name T28
Test name
Test status
Simulation time 57158939506 ps
CPU time 588.87 seconds
Started Feb 29 01:23:29 PM PST 24
Finished Feb 29 01:33:19 PM PST 24
Peak memory 226304 kb
Host smart-f7da1927-328a-4b56-8ee7-c2b3cd313c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064001668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3064001668
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1866716411
Short name T545
Test name
Test status
Simulation time 82821263880 ps
CPU time 144.83 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:25:53 PM PST 24
Peak memory 199292 kb
Host smart-1400443a-2e87-494e-8980-13a0f9a3f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866716411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1866716411
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.594367767
Short name T478
Test name
Test status
Simulation time 12710358 ps
CPU time 0.58 seconds
Started Feb 29 01:19:30 PM PST 24
Finished Feb 29 01:19:32 PM PST 24
Peak memory 194952 kb
Host smart-cd362449-35c2-4b47-b643-6ff42f8f5ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594367767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.594367767
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1471837078
Short name T236
Test name
Test status
Simulation time 136940946639 ps
CPU time 57.22 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:20:29 PM PST 24
Peak memory 199624 kb
Host smart-f370898e-2a08-401b-be13-c00cb995ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471837078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1471837078
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1048558798
Short name T981
Test name
Test status
Simulation time 123337578020 ps
CPU time 70.65 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:20:39 PM PST 24
Peak memory 199528 kb
Host smart-d4b1fba3-d805-464d-a929-e841895838c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048558798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1048558798
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.4073917587
Short name T860
Test name
Test status
Simulation time 481259430852 ps
CPU time 672.19 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:30:40 PM PST 24
Peak memory 199580 kb
Host smart-b5e7708c-4265-4b2a-934e-b9d8f8001a2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073917587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4073917587
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_loopback.3051471935
Short name T876
Test name
Test status
Simulation time 3754638028 ps
CPU time 16.57 seconds
Started Feb 29 01:19:25 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 198756 kb
Host smart-2f08e0fd-dd41-4c1f-b271-9f508d80f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051471935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3051471935
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.854310646
Short name T1054
Test name
Test status
Simulation time 2692266218 ps
CPU time 4.26 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:19:32 PM PST 24
Peak memory 194568 kb
Host smart-3535c533-311f-44e7-81ab-7c4251c67c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854310646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.854310646
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1852585799
Short name T680
Test name
Test status
Simulation time 11218706102 ps
CPU time 536.08 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:28:25 PM PST 24
Peak memory 199520 kb
Host smart-829db78a-da01-4f33-89e6-61c7e884784a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852585799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1852585799
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.51652538
Short name T660
Test name
Test status
Simulation time 3884205261 ps
CPU time 29.24 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:57 PM PST 24
Peak memory 197412 kb
Host smart-4fb2e1a5-def0-444a-a286-dc56cbf47cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51652538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.51652538
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.799295342
Short name T325
Test name
Test status
Simulation time 118332633175 ps
CPU time 78.57 seconds
Started Feb 29 01:19:31 PM PST 24
Finished Feb 29 01:20:50 PM PST 24
Peak memory 199776 kb
Host smart-79ddc36b-9fff-4faa-8131-d8696842d9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799295342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.799295342
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1305408164
Short name T763
Test name
Test status
Simulation time 441225291 ps
CPU time 1.37 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 194944 kb
Host smart-a9a199f8-0eec-4394-9217-3b77a167ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305408164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1305408164
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.543981218
Short name T575
Test name
Test status
Simulation time 11589498576 ps
CPU time 28.99 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:19:56 PM PST 24
Peak memory 199656 kb
Host smart-8162653f-9af5-4668-a332-13e868280a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543981218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.543981218
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3283708084
Short name T717
Test name
Test status
Simulation time 1721452284 ps
CPU time 1.12 seconds
Started Feb 29 01:19:28 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 197788 kb
Host smart-0e50eadd-41f9-4eaf-b5a2-ae35729bc9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283708084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3283708084
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1919904507
Short name T445
Test name
Test status
Simulation time 99824424730 ps
CPU time 16.09 seconds
Started Feb 29 01:19:26 PM PST 24
Finished Feb 29 01:19:44 PM PST 24
Peak memory 198232 kb
Host smart-26d5ed52-a7a2-4379-9d44-695d21b67608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919904507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1919904507
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2894313324
Short name T954
Test name
Test status
Simulation time 61183904682 ps
CPU time 12.84 seconds
Started Feb 29 01:23:27 PM PST 24
Finished Feb 29 01:23:40 PM PST 24
Peak memory 199536 kb
Host smart-a9c48b41-8b95-4cf5-b387-36231c25ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894313324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2894313324
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2976785373
Short name T448
Test name
Test status
Simulation time 76779729278 ps
CPU time 622.57 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:33:51 PM PST 24
Peak memory 215096 kb
Host smart-95ffaba7-9f32-4da3-afe9-697c977d5523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976785373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2976785373
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3650610694
Short name T317
Test name
Test status
Simulation time 28816993654 ps
CPU time 34.55 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:24:03 PM PST 24
Peak memory 199484 kb
Host smart-e7e91089-2eee-4bf8-a8fd-e096ffd3d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650610694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3650610694
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3535866686
Short name T315
Test name
Test status
Simulation time 18943959400 ps
CPU time 28.6 seconds
Started Feb 29 01:23:28 PM PST 24
Finished Feb 29 01:23:57 PM PST 24
Peak memory 199576 kb
Host smart-7c15e54d-e63d-4e36-923a-1b1b51c01c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535866686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3535866686
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2047143008
Short name T1055
Test name
Test status
Simulation time 180343304344 ps
CPU time 149.06 seconds
Started Feb 29 01:23:36 PM PST 24
Finished Feb 29 01:26:06 PM PST 24
Peak memory 199324 kb
Host smart-ba95db55-af07-4d31-83aa-490c5d457e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047143008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2047143008
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.392429977
Short name T33
Test name
Test status
Simulation time 45105478459 ps
CPU time 273.61 seconds
Started Feb 29 01:23:36 PM PST 24
Finished Feb 29 01:28:10 PM PST 24
Peak memory 216096 kb
Host smart-33a78062-abc7-4746-924c-fcf1578bad8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392429977 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.392429977
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1255059199
Short name T886
Test name
Test status
Simulation time 27170836802 ps
CPU time 41.74 seconds
Started Feb 29 01:23:40 PM PST 24
Finished Feb 29 01:24:22 PM PST 24
Peak memory 197684 kb
Host smart-fd91e7a0-a096-48a2-a297-58c839515689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255059199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1255059199
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1835776551
Short name T1070
Test name
Test status
Simulation time 76057515826 ps
CPU time 27.24 seconds
Started Feb 29 01:23:38 PM PST 24
Finished Feb 29 01:24:06 PM PST 24
Peak memory 199528 kb
Host smart-846a0caf-d041-4904-afd9-6f3bd32c5685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835776551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1835776551
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1214461698
Short name T20
Test name
Test status
Simulation time 11254075296 ps
CPU time 312.7 seconds
Started Feb 29 01:23:37 PM PST 24
Finished Feb 29 01:28:50 PM PST 24
Peak memory 215252 kb
Host smart-a7af9c84-8d3f-4af0-ae6f-630352970564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214461698 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1214461698
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1086468238
Short name T47
Test name
Test status
Simulation time 196577963408 ps
CPU time 170.49 seconds
Started Feb 29 01:23:37 PM PST 24
Finished Feb 29 01:26:27 PM PST 24
Peak memory 199792 kb
Host smart-e644fb7e-3aff-49bc-ba1f-54a263087f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086468238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1086468238
Directory /workspace/99.uart_fifo_reset/latest
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