Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	94836	1			T1	17		T2	2		T3	15
all_values[1]	94836	1			T1	17		T2	2		T3	15
all_values[2]	94836	1			T1	17		T2	2		T3	15
all_values[3]	94836	1			T1	17		T2	2		T3	15
all_values[4]	94836	1			T1	17		T2	2		T3	15
all_values[5]	94836	1			T1	17		T2	2		T3	15
all_values[6]	94836	1			T1	17		T2	2		T3	15
all_values[7]	94836	1			T1	17		T2	2		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

388412

1

T1

80

T2

6

T3

51

auto[1]

370276

1

T1

56

T2

10

T3

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

743883

1

T1

128

T2

15

T3

114

auto[1]

14805

1

T1

8

T2

1

T3

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	48836	1			T1	1		T2	1		T3	9
all_values[0]	auto[0]	auto[1]	2277	1			T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[0]	41724	1			T1	13		T3	3		T4	27
all_values[0]	auto[1]	auto[1]	1999	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[0]	46269	1			T1	5		T3	9		T4	8
all_values[1]	auto[0]	auto[1]	2211	1			T4	1		T5	2		T7	2
all_values[1]	auto[1]	auto[0]	44297	1			T1	11		T2	2		T3	5
all_values[1]	auto[1]	auto[1]	2059	1			T1	1		T3	1		T5	1
all_values[2]	auto[0]	auto[0]	42968	1			T1	13		T3	2		T4	8
all_values[2]	auto[0]	auto[1]	2156	1			T1	1		T4	1		T5	1
all_values[2]	auto[1]	auto[0]	47664	1			T1	2		T2	2		T3	11
all_values[2]	auto[1]	auto[1]	2048	1			T1	1		T3	2		T5	1
all_values[3]	auto[0]	auto[0]	49541	1			T1	12		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	162	1			T11	2		T12	3		T24	1
all_values[3]	auto[1]	auto[0]	44979	1			T1	5		T3	11		T5	1
all_values[3]	auto[1]	auto[1]	154	1			T11	1		T12	3		T24	3
all_values[4]	auto[0]	auto[0]	45896	1			T1	9		T3	4		T4	19
all_values[4]	auto[0]	auto[1]	325	1			T11	5		T12	3		T24	3
all_values[4]	auto[1]	auto[0]	48258	1			T1	8		T2	2		T3	11
all_values[4]	auto[1]	auto[1]	357	1			T11	1		T12	2		T24	1
all_values[5]	auto[0]	auto[0]	47923	1			T1	14		T2	2		T3	6
all_values[5]	auto[0]	auto[1]	120	1			T11	1		T12	1		T24	2
all_values[5]	auto[1]	auto[0]	46678	1			T1	3		T3	9		T4	9
all_values[5]	auto[1]	auto[1]	115	1			T11	3		T12	1		T24	1
all_values[6]	auto[0]	auto[0]	46623	1			T1	9		T3	11		T4	9
all_values[6]	auto[0]	auto[1]	104	1			T11	3		T12	1		T44	3
all_values[6]	auto[1]	auto[0]	47990	1			T1	8		T2	2		T3	4
all_values[6]	auto[1]	auto[1]	119	1			T12	2		T44	4		T129	3
all_values[7]	auto[0]	auto[0]	52693	1			T1	14		T3	4		T4	19
all_values[7]	auto[0]	auto[1]	308	1			T11	1		T53	3		T12	3
all_values[7]	auto[1]	auto[0]	41544	1			T1	1		T2	2		T3	11
all_values[7]	auto[1]	auto[1]	291	1			T1	2		T9	2		T11	3