Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2009

1

T1

1

T2

1

T3

1

auto[UartRx]

2009

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3856	1			T1	2		T2	2		T3	2
values[1]	27	1			T11	2		T24	1		T32	1
values[2]	13	1			T32	2		T33	1		T355	1
values[3]	13	1			T32	2		T34	1		T35	1
values[4]	8	1			T31	1		T24	1		T427	1
values[5]	11	1			T21	1		T25	3		T32	2
values[6]	15	1			T11	1		T12	1		T31	2
values[7]	17	1			T34	2		T112	1		T445	2
values[8]	16	1			T112	1		T427	2		T355	2
values[9]	12	1			T33	2		T355	1		T54	1
values[10]	20	1			T21	1		T31	1		T33	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1964	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	9	1			T24	1		T55	1		T446	1
auto[UartTx]	values[2]	5	1			T32	1		T33	1		T355	1
auto[UartTx]	values[3]	3	1			T32	1		T35	1		T447	1
auto[UartTx]	values[4]	3	1			T31	1		T446	1		T448	1
auto[UartTx]	values[5]	2	1			T25	1		T35	1		-	-
auto[UartTx]	values[6]	3	1			T31	1		T55	1		T449	1
auto[UartTx]	values[7]	5	1			T34	1		T56	1		T450	1
auto[UartTx]	values[8]	6	1			T427	1		T56	1		T450	1
auto[UartTx]	values[9]	3	1			T355	1		T54	1		T303	1
auto[UartTx]	values[10]	6	1			T33	2		T34	1		T352	1
auto[UartRx]	values[0]	1892	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	18	1			T11	2		T32	1		T35	1
auto[UartRx]	values[2]	8	1			T32	1		T54	1		T113	1
auto[UartRx]	values[3]	10	1			T32	1		T34	1		T112	1
auto[UartRx]	values[4]	5	1			T24	1		T427	1		T303	1
auto[UartRx]	values[5]	9	1			T21	1		T25	2		T32	2
auto[UartRx]	values[6]	12	1			T11	1		T12	1		T31	1
auto[UartRx]	values[7]	12	1			T34	1		T112	1		T445	2
auto[UartRx]	values[8]	10	1			T112	1		T427	1		T355	2
auto[UartRx]	values[9]	9	1			T33	2		T303	1		T445	1
auto[UartRx]	values[10]	14	1			T21	1		T31	1		T54	1