Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1677	1			T1	1		T2	3		T3	1
auto[BaudRate115200]	1749	1			T2	3		T3	1		T5	2
auto[BaudRate230400]	1515	1			T1	1		T2	3		T3	1
auto[BaudRate128Kbps]	1574	1			T1	1		T3	3		T4	1
auto[BaudRate256Kbps]	1669	1			T1	1		T3	2		T5	1
auto[BaudRate1Mbps]	1445	1			T1	1		T2	3		T3	1
auto[BaudRate1p5Mbps]	1055	1			T4	1		T5	1		T7	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1002	1			T15	5		T51	5		T311	7
freqs[25]	1212	1			T9	10		T119	1		T22	15
freqs[48]	450	1			T5	9		T20	15		T43	5
freqs[50]	424	1			T21	51		T41	4		T152	8
freqs[100]	757	1			T3	9		T42	10		T46	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	207	1			T51	1		T311	3		T390	1
auto[BaudRate9600]	freqs[25]	194	1			T9	1		T175	1		T451	7
auto[BaudRate9600]	freqs[48]	63	1			T20	8		T148	1		T139	3
auto[BaudRate9600]	freqs[50]	63	1			T21	10		T41	1		T152	3
auto[BaudRate9600]	freqs[100]	107	1			T3	1		T42	1		T16	1
auto[BaudRate115200]	freqs[24]	166	1			T51	1		T136	2		T390	2
auto[BaudRate115200]	freqs[25]	170	1			T9	2		T22	12		T175	3
auto[BaudRate115200]	freqs[48]	85	1			T5	2		T20	7		T43	1
auto[BaudRate115200]	freqs[50]	61	1			T21	7		T152	2		T399	3
auto[BaudRate115200]	freqs[100]	96	1			T3	1		T53	2		T394	3
auto[BaudRate230400]	freqs[24]	149	1			T15	1		T136	2		T390	1
auto[BaudRate230400]	freqs[25]	179	1			T9	1		T22	3		T175	1
auto[BaudRate230400]	freqs[48]	60	1			T5	1		T43	3		T199	1
auto[BaudRate230400]	freqs[50]	53	1			T21	10		T41	2		T399	2
auto[BaudRate230400]	freqs[100]	100	1			T3	1		T42	2		T46	1
auto[BaudRate128Kbps]	freqs[24]	140	1			T15	3		T51	2		T311	1
auto[BaudRate128Kbps]	freqs[25]	179	1			T9	2		T175	1		T45	1
auto[BaudRate128Kbps]	freqs[48]	47	1			T5	1		T168	1		T148	2
auto[BaudRate128Kbps]	freqs[50]	55	1			T21	1		T152	1		T399	2
auto[BaudRate128Kbps]	freqs[100]	134	1			T3	3		T42	2		T46	1
auto[BaudRate256Kbps]	freqs[24]	124	1			T15	1		T311	1		T107	1
auto[BaudRate256Kbps]	freqs[25]	188	1			T9	2		T45	1		T406	2
auto[BaudRate256Kbps]	freqs[48]	70	1			T5	1		T199	1		T168	1
auto[BaudRate256Kbps]	freqs[50]	63	1			T21	9		T152	1		T428	3
auto[BaudRate256Kbps]	freqs[100]	92	1			T3	2		T42	1		T46	1
auto[BaudRate1Mbps]	freqs[24]	143	1			T311	1		T396	2		T390	2
auto[BaudRate1Mbps]	freqs[25]	188	1			T9	1		T119	1		T175	3
auto[BaudRate1Mbps]	freqs[48]	63	1			T5	3		T199	2		T168	1
auto[BaudRate1Mbps]	freqs[50]	75	1			T21	6		T41	1		T104	1
auto[BaudRate1Mbps]	freqs[100]	114	1			T3	1		T42	1		T46	1
auto[BaudRate1p5Mbps]	freqs[25]	114	1			T9	1		T45	1		T110	1
auto[BaudRate1p5Mbps]	freqs[48]	62	1			T5	1		T43	1		T199	1
auto[BaudRate1p5Mbps]	freqs[50]	54	1			T21	8		T152	1		T145	3
auto[BaudRate1p5Mbps]	freqs[100]	114	1			T42	3		T46	1		T53	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded