Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1983 1 T8 1 T21 2 T36 1
all_levels[1] 421 1 T3 1 T5 2 T13 6
all_levels[2] 358 1 T36 1 T13 1 T18 2
all_levels[3] 370 1 T4 1 T9 2 T14 1
all_levels[4] 317 1 T1 1 T7 1 T18 5
all_levels[5] 304 1 T7 2 T9 1 T41 1
all_levels[6] 292 1 T39 1 T41 2 T127 2
all_levels[7] 218 1 T5 1 T42 1 T50 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%