Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	94836	1			T1	17		T2	2		T3	15
all_pins[1]	94836	1			T1	17		T2	2		T3	15
all_pins[2]	94836	1			T1	17		T2	2		T3	15
all_pins[3]	94836	1			T1	17		T2	2		T3	15
all_pins[4]	94836	1			T1	17		T2	2		T3	15
all_pins[5]	94836	1			T1	17		T2	2		T3	15
all_pins[6]	94836	1			T1	17		T2	2		T3	15
all_pins[7]	94836	1			T1	17		T2	2		T3	15

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	750867	1			T1	131		T2	16		T3	115
values[0x1]	7821	1			T1	5		T3	5		T4	1
transitions[0x0=>0x1]	7118	1			T1	3		T3	3		T4	1
transitions[0x1=>0x0]	7131	1			T1	3		T3	3		T4	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92800	1			T1	16		T2	2		T3	14
all_pins[0]	values[0x1]	2036	1			T1	1		T3	1		T4	1
all_pins[0]	transitions[0x0=>0x1]	1775	1			T1	1		T4	1		T7	3
all_pins[0]	transitions[0x1=>0x0]	1793	1			T1	1		T5	1		T9	1
all_pins[1]	values[0x0]	92782	1			T1	16		T2	2		T3	14
all_pins[1]	values[0x1]	2054	1			T1	1		T3	1		T5	1
all_pins[1]	transitions[0x0=>0x1]	1824	1			T5	1		T9	3		T21	2
all_pins[1]	transitions[0x1=>0x0]	1863	1			T3	1		T5	1		T7	3
all_pins[2]	values[0x0]	92743	1			T1	16		T2	2		T3	13
all_pins[2]	values[0x1]	2093	1			T1	1		T3	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	2065	1			T1	1		T3	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	126	1			T11	1		T12	3		T24	2
all_pins[3]	values[0x0]	94682	1			T1	17		T2	2		T3	15
all_pins[3]	values[0x1]	154	1			T11	1		T12	3		T24	3
all_pins[3]	transitions[0x0=>0x1]	136	1			T11	1		T12	3		T24	3
all_pins[3]	transitions[0x1=>0x0]	339	1			T11	1		T12	2		T24	1
all_pins[4]	values[0x0]	94479	1			T1	17		T2	2		T3	15
all_pins[4]	values[0x1]	357	1			T11	1		T12	2		T24	1
all_pins[4]	transitions[0x0=>0x1]	306	1			T12	2		T24	1		T16	11
all_pins[4]	transitions[0x1=>0x0]	101	1			T11	2		T12	1		T24	1
all_pins[5]	values[0x0]	94684	1			T1	17		T2	2		T3	15
all_pins[5]	values[0x1]	152	1			T11	3		T12	1		T24	1
all_pins[5]	transitions[0x0=>0x1]	121	1			T11	3		T12	1		T24	1
all_pins[5]	transitions[0x1=>0x0]	653	1			T3	1		T5	1		T7	4
all_pins[6]	values[0x0]	94152	1			T1	17		T2	2		T3	14
all_pins[6]	values[0x1]	684	1			T3	1		T5	1		T7	4
all_pins[6]	transitions[0x0=>0x1]	648	1			T3	1		T5	1		T7	4
all_pins[6]	transitions[0x1=>0x0]	255	1			T1	2		T9	2		T11	3
all_pins[7]	values[0x0]	94545	1			T1	15		T2	2		T3	15
all_pins[7]	values[0x1]	291	1			T1	2		T9	2		T11	3
all_pins[7]	transitions[0x0=>0x1]	243	1			T1	1		T11	3		T53	2
all_pins[7]	transitions[0x1=>0x0]	2001	1			T3	1		T4	1		T7	4