Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	502	1			T11	7		T12	7		T24	7
all_values[1]	502	1			T11	7		T12	7		T24	7
all_values[2]	502	1			T11	7		T12	7		T24	7
all_values[3]	502	1			T11	7		T12	7		T24	7
all_values[4]	502	1			T11	7		T12	7		T24	7
all_values[5]	502	1			T11	7		T12	7		T24	7
all_values[6]	502	1			T11	7		T12	7		T24	7
all_values[7]	502	1			T11	7		T12	7		T24	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2134

1

T11

38

T12

34

T24

20

auto[1]

1882

1

T11

18

T12

22

T24

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1533

1

T11

19

T12

21

T24

15

auto[1]

2483

1

T11

37

T12

35

T24

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333

1

T11

32

T12

31

T24

30

auto[1]

1683

1

T11

24

T12

25

T24

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	101	1			T11	1		T12	1		T44	6
all_values[0]	auto[0]	auto[0]	auto[1]	54	1			T11	2		T12	2		T24	2
all_values[0]	auto[0]	auto[1]	auto[0]	75	1			T12	1		T44	2		T169	4
all_values[0]	auto[0]	auto[1]	auto[1]	48	1			T145	2		T122	1		T177	2
all_values[0]	auto[1]	auto[0]	auto[1]	115	1			T11	3		T12	2		T24	4
all_values[0]	auto[1]	auto[1]	auto[1]	109	1			T11	1		T12	1		T24	1
all_values[1]	auto[0]	auto[0]	auto[0]	102	1			T11	3		T12	1		T44	4
all_values[1]	auto[0]	auto[0]	auto[1]	48	1			T11	1		T24	1		T44	1
all_values[1]	auto[0]	auto[1]	auto[0]	84	1			T12	2		T44	2		T129	1
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T11	1		T12	1		T129	1
all_values[1]	auto[1]	auto[0]	auto[1]	110	1			T11	2		T12	1		T24	1
all_values[1]	auto[1]	auto[1]	auto[1]	114	1			T12	2		T24	5		T44	4
all_values[2]	auto[0]	auto[0]	auto[0]	91	1			T11	2		T12	4		T44	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T11	2		T24	1		T44	2
all_values[2]	auto[0]	auto[1]	auto[0]	81	1			T12	2		T24	2		T44	2
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T24	2		T44	1		T129	2
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T12	1		T24	1		T44	4
all_values[2]	auto[1]	auto[1]	auto[1]	111	1			T11	3		T24	1		T44	4
all_values[3]	auto[0]	auto[0]	auto[0]	122	1			T11	3		T12	1		T44	4
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T12	3		T44	1		T145	1
all_values[3]	auto[0]	auto[1]	auto[0]	84	1			T11	1		T24	2		T129	1
all_values[3]	auto[0]	auto[1]	auto[1]	42	1			T24	2		T33	2		T347	4
all_values[3]	auto[1]	auto[0]	auto[1]	113	1			T11	2		T12	1		T44	5
all_values[3]	auto[1]	auto[1]	auto[1]	84	1			T11	1		T12	2		T24	3
all_values[4]	auto[0]	auto[0]	auto[0]	105	1			T12	2		T44	6		T129	2
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T11	3		T24	1		T44	1
all_values[4]	auto[0]	auto[1]	auto[0]	89	1			T24	1		T44	2		T145	1
all_values[4]	auto[0]	auto[1]	auto[1]	44	1			T12	1		T24	2		T145	1
all_values[4]	auto[1]	auto[0]	auto[1]	132	1			T11	2		T12	4		T24	2
all_values[4]	auto[1]	auto[1]	auto[1]	75	1			T11	2		T24	1		T129	1
all_values[5]	auto[0]	auto[0]	auto[0]	96	1			T11	1		T12	1		T44	1
all_values[5]	auto[0]	auto[0]	auto[1]	42	1			T24	1		T44	1		T177	1
all_values[5]	auto[0]	auto[1]	auto[0]	98	1			T11	1		T12	3		T24	3
all_values[5]	auto[0]	auto[1]	auto[1]	48	1			T11	1		T12	1		T24	1
all_values[5]	auto[1]	auto[0]	auto[1]	127	1			T11	2		T12	2		T24	1
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T11	2		T24	1		T44	2
all_values[6]	auto[0]	auto[0]	auto[0]	114	1			T11	3		T12	2		T24	3
all_values[6]	auto[0]	auto[0]	auto[1]	43	1			T11	1		T145	1		T122	2
all_values[6]	auto[0]	auto[1]	auto[0]	93	1			T11	1		T12	1		T24	4
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T12	1		T129	2		T169	1
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T11	1		T12	2		T44	3
all_values[6]	auto[1]	auto[1]	auto[1]	87	1			T11	1		T12	1		T44	5
all_values[7]	auto[0]	auto[0]	auto[0]	93	1			T11	2		T44	1		T129	1
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T12	1		T44	1		T129	1
all_values[7]	auto[0]	auto[1]	auto[0]	105	1			T11	1		T44	1		T129	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T11	2		T24	2		T44	5
all_values[7]	auto[1]	auto[0]	auto[1]	101	1			T11	2		T12	3		T24	2
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T12	3		T24	3		T44	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal