Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.79 98.45 100.00 99.76 100.00 97.56


Total test records in report: 1232
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T1045 /workspace/coverage/default/9.uart_tx_ovrd.3036656265 Mar 03 01:23:28 PM PST 24 Mar 03 01:23:30 PM PST 24 1754256928 ps
T1046 /workspace/coverage/default/38.uart_alert_test.1692107221 Mar 03 01:26:49 PM PST 24 Mar 03 01:26:51 PM PST 24 116235769 ps
T1047 /workspace/coverage/default/208.uart_fifo_reset.2764480311 Mar 03 01:30:04 PM PST 24 Mar 03 01:30:20 PM PST 24 124409004995 ps
T337 /workspace/coverage/default/280.uart_fifo_reset.1605077835 Mar 03 01:30:36 PM PST 24 Mar 03 01:31:08 PM PST 24 19329371443 ps
T1048 /workspace/coverage/default/31.uart_fifo_reset.1353134600 Mar 03 01:25:57 PM PST 24 Mar 03 01:26:20 PM PST 24 48283440342 ps
T1049 /workspace/coverage/default/114.uart_fifo_reset.1526926697 Mar 03 01:29:05 PM PST 24 Mar 03 01:29:27 PM PST 24 22797689546 ps
T1050 /workspace/coverage/default/33.uart_rx_oversample.3024291377 Mar 03 01:26:07 PM PST 24 Mar 03 01:26:37 PM PST 24 3504839640 ps
T447 /workspace/coverage/default/49.uart_stress_all_with_rand_reset.667432850 Mar 03 01:28:07 PM PST 24 Mar 03 01:32:33 PM PST 24 16980624078 ps
T1051 /workspace/coverage/default/87.uart_fifo_reset.4132932910 Mar 03 01:28:42 PM PST 24 Mar 03 01:31:21 PM PST 24 111314021624 ps
T1052 /workspace/coverage/default/222.uart_fifo_reset.3995996753 Mar 03 01:30:09 PM PST 24 Mar 03 01:30:50 PM PST 24 25351722504 ps
T1053 /workspace/coverage/default/46.uart_perf.22934912 Mar 03 01:27:49 PM PST 24 Mar 03 01:30:51 PM PST 24 11649939138 ps
T1054 /workspace/coverage/default/10.uart_perf.3796392765 Mar 03 01:23:38 PM PST 24 Mar 03 01:24:53 PM PST 24 20942008705 ps
T116 /workspace/coverage/default/63.uart_stress_all_with_rand_reset.597993617 Mar 03 01:28:23 PM PST 24 Mar 03 01:40:12 PM PST 24 463009988686 ps
T1055 /workspace/coverage/default/8.uart_intr.3402861137 Mar 03 01:23:17 PM PST 24 Mar 03 01:26:24 PM PST 24 496765169909 ps
T371 /workspace/coverage/default/194.uart_fifo_reset.3943742286 Mar 03 01:29:53 PM PST 24 Mar 03 01:30:58 PM PST 24 40535384120 ps
T1056 /workspace/coverage/default/39.uart_loopback.1315157847 Mar 03 01:26:56 PM PST 24 Mar 03 01:27:04 PM PST 24 9436204668 ps
T1057 /workspace/coverage/default/4.uart_tx_rx.246814016 Mar 03 01:22:49 PM PST 24 Mar 03 01:23:20 PM PST 24 278488722114 ps
T1058 /workspace/coverage/default/215.uart_fifo_reset.442038001 Mar 03 01:30:01 PM PST 24 Mar 03 01:32:44 PM PST 24 82303429185 ps
T198 /workspace/coverage/default/185.uart_fifo_reset.2629658781 Mar 03 01:29:50 PM PST 24 Mar 03 01:30:11 PM PST 24 124379693141 ps
T1059 /workspace/coverage/default/179.uart_fifo_reset.807084468 Mar 03 01:29:47 PM PST 24 Mar 03 01:30:27 PM PST 24 20575691103 ps
T1060 /workspace/coverage/default/22.uart_rx_parity_err.2506335332 Mar 03 01:24:53 PM PST 24 Mar 03 01:25:36 PM PST 24 26936638338 ps
T1061 /workspace/coverage/default/49.uart_rx_start_bit_filter.2370946180 Mar 03 01:28:06 PM PST 24 Mar 03 01:28:09 PM PST 24 4334579094 ps
T1062 /workspace/coverage/default/29.uart_fifo_reset.3982103390 Mar 03 01:25:42 PM PST 24 Mar 03 01:25:57 PM PST 24 19187550430 ps
T1063 /workspace/coverage/default/43.uart_tx_rx.3871848308 Mar 03 01:27:12 PM PST 24 Mar 03 01:28:08 PM PST 24 27297264732 ps
T1064 /workspace/coverage/default/48.uart_stress_all.294076946 Mar 03 01:28:07 PM PST 24 Mar 03 01:40:26 PM PST 24 318800415073 ps
T1065 /workspace/coverage/default/10.uart_rx_start_bit_filter.955319621 Mar 03 01:23:28 PM PST 24 Mar 03 01:23:34 PM PST 24 3110214871 ps
T1066 /workspace/coverage/default/3.uart_intr.2526759843 Mar 03 01:22:40 PM PST 24 Mar 03 01:25:29 PM PST 24 62352962417 ps
T1067 /workspace/coverage/default/204.uart_fifo_reset.3910711066 Mar 03 01:29:56 PM PST 24 Mar 03 01:31:01 PM PST 24 165458003400 ps
T1068 /workspace/coverage/default/7.uart_rx_parity_err.1340244940 Mar 03 01:23:08 PM PST 24 Mar 03 01:29:09 PM PST 24 137294843482 ps
T1069 /workspace/coverage/default/16.uart_intr.2504870049 Mar 03 01:24:13 PM PST 24 Mar 03 01:24:34 PM PST 24 31967351928 ps
T1070 /workspace/coverage/default/33.uart_noise_filter.2118125520 Mar 03 01:26:12 PM PST 24 Mar 03 01:26:35 PM PST 24 44912915629 ps
T1071 /workspace/coverage/default/1.uart_rx_start_bit_filter.4182834937 Mar 03 01:22:35 PM PST 24 Mar 03 01:23:13 PM PST 24 46832197971 ps
T1072 /workspace/coverage/default/49.uart_intr.4129179101 Mar 03 01:28:05 PM PST 24 Mar 03 01:33:14 PM PST 24 622069393217 ps
T1073 /workspace/coverage/default/22.uart_smoke.3513270715 Mar 03 01:24:54 PM PST 24 Mar 03 01:25:02 PM PST 24 5683273867 ps
T1074 /workspace/coverage/default/12.uart_rx_oversample.918595425 Mar 03 01:23:44 PM PST 24 Mar 03 01:24:07 PM PST 24 3405817206 ps
T1075 /workspace/coverage/default/256.uart_fifo_reset.28347016 Mar 03 01:30:20 PM PST 24 Mar 03 01:30:51 PM PST 24 20218211099 ps
T1076 /workspace/coverage/default/22.uart_rx_oversample.3258599648 Mar 03 01:24:54 PM PST 24 Mar 03 01:25:01 PM PST 24 3710933906 ps
T1077 /workspace/coverage/default/259.uart_fifo_reset.309303052 Mar 03 01:30:22 PM PST 24 Mar 03 01:30:48 PM PST 24 101041444356 ps
T1078 /workspace/coverage/default/36.uart_perf.3887848208 Mar 03 01:26:36 PM PST 24 Mar 03 01:28:59 PM PST 24 5372364189 ps
T1079 /workspace/coverage/default/4.uart_fifo_overflow.1246784927 Mar 03 01:22:51 PM PST 24 Mar 03 01:28:57 PM PST 24 359195294503 ps
T1080 /workspace/coverage/default/3.uart_rx_parity_err.2806435489 Mar 03 01:22:48 PM PST 24 Mar 03 01:23:59 PM PST 24 45738708788 ps
T1081 /workspace/coverage/default/248.uart_fifo_reset.389618873 Mar 03 01:30:23 PM PST 24 Mar 03 01:31:39 PM PST 24 42309714293 ps
T1082 /workspace/coverage/default/25.uart_smoke.1320212835 Mar 03 01:25:07 PM PST 24 Mar 03 01:25:13 PM PST 24 844171725 ps
T1083 /workspace/coverage/default/45.uart_tx_ovrd.3188169700 Mar 03 01:27:32 PM PST 24 Mar 03 01:27:45 PM PST 24 7239859957 ps
T327 /workspace/coverage/default/166.uart_fifo_reset.2947847864 Mar 03 01:29:41 PM PST 24 Mar 03 01:30:00 PM PST 24 10859248711 ps
T1084 /workspace/coverage/default/25.uart_rx_parity_err.2000191727 Mar 03 01:25:17 PM PST 24 Mar 03 01:25:51 PM PST 24 18777173408 ps
T1085 /workspace/coverage/default/19.uart_rx_parity_err.4188762764 Mar 03 01:24:38 PM PST 24 Mar 03 01:25:29 PM PST 24 140708929641 ps
T1086 /workspace/coverage/default/54.uart_fifo_reset.1705313240 Mar 03 01:28:13 PM PST 24 Mar 03 01:28:44 PM PST 24 21797431042 ps
T1087 /workspace/coverage/default/238.uart_fifo_reset.4183759746 Mar 03 01:30:17 PM PST 24 Mar 03 01:30:39 PM PST 24 123223680709 ps
T1088 /workspace/coverage/default/48.uart_rx_start_bit_filter.1162657094 Mar 03 01:28:03 PM PST 24 Mar 03 01:28:11 PM PST 24 4078140137 ps
T1089 /workspace/coverage/default/205.uart_fifo_reset.1550786245 Mar 03 01:30:00 PM PST 24 Mar 03 01:30:23 PM PST 24 20423824139 ps
T1090 /workspace/coverage/default/136.uart_fifo_reset.1429351313 Mar 03 01:29:19 PM PST 24 Mar 03 01:30:47 PM PST 24 44680353487 ps
T57 /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1772100598 Mar 03 01:22:25 PM PST 24 Mar 03 01:28:19 PM PST 24 40939403178 ps
T1091 /workspace/coverage/default/187.uart_fifo_reset.3878078694 Mar 03 01:29:48 PM PST 24 Mar 03 01:30:24 PM PST 24 89891952333 ps
T1092 /workspace/coverage/default/18.uart_fifo_full.3632286221 Mar 03 01:24:21 PM PST 24 Mar 03 01:25:09 PM PST 24 62783128172 ps
T1093 /workspace/coverage/default/35.uart_smoke.4182808108 Mar 03 01:26:21 PM PST 24 Mar 03 01:26:23 PM PST 24 279372276 ps
T1094 /workspace/coverage/default/44.uart_rx_oversample.2660235007 Mar 03 01:27:24 PM PST 24 Mar 03 01:27:57 PM PST 24 4339242398 ps
T1095 /workspace/coverage/default/5.uart_noise_filter.3094243190 Mar 03 01:22:55 PM PST 24 Mar 03 01:24:31 PM PST 24 112583216664 ps
T1096 /workspace/coverage/default/109.uart_fifo_reset.2677961912 Mar 03 01:28:56 PM PST 24 Mar 03 01:32:17 PM PST 24 113310144667 ps
T1097 /workspace/coverage/default/31.uart_fifo_full.360296 Mar 03 01:26:01 PM PST 24 Mar 03 01:26:34 PM PST 24 40647504215 ps
T1098 /workspace/coverage/default/20.uart_fifo_overflow.1408404948 Mar 03 01:24:48 PM PST 24 Mar 03 01:25:19 PM PST 24 107082508002 ps
T295 /workspace/coverage/default/287.uart_fifo_reset.3116206797 Mar 03 01:30:43 PM PST 24 Mar 03 01:30:54 PM PST 24 13804126918 ps
T1099 /workspace/coverage/default/4.uart_loopback.2155911317 Mar 03 01:22:49 PM PST 24 Mar 03 01:23:11 PM PST 24 10054402705 ps
T1100 /workspace/coverage/default/41.uart_rx_start_bit_filter.4288989257 Mar 03 01:27:14 PM PST 24 Mar 03 01:27:17 PM PST 24 27530600845 ps
T117 /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1009398136 Mar 03 01:24:39 PM PST 24 Mar 03 01:30:18 PM PST 24 30548973513 ps
T1101 /workspace/coverage/default/20.uart_smoke.2847951688 Mar 03 01:24:39 PM PST 24 Mar 03 01:24:43 PM PST 24 976473597 ps
T1102 /workspace/coverage/default/7.uart_stress_all.3166803865 Mar 03 01:23:09 PM PST 24 Mar 03 01:49:40 PM PST 24 1886676705634 ps
T1103 /workspace/coverage/cover_reg_top/19.uart_tl_errors.576729494 Mar 03 02:01:10 PM PST 24 Mar 03 02:01:11 PM PST 24 65243570 ps
T1104 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2813337332 Mar 03 02:00:27 PM PST 24 Mar 03 02:00:29 PM PST 24 1657366572 ps
T81 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.168839913 Mar 03 02:01:05 PM PST 24 Mar 03 02:01:06 PM PST 24 24456129 ps
T1105 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1659312627 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:42 PM PST 24 20818280 ps
T1106 /workspace/coverage/cover_reg_top/7.uart_intr_test.1743193607 Mar 03 02:00:48 PM PST 24 Mar 03 02:00:50 PM PST 24 17612357 ps
T1107 /workspace/coverage/cover_reg_top/30.uart_intr_test.462771820 Mar 03 02:01:23 PM PST 24 Mar 03 02:01:24 PM PST 24 15882672 ps
T82 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3925811041 Mar 03 02:00:32 PM PST 24 Mar 03 02:00:33 PM PST 24 24415591 ps
T1108 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2671423207 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:59 PM PST 24 62415061 ps
T1109 /workspace/coverage/cover_reg_top/32.uart_intr_test.3662534210 Mar 03 02:01:19 PM PST 24 Mar 03 02:01:20 PM PST 24 14825493 ps
T83 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2844439469 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 31601226 ps
T1110 /workspace/coverage/cover_reg_top/28.uart_intr_test.3180572602 Mar 03 02:01:17 PM PST 24 Mar 03 02:01:18 PM PST 24 46203396 ps
T1111 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.904254623 Mar 03 02:00:27 PM PST 24 Mar 03 02:00:28 PM PST 24 143507894 ps
T90 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2183434301 Mar 03 02:00:51 PM PST 24 Mar 03 02:00:54 PM PST 24 171043264 ps
T84 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3169434144 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 48915721 ps
T91 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.705900051 Mar 03 02:00:23 PM PST 24 Mar 03 02:00:25 PM PST 24 289217207 ps
T1112 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.521294478 Mar 03 02:01:14 PM PST 24 Mar 03 02:01:15 PM PST 24 81026456 ps
T1113 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3901838777 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:43 PM PST 24 58931113 ps
T85 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1199375000 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 86955959 ps
T1114 /workspace/coverage/cover_reg_top/6.uart_intr_test.3748974997 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:52 PM PST 24 30862897 ps
T58 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1012102245 Mar 03 02:00:34 PM PST 24 Mar 03 02:00:36 PM PST 24 15236272 ps
T1115 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4251540873 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:08 PM PST 24 38943329 ps
T86 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1876485527 Mar 03 02:01:05 PM PST 24 Mar 03 02:01:06 PM PST 24 31557241 ps
T92 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3221660445 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:42 PM PST 24 662854723 ps
T389 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2093140386 Mar 03 02:00:40 PM PST 24 Mar 03 02:00:41 PM PST 24 101052321 ps
T1116 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.376359481 Mar 03 02:01:05 PM PST 24 Mar 03 02:01:06 PM PST 24 313590557 ps
T1117 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3728875355 Mar 03 02:00:48 PM PST 24 Mar 03 02:00:51 PM PST 24 218026491 ps
T1118 /workspace/coverage/cover_reg_top/2.uart_intr_test.2359265996 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 12250253 ps
T1119 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3954841625 Mar 03 02:00:27 PM PST 24 Mar 03 02:00:29 PM PST 24 44739809 ps
T95 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3574416544 Mar 03 02:00:40 PM PST 24 Mar 03 02:00:41 PM PST 24 47818769 ps
T1120 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2502846855 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:59 PM PST 24 125000751 ps
T87 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2331193309 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 120519043 ps
T88 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3776809907 Mar 03 02:00:23 PM PST 24 Mar 03 02:00:24 PM PST 24 39039023 ps
T89 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2015345311 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:42 PM PST 24 42061296 ps
T59 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3422465887 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:14 PM PST 24 24041200 ps
T1121 /workspace/coverage/cover_reg_top/34.uart_intr_test.1780468324 Mar 03 02:01:16 PM PST 24 Mar 03 02:01:17 PM PST 24 11163688 ps
T1122 /workspace/coverage/cover_reg_top/7.uart_tl_errors.799631694 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:53 PM PST 24 1010797101 ps
T1123 /workspace/coverage/cover_reg_top/27.uart_intr_test.4108870938 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:26 PM PST 24 98424946 ps
T1124 /workspace/coverage/cover_reg_top/12.uart_tl_errors.4016335916 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 29902963 ps
T1125 /workspace/coverage/cover_reg_top/14.uart_intr_test.352525938 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 17886226 ps
T93 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2747568294 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:13 PM PST 24 685829063 ps
T1126 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1454614343 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:52 PM PST 24 22698492 ps
T1127 /workspace/coverage/cover_reg_top/49.uart_intr_test.3239861238 Mar 03 02:01:23 PM PST 24 Mar 03 02:01:24 PM PST 24 14432208 ps
T1128 /workspace/coverage/cover_reg_top/4.uart_intr_test.550210646 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:41 PM PST 24 45688285 ps
T1129 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.982087472 Mar 03 02:00:22 PM PST 24 Mar 03 02:00:26 PM PST 24 504822010 ps
T96 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1725969551 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 81141810 ps
T1130 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1323161339 Mar 03 02:01:08 PM PST 24 Mar 03 02:01:09 PM PST 24 59602062 ps
T1131 /workspace/coverage/cover_reg_top/37.uart_intr_test.3269756748 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:19 PM PST 24 12107156 ps
T1132 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1908088691 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:59 PM PST 24 89327491 ps
T1133 /workspace/coverage/cover_reg_top/26.uart_intr_test.592164411 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:19 PM PST 24 127001020 ps
T1134 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.373292256 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:59 PM PST 24 22185367 ps
T1135 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.368734895 Mar 03 02:00:33 PM PST 24 Mar 03 02:00:34 PM PST 24 16773615 ps
T1136 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3321029242 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 67049984 ps
T62 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1644175563 Mar 03 02:00:32 PM PST 24 Mar 03 02:00:35 PM PST 24 1025214335 ps
T60 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3091114453 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:06 PM PST 24 58105173 ps
T1137 /workspace/coverage/cover_reg_top/20.uart_intr_test.989551727 Mar 03 02:01:17 PM PST 24 Mar 03 02:01:18 PM PST 24 13307110 ps
T61 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1438574185 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 68781538 ps
T1138 /workspace/coverage/cover_reg_top/19.uart_intr_test.2641053557 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:12 PM PST 24 15173622 ps
T1139 /workspace/coverage/cover_reg_top/18.uart_intr_test.1717267536 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:14 PM PST 24 36043512 ps
T1140 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2171891426 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:10 PM PST 24 111328729 ps
T63 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.515207634 Mar 03 02:00:27 PM PST 24 Mar 03 02:00:28 PM PST 24 22349549 ps
T1141 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2069614114 Mar 03 02:00:43 PM PST 24 Mar 03 02:00:44 PM PST 24 213257837 ps
T1142 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1036597575 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 17985279 ps
T1143 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3226798025 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 16520377 ps
T1144 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.956622176 Mar 03 02:00:34 PM PST 24 Mar 03 02:00:36 PM PST 24 93373460 ps
T1145 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1184402808 Mar 03 02:00:48 PM PST 24 Mar 03 02:00:50 PM PST 24 30270494 ps
T1146 /workspace/coverage/cover_reg_top/1.uart_intr_test.1243615500 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:28 PM PST 24 12430182 ps
T1147 /workspace/coverage/cover_reg_top/3.uart_intr_test.3482105984 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:41 PM PST 24 34631119 ps
T1148 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1488369788 Mar 03 02:00:33 PM PST 24 Mar 03 02:00:34 PM PST 24 229202387 ps
T94 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.45754466 Mar 03 02:00:26 PM PST 24 Mar 03 02:00:28 PM PST 24 119534952 ps
T1149 /workspace/coverage/cover_reg_top/39.uart_intr_test.3442385266 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:18 PM PST 24 19119570 ps
T1150 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1870485231 Mar 03 02:00:23 PM PST 24 Mar 03 02:00:25 PM PST 24 160239579 ps
T1151 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1005930557 Mar 03 02:01:11 PM PST 24 Mar 03 02:01:12 PM PST 24 22237469 ps
T1152 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2880054546 Mar 03 02:01:14 PM PST 24 Mar 03 02:01:15 PM PST 24 18289957 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.175026984 Mar 03 02:00:22 PM PST 24 Mar 03 02:00:24 PM PST 24 163113546 ps
T1154 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3751133529 Mar 03 02:00:26 PM PST 24 Mar 03 02:00:27 PM PST 24 46721426 ps
T1155 /workspace/coverage/cover_reg_top/16.uart_tl_errors.385943542 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:09 PM PST 24 606999025 ps
T1156 /workspace/coverage/cover_reg_top/41.uart_intr_test.4005104097 Mar 03 02:01:21 PM PST 24 Mar 03 02:01:22 PM PST 24 29813164 ps
T1157 /workspace/coverage/cover_reg_top/43.uart_intr_test.2809464507 Mar 03 02:01:19 PM PST 24 Mar 03 02:01:20 PM PST 24 43504707 ps
T1158 /workspace/coverage/cover_reg_top/9.uart_intr_test.1969864703 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:59 PM PST 24 41447643 ps
T64 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1877427470 Mar 03 02:00:21 PM PST 24 Mar 03 02:00:23 PM PST 24 17717769 ps
T1159 /workspace/coverage/cover_reg_top/46.uart_intr_test.1921369835 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:26 PM PST 24 43797787 ps
T1160 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1797916337 Mar 03 02:00:33 PM PST 24 Mar 03 02:00:34 PM PST 24 21635213 ps
T1161 /workspace/coverage/cover_reg_top/38.uart_intr_test.2699035946 Mar 03 02:01:26 PM PST 24 Mar 03 02:01:26 PM PST 24 12409594 ps
T99 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2217945760 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:58 PM PST 24 212677213 ps
T80 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1949315570 Mar 03 02:01:14 PM PST 24 Mar 03 02:01:15 PM PST 24 186070534 ps
T1162 /workspace/coverage/cover_reg_top/8.uart_intr_test.180295256 Mar 03 02:00:56 PM PST 24 Mar 03 02:00:58 PM PST 24 12096484 ps
T1163 /workspace/coverage/cover_reg_top/21.uart_intr_test.1194381627 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:19 PM PST 24 13378985 ps
T1164 /workspace/coverage/cover_reg_top/33.uart_intr_test.3598758566 Mar 03 02:01:19 PM PST 24 Mar 03 02:01:20 PM PST 24 22620495 ps
T1165 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3716087168 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:14 PM PST 24 48933523 ps
T1166 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2807931811 Mar 03 02:00:48 PM PST 24 Mar 03 02:00:50 PM PST 24 23614027 ps
T1167 /workspace/coverage/cover_reg_top/29.uart_intr_test.3036198403 Mar 03 02:01:21 PM PST 24 Mar 03 02:01:21 PM PST 24 24441036 ps
T70 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.808619452 Mar 03 02:00:27 PM PST 24 Mar 03 02:00:28 PM PST 24 30580925 ps
T1168 /workspace/coverage/cover_reg_top/11.uart_intr_test.84170696 Mar 03 02:01:08 PM PST 24 Mar 03 02:01:09 PM PST 24 21269340 ps
T1169 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3583735672 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 70671224 ps
T1170 /workspace/coverage/cover_reg_top/31.uart_intr_test.3382108792 Mar 03 02:01:19 PM PST 24 Mar 03 02:01:20 PM PST 24 18287240 ps
T65 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2789219000 Mar 03 02:00:21 PM PST 24 Mar 03 02:00:24 PM PST 24 33183504 ps
T1171 /workspace/coverage/cover_reg_top/14.uart_csr_rw.457413945 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 23417244 ps
T1172 /workspace/coverage/cover_reg_top/45.uart_intr_test.375824145 Mar 03 02:01:26 PM PST 24 Mar 03 02:01:26 PM PST 24 76285940 ps
T1173 /workspace/coverage/cover_reg_top/48.uart_intr_test.2056138333 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:26 PM PST 24 56586565 ps
T100 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3106102064 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:15 PM PST 24 385163525 ps
T1174 /workspace/coverage/cover_reg_top/10.uart_intr_test.427316056 Mar 03 02:00:58 PM PST 24 Mar 03 02:00:59 PM PST 24 36912149 ps
T66 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2458112982 Mar 03 02:00:57 PM PST 24 Mar 03 02:00:58 PM PST 24 52385319 ps
T1175 /workspace/coverage/cover_reg_top/5.uart_csr_rw.770629525 Mar 03 02:00:43 PM PST 24 Mar 03 02:00:45 PM PST 24 60802661 ps
T98 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2945236299 Mar 03 02:00:58 PM PST 24 Mar 03 02:00:59 PM PST 24 50974875 ps
T97 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1723130519 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:52 PM PST 24 294236233 ps
T1176 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2246035476 Mar 03 02:01:05 PM PST 24 Mar 03 02:01:06 PM PST 24 52795520 ps
T1177 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4286234634 Mar 03 02:00:35 PM PST 24 Mar 03 02:00:36 PM PST 24 41238861 ps
T1178 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1868763872 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:10 PM PST 24 36715278 ps
T1179 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2613803097 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 28681299 ps
T1180 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3367041355 Mar 03 02:00:57 PM PST 24 Mar 03 02:01:00 PM PST 24 53096924 ps
T1181 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2215577669 Mar 03 02:00:56 PM PST 24 Mar 03 02:00:58 PM PST 24 15180753 ps
T1182 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1046904546 Mar 03 02:00:59 PM PST 24 Mar 03 02:01:00 PM PST 24 124208465 ps
T1183 /workspace/coverage/cover_reg_top/1.uart_tl_errors.528977595 Mar 03 02:00:21 PM PST 24 Mar 03 02:00:24 PM PST 24 624485226 ps
T1184 /workspace/coverage/cover_reg_top/18.uart_csr_rw.349071768 Mar 03 02:01:11 PM PST 24 Mar 03 02:01:11 PM PST 24 102494850 ps
T1185 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2852852208 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:15 PM PST 24 128265851 ps
T1186 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2780347284 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:09 PM PST 24 24954770 ps
T1187 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3361063960 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:13 PM PST 24 360091383 ps
T1188 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.966495701 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:15 PM PST 24 261287558 ps
T1189 /workspace/coverage/cover_reg_top/47.uart_intr_test.4017447402 Mar 03 02:01:24 PM PST 24 Mar 03 02:01:25 PM PST 24 13457410 ps
T1190 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.791947075 Mar 03 02:01:05 PM PST 24 Mar 03 02:01:06 PM PST 24 661630108 ps
T1191 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3844300738 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:52 PM PST 24 30140297 ps
T1192 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2766681699 Mar 03 02:01:13 PM PST 24 Mar 03 02:01:14 PM PST 24 72076326 ps
T1193 /workspace/coverage/cover_reg_top/24.uart_intr_test.2342058574 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:18 PM PST 24 12855208 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.341382103 Mar 03 02:00:34 PM PST 24 Mar 03 02:00:36 PM PST 24 26934428 ps
T1194 /workspace/coverage/cover_reg_top/25.uart_intr_test.16727436 Mar 03 02:01:23 PM PST 24 Mar 03 02:01:24 PM PST 24 14094732 ps
T1195 /workspace/coverage/cover_reg_top/12.uart_csr_rw.278052953 Mar 03 02:01:03 PM PST 24 Mar 03 02:01:04 PM PST 24 140458689 ps
T1196 /workspace/coverage/cover_reg_top/44.uart_intr_test.186302099 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:26 PM PST 24 21317067 ps
T1197 /workspace/coverage/cover_reg_top/5.uart_intr_test.1295470881 Mar 03 02:00:40 PM PST 24 Mar 03 02:00:41 PM PST 24 44833463 ps
T68 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.594353857 Mar 03 02:00:40 PM PST 24 Mar 03 02:00:41 PM PST 24 16102658 ps
T1198 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2534426597 Mar 03 02:00:49 PM PST 24 Mar 03 02:00:52 PM PST 24 59566991 ps
T1199 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3849077446 Mar 03 02:01:14 PM PST 24 Mar 03 02:01:15 PM PST 24 119831092 ps
T1200 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2500385463 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 49623485 ps
T1201 /workspace/coverage/cover_reg_top/0.uart_intr_test.97444223 Mar 03 02:00:20 PM PST 24 Mar 03 02:00:21 PM PST 24 37661103 ps
T1202 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1470999107 Mar 03 02:00:58 PM PST 24 Mar 03 02:00:59 PM PST 24 66752580 ps
T1203 /workspace/coverage/cover_reg_top/23.uart_intr_test.2868947750 Mar 03 02:01:19 PM PST 24 Mar 03 02:01:19 PM PST 24 15308539 ps
T1204 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2493603471 Mar 03 02:00:23 PM PST 24 Mar 03 02:00:25 PM PST 24 347412456 ps
T1205 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1359227597 Mar 03 02:01:11 PM PST 24 Mar 03 02:01:12 PM PST 24 17371384 ps
T1206 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1785873378 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:10 PM PST 24 36327751 ps
T1207 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2690882940 Mar 03 02:00:39 PM PST 24 Mar 03 02:00:39 PM PST 24 85593597 ps
T1208 /workspace/coverage/cover_reg_top/17.uart_intr_test.2721756335 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:13 PM PST 24 12391815 ps
T1209 /workspace/coverage/cover_reg_top/35.uart_intr_test.2873412886 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:25 PM PST 24 77271303 ps
T1210 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3991405332 Mar 03 02:00:42 PM PST 24 Mar 03 02:00:44 PM PST 24 28521618 ps
T1211 /workspace/coverage/cover_reg_top/22.uart_intr_test.982796163 Mar 03 02:01:18 PM PST 24 Mar 03 02:01:19 PM PST 24 24263890 ps
T1212 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1213645237 Mar 03 02:00:59 PM PST 24 Mar 03 02:00:59 PM PST 24 111480531 ps
T1213 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3993262161 Mar 03 02:00:56 PM PST 24 Mar 03 02:00:58 PM PST 24 37208021 ps
T1214 /workspace/coverage/cover_reg_top/40.uart_intr_test.3730912093 Mar 03 02:01:25 PM PST 24 Mar 03 02:01:26 PM PST 24 17748327 ps
T1215 /workspace/coverage/cover_reg_top/42.uart_intr_test.1470418284 Mar 03 02:01:23 PM PST 24 Mar 03 02:01:24 PM PST 24 11964539 ps
T1216 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1616266285 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:41 PM PST 24 14554412 ps
T1217 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3984587533 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 99349557 ps
T1218 /workspace/coverage/cover_reg_top/16.uart_intr_test.2759800884 Mar 03 02:01:12 PM PST 24 Mar 03 02:01:13 PM PST 24 13836529 ps
T1219 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.960706811 Mar 03 02:01:10 PM PST 24 Mar 03 02:01:11 PM PST 24 110396936 ps
T1220 /workspace/coverage/cover_reg_top/15.uart_intr_test.302082101 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 24020663 ps
T1221 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4273172179 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:11 PM PST 24 109557442 ps
T1222 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2564185218 Mar 03 02:00:34 PM PST 24 Mar 03 02:00:36 PM PST 24 26716932 ps
T1223 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1267358547 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 49727762 ps
T1224 /workspace/coverage/cover_reg_top/36.uart_intr_test.2925433574 Mar 03 02:01:23 PM PST 24 Mar 03 02:01:24 PM PST 24 13646975 ps
T1225 /workspace/coverage/cover_reg_top/12.uart_intr_test.1246150306 Mar 03 02:01:04 PM PST 24 Mar 03 02:01:04 PM PST 24 36379364 ps
T1226 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2240154226 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:10 PM PST 24 47668975 ps
T1227 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4280622207 Mar 03 02:01:06 PM PST 24 Mar 03 02:01:07 PM PST 24 200724209 ps
T1228 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2475710489 Mar 03 02:01:09 PM PST 24 Mar 03 02:01:11 PM PST 24 60750266 ps
T1229 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2631552451 Mar 03 02:00:39 PM PST 24 Mar 03 02:00:41 PM PST 24 115272068 ps
T1230 /workspace/coverage/cover_reg_top/13.uart_intr_test.2377669101 Mar 03 02:01:07 PM PST 24 Mar 03 02:01:08 PM PST 24 42551941 ps
T1231 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1932092904 Mar 03 02:00:41 PM PST 24 Mar 03 02:00:42 PM PST 24 22470840 ps
T69 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3764769444 Mar 03 02:00:28 PM PST 24 Mar 03 02:00:29 PM PST 24 70730983 ps
T1232 /workspace/coverage/cover_reg_top/7.uart_csr_rw.669726154 Mar 03 02:00:50 PM PST 24 Mar 03 02:00:53 PM PST 24 29113723 ps

Test location /workspace/coverage/default/15.uart_rx_parity_err.4011174318
Short name T9
Test name
Test status
Simulation time 163874730896 ps
CPU time 71.42 seconds
Started Mar 03 01:24:09 PM PST 24
Finished Mar 03 01:25:21 PM PST 24
Peak memory 199664 kb
Host smart-5c835536-08d8-493e-8336-306e42e1010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011174318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4011174318
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.255111108
Short name T11
Test name
Test status
Simulation time 51042784139 ps
CPU time 493.67 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:37:04 PM PST 24
Peak memory 215164 kb
Host smart-15d82e6c-0bc3-4347-be60-978f4cc60c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255111108 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.255111108
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.1442394059
Short name T16
Test name
Test status
Simulation time 361538279000 ps
CPU time 1141.3 seconds
Started Mar 03 01:26:21 PM PST 24
Finished Mar 03 01:45:23 PM PST 24
Peak memory 199816 kb
Host smart-1332714e-f3c4-42e3-a1a1-01a6509feacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442394059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1442394059
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.220203571
Short name T129
Test name
Test status
Simulation time 400805881678 ps
CPU time 1140.04 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:42:53 PM PST 24
Peak memory 199640 kb
Host smart-37b456b3-d4bb-48b9-829b-ac0936f721a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220203571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.220203571
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2695796504
Short name T21
Test name
Test status
Simulation time 74789145053 ps
CPU time 467.93 seconds
Started Mar 03 01:24:17 PM PST 24
Finished Mar 03 01:32:06 PM PST 24
Peak memory 216288 kb
Host smart-c801bd71-3a31-4ed1-8a96-bd089f467900
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695796504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2695796504
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.3174296521
Short name T44
Test name
Test status
Simulation time 387917577074 ps
CPU time 199.31 seconds
Started Mar 03 01:24:06 PM PST 24
Finished Mar 03 01:27:26 PM PST 24
Peak memory 208036 kb
Host smart-a43a3ae4-80b3-47b9-8881-9547118dc1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174296521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3174296521
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2446667693
Short name T7
Test name
Test status
Simulation time 41932759227 ps
CPU time 72.05 seconds
Started Mar 03 01:27:15 PM PST 24
Finished Mar 03 01:28:27 PM PST 24
Peak memory 199508 kb
Host smart-8d741852-8f25-4e95-a2d2-370615cd19c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446667693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2446667693
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.1856490110
Short name T139
Test name
Test status
Simulation time 341072154723 ps
CPU time 327.84 seconds
Started Mar 03 01:22:35 PM PST 24
Finished Mar 03 01:28:03 PM PST 24
Peak memory 199740 kb
Host smart-25f4846d-fd9c-475d-9a37-4a6408b0a8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856490110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1856490110
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2167334942
Short name T28
Test name
Test status
Simulation time 1543996018 ps
CPU time 0.89 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:22:43 PM PST 24
Peak memory 217212 kb
Host smart-e77253d6-01f6-46a4-8467-24cc2103eb67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167334942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2167334942
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2070542185
Short name T328
Test name
Test status
Simulation time 39236698811 ps
CPU time 32.44 seconds
Started Mar 03 01:26:36 PM PST 24
Finished Mar 03 01:27:09 PM PST 24
Peak memory 199120 kb
Host smart-950bdc41-5d50-4da8-b4d2-966a1c29d1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070542185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2070542185
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.20327024
Short name T42
Test name
Test status
Simulation time 37296861270 ps
CPU time 67.91 seconds
Started Mar 03 01:29:50 PM PST 24
Finished Mar 03 01:30:58 PM PST 24
Peak memory 199684 kb
Host smart-282c0fde-995e-47c4-92bf-5d66a6797747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20327024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.20327024
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3292632054
Short name T396
Test name
Test status
Simulation time 163198439865 ps
CPU time 381.76 seconds
Started Mar 03 01:23:28 PM PST 24
Finished Mar 03 01:29:51 PM PST 24
Peak memory 199672 kb
Host smart-358d9c01-a8c1-42ee-a8b9-786a3dd639f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292632054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3292632054
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.4102484111
Short name T24
Test name
Test status
Simulation time 259280871725 ps
CPU time 545.69 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:37:56 PM PST 24
Peak memory 216288 kb
Host smart-d15f59c1-52b0-476f-b16d-7941a27ad4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102484111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.4102484111
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1445390437
Short name T323
Test name
Test status
Simulation time 198588885461 ps
CPU time 25.38 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:28:32 PM PST 24
Peak memory 199192 kb
Host smart-1b936cb7-5a27-4ee7-a140-0717c363e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445390437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1445390437
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_stress_all.3182288383
Short name T347
Test name
Test status
Simulation time 163945659747 ps
CPU time 456.25 seconds
Started Mar 03 01:25:20 PM PST 24
Finished Mar 03 01:32:57 PM PST 24
Peak memory 199732 kb
Host smart-2283528a-a3e3-4f76-860a-2424ba90a1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182288383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3182288383
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1297106870
Short name T105
Test name
Test status
Simulation time 88988899025 ps
CPU time 242.38 seconds
Started Mar 03 01:27:17 PM PST 24
Finished Mar 03 01:31:20 PM PST 24
Peak memory 199672 kb
Host smart-b42302cb-d54c-459d-9820-79867961a27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297106870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1297106870
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_fifo_full.529342959
Short name T106
Test name
Test status
Simulation time 220663456973 ps
CPU time 55.78 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 01:28:28 PM PST 24
Peak memory 199556 kb
Host smart-17efe4bd-c9e6-4b76-bee5-b1d88d24c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529342959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.529342959
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_stress_all.3820165230
Short name T188
Test name
Test status
Simulation time 1274889568412 ps
CPU time 2100.64 seconds
Started Mar 03 01:26:27 PM PST 24
Finished Mar 03 02:01:29 PM PST 24
Peak memory 199684 kb
Host smart-0dcc3bbb-5268-4140-8ebb-4311c294175e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820165230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3820165230
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_perf.2684866985
Short name T410
Test name
Test status
Simulation time 28721251482 ps
CPU time 1300.22 seconds
Started Mar 03 01:22:56 PM PST 24
Finished Mar 03 01:44:36 PM PST 24
Peak memory 199560 kb
Host smart-a443d6e0-6f07-4d1e-9d64-5f11c2328c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684866985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2684866985
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.705900051
Short name T91
Test name
Test status
Simulation time 289217207 ps
CPU time 1.3 seconds
Started Mar 03 02:00:23 PM PST 24
Finished Mar 03 02:00:25 PM PST 24
Peak memory 199116 kb
Host smart-b107d062-44d8-4940-9c6b-9438460580c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705900051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.705900051
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_alert_test.4009807435
Short name T6
Test name
Test status
Simulation time 81715045 ps
CPU time 0.56 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:22:34 PM PST 24
Peak memory 195284 kb
Host smart-a6e89410-2a77-47f9-8a07-70d007818f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009807435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4009807435
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_perf.1820509735
Short name T399
Test name
Test status
Simulation time 31854674410 ps
CPU time 971.89 seconds
Started Mar 03 01:23:08 PM PST 24
Finished Mar 03 01:39:20 PM PST 24
Peak memory 199660 kb
Host smart-e97e5f04-6998-4bdf-8c0d-6caad4137ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820509735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1820509735
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3091114453
Short name T60
Test name
Test status
Simulation time 58105173 ps
CPU time 0.63 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 195504 kb
Host smart-5e94558d-91b4-43e2-8701-7e4503eec8df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091114453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3091114453
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1077608964
Short name T340
Test name
Test status
Simulation time 163726691660 ps
CPU time 319.4 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:30:28 PM PST 24
Peak memory 199660 kb
Host smart-a2fe833f-13f7-40a7-9645-e22ea3c2fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077608964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1077608964
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2733195216
Short name T353
Test name
Test status
Simulation time 258716274510 ps
CPU time 139.07 seconds
Started Mar 03 01:24:13 PM PST 24
Finished Mar 03 01:26:33 PM PST 24
Peak memory 199764 kb
Host smart-99c78c07-f805-47d7-91fb-e2405529b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733195216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2733195216
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1873875623
Short name T392
Test name
Test status
Simulation time 147453127781 ps
CPU time 237.14 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:26:59 PM PST 24
Peak memory 199604 kb
Host smart-c9bb4c7b-2b46-4d34-b1ce-9b46f98ab246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873875623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1873875623
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.933118354
Short name T108
Test name
Test status
Simulation time 27185861543 ps
CPU time 50.04 seconds
Started Mar 03 01:29:54 PM PST 24
Finished Mar 03 01:30:46 PM PST 24
Peak memory 199616 kb
Host smart-593ca3ef-1ca5-4695-8fb6-ab5ba9aca170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933118354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.933118354
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3776809907
Short name T88
Test name
Test status
Simulation time 39039023 ps
CPU time 0.62 seconds
Started Mar 03 02:00:23 PM PST 24
Finished Mar 03 02:00:24 PM PST 24
Peak memory 195580 kb
Host smart-ef1bdd9d-c987-4a73-9684-0acbc509d709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776809907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3776809907
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3582159016
Short name T112
Test name
Test status
Simulation time 251129780125 ps
CPU time 723.41 seconds
Started Mar 03 01:25:05 PM PST 24
Finished Mar 03 01:37:09 PM PST 24
Peak memory 214060 kb
Host smart-76968a30-cf7a-4cca-8fd0-271579e2d454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582159016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3582159016
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2078899694
Short name T135
Test name
Test status
Simulation time 26747995888 ps
CPU time 16.26 seconds
Started Mar 03 01:24:06 PM PST 24
Finished Mar 03 01:24:23 PM PST 24
Peak memory 199652 kb
Host smart-5b562119-539b-4b04-83ce-71cbdae10f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078899694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2078899694
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2106464000
Short name T175
Test name
Test status
Simulation time 79637883042 ps
CPU time 33.54 seconds
Started Mar 03 01:30:22 PM PST 24
Finished Mar 03 01:30:56 PM PST 24
Peak memory 199672 kb
Host smart-d794d2f9-d83a-45d6-82ef-dc2885aa8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106464000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2106464000
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3588798227
Short name T163
Test name
Test status
Simulation time 160970966869 ps
CPU time 151.78 seconds
Started Mar 03 01:29:40 PM PST 24
Finished Mar 03 01:32:11 PM PST 24
Peak memory 199632 kb
Host smart-981e0e0d-fe2d-46ae-914d-f400616d2214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588798227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3588798227
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3639290776
Short name T133
Test name
Test status
Simulation time 136748255055 ps
CPU time 97.87 seconds
Started Mar 03 01:30:35 PM PST 24
Finished Mar 03 01:32:13 PM PST 24
Peak memory 199528 kb
Host smart-97bec71e-b253-49f7-bfcb-a7d7f11d8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639290776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3639290776
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3201244065
Short name T206
Test name
Test status
Simulation time 144060334215 ps
CPU time 230.37 seconds
Started Mar 03 01:28:20 PM PST 24
Finished Mar 03 01:32:11 PM PST 24
Peak memory 199708 kb
Host smart-e29a023b-5537-463d-be95-ab423eda9e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201244065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3201244065
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1063961463
Short name T12
Test name
Test status
Simulation time 687670851560 ps
CPU time 708.36 seconds
Started Mar 03 01:28:35 PM PST 24
Finished Mar 03 01:40:24 PM PST 24
Peak memory 224444 kb
Host smart-ae60603a-5be6-437a-9396-12b1497643a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063961463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1063961463
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2325930005
Short name T190
Test name
Test status
Simulation time 66663586698 ps
CPU time 27.75 seconds
Started Mar 03 01:29:17 PM PST 24
Finished Mar 03 01:29:45 PM PST 24
Peak memory 199444 kb
Host smart-8cf75a7e-bccd-4be4-829a-8586744c02da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325930005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2325930005
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.221205152
Short name T303
Test name
Test status
Simulation time 234063989133 ps
CPU time 1460.79 seconds
Started Mar 03 01:26:47 PM PST 24
Finished Mar 03 01:51:08 PM PST 24
Peak memory 229672 kb
Host smart-dc5be36e-aa21-4c5b-81a4-84bbd3c0d53d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221205152 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.221205152
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1607598664
Short name T35
Test name
Test status
Simulation time 173717767143 ps
CPU time 429.45 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:35:43 PM PST 24
Peak memory 216272 kb
Host smart-b8aeeee5-b91c-4707-9cb0-0cf96e719b75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607598664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1607598664
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1528084467
Short name T31
Test name
Test status
Simulation time 71659604367 ps
CPU time 472.63 seconds
Started Mar 03 01:28:42 PM PST 24
Finished Mar 03 01:36:35 PM PST 24
Peak memory 215612 kb
Host smart-bc3780a2-f0ef-49b9-bcb8-92b3d1a9d0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528084467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1528084467
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2246035476
Short name T1176
Test name
Test status
Simulation time 52795520 ps
CPU time 0.94 seconds
Started Mar 03 02:01:05 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 198760 kb
Host smart-528fd5c1-4ae8-4d78-a17d-df9390975e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246035476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2246035476
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4159897251
Short name T201
Test name
Test status
Simulation time 174177681230 ps
CPU time 286.79 seconds
Started Mar 03 01:28:55 PM PST 24
Finished Mar 03 01:33:42 PM PST 24
Peak memory 199760 kb
Host smart-0f7ff852-57f4-43d2-80b4-7f42ab6b88c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159897251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4159897251
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1159030255
Short name T226
Test name
Test status
Simulation time 201834079011 ps
CPU time 169.48 seconds
Started Mar 03 01:29:27 PM PST 24
Finished Mar 03 01:32:17 PM PST 24
Peak memory 199544 kb
Host smart-26d3f201-c29b-490b-a123-409468156e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159030255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1159030255
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.3268374381
Short name T324
Test name
Test status
Simulation time 183995832406 ps
CPU time 273.72 seconds
Started Mar 03 01:24:55 PM PST 24
Finished Mar 03 01:29:29 PM PST 24
Peak memory 199708 kb
Host smart-2f7e1b63-b288-466b-b15a-c252d9ef8fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268374381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3268374381
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all.1495725972
Short name T235
Test name
Test status
Simulation time 300750603137 ps
CPU time 139.85 seconds
Started Mar 03 01:22:58 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 199516 kb
Host smart-e3c0f13a-c6b9-4aef-9593-d1dae907fdd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495725972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1495725972
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.597993617
Short name T116
Test name
Test status
Simulation time 463009988686 ps
CPU time 708.16 seconds
Started Mar 03 01:28:23 PM PST 24
Finished Mar 03 01:40:12 PM PST 24
Peak memory 224532 kb
Host smart-99e96cd9-f79f-4d2f-9b0f-0d4981a1982b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597993617 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.597993617
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.420491629
Short name T294
Test name
Test status
Simulation time 60850843286 ps
CPU time 77.45 seconds
Started Mar 03 01:29:32 PM PST 24
Finished Mar 03 01:30:50 PM PST 24
Peak memory 199600 kb
Host smart-ac95c089-300b-4e57-acab-1cab200ed2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420491629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.420491629
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2581128073
Short name T222
Test name
Test status
Simulation time 338443509183 ps
CPU time 82.88 seconds
Started Mar 03 01:29:34 PM PST 24
Finished Mar 03 01:30:57 PM PST 24
Peak memory 199672 kb
Host smart-3642288b-854b-454b-ba5e-fca61e82e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581128073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2581128073
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2183445072
Short name T158
Test name
Test status
Simulation time 181343014060 ps
CPU time 278.2 seconds
Started Mar 03 01:29:49 PM PST 24
Finished Mar 03 01:34:27 PM PST 24
Peak memory 199720 kb
Host smart-542a9918-99cd-4f98-b8e1-95255182623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183445072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2183445072
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.41191254
Short name T253
Test name
Test status
Simulation time 154365658424 ps
CPU time 155.46 seconds
Started Mar 03 01:22:40 PM PST 24
Finished Mar 03 01:25:18 PM PST 24
Peak memory 199572 kb
Host smart-99d5bdef-f716-4397-a7e6-7e772a4c3ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41191254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.41191254
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1772100598
Short name T57
Test name
Test status
Simulation time 40939403178 ps
CPU time 354.53 seconds
Started Mar 03 01:22:25 PM PST 24
Finished Mar 03 01:28:19 PM PST 24
Peak memory 215668 kb
Host smart-fd7355b5-a231-4932-b43e-bc5b13cc1e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772100598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1772100598
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4043935464
Short name T208
Test name
Test status
Simulation time 20567139562 ps
CPU time 16 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:22:50 PM PST 24
Peak memory 199676 kb
Host smart-a54189c2-21a1-42ce-a101-146347a5e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043935464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4043935464
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1526926697
Short name T1049
Test name
Test status
Simulation time 22797689546 ps
CPU time 21.25 seconds
Started Mar 03 01:29:05 PM PST 24
Finished Mar 03 01:29:27 PM PST 24
Peak memory 199664 kb
Host smart-dc7d6637-10c0-4197-8346-3184ce631e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526926697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1526926697
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4066606778
Short name T257
Test name
Test status
Simulation time 107367302319 ps
CPU time 182.59 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:32:22 PM PST 24
Peak memory 199684 kb
Host smart-d862b105-7313-4cce-9ac5-aa22e6193f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066606778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4066606778
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4289582770
Short name T238
Test name
Test status
Simulation time 80501435827 ps
CPU time 31.92 seconds
Started Mar 03 01:29:34 PM PST 24
Finished Mar 03 01:30:06 PM PST 24
Peak memory 199732 kb
Host smart-37fae628-b7e0-483b-8fad-92853e067326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289582770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4289582770
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1384105373
Short name T142
Test name
Test status
Simulation time 197761633004 ps
CPU time 33.07 seconds
Started Mar 03 01:29:39 PM PST 24
Finished Mar 03 01:30:12 PM PST 24
Peak memory 198012 kb
Host smart-37323e2c-a83f-4fa5-85d5-67dd38cca48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384105373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1384105373
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1613047293
Short name T321
Test name
Test status
Simulation time 29786794152 ps
CPU time 14.01 seconds
Started Mar 03 01:29:48 PM PST 24
Finished Mar 03 01:30:02 PM PST 24
Peak memory 199364 kb
Host smart-51b07940-6484-494e-b125-bddfaf968d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613047293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1613047293
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2004738672
Short name T298
Test name
Test status
Simulation time 113681259980 ps
CPU time 49.74 seconds
Started Mar 03 01:29:54 PM PST 24
Finished Mar 03 01:30:45 PM PST 24
Peak memory 199672 kb
Host smart-5f7cb8a9-439c-487f-9ff2-68fbc24ebcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004738672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2004738672
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3352301811
Short name T243
Test name
Test status
Simulation time 155631285612 ps
CPU time 56.4 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:30:59 PM PST 24
Peak memory 199740 kb
Host smart-be4492cf-a936-406f-80c5-dfd9fdc88f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352301811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3352301811
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1744345684
Short name T185
Test name
Test status
Simulation time 17637981134 ps
CPU time 31.44 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:36 PM PST 24
Peak memory 199636 kb
Host smart-acfd6cd4-a0fe-4b94-aa67-ad97cd424c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744345684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1744345684
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2561135673
Short name T240
Test name
Test status
Simulation time 109610244328 ps
CPU time 54.53 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:25:58 PM PST 24
Peak memory 199708 kb
Host smart-9d3ea45a-45b2-49d6-b735-d4686a428375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561135673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2561135673
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.748712236
Short name T280
Test name
Test status
Simulation time 207984434380 ps
CPU time 361.05 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:32:15 PM PST 24
Peak memory 199624 kb
Host smart-def2b7e9-f759-4291-bc60-27a3ffcad21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748712236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.748712236
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.737204715
Short name T302
Test name
Test status
Simulation time 40283259760 ps
CPU time 11.43 seconds
Started Mar 03 01:27:42 PM PST 24
Finished Mar 03 01:27:54 PM PST 24
Peak memory 199652 kb
Host smart-491e359b-ff2c-498f-a564-af760bcb5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737204715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.737204715
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.210665390
Short name T359
Test name
Test status
Simulation time 165202387919 ps
CPU time 126.13 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:24:41 PM PST 24
Peak memory 199608 kb
Host smart-181fa84d-39d6-4cd5-a296-e4c5e5bfe566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210665390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.210665390
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3084354352
Short name T183
Test name
Test status
Simulation time 31686535472 ps
CPU time 25.56 seconds
Started Mar 03 01:23:29 PM PST 24
Finished Mar 03 01:23:56 PM PST 24
Peak memory 198864 kb
Host smart-736027b6-dcd4-4615-83cd-66c1bf8d5ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084354352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3084354352
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.492220956
Short name T136
Test name
Test status
Simulation time 71178639203 ps
CPU time 35.11 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:24:13 PM PST 24
Peak memory 199600 kb
Host smart-f652a499-bde1-4b31-9005-3f3a0211aa16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492220956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.492220956
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.230200658
Short name T4
Test name
Test status
Simulation time 12336808581 ps
CPU time 19.48 seconds
Started Mar 03 01:29:01 PM PST 24
Finished Mar 03 01:29:20 PM PST 24
Peak memory 199632 kb
Host smart-d057d479-f7fe-4fca-942a-76c6d9f71b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230200658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.230200658
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1089667961
Short name T301
Test name
Test status
Simulation time 24233160381 ps
CPU time 33.41 seconds
Started Mar 03 01:29:02 PM PST 24
Finished Mar 03 01:29:36 PM PST 24
Peak memory 199100 kb
Host smart-00c06d24-b4c7-4f5c-8157-fd705e350d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089667961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1089667961
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2552730241
Short name T312
Test name
Test status
Simulation time 15058780671 ps
CPU time 6.84 seconds
Started Mar 03 01:29:02 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199104 kb
Host smart-3c3a9c2e-9980-4f26-96d8-d9df1016dde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552730241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2552730241
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.418973802
Short name T5
Test name
Test status
Simulation time 29517190567 ps
CPU time 26.18 seconds
Started Mar 03 01:29:02 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199716 kb
Host smart-09f6dc27-b7b2-44c3-bb23-8be2d155e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418973802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.418973802
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2137086569
Short name T130
Test name
Test status
Simulation time 27182489256 ps
CPU time 15 seconds
Started Mar 03 01:29:11 PM PST 24
Finished Mar 03 01:29:26 PM PST 24
Peak memory 199652 kb
Host smart-64352edf-377c-41d4-be44-55475238a922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137086569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2137086569
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4133888110
Short name T715
Test name
Test status
Simulation time 103985906053 ps
CPU time 102.24 seconds
Started Mar 03 01:29:17 PM PST 24
Finished Mar 03 01:31:00 PM PST 24
Peak memory 199748 kb
Host smart-f57ff838-3b14-487b-95d5-2d3beebc65a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133888110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4133888110
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.324586035
Short name T229
Test name
Test status
Simulation time 26093885385 ps
CPU time 20.25 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:24:34 PM PST 24
Peak memory 199604 kb
Host smart-3435e0cc-57cd-418d-b339-73acd72cd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324586035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.324586035
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3758560352
Short name T304
Test name
Test status
Simulation time 99893784915 ps
CPU time 86.45 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:26:04 PM PST 24
Peak memory 199720 kb
Host smart-f7fd37eb-c5a4-486e-b7de-a9d150c624fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758560352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3758560352
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2177053599
Short name T358
Test name
Test status
Simulation time 40338789410 ps
CPU time 40.82 seconds
Started Mar 03 01:29:54 PM PST 24
Finished Mar 03 01:30:36 PM PST 24
Peak memory 199732 kb
Host smart-8e1f3225-ab9f-4d14-af0f-1d9234d1f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177053599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2177053599
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.302904181
Short name T273
Test name
Test status
Simulation time 117246836942 ps
CPU time 89.29 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:31:32 PM PST 24
Peak memory 199600 kb
Host smart-5fd2a131-877b-4738-aa3d-3551b254bf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302904181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.302904181
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.148470006
Short name T212
Test name
Test status
Simulation time 172940959152 ps
CPU time 72.05 seconds
Started Mar 03 01:30:00 PM PST 24
Finished Mar 03 01:31:14 PM PST 24
Peak memory 199564 kb
Host smart-df1fd700-5210-45dd-a29d-204a9b6c540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148470006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.148470006
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1902611737
Short name T251
Test name
Test status
Simulation time 94420595827 ps
CPU time 29.32 seconds
Started Mar 03 01:30:09 PM PST 24
Finished Mar 03 01:30:38 PM PST 24
Peak memory 199556 kb
Host smart-3b78cf03-e5c4-4b37-831b-110647455bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902611737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1902611737
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3068632840
Short name T186
Test name
Test status
Simulation time 147138157579 ps
CPU time 23.01 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:30:40 PM PST 24
Peak memory 199632 kb
Host smart-88235bec-5b74-4bda-8c4c-6c9e3b587fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068632840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3068632840
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4213479819
Short name T278
Test name
Test status
Simulation time 65278486751 ps
CPU time 28.86 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:25:35 PM PST 24
Peak memory 199440 kb
Host smart-bdf45230-350d-4dc9-a3a7-4d2fa0976a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213479819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4213479819
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1920392303
Short name T271
Test name
Test status
Simulation time 59451557952 ps
CPU time 25.66 seconds
Started Mar 03 01:30:19 PM PST 24
Finished Mar 03 01:30:44 PM PST 24
Peak memory 199372 kb
Host smart-6b069391-e1ec-4c66-b825-3b35b604b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920392303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1920392303
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1574857342
Short name T248
Test name
Test status
Simulation time 82094210672 ps
CPU time 66.41 seconds
Started Mar 03 01:30:35 PM PST 24
Finished Mar 03 01:31:42 PM PST 24
Peak memory 199612 kb
Host smart-a543588f-cacd-4818-b404-a556d54e7ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574857342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1574857342
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.387133851
Short name T218
Test name
Test status
Simulation time 11413886221 ps
CPU time 40.04 seconds
Started Mar 03 01:30:51 PM PST 24
Finished Mar 03 01:31:32 PM PST 24
Peak memory 199588 kb
Host smart-f7292b2e-b13c-485b-8cf4-c13441a09d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387133851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.387133851
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3895150340
Short name T367
Test name
Test status
Simulation time 8363151833 ps
CPU time 7.97 seconds
Started Mar 03 01:30:52 PM PST 24
Finished Mar 03 01:31:00 PM PST 24
Peak memory 199540 kb
Host smart-d668d1f3-c834-419d-95e1-ff4ade6e8e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895150340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3895150340
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3588141322
Short name T14
Test name
Test status
Simulation time 30259629592 ps
CPU time 15.19 seconds
Started Mar 03 01:30:52 PM PST 24
Finished Mar 03 01:31:08 PM PST 24
Peak memory 197976 kb
Host smart-2d5ba133-6ec5-43da-bd47-de9819e16c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588141322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3588141322
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1962317552
Short name T284
Test name
Test status
Simulation time 339503097094 ps
CPU time 2365.29 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 02:08:00 PM PST 24
Peak memory 240848 kb
Host smart-49ee14b2-513c-49a7-9429-85b0b37621d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962317552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1962317552
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.739849744
Short name T866
Test name
Test status
Simulation time 156716189368 ps
CPU time 95.39 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:24:02 PM PST 24
Peak memory 199556 kb
Host smart-7796dadb-eda4-47e3-82f5-cc6da519e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739849744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.739849744
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3540351256
Short name T381
Test name
Test status
Simulation time 209579432613 ps
CPU time 61.31 seconds
Started Mar 03 01:22:32 PM PST 24
Finished Mar 03 01:23:34 PM PST 24
Peak memory 199672 kb
Host smart-20f3ef6d-a8cc-4196-ab69-bd352a9c85f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540351256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3540351256
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3650221928
Short name T171
Test name
Test status
Simulation time 57984069291 ps
CPU time 26.43 seconds
Started Mar 03 01:23:35 PM PST 24
Finished Mar 03 01:24:02 PM PST 24
Peak memory 199760 kb
Host smart-af935298-14f6-4b03-9bf5-85e45729747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650221928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3650221928
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3487132663
Short name T209
Test name
Test status
Simulation time 86379613928 ps
CPU time 409.07 seconds
Started Mar 03 01:28:55 PM PST 24
Finished Mar 03 01:35:45 PM PST 24
Peak memory 199680 kb
Host smart-44c532ef-d555-468f-8182-eef80e0540b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487132663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3487132663
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2791447647
Short name T265
Test name
Test status
Simulation time 30061691311 ps
CPU time 42.68 seconds
Started Mar 03 01:28:58 PM PST 24
Finished Mar 03 01:29:41 PM PST 24
Peak memory 199624 kb
Host smart-5a1e3eee-b53b-4a20-b157-e2be8757b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791447647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2791447647
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2163373096
Short name T37
Test name
Test status
Simulation time 28969863266 ps
CPU time 46.62 seconds
Started Mar 03 01:23:36 PM PST 24
Finished Mar 03 01:24:24 PM PST 24
Peak memory 199656 kb
Host smart-79710c58-f797-4d76-81d7-07862ea1c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163373096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2163373096
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2564263257
Short name T370
Test name
Test status
Simulation time 110697304808 ps
CPU time 186.65 seconds
Started Mar 03 01:29:04 PM PST 24
Finished Mar 03 01:32:11 PM PST 24
Peak memory 199612 kb
Host smart-a0df7fe3-0eba-487b-a527-95bb8e759d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564263257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2564263257
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2881954538
Short name T286
Test name
Test status
Simulation time 15068349396 ps
CPU time 8.21 seconds
Started Mar 03 01:29:13 PM PST 24
Finished Mar 03 01:29:22 PM PST 24
Peak memory 199676 kb
Host smart-78da899d-b268-4f29-8e00-16c63bf466a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881954538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2881954538
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3757669578
Short name T249
Test name
Test status
Simulation time 133938057334 ps
CPU time 155.86 seconds
Started Mar 03 01:24:02 PM PST 24
Finished Mar 03 01:26:39 PM PST 24
Peak memory 199644 kb
Host smart-e3b9389e-29e2-482e-bfc0-c30b896e99d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757669578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3757669578
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.836891537
Short name T318
Test name
Test status
Simulation time 122409149103 ps
CPU time 52.91 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:30:11 PM PST 24
Peak memory 199632 kb
Host smart-525b86a3-60b4-4d9f-9c45-094419fa7742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836891537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.836891537
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.804148719
Short name T258
Test name
Test status
Simulation time 44869566089 ps
CPU time 9.55 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199212 kb
Host smart-187e7833-3d4b-4338-9348-ec573eaf6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804148719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.804148719
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.251553499
Short name T293
Test name
Test status
Simulation time 224389684912 ps
CPU time 93.57 seconds
Started Mar 03 01:29:34 PM PST 24
Finished Mar 03 01:31:08 PM PST 24
Peak memory 199588 kb
Host smart-cbe28c74-3c1b-4e02-8e1a-2cad058723ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251553499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.251553499
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2947847864
Short name T327
Test name
Test status
Simulation time 10859248711 ps
CPU time 19.09 seconds
Started Mar 03 01:29:41 PM PST 24
Finished Mar 03 01:30:00 PM PST 24
Peak memory 199548 kb
Host smart-1e9cff13-6d4f-4158-ae05-11e974c53113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947847864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2947847864
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4094400501
Short name T297
Test name
Test status
Simulation time 180474724657 ps
CPU time 348.45 seconds
Started Mar 03 01:29:49 PM PST 24
Finished Mar 03 01:35:37 PM PST 24
Peak memory 199636 kb
Host smart-b9d58bb5-b580-42be-a87a-49ca1ee5c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094400501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4094400501
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2615933347
Short name T334
Test name
Test status
Simulation time 173312171877 ps
CPU time 43.41 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:25:22 PM PST 24
Peak memory 199632 kb
Host smart-94537a3c-34de-4071-bab3-44d226324526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615933347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2615933347
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3768985437
Short name T307
Test name
Test status
Simulation time 73136294362 ps
CPU time 21.29 seconds
Started Mar 03 01:29:56 PM PST 24
Finished Mar 03 01:30:18 PM PST 24
Peak memory 199692 kb
Host smart-ef395004-55fd-4c6b-b8ae-feb44e783f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768985437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3768985437
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3943742286
Short name T371
Test name
Test status
Simulation time 40535384120 ps
CPU time 63.25 seconds
Started Mar 03 01:29:53 PM PST 24
Finished Mar 03 01:30:58 PM PST 24
Peak memory 199192 kb
Host smart-405319f0-e276-467e-a10c-7c2e4626eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943742286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3943742286
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1632403024
Short name T132
Test name
Test status
Simulation time 41483026117 ps
CPU time 14.75 seconds
Started Mar 03 01:29:57 PM PST 24
Finished Mar 03 01:30:12 PM PST 24
Peak memory 198808 kb
Host smart-c0543980-14ff-4af8-b409-08fe3ed1bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632403024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1632403024
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.137586830
Short name T380
Test name
Test status
Simulation time 61205106072 ps
CPU time 35.2 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:23:08 PM PST 24
Peak memory 199692 kb
Host smart-2fef2501-8cbd-4708-8586-8549ffe9bfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137586830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.137586830
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2622112212
Short name T300
Test name
Test status
Simulation time 96996571270 ps
CPU time 85.7 seconds
Started Mar 03 01:24:52 PM PST 24
Finished Mar 03 01:26:18 PM PST 24
Peak memory 199460 kb
Host smart-41554958-3e6f-411f-be5e-ae341ee7915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622112212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2622112212
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3687791909
Short name T346
Test name
Test status
Simulation time 95222683133 ps
CPU time 81.94 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:31:24 PM PST 24
Peak memory 199692 kb
Host smart-477c82d1-2152-4c5e-ac9c-f36e9135c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687791909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3687791909
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.816644069
Short name T77
Test name
Test status
Simulation time 234044591892 ps
CPU time 375.43 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:31:19 PM PST 24
Peak memory 199524 kb
Host smart-109d182a-fe76-473e-97e1-c9389a286386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816644069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.816644069
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2537639701
Short name T338
Test name
Test status
Simulation time 7450321297 ps
CPU time 8.15 seconds
Started Mar 03 01:30:08 PM PST 24
Finished Mar 03 01:30:16 PM PST 24
Peak memory 199592 kb
Host smart-926c7b4a-4510-48b0-a355-f39fe1e054f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537639701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2537639701
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1086086600
Short name T166
Test name
Test status
Simulation time 71592363956 ps
CPU time 55.35 seconds
Started Mar 03 01:30:09 PM PST 24
Finished Mar 03 01:31:05 PM PST 24
Peak memory 199604 kb
Host smart-6e7ded57-2514-46ea-a70f-0a572d00da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086086600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1086086600
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3396617668
Short name T386
Test name
Test status
Simulation time 105332860294 ps
CPU time 181.06 seconds
Started Mar 03 01:30:10 PM PST 24
Finished Mar 03 01:33:12 PM PST 24
Peak memory 199640 kb
Host smart-090355e9-f982-4699-9970-26f4d65c202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396617668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3396617668
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.582564994
Short name T335
Test name
Test status
Simulation time 28847151339 ps
CPU time 46.83 seconds
Started Mar 03 01:30:16 PM PST 24
Finished Mar 03 01:31:02 PM PST 24
Peak memory 199684 kb
Host smart-f8417694-0246-4069-a1e6-3a268facf0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582564994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.582564994
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4266597884
Short name T355
Test name
Test status
Simulation time 6126779002 ps
CPU time 71.4 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:26:20 PM PST 24
Peak memory 199708 kb
Host smart-3de7bb31-7595-40aa-b6c2-80cff5b8f6b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266597884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4266597884
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3178719979
Short name T361
Test name
Test status
Simulation time 84282545335 ps
CPU time 91.13 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:31:48 PM PST 24
Peak memory 199660 kb
Host smart-2bd1c7b6-41a2-4ab4-8a3b-d83ff6d47c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178719979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3178719979
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3899968087
Short name T291
Test name
Test status
Simulation time 104907024312 ps
CPU time 225.96 seconds
Started Mar 03 01:30:16 PM PST 24
Finished Mar 03 01:34:02 PM PST 24
Peak memory 199668 kb
Host smart-bf154e84-b5be-43b0-88e5-186d28eaa36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899968087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3899968087
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3717051933
Short name T309
Test name
Test status
Simulation time 31387178070 ps
CPU time 29.26 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:30:47 PM PST 24
Peak memory 199668 kb
Host smart-1335ce3c-cb38-49ff-b39b-c4e649b86698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717051933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3717051933
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3537862451
Short name T231
Test name
Test status
Simulation time 34651259907 ps
CPU time 68.18 seconds
Started Mar 03 01:30:32 PM PST 24
Finished Mar 03 01:31:40 PM PST 24
Peak memory 199688 kb
Host smart-d7c1a812-9411-4a9d-8b31-847a086e1379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537862451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3537862451
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3811526929
Short name T137
Test name
Test status
Simulation time 33468321308 ps
CPU time 50.41 seconds
Started Mar 03 01:30:28 PM PST 24
Finished Mar 03 01:31:19 PM PST 24
Peak memory 199568 kb
Host smart-1907e5ae-1365-4bc9-a832-4d342e44b690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811526929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3811526929
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1478735565
Short name T388
Test name
Test status
Simulation time 142299146251 ps
CPU time 52.8 seconds
Started Mar 03 01:25:22 PM PST 24
Finished Mar 03 01:26:15 PM PST 24
Peak memory 198676 kb
Host smart-462c7690-6391-4ed0-a790-07f71a0ccc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478735565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1478735565
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1611496137
Short name T184
Test name
Test status
Simulation time 62237328563 ps
CPU time 27.47 seconds
Started Mar 03 01:25:31 PM PST 24
Finished Mar 03 01:26:00 PM PST 24
Peak memory 199624 kb
Host smart-648a4039-0374-4004-9af1-aaec1428dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611496137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1611496137
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3259189679
Short name T354
Test name
Test status
Simulation time 67068654422 ps
CPU time 48.33 seconds
Started Mar 03 01:30:28 PM PST 24
Finished Mar 03 01:31:16 PM PST 24
Peak memory 199684 kb
Host smart-f9a726cc-b65c-4538-8bd0-037073d8272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259189679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3259189679
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3306422958
Short name T360
Test name
Test status
Simulation time 186362095278 ps
CPU time 37.77 seconds
Started Mar 03 01:30:51 PM PST 24
Finished Mar 03 01:31:29 PM PST 24
Peak memory 199624 kb
Host smart-de47a8ea-6af6-4d1f-952a-537055ec81fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306422958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3306422958
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4011515137
Short name T50
Test name
Test status
Simulation time 63468230001 ps
CPU time 83.04 seconds
Started Mar 03 01:26:33 PM PST 24
Finished Mar 03 01:27:56 PM PST 24
Peak memory 199568 kb
Host smart-85d963ab-02b9-477c-9db1-1c8b969fe59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011515137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4011515137
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3319688940
Short name T332
Test name
Test status
Simulation time 157101685199 ps
CPU time 32.4 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:27:30 PM PST 24
Peak memory 199312 kb
Host smart-fddfcea4-e838-49f3-bacf-b20e2df8ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319688940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3319688940
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2556130481
Short name T40
Test name
Test status
Simulation time 193256102256 ps
CPU time 280.2 seconds
Started Mar 03 01:27:45 PM PST 24
Finished Mar 03 01:32:25 PM PST 24
Peak memory 199648 kb
Host smart-3775c97b-4bda-44f4-83be-d7ad3e444adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556130481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2556130481
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.247816785
Short name T232
Test name
Test status
Simulation time 45844550386 ps
CPU time 20.14 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:28:26 PM PST 24
Peak memory 199724 kb
Host smart-6c76d13f-8b89-4510-8f4d-f3313d324230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247816785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.247816785
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.879355272
Short name T272
Test name
Test status
Simulation time 32011560744 ps
CPU time 54.65 seconds
Started Mar 03 01:28:14 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199688 kb
Host smart-85613004-8c8d-40f3-8721-cb720f03edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879355272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.879355272
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2091741611
Short name T326
Test name
Test status
Simulation time 35503428870 ps
CPU time 56.49 seconds
Started Mar 03 01:28:19 PM PST 24
Finished Mar 03 01:29:16 PM PST 24
Peak memory 199640 kb
Host smart-0a78be63-78e3-40bd-ab21-669d2eb81a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091741611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2091741611
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3725914214
Short name T305
Test name
Test status
Simulation time 122768664235 ps
CPU time 763.04 seconds
Started Mar 03 01:23:00 PM PST 24
Finished Mar 03 01:35:44 PM PST 24
Peak memory 199600 kb
Host smart-4f179436-0dc8-4fee-9bc9-5f378f553aa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725914214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3725914214
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2577784212
Short name T237
Test name
Test status
Simulation time 75570736317 ps
CPU time 117.81 seconds
Started Mar 03 01:28:32 PM PST 24
Finished Mar 03 01:30:30 PM PST 24
Peak memory 199564 kb
Host smart-d01888e0-8844-41d2-9413-af848155544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577784212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2577784212
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2789219000
Short name T65
Test name
Test status
Simulation time 33183504 ps
CPU time 0.79 seconds
Started Mar 03 02:00:21 PM PST 24
Finished Mar 03 02:00:24 PM PST 24
Peak memory 196296 kb
Host smart-14628af9-401d-4c0b-b116-7a27404c5ebc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789219000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2789219000
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.982087472
Short name T1129
Test name
Test status
Simulation time 504822010 ps
CPU time 2.64 seconds
Started Mar 03 02:00:22 PM PST 24
Finished Mar 03 02:00:26 PM PST 24
Peak memory 197828 kb
Host smart-cc8b98c8-ae22-47a7-b47b-6df67ed1b092
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982087472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.982087472
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.175026984
Short name T1153
Test name
Test status
Simulation time 163113546 ps
CPU time 0.6 seconds
Started Mar 03 02:00:22 PM PST 24
Finished Mar 03 02:00:24 PM PST 24
Peak memory 195492 kb
Host smart-d95a23f2-72e9-4916-837a-4fa99c3f1a63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175026984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.175026984
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1870485231
Short name T1150
Test name
Test status
Simulation time 160239579 ps
CPU time 0.83 seconds
Started Mar 03 02:00:23 PM PST 24
Finished Mar 03 02:00:25 PM PST 24
Peak memory 199268 kb
Host smart-1e736414-6481-4a81-a3df-875c729788df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870485231 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1870485231
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1877427470
Short name T64
Test name
Test status
Simulation time 17717769 ps
CPU time 0.6 seconds
Started Mar 03 02:00:21 PM PST 24
Finished Mar 03 02:00:23 PM PST 24
Peak memory 195492 kb
Host smart-c2df71ef-3d8a-436b-90aa-0d2e67f4310f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877427470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1877427470
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.97444223
Short name T1201
Test name
Test status
Simulation time 37661103 ps
CPU time 0.54 seconds
Started Mar 03 02:00:20 PM PST 24
Finished Mar 03 02:00:21 PM PST 24
Peak memory 194372 kb
Host smart-c4804ecd-5663-42c7-b041-068557463f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97444223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.97444223
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2493603471
Short name T1204
Test name
Test status
Simulation time 347412456 ps
CPU time 1.83 seconds
Started Mar 03 02:00:23 PM PST 24
Finished Mar 03 02:00:25 PM PST 24
Peak memory 200132 kb
Host smart-1496fe77-b325-4d03-9e83-8fb8f9cc0995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493603471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2493603471
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.808619452
Short name T70
Test name
Test status
Simulation time 30580925 ps
CPU time 0.76 seconds
Started Mar 03 02:00:27 PM PST 24
Finished Mar 03 02:00:28 PM PST 24
Peak memory 196288 kb
Host smart-a626a97e-aa31-41fe-8685-890ab9f2eccf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808619452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.808619452
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3764769444
Short name T69
Test name
Test status
Simulation time 70730983 ps
CPU time 1.38 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 197528 kb
Host smart-18fadc5c-db0f-4e62-8a52-699d6a8e8688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764769444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3764769444
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.515207634
Short name T63
Test name
Test status
Simulation time 22349549 ps
CPU time 0.57 seconds
Started Mar 03 02:00:27 PM PST 24
Finished Mar 03 02:00:28 PM PST 24
Peak memory 195484 kb
Host smart-5d69aeb6-a9ea-4c6b-8a55-45e50be4a2c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515207634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.515207634
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.904254623
Short name T1111
Test name
Test status
Simulation time 143507894 ps
CPU time 0.69 seconds
Started Mar 03 02:00:27 PM PST 24
Finished Mar 03 02:00:28 PM PST 24
Peak memory 197412 kb
Host smart-e3169c62-47e4-42fb-bba9-a62f16676dc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904254623 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.904254623
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3169434144
Short name T84
Test name
Test status
Simulation time 48915721 ps
CPU time 0.61 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 195480 kb
Host smart-6e526d8b-cc07-4ac2-a7dc-015d217d8613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169434144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3169434144
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1243615500
Short name T1146
Test name
Test status
Simulation time 12430182 ps
CPU time 0.57 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:28 PM PST 24
Peak memory 185128 kb
Host smart-3f55c378-f94c-4dd5-aa03-e313624f6225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243615500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1243615500
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2844439469
Short name T83
Test name
Test status
Simulation time 31601226 ps
CPU time 0.71 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 196856 kb
Host smart-8030f1c0-762d-4409-9884-dd595663d052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844439469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2844439469
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.528977595
Short name T1183
Test name
Test status
Simulation time 624485226 ps
CPU time 1.43 seconds
Started Mar 03 02:00:21 PM PST 24
Finished Mar 03 02:00:24 PM PST 24
Peak memory 200172 kb
Host smart-79fbc8d3-919e-4b99-a95d-1b0757b27e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528977595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.528977595
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.45754466
Short name T94
Test name
Test status
Simulation time 119534952 ps
CPU time 1.35 seconds
Started Mar 03 02:00:26 PM PST 24
Finished Mar 03 02:00:28 PM PST 24
Peak memory 199164 kb
Host smart-973055eb-ecf2-45d7-a512-67d7473be936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45754466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.45754466
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1323161339
Short name T1130
Test name
Test status
Simulation time 59602062 ps
CPU time 0.86 seconds
Started Mar 03 02:01:08 PM PST 24
Finished Mar 03 02:01:09 PM PST 24
Peak memory 199956 kb
Host smart-2bb876df-7369-4df9-a075-6677e3362503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323161339 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1323161339
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1213645237
Short name T1212
Test name
Test status
Simulation time 111480531 ps
CPU time 0.6 seconds
Started Mar 03 02:00:59 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 195476 kb
Host smart-591de9d9-304e-487e-89ed-ac5421bce2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213645237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1213645237
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.427316056
Short name T1174
Test name
Test status
Simulation time 36912149 ps
CPU time 0.57 seconds
Started Mar 03 02:00:58 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 185192 kb
Host smart-1d7d2456-5587-436c-a9a8-04301ae05df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427316056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.427316056
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2613803097
Short name T1179
Test name
Test status
Simulation time 28681299 ps
CPU time 0.72 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 197056 kb
Host smart-9305823a-b294-4de1-8adc-dc2fa813fa63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613803097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2613803097
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3367041355
Short name T1180
Test name
Test status
Simulation time 53096924 ps
CPU time 1.54 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:01:00 PM PST 24
Peak memory 200068 kb
Host smart-8c6ce591-a31d-4426-9204-70a1453fea05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367041355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3367041355
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2945236299
Short name T98
Test name
Test status
Simulation time 50974875 ps
CPU time 0.95 seconds
Started Mar 03 02:00:58 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 198652 kb
Host smart-2c4c0b83-5d1f-478d-82ca-aca93dd12214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945236299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2945236299
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1785873378
Short name T1206
Test name
Test status
Simulation time 36327751 ps
CPU time 1.08 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:10 PM PST 24
Peak memory 200084 kb
Host smart-e9947c44-c63b-4970-8748-45e22724d2ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785873378 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1785873378
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1036597575
Short name T1142
Test name
Test status
Simulation time 17985279 ps
CPU time 0.61 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 195552 kb
Host smart-4131bbd9-14cb-4d53-9fc0-3750508b0c88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036597575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1036597575
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.84170696
Short name T1168
Test name
Test status
Simulation time 21269340 ps
CPU time 0.58 seconds
Started Mar 03 02:01:08 PM PST 24
Finished Mar 03 02:01:09 PM PST 24
Peak memory 185256 kb
Host smart-10c0a086-c799-4a37-a751-f09f068d81a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84170696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.84170696
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3226798025
Short name T1143
Test name
Test status
Simulation time 16520377 ps
CPU time 0.67 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 195564 kb
Host smart-ccf54df3-7b2f-4d64-b7f2-4f251e0fe3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226798025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3226798025
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3583735672
Short name T1169
Test name
Test status
Simulation time 70671224 ps
CPU time 1.74 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 200132 kb
Host smart-155a849b-5d9d-4a40-874c-bf0efd9042df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583735672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3583735672
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1868763872
Short name T1178
Test name
Test status
Simulation time 36715278 ps
CPU time 0.92 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:10 PM PST 24
Peak memory 199988 kb
Host smart-fefadb2b-e280-45af-bae8-2809c9c1ee65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868763872 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1868763872
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.278052953
Short name T1195
Test name
Test status
Simulation time 140458689 ps
CPU time 0.59 seconds
Started Mar 03 02:01:03 PM PST 24
Finished Mar 03 02:01:04 PM PST 24
Peak memory 195324 kb
Host smart-2d2665b8-e10a-4ac6-8ef8-a51e2e00e14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278052953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.278052953
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1246150306
Short name T1225
Test name
Test status
Simulation time 36379364 ps
CPU time 0.56 seconds
Started Mar 03 02:01:04 PM PST 24
Finished Mar 03 02:01:04 PM PST 24
Peak memory 185268 kb
Host smart-d2594532-c00b-452c-a5b2-d4043b983735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246150306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1246150306
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1199375000
Short name T85
Test name
Test status
Simulation time 86955959 ps
CPU time 0.63 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 195692 kb
Host smart-045c1bcf-9e77-46a5-9ef6-1df0b1aac32a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199375000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1199375000
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4016335916
Short name T1124
Test name
Test status
Simulation time 29902963 ps
CPU time 1.73 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 200072 kb
Host smart-db917f7d-e06a-4495-afb6-a0a834354fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016335916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4016335916
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3321029242
Short name T1136
Test name
Test status
Simulation time 67049984 ps
CPU time 0.97 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 198572 kb
Host smart-4f5d415f-4369-4135-a0e0-d308ec2051fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321029242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3321029242
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.376359481
Short name T1116
Test name
Test status
Simulation time 313590557 ps
CPU time 1.11 seconds
Started Mar 03 02:01:05 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 200060 kb
Host smart-a8143fef-c706-463f-bbe2-8a262e07abfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376359481 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.376359481
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2240154226
Short name T1226
Test name
Test status
Simulation time 47668975 ps
CPU time 0.59 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:10 PM PST 24
Peak memory 195376 kb
Host smart-930c476b-1181-4de3-ab45-1a1219fbf39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240154226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2240154226
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2377669101
Short name T1230
Test name
Test status
Simulation time 42551941 ps
CPU time 0.57 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 194492 kb
Host smart-ae99af8b-4c1f-4c14-b1d4-19ebc997c49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377669101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2377669101
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.168839913
Short name T81
Test name
Test status
Simulation time 24456129 ps
CPU time 0.64 seconds
Started Mar 03 02:01:05 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 196724 kb
Host smart-93905f8e-1eab-4248-baee-88a477d49f9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168839913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.168839913
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4273172179
Short name T1221
Test name
Test status
Simulation time 109557442 ps
CPU time 1.61 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:11 PM PST 24
Peak memory 200124 kb
Host smart-b5c0a773-6d74-4096-aced-1f74b8c1b1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273172179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4273172179
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3984587533
Short name T1217
Test name
Test status
Simulation time 99349557 ps
CPU time 1.36 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 199192 kb
Host smart-a63f2955-07bb-44c6-9683-b5f155a413f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984587533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3984587533
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1267358547
Short name T1223
Test name
Test status
Simulation time 49727762 ps
CPU time 1.31 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 200100 kb
Host smart-31f9b5b4-997a-424b-a812-29081bceb80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267358547 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1267358547
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.457413945
Short name T1171
Test name
Test status
Simulation time 23417244 ps
CPU time 0.6 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 195432 kb
Host smart-9ab8cc15-a09a-4ba6-b31e-bfaab72b2b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457413945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.457413945
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.352525938
Short name T1125
Test name
Test status
Simulation time 17886226 ps
CPU time 0.61 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 185240 kb
Host smart-0f672830-f6b0-436c-8ccc-fe7b90ae8b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352525938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.352525938
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2331193309
Short name T87
Test name
Test status
Simulation time 120519043 ps
CPU time 0.77 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 197036 kb
Host smart-51270c2e-7331-4f9e-8c3f-77927005eb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331193309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2331193309
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2475710489
Short name T1228
Test name
Test status
Simulation time 60750266 ps
CPU time 1.64 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:11 PM PST 24
Peak memory 200044 kb
Host smart-02235c3a-5c7d-4c00-b860-c36345b4d877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475710489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2475710489
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4280622207
Short name T1227
Test name
Test status
Simulation time 200724209 ps
CPU time 0.94 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:07 PM PST 24
Peak memory 198880 kb
Host smart-a5c7ec0b-6967-4d9f-87d3-cc4fc55e1763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280622207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4280622207
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2500385463
Short name T1200
Test name
Test status
Simulation time 49623485 ps
CPU time 0.76 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 197484 kb
Host smart-c5ffcf83-8b16-4b84-96db-b11b05b51e39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500385463 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2500385463
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.302082101
Short name T1220
Test name
Test status
Simulation time 24020663 ps
CPU time 0.6 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 185252 kb
Host smart-2e1b19b0-5ef8-4da4-81b4-50664b218970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302082101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.302082101
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1876485527
Short name T86
Test name
Test status
Simulation time 31557241 ps
CPU time 0.66 seconds
Started Mar 03 02:01:05 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 195884 kb
Host smart-d45aa551-5402-4551-b998-9a5a108a4568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876485527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1876485527
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4251540873
Short name T1115
Test name
Test status
Simulation time 38943329 ps
CPU time 1.16 seconds
Started Mar 03 02:01:06 PM PST 24
Finished Mar 03 02:01:08 PM PST 24
Peak memory 199976 kb
Host smart-509f72ab-babc-4037-ba5b-1d908bf215da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251540873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4251540873
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.791947075
Short name T1190
Test name
Test status
Simulation time 661630108 ps
CPU time 0.93 seconds
Started Mar 03 02:01:05 PM PST 24
Finished Mar 03 02:01:06 PM PST 24
Peak memory 199020 kb
Host smart-bc11de07-7238-4eed-bce1-d48f4cc70d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791947075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.791947075
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1005930557
Short name T1151
Test name
Test status
Simulation time 22237469 ps
CPU time 1.09 seconds
Started Mar 03 02:01:11 PM PST 24
Finished Mar 03 02:01:12 PM PST 24
Peak memory 199980 kb
Host smart-5ef6a9b9-e1a8-4705-b901-e9baae84224b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005930557 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1005930557
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1359227597
Short name T1205
Test name
Test status
Simulation time 17371384 ps
CPU time 0.61 seconds
Started Mar 03 02:01:11 PM PST 24
Finished Mar 03 02:01:12 PM PST 24
Peak memory 195484 kb
Host smart-df475a62-56e0-44de-b0c4-6b77d8aa8a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359227597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1359227597
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2759800884
Short name T1218
Test name
Test status
Simulation time 13836529 ps
CPU time 0.65 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:13 PM PST 24
Peak memory 194484 kb
Host smart-58a0528f-b09f-4e09-ad79-1d50fca2a99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759800884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2759800884
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2766681699
Short name T1192
Test name
Test status
Simulation time 72076326 ps
CPU time 0.72 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:14 PM PST 24
Peak memory 194884 kb
Host smart-f748cfa4-5578-4605-bcac-55b9e996a29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766681699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2766681699
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.385943542
Short name T1155
Test name
Test status
Simulation time 606999025 ps
CPU time 1.81 seconds
Started Mar 03 02:01:07 PM PST 24
Finished Mar 03 02:01:09 PM PST 24
Peak memory 200064 kb
Host smart-9c542118-1788-4fd1-a6b2-b4b8f2cfd879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385943542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.385943542
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3361063960
Short name T1187
Test name
Test status
Simulation time 360091383 ps
CPU time 1.32 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:13 PM PST 24
Peak memory 199000 kb
Host smart-87d6523f-e24e-4f22-8f6d-019815730a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361063960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3361063960
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.521294478
Short name T1112
Test name
Test status
Simulation time 81026456 ps
CPU time 1.1 seconds
Started Mar 03 02:01:14 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 199936 kb
Host smart-33a1ad5c-bb09-406d-acf3-4a49e48fdbb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521294478 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.521294478
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3422465887
Short name T59
Test name
Test status
Simulation time 24041200 ps
CPU time 0.57 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:14 PM PST 24
Peak memory 195460 kb
Host smart-76ed972f-1952-4471-a6da-2a03f74f1077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422465887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3422465887
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2721756335
Short name T1208
Test name
Test status
Simulation time 12391815 ps
CPU time 0.61 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:13 PM PST 24
Peak memory 194484 kb
Host smart-34fcd903-6302-4bb3-9249-f5b509089294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721756335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2721756335
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.960706811
Short name T1219
Test name
Test status
Simulation time 110396936 ps
CPU time 0.77 seconds
Started Mar 03 02:01:10 PM PST 24
Finished Mar 03 02:01:11 PM PST 24
Peak memory 197588 kb
Host smart-6345230f-0dc6-4bc8-aa06-4a3e2ae12429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960706811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.960706811
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3849077446
Short name T1199
Test name
Test status
Simulation time 119831092 ps
CPU time 1.28 seconds
Started Mar 03 02:01:14 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 200136 kb
Host smart-4472f7de-caae-406f-a2ea-9d872998958b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849077446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3849077446
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.966495701
Short name T1188
Test name
Test status
Simulation time 261287558 ps
CPU time 1.27 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 199144 kb
Host smart-8b4f2c51-d8b3-4b6f-b098-771b98a21ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966495701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.966495701
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2880054546
Short name T1152
Test name
Test status
Simulation time 18289957 ps
CPU time 0.81 seconds
Started Mar 03 02:01:14 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 199540 kb
Host smart-2a3d64da-d41f-40db-a1e5-61ad070bdf5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880054546 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2880054546
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.349071768
Short name T1184
Test name
Test status
Simulation time 102494850 ps
CPU time 0.59 seconds
Started Mar 03 02:01:11 PM PST 24
Finished Mar 03 02:01:11 PM PST 24
Peak memory 195432 kb
Host smart-fe99d9a3-f45f-4e9a-99c9-58c2f0870151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349071768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.349071768
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1717267536
Short name T1139
Test name
Test status
Simulation time 36043512 ps
CPU time 0.58 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:14 PM PST 24
Peak memory 194448 kb
Host smart-aa729929-2ff6-491a-91e3-b5c794edfb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717267536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1717267536
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2780347284
Short name T1186
Test name
Test status
Simulation time 24954770 ps
CPU time 0.69 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:09 PM PST 24
Peak memory 197020 kb
Host smart-fbd7110d-8e5b-4a8f-adb5-6c50999d79f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780347284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2780347284
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2852852208
Short name T1185
Test name
Test status
Simulation time 128265851 ps
CPU time 2.46 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 200152 kb
Host smart-3846c05d-8f01-4c58-8ae2-fe32ef4ab81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852852208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2852852208
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3106102064
Short name T100
Test name
Test status
Simulation time 385163525 ps
CPU time 1.28 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 199376 kb
Host smart-0fb9faae-9f63-48a3-ad07-59f6cb616adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106102064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3106102064
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3716087168
Short name T1165
Test name
Test status
Simulation time 48933523 ps
CPU time 0.71 seconds
Started Mar 03 02:01:13 PM PST 24
Finished Mar 03 02:01:14 PM PST 24
Peak memory 196904 kb
Host smart-2e43ee3b-f2bd-48d0-ab97-3a735f22dace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716087168 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3716087168
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1949315570
Short name T80
Test name
Test status
Simulation time 186070534 ps
CPU time 0.6 seconds
Started Mar 03 02:01:14 PM PST 24
Finished Mar 03 02:01:15 PM PST 24
Peak memory 195448 kb
Host smart-ae141aa5-cc91-464c-af34-4394b6d10f28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949315570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1949315570
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2641053557
Short name T1138
Test name
Test status
Simulation time 15173622 ps
CPU time 0.59 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:12 PM PST 24
Peak memory 185212 kb
Host smart-8d621898-8a50-4808-a018-6c91350844d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641053557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2641053557
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2171891426
Short name T1140
Test name
Test status
Simulation time 111328729 ps
CPU time 0.74 seconds
Started Mar 03 02:01:09 PM PST 24
Finished Mar 03 02:01:10 PM PST 24
Peak memory 197984 kb
Host smart-0c4cf8ff-c5fa-4b20-8734-d69acf6c3a6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171891426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2171891426
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.576729494
Short name T1103
Test name
Test status
Simulation time 65243570 ps
CPU time 1.39 seconds
Started Mar 03 02:01:10 PM PST 24
Finished Mar 03 02:01:11 PM PST 24
Peak memory 200112 kb
Host smart-82cde923-aa9e-4d20-96b8-e5777a7a9db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576729494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.576729494
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2747568294
Short name T93
Test name
Test status
Simulation time 685829063 ps
CPU time 1.33 seconds
Started Mar 03 02:01:12 PM PST 24
Finished Mar 03 02:01:13 PM PST 24
Peak memory 199000 kb
Host smart-0c5639e7-bca6-4642-8f43-4c54ad441e10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747568294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2747568294
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.956622176
Short name T1144
Test name
Test status
Simulation time 93373460 ps
CPU time 0.76 seconds
Started Mar 03 02:00:34 PM PST 24
Finished Mar 03 02:00:36 PM PST 24
Peak memory 196416 kb
Host smart-6dca1e43-64f9-4bc1-9a9e-f71ccb35ae8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956622176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.956622176
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2813337332
Short name T1104
Test name
Test status
Simulation time 1657366572 ps
CPU time 2.51 seconds
Started Mar 03 02:00:27 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 197816 kb
Host smart-66af69ad-42b3-4a66-ad57-643ee3773b8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813337332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2813337332
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1438574185
Short name T61
Test name
Test status
Simulation time 68781538 ps
CPU time 0.61 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 195432 kb
Host smart-74dea137-22a8-48e9-8858-f4efe511531b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438574185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1438574185
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.368734895
Short name T1135
Test name
Test status
Simulation time 16773615 ps
CPU time 0.69 seconds
Started Mar 03 02:00:33 PM PST 24
Finished Mar 03 02:00:34 PM PST 24
Peak memory 196484 kb
Host smart-0bdd117d-50b5-493c-8267-0095d157b8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368734895 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.368734895
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1012102245
Short name T58
Test name
Test status
Simulation time 15236272 ps
CPU time 0.61 seconds
Started Mar 03 02:00:34 PM PST 24
Finished Mar 03 02:00:36 PM PST 24
Peak memory 195324 kb
Host smart-9106079d-2ef7-41d8-8cb0-ed516ccfab01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012102245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1012102245
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2359265996
Short name T1118
Test name
Test status
Simulation time 12250253 ps
CPU time 0.56 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 185248 kb
Host smart-4c2910db-b124-44eb-9c02-bc7da2204645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359265996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2359265996
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3751133529
Short name T1154
Test name
Test status
Simulation time 46721426 ps
CPU time 0.63 seconds
Started Mar 03 02:00:26 PM PST 24
Finished Mar 03 02:00:27 PM PST 24
Peak memory 194556 kb
Host smart-2b109934-de22-4bec-813c-3ae068f2a4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751133529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3751133529
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3954841625
Short name T1119
Test name
Test status
Simulation time 44739809 ps
CPU time 1.18 seconds
Started Mar 03 02:00:27 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 200120 kb
Host smart-d67cb558-c885-4047-8703-dcc05670a048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954841625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3954841625
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1725969551
Short name T96
Test name
Test status
Simulation time 81141810 ps
CPU time 1.36 seconds
Started Mar 03 02:00:28 PM PST 24
Finished Mar 03 02:00:29 PM PST 24
Peak memory 199260 kb
Host smart-f49b8460-0084-446f-915d-a2ab40c2a2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725969551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1725969551
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.989551727
Short name T1137
Test name
Test status
Simulation time 13307110 ps
CPU time 0.56 seconds
Started Mar 03 02:01:17 PM PST 24
Finished Mar 03 02:01:18 PM PST 24
Peak memory 185252 kb
Host smart-2c14c21b-40b2-4d04-82c4-7697c0f49bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989551727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.989551727
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1194381627
Short name T1163
Test name
Test status
Simulation time 13378985 ps
CPU time 0.61 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:19 PM PST 24
Peak memory 194404 kb
Host smart-af43f839-d1c0-4049-b200-0129323237e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194381627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1194381627
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.982796163
Short name T1211
Test name
Test status
Simulation time 24263890 ps
CPU time 0.56 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:19 PM PST 24
Peak memory 185260 kb
Host smart-d593c53f-1b28-4456-8d0f-75c53d35b492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982796163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.982796163
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2868947750
Short name T1203
Test name
Test status
Simulation time 15308539 ps
CPU time 0.59 seconds
Started Mar 03 02:01:19 PM PST 24
Finished Mar 03 02:01:19 PM PST 24
Peak memory 194400 kb
Host smart-9e59fdef-0d37-472c-9261-8267232a6678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868947750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2868947750
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2342058574
Short name T1193
Test name
Test status
Simulation time 12855208 ps
CPU time 0.56 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:18 PM PST 24
Peak memory 185248 kb
Host smart-a655000e-1d08-4c8e-8d1a-323b94edcede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342058574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2342058574
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.16727436
Short name T1194
Test name
Test status
Simulation time 14094732 ps
CPU time 0.57 seconds
Started Mar 03 02:01:23 PM PST 24
Finished Mar 03 02:01:24 PM PST 24
Peak memory 185244 kb
Host smart-910d367a-1f09-4ee7-a2cd-c5e8ef935a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.16727436
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.592164411
Short name T1133
Test name
Test status
Simulation time 127001020 ps
CPU time 0.59 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:19 PM PST 24
Peak memory 185252 kb
Host smart-8ae3970f-a39e-45ea-8b78-c5b96689e836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592164411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.592164411
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4108870938
Short name T1123
Test name
Test status
Simulation time 98424946 ps
CPU time 0.6 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 194496 kb
Host smart-02a9d149-be36-4fff-9117-063d84bbdcba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108870938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4108870938
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3180572602
Short name T1110
Test name
Test status
Simulation time 46203396 ps
CPU time 0.55 seconds
Started Mar 03 02:01:17 PM PST 24
Finished Mar 03 02:01:18 PM PST 24
Peak memory 194452 kb
Host smart-db257dcf-47f2-47f8-af6d-cf48f6058e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180572602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3180572602
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3036198403
Short name T1167
Test name
Test status
Simulation time 24441036 ps
CPU time 0.57 seconds
Started Mar 03 02:01:21 PM PST 24
Finished Mar 03 02:01:21 PM PST 24
Peak memory 185136 kb
Host smart-e20bcdb7-f71e-4df3-b715-8ab648daf26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036198403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3036198403
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.341382103
Short name T67
Test name
Test status
Simulation time 26934428 ps
CPU time 0.67 seconds
Started Mar 03 02:00:34 PM PST 24
Finished Mar 03 02:00:36 PM PST 24
Peak memory 194832 kb
Host smart-6a2374d7-6676-4db7-8ced-288efa3c7c50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341382103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.341382103
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1644175563
Short name T62
Test name
Test status
Simulation time 1025214335 ps
CPU time 2.57 seconds
Started Mar 03 02:00:32 PM PST 24
Finished Mar 03 02:00:35 PM PST 24
Peak memory 197796 kb
Host smart-aa2eed8c-2d7d-48d3-831f-33eb58a9046e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644175563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1644175563
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1616266285
Short name T1216
Test name
Test status
Simulation time 14554412 ps
CPU time 0.58 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 195324 kb
Host smart-a8fd9241-bf49-4ff8-ad40-7e1ede6b2789
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616266285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1616266285
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4286234634
Short name T1177
Test name
Test status
Simulation time 41238861 ps
CPU time 1.08 seconds
Started Mar 03 02:00:35 PM PST 24
Finished Mar 03 02:00:36 PM PST 24
Peak memory 200144 kb
Host smart-cfd04cb4-2be0-40c7-9d5c-80da049b33fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286234634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4286234634
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3925811041
Short name T82
Test name
Test status
Simulation time 24415591 ps
CPU time 0.58 seconds
Started Mar 03 02:00:32 PM PST 24
Finished Mar 03 02:00:33 PM PST 24
Peak memory 195448 kb
Host smart-bfe1cafe-e0fe-4454-b73c-b67936386319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925811041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3925811041
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3482105984
Short name T1147
Test name
Test status
Simulation time 34631119 ps
CPU time 0.55 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 185080 kb
Host smart-42579785-5571-43da-afa7-485c245dc08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482105984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3482105984
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1797916337
Short name T1160
Test name
Test status
Simulation time 21635213 ps
CPU time 0.64 seconds
Started Mar 03 02:00:33 PM PST 24
Finished Mar 03 02:00:34 PM PST 24
Peak memory 194548 kb
Host smart-c1f73506-8964-47d7-86dd-5d21b7d2d603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797916337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1797916337
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2564185218
Short name T1222
Test name
Test status
Simulation time 26716932 ps
CPU time 1.42 seconds
Started Mar 03 02:00:34 PM PST 24
Finished Mar 03 02:00:36 PM PST 24
Peak memory 200112 kb
Host smart-04f45880-2b6c-446f-a839-b19e57a95ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564185218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2564185218
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2093140386
Short name T389
Test name
Test status
Simulation time 101052321 ps
CPU time 0.92 seconds
Started Mar 03 02:00:40 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 198744 kb
Host smart-e4666f55-be14-4e1c-b74d-14bd59a52c04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093140386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2093140386
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.462771820
Short name T1107
Test name
Test status
Simulation time 15882672 ps
CPU time 0.59 seconds
Started Mar 03 02:01:23 PM PST 24
Finished Mar 03 02:01:24 PM PST 24
Peak memory 185244 kb
Host smart-8b5031f3-ef77-4189-abe2-757f402eaad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462771820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.462771820
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3382108792
Short name T1170
Test name
Test status
Simulation time 18287240 ps
CPU time 0.6 seconds
Started Mar 03 02:01:19 PM PST 24
Finished Mar 03 02:01:20 PM PST 24
Peak memory 185264 kb
Host smart-7ac46915-d8cb-4cf1-981f-c56472d1a778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382108792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3382108792
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3662534210
Short name T1109
Test name
Test status
Simulation time 14825493 ps
CPU time 0.6 seconds
Started Mar 03 02:01:19 PM PST 24
Finished Mar 03 02:01:20 PM PST 24
Peak memory 194472 kb
Host smart-0189c5f8-afe6-4642-9c41-d1d1516956fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662534210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3662534210
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3598758566
Short name T1164
Test name
Test status
Simulation time 22620495 ps
CPU time 0.57 seconds
Started Mar 03 02:01:19 PM PST 24
Finished Mar 03 02:01:20 PM PST 24
Peak memory 185268 kb
Host smart-3248f520-7367-4621-97b3-6571b8b1f618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598758566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3598758566
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1780468324
Short name T1121
Test name
Test status
Simulation time 11163688 ps
CPU time 0.57 seconds
Started Mar 03 02:01:16 PM PST 24
Finished Mar 03 02:01:17 PM PST 24
Peak memory 185248 kb
Host smart-2b7fa452-253f-4c2e-9c68-214858ed3416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780468324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1780468324
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2873412886
Short name T1209
Test name
Test status
Simulation time 77271303 ps
CPU time 0.57 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:25 PM PST 24
Peak memory 185272 kb
Host smart-c4c05d63-3dc8-4d49-8007-f689ecdd0f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873412886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2873412886
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2925433574
Short name T1224
Test name
Test status
Simulation time 13646975 ps
CPU time 0.59 seconds
Started Mar 03 02:01:23 PM PST 24
Finished Mar 03 02:01:24 PM PST 24
Peak memory 185260 kb
Host smart-5d904c5e-268f-44b1-a2b0-b84cefb03ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925433574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2925433574
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3269756748
Short name T1131
Test name
Test status
Simulation time 12107156 ps
CPU time 0.55 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:19 PM PST 24
Peak memory 185268 kb
Host smart-a8bd8c1d-dfeb-411e-b692-158cafe6adc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269756748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3269756748
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2699035946
Short name T1161
Test name
Test status
Simulation time 12409594 ps
CPU time 0.57 seconds
Started Mar 03 02:01:26 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 185272 kb
Host smart-2c99b1de-b901-42ef-beaa-33fb965fa92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699035946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2699035946
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3442385266
Short name T1149
Test name
Test status
Simulation time 19119570 ps
CPU time 0.58 seconds
Started Mar 03 02:01:18 PM PST 24
Finished Mar 03 02:01:18 PM PST 24
Peak memory 185260 kb
Host smart-ae62e25d-88b5-4fc4-8729-f7ceaebb5bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442385266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3442385266
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.594353857
Short name T68
Test name
Test status
Simulation time 16102658 ps
CPU time 0.72 seconds
Started Mar 03 02:00:40 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 196104 kb
Host smart-01dd102e-cdd5-4836-8069-6040855dea67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594353857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.594353857
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3901838777
Short name T1113
Test name
Test status
Simulation time 58931113 ps
CPU time 2.24 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:43 PM PST 24
Peak memory 197676 kb
Host smart-d22e42bc-7660-4079-9ce2-91fd99e0109b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901838777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3901838777
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1659312627
Short name T1105
Test name
Test status
Simulation time 20818280 ps
CPU time 0.59 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:42 PM PST 24
Peak memory 195504 kb
Host smart-eaebbe5e-ba70-4b13-a229-67cfdbaacdb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659312627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1659312627
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3991405332
Short name T1210
Test name
Test status
Simulation time 28521618 ps
CPU time 1.29 seconds
Started Mar 03 02:00:42 PM PST 24
Finished Mar 03 02:00:44 PM PST 24
Peak memory 200068 kb
Host smart-143d290e-0331-42a7-9b3c-daabfbc05e3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991405332 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3991405332
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1932092904
Short name T1231
Test name
Test status
Simulation time 22470840 ps
CPU time 0.58 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:42 PM PST 24
Peak memory 195524 kb
Host smart-e8ba6372-856e-4423-9095-dfa5834be1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932092904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1932092904
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.550210646
Short name T1128
Test name
Test status
Simulation time 45688285 ps
CPU time 0.55 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 185436 kb
Host smart-e15fe239-8149-412b-a81a-8493eaf5bc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550210646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.550210646
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2015345311
Short name T89
Test name
Test status
Simulation time 42061296 ps
CPU time 0.65 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:42 PM PST 24
Peak memory 194776 kb
Host smart-4e094338-8447-4ed0-acde-f7b554029e68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015345311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2015345311
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1488369788
Short name T1148
Test name
Test status
Simulation time 229202387 ps
CPU time 1.33 seconds
Started Mar 03 02:00:33 PM PST 24
Finished Mar 03 02:00:34 PM PST 24
Peak memory 200048 kb
Host smart-0f29b029-2602-4ac7-a92f-7be402295406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488369788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1488369788
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3574416544
Short name T95
Test name
Test status
Simulation time 47818769 ps
CPU time 0.92 seconds
Started Mar 03 02:00:40 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 198828 kb
Host smart-01434c46-6b9b-41ac-8fbc-e8d2d1772da9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574416544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3574416544
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3730912093
Short name T1214
Test name
Test status
Simulation time 17748327 ps
CPU time 0.59 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 185272 kb
Host smart-ce973873-752e-48da-971d-2ce196f3eb61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730912093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3730912093
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4005104097
Short name T1156
Test name
Test status
Simulation time 29813164 ps
CPU time 0.58 seconds
Started Mar 03 02:01:21 PM PST 24
Finished Mar 03 02:01:22 PM PST 24
Peak memory 185240 kb
Host smart-cc33d829-7175-4565-b165-fe8a34f4a7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005104097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4005104097
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1470418284
Short name T1215
Test name
Test status
Simulation time 11964539 ps
CPU time 0.57 seconds
Started Mar 03 02:01:23 PM PST 24
Finished Mar 03 02:01:24 PM PST 24
Peak memory 194484 kb
Host smart-6c013458-cacb-4487-8c07-c7dbc35eb607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470418284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1470418284
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2809464507
Short name T1157
Test name
Test status
Simulation time 43504707 ps
CPU time 0.58 seconds
Started Mar 03 02:01:19 PM PST 24
Finished Mar 03 02:01:20 PM PST 24
Peak memory 194488 kb
Host smart-97d76f3a-c4ff-4933-9608-3135daf4d46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809464507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2809464507
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.186302099
Short name T1196
Test name
Test status
Simulation time 21317067 ps
CPU time 0.59 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 194448 kb
Host smart-cf23a024-1d1a-47e0-8bed-98b6eef2d8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186302099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.186302099
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.375824145
Short name T1172
Test name
Test status
Simulation time 76285940 ps
CPU time 0.57 seconds
Started Mar 03 02:01:26 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 185124 kb
Host smart-ac4171a5-5d2e-4919-a010-15cb3ee1ac3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375824145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.375824145
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1921369835
Short name T1159
Test name
Test status
Simulation time 43797787 ps
CPU time 0.57 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 185212 kb
Host smart-7a8198dc-2222-4ef1-8b77-977b1427a8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921369835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1921369835
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4017447402
Short name T1189
Test name
Test status
Simulation time 13457410 ps
CPU time 0.56 seconds
Started Mar 03 02:01:24 PM PST 24
Finished Mar 03 02:01:25 PM PST 24
Peak memory 185208 kb
Host smart-bc832623-a328-4c29-8110-45960296132e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017447402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4017447402
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2056138333
Short name T1173
Test name
Test status
Simulation time 56586565 ps
CPU time 0.57 seconds
Started Mar 03 02:01:25 PM PST 24
Finished Mar 03 02:01:26 PM PST 24
Peak memory 185248 kb
Host smart-dee9a773-19d7-40f4-90ac-ff9033deed0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056138333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2056138333
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3239861238
Short name T1127
Test name
Test status
Simulation time 14432208 ps
CPU time 0.57 seconds
Started Mar 03 02:01:23 PM PST 24
Finished Mar 03 02:01:24 PM PST 24
Peak memory 194432 kb
Host smart-3ae07e6d-68d1-474e-a48c-068376f72724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239861238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3239861238
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2069614114
Short name T1141
Test name
Test status
Simulation time 213257837 ps
CPU time 0.81 seconds
Started Mar 03 02:00:43 PM PST 24
Finished Mar 03 02:00:44 PM PST 24
Peak memory 198952 kb
Host smart-56b234f5-28d4-4950-b667-c78ec60f6e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069614114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2069614114
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.770629525
Short name T1175
Test name
Test status
Simulation time 60802661 ps
CPU time 0.61 seconds
Started Mar 03 02:00:43 PM PST 24
Finished Mar 03 02:00:45 PM PST 24
Peak memory 195344 kb
Host smart-7c9e97f0-7794-4089-8b46-43a0350e0c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770629525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.770629525
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1295470881
Short name T1197
Test name
Test status
Simulation time 44833463 ps
CPU time 0.54 seconds
Started Mar 03 02:00:40 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 185436 kb
Host smart-5ca07c8f-3712-452a-aa74-71d3e824f2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295470881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1295470881
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2690882940
Short name T1207
Test name
Test status
Simulation time 85593597 ps
CPU time 0.62 seconds
Started Mar 03 02:00:39 PM PST 24
Finished Mar 03 02:00:39 PM PST 24
Peak memory 195836 kb
Host smart-0e9a11bc-080e-4747-a7dc-acaaa7361e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690882940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2690882940
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2631552451
Short name T1229
Test name
Test status
Simulation time 115272068 ps
CPU time 1.35 seconds
Started Mar 03 02:00:39 PM PST 24
Finished Mar 03 02:00:41 PM PST 24
Peak memory 200160 kb
Host smart-b8fac73c-5dd9-44b4-b8bb-0b2abb6c7a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631552451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2631552451
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3221660445
Short name T92
Test name
Test status
Simulation time 662854723 ps
CPU time 1.33 seconds
Started Mar 03 02:00:41 PM PST 24
Finished Mar 03 02:00:42 PM PST 24
Peak memory 199036 kb
Host smart-40a52ba5-70b6-4932-8474-a847e916cfc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221660445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3221660445
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1184402808
Short name T1145
Test name
Test status
Simulation time 30270494 ps
CPU time 0.64 seconds
Started Mar 03 02:00:48 PM PST 24
Finished Mar 03 02:00:50 PM PST 24
Peak memory 197436 kb
Host smart-7fc12017-8b6f-497d-8d6b-b709d0b56abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184402808 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1184402808
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1454614343
Short name T1126
Test name
Test status
Simulation time 22698492 ps
CPU time 0.59 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:52 PM PST 24
Peak memory 195324 kb
Host smart-58468313-ae2c-4565-a054-7cbeb5dc0cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454614343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1454614343
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3748974997
Short name T1114
Test name
Test status
Simulation time 30862897 ps
CPU time 0.57 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:52 PM PST 24
Peak memory 185080 kb
Host smart-d3ca4892-4676-4a05-b218-a08917f728ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748974997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3748974997
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3844300738
Short name T1191
Test name
Test status
Simulation time 30140297 ps
CPU time 0.76 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:52 PM PST 24
Peak memory 196892 kb
Host smart-f6eaccd2-ed11-4da1-9d9d-11ef46cd1998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844300738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3844300738
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3728875355
Short name T1117
Test name
Test status
Simulation time 218026491 ps
CPU time 1.56 seconds
Started Mar 03 02:00:48 PM PST 24
Finished Mar 03 02:00:51 PM PST 24
Peak memory 200180 kb
Host smart-c974deaa-cf3e-4ad9-b03a-d04b1e68ecea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728875355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3728875355
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1723130519
Short name T97
Test name
Test status
Simulation time 294236233 ps
CPU time 1.28 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:52 PM PST 24
Peak memory 199196 kb
Host smart-1cc2961e-eca2-4bd7-84b5-1056fe9a928b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723130519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1723130519
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2807931811
Short name T1166
Test name
Test status
Simulation time 23614027 ps
CPU time 0.74 seconds
Started Mar 03 02:00:48 PM PST 24
Finished Mar 03 02:00:50 PM PST 24
Peak memory 198028 kb
Host smart-903b592c-b41a-4055-b1e9-3ffb570adb9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807931811 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2807931811
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.669726154
Short name T1232
Test name
Test status
Simulation time 29113723 ps
CPU time 0.61 seconds
Started Mar 03 02:00:50 PM PST 24
Finished Mar 03 02:00:53 PM PST 24
Peak memory 195520 kb
Host smart-9b1ad322-3632-475b-9cae-b177559e86d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669726154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.669726154
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1743193607
Short name T1106
Test name
Test status
Simulation time 17612357 ps
CPU time 0.57 seconds
Started Mar 03 02:00:48 PM PST 24
Finished Mar 03 02:00:50 PM PST 24
Peak memory 185168 kb
Host smart-4dde89e5-b701-4f50-a482-f2ed1d9f30d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743193607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1743193607
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2534426597
Short name T1198
Test name
Test status
Simulation time 59566991 ps
CPU time 0.77 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:52 PM PST 24
Peak memory 197008 kb
Host smart-85afe479-e754-421b-9fca-0da2d8d67490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534426597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2534426597
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.799631694
Short name T1122
Test name
Test status
Simulation time 1010797101 ps
CPU time 2.81 seconds
Started Mar 03 02:00:49 PM PST 24
Finished Mar 03 02:00:53 PM PST 24
Peak memory 200164 kb
Host smart-3e6feea1-5742-4c78-987f-0fecbee0a96a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799631694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.799631694
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2183434301
Short name T90
Test name
Test status
Simulation time 171043264 ps
CPU time 1.06 seconds
Started Mar 03 02:00:51 PM PST 24
Finished Mar 03 02:00:54 PM PST 24
Peak memory 199048 kb
Host smart-1b34bdb9-63af-4f42-bafe-2083567bc9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183434301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2183434301
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1470999107
Short name T1202
Test name
Test status
Simulation time 66752580 ps
CPU time 0.82 seconds
Started Mar 03 02:00:58 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 199284 kb
Host smart-e7dbfa0e-564a-49a8-8d2b-2fa49835392b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470999107 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1470999107
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2458112982
Short name T66
Test name
Test status
Simulation time 52385319 ps
CPU time 0.57 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:58 PM PST 24
Peak memory 195488 kb
Host smart-83f4a082-e075-4788-9dab-1c7edd7ffcf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458112982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2458112982
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.180295256
Short name T1162
Test name
Test status
Simulation time 12096484 ps
CPU time 0.56 seconds
Started Mar 03 02:00:56 PM PST 24
Finished Mar 03 02:00:58 PM PST 24
Peak memory 185244 kb
Host smart-291ff5af-22dc-460d-bb20-e64da6ef4ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180295256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.180295256
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3993262161
Short name T1213
Test name
Test status
Simulation time 37208021 ps
CPU time 0.6 seconds
Started Mar 03 02:00:56 PM PST 24
Finished Mar 03 02:00:58 PM PST 24
Peak memory 194556 kb
Host smart-11d37f2b-f300-43eb-bd59-50885ee6b8de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993262161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3993262161
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2502846855
Short name T1120
Test name
Test status
Simulation time 125000751 ps
CPU time 1.75 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 200060 kb
Host smart-6a8a2306-ebd2-4009-93a8-47ea8a284556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502846855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2502846855
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2217945760
Short name T99
Test name
Test status
Simulation time 212677213 ps
CPU time 1 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:58 PM PST 24
Peak memory 198928 kb
Host smart-ace94653-7c7a-4ab2-bbea-ae72e2f9d72b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217945760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2217945760
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.373292256
Short name T1134
Test name
Test status
Simulation time 22185367 ps
CPU time 0.75 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 198076 kb
Host smart-9f56cae5-79b8-48b5-9c37-1c1c11f69b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373292256 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.373292256
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2215577669
Short name T1181
Test name
Test status
Simulation time 15180753 ps
CPU time 0.64 seconds
Started Mar 03 02:00:56 PM PST 24
Finished Mar 03 02:00:58 PM PST 24
Peak memory 195488 kb
Host smart-1073802a-b4d5-4ca1-8190-8070fcb5cd87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215577669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2215577669
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1969864703
Short name T1158
Test name
Test status
Simulation time 41447643 ps
CPU time 0.58 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 185260 kb
Host smart-2b27f5be-6ac4-4e9b-8e21-450f9751fd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969864703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1969864703
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1908088691
Short name T1132
Test name
Test status
Simulation time 89327491 ps
CPU time 0.71 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 196976 kb
Host smart-d4e1db4f-231c-45c4-8f54-264c854bf0d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908088691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1908088691
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2671423207
Short name T1108
Test name
Test status
Simulation time 62415061 ps
CPU time 1.28 seconds
Started Mar 03 02:00:57 PM PST 24
Finished Mar 03 02:00:59 PM PST 24
Peak memory 200044 kb
Host smart-b6a37d36-8f95-4da1-9e5a-a44611fae48c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671423207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2671423207
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1046904546
Short name T1182
Test name
Test status
Simulation time 124208465 ps
CPU time 1.42 seconds
Started Mar 03 02:00:59 PM PST 24
Finished Mar 03 02:01:00 PM PST 24
Peak memory 199316 kb
Host smart-07b3ffeb-1c55-475b-a3c5-83a9d6294db0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046904546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1046904546
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.718697629
Short name T550
Test name
Test status
Simulation time 13882710 ps
CPU time 0.58 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:22:35 PM PST 24
Peak memory 195108 kb
Host smart-dc201f22-8c04-43c9-b55f-163e7c005db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718697629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.718697629
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2407335439
Short name T234
Test name
Test status
Simulation time 51707714960 ps
CPU time 70.38 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:23:37 PM PST 24
Peak memory 199640 kb
Host smart-2fcfef98-dfc0-452b-b143-f3f3ae387b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407335439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2407335439
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1512512023
Short name T343
Test name
Test status
Simulation time 96133298280 ps
CPU time 17.43 seconds
Started Mar 03 01:22:28 PM PST 24
Finished Mar 03 01:22:45 PM PST 24
Peak memory 198892 kb
Host smart-464e2f9f-2ed8-489d-8e4f-8f946abb6bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512512023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1512512023
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1723217466
Short name T994
Test name
Test status
Simulation time 29066793729 ps
CPU time 28.31 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:22:55 PM PST 24
Peak memory 198652 kb
Host smart-a61f8abd-97fa-4e3c-af23-21e4073dc044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723217466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1723217466
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3827936566
Short name T673
Test name
Test status
Simulation time 2498303816 ps
CPU time 4.07 seconds
Started Mar 03 01:22:31 PM PST 24
Finished Mar 03 01:22:35 PM PST 24
Peak memory 195268 kb
Host smart-1b8c17b5-c76f-41bd-8582-e648c590e8e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827936566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3827936566
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.64325685
Short name T712
Test name
Test status
Simulation time 159899427518 ps
CPU time 1209.05 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:42:36 PM PST 24
Peak memory 199684 kb
Host smart-e0306f3b-8bc1-436e-ac0f-94b071e06101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64325685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.64325685
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2689444078
Short name T525
Test name
Test status
Simulation time 10713030763 ps
CPU time 9.73 seconds
Started Mar 03 01:22:27 PM PST 24
Finished Mar 03 01:22:37 PM PST 24
Peak memory 198160 kb
Host smart-43921e71-93b5-4be0-b2ec-02ac3c9d05ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689444078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2689444078
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.2359910446
Short name T718
Test name
Test status
Simulation time 9162904557 ps
CPU time 146.56 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:24:53 PM PST 24
Peak memory 199568 kb
Host smart-bc301d05-e370-4a03-844a-5daf0de69bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359910446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2359910446
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2401954051
Short name T604
Test name
Test status
Simulation time 1694373941 ps
CPU time 1.34 seconds
Started Mar 03 01:22:25 PM PST 24
Finished Mar 03 01:22:27 PM PST 24
Peak memory 195124 kb
Host smart-883d027b-958a-428c-bda0-71882a4be959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401954051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2401954051
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2937924014
Short name T29
Test name
Test status
Simulation time 76036785 ps
CPU time 0.78 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:22:35 PM PST 24
Peak memory 217196 kb
Host smart-9b574d31-ded6-406b-a050-dbcb823957ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937924014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2937924014
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.247047261
Short name T439
Test name
Test status
Simulation time 885289983 ps
CPU time 2.44 seconds
Started Mar 03 01:22:27 PM PST 24
Finished Mar 03 01:22:30 PM PST 24
Peak memory 198012 kb
Host smart-c33464df-231e-49ca-8d66-7b538b8b45d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247047261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.247047261
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.777017909
Short name T423
Test name
Test status
Simulation time 6345666781 ps
CPU time 12.45 seconds
Started Mar 03 01:22:25 PM PST 24
Finished Mar 03 01:22:38 PM PST 24
Peak memory 199664 kb
Host smart-8de77cc0-be69-49c5-aa35-e8d23a908095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777017909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.777017909
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3921698927
Short name T1000
Test name
Test status
Simulation time 52318896901 ps
CPU time 64.9 seconds
Started Mar 03 01:22:26 PM PST 24
Finished Mar 03 01:23:31 PM PST 24
Peak memory 199632 kb
Host smart-1be11914-2b5c-4d98-abc2-db089ffaa690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921698927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3921698927
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_intr.3320384661
Short name T706
Test name
Test status
Simulation time 24292917421 ps
CPU time 8.92 seconds
Started Mar 03 01:22:35 PM PST 24
Finished Mar 03 01:22:44 PM PST 24
Peak memory 198304 kb
Host smart-4c5eaff8-dfa4-4f7e-b7f6-2e93cc672800
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320384661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3320384661
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4133729587
Short name T672
Test name
Test status
Simulation time 71080172289 ps
CPU time 567.11 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:32:00 PM PST 24
Peak memory 199652 kb
Host smart-1b441655-f08c-4ce4-9176-bb91c056dceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133729587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4133729587
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.4048229939
Short name T472
Test name
Test status
Simulation time 10268332269 ps
CPU time 31.68 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:23:05 PM PST 24
Peak memory 198784 kb
Host smart-27473f81-0f56-4f6a-9c57-e3809b3ffd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048229939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4048229939
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4151271640
Short name T205
Test name
Test status
Simulation time 21649382404 ps
CPU time 33.1 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:23:07 PM PST 24
Peak memory 196912 kb
Host smart-c2399c61-befd-48cc-a6df-188703f76aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151271640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4151271640
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2833815546
Short name T655
Test name
Test status
Simulation time 3361768840 ps
CPU time 113.64 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:24:27 PM PST 24
Peak memory 199676 kb
Host smart-bbb98499-19e6-4a10-8629-67fc0de6d2f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833815546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2833815546
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.432767579
Short name T611
Test name
Test status
Simulation time 3269449878 ps
CPU time 16.49 seconds
Started Mar 03 01:22:32 PM PST 24
Finished Mar 03 01:22:49 PM PST 24
Peak memory 198100 kb
Host smart-449db1c2-35f3-4415-9d17-e44cecbcdb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432767579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.432767579
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3167814902
Short name T865
Test name
Test status
Simulation time 58990211651 ps
CPU time 23.67 seconds
Started Mar 03 01:22:35 PM PST 24
Finished Mar 03 01:22:59 PM PST 24
Peak memory 198656 kb
Host smart-150f23f1-942a-414a-8677-bf3a69f9d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167814902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3167814902
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4182834937
Short name T1071
Test name
Test status
Simulation time 46832197971 ps
CPU time 37.88 seconds
Started Mar 03 01:22:35 PM PST 24
Finished Mar 03 01:23:13 PM PST 24
Peak memory 195144 kb
Host smart-f4377e6a-70e6-493f-8359-12f0b9bc2855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182834937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4182834937
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3141818442
Short name T30
Test name
Test status
Simulation time 264809018 ps
CPU time 0.91 seconds
Started Mar 03 01:22:36 PM PST 24
Finished Mar 03 01:22:38 PM PST 24
Peak memory 217048 kb
Host smart-5e2f983d-b61f-47f0-965e-78edff22aabc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141818442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3141818442
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4165775756
Short name T934
Test name
Test status
Simulation time 470386659 ps
CPU time 1.28 seconds
Started Mar 03 01:22:38 PM PST 24
Finished Mar 03 01:22:39 PM PST 24
Peak memory 198532 kb
Host smart-f7f600aa-5158-47c5-9b01-8eff2078f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165775756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4165775756
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3676406952
Short name T1018
Test name
Test status
Simulation time 7094256537 ps
CPU time 12.96 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:22:47 PM PST 24
Peak memory 199296 kb
Host smart-71fbb720-508e-4ee7-ba93-ce44fea50b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676406952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3676406952
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.979272081
Short name T955
Test name
Test status
Simulation time 55517438504 ps
CPU time 36.12 seconds
Started Mar 03 01:22:32 PM PST 24
Finished Mar 03 01:23:09 PM PST 24
Peak memory 199736 kb
Host smart-aedb131e-1ea8-47a4-809d-e59ff7ef201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979272081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.979272081
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.100658334
Short name T536
Test name
Test status
Simulation time 42400878 ps
CPU time 0.63 seconds
Started Mar 03 01:23:39 PM PST 24
Finished Mar 03 01:23:41 PM PST 24
Peak memory 195256 kb
Host smart-59993893-1b06-4612-912e-0577c01076de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100658334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.100658334
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1106089588
Short name T806
Test name
Test status
Simulation time 245690141087 ps
CPU time 42.08 seconds
Started Mar 03 01:23:30 PM PST 24
Finished Mar 03 01:24:12 PM PST 24
Peak memory 199724 kb
Host smart-aadd8174-af55-45fe-9160-4d8533bbd268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106089588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1106089588
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1821930478
Short name T376
Test name
Test status
Simulation time 76660933526 ps
CPU time 30.25 seconds
Started Mar 03 01:23:31 PM PST 24
Finished Mar 03 01:24:02 PM PST 24
Peak memory 198532 kb
Host smart-ad8e13bf-e38f-471c-a55b-51431aefc01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821930478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1821930478
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.1306478591
Short name T481
Test name
Test status
Simulation time 67049775453 ps
CPU time 60.92 seconds
Started Mar 03 01:23:30 PM PST 24
Finished Mar 03 01:24:31 PM PST 24
Peak memory 199612 kb
Host smart-91a94cfc-c0cc-4172-a461-5bb3392be03f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306478591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1306478591
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3207742123
Short name T567
Test name
Test status
Simulation time 143070783766 ps
CPU time 623.76 seconds
Started Mar 03 01:23:39 PM PST 24
Finished Mar 03 01:34:04 PM PST 24
Peak memory 199744 kb
Host smart-c5bd9407-c250-4806-a17b-0da4cabf09a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207742123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3207742123
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.33803390
Short name T847
Test name
Test status
Simulation time 12332366328 ps
CPU time 7.57 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:23:46 PM PST 24
Peak memory 197540 kb
Host smart-48060e15-c8b9-48af-b9f0-1569cdca22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33803390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.33803390
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.435094799
Short name T741
Test name
Test status
Simulation time 113496516615 ps
CPU time 57.3 seconds
Started Mar 03 01:23:27 PM PST 24
Finished Mar 03 01:24:25 PM PST 24
Peak memory 208028 kb
Host smart-b79359d7-3d32-4bdf-807d-5c785050a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435094799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.435094799
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3796392765
Short name T1054
Test name
Test status
Simulation time 20942008705 ps
CPU time 72.8 seconds
Started Mar 03 01:23:38 PM PST 24
Finished Mar 03 01:24:53 PM PST 24
Peak memory 199636 kb
Host smart-9533fb03-e984-43f6-8e18-d3e7be5b4913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796392765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3796392765
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.878895173
Short name T799
Test name
Test status
Simulation time 4059191420 ps
CPU time 18.93 seconds
Started Mar 03 01:23:30 PM PST 24
Finished Mar 03 01:23:50 PM PST 24
Peak memory 198332 kb
Host smart-6ff4a390-0e35-419f-95f8-f52d53b25c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878895173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.878895173
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1767671118
Short name T730
Test name
Test status
Simulation time 35976811922 ps
CPU time 16.88 seconds
Started Mar 03 01:23:32 PM PST 24
Finished Mar 03 01:23:49 PM PST 24
Peak memory 198812 kb
Host smart-cb940da9-6fb9-4e4d-afd6-370aaf4ebb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767671118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1767671118
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.955319621
Short name T1065
Test name
Test status
Simulation time 3110214871 ps
CPU time 4.86 seconds
Started Mar 03 01:23:28 PM PST 24
Finished Mar 03 01:23:34 PM PST 24
Peak memory 195180 kb
Host smart-8a2dd1de-06f6-4adb-ab8c-92cfa1d8e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955319621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.955319621
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2963780114
Short name T685
Test name
Test status
Simulation time 293071893 ps
CPU time 1.36 seconds
Started Mar 03 01:23:35 PM PST 24
Finished Mar 03 01:23:37 PM PST 24
Peak memory 197972 kb
Host smart-4d4d1392-625f-4bdd-8eba-9645221867d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963780114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2963780114
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.847264710
Short name T1029
Test name
Test status
Simulation time 172673878751 ps
CPU time 153.02 seconds
Started Mar 03 01:23:35 PM PST 24
Finished Mar 03 01:26:10 PM PST 24
Peak memory 199676 kb
Host smart-e98b9233-3687-400d-ad90-e7501bd4d2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847264710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.847264710
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4208178975
Short name T73
Test name
Test status
Simulation time 7150063912 ps
CPU time 15.94 seconds
Started Mar 03 01:23:36 PM PST 24
Finished Mar 03 01:23:53 PM PST 24
Peak memory 199096 kb
Host smart-6a5985ef-7b5b-4d3c-be62-aa5b87eae18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208178975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4208178975
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.686773435
Short name T999
Test name
Test status
Simulation time 28380069055 ps
CPU time 46.91 seconds
Started Mar 03 01:28:55 PM PST 24
Finished Mar 03 01:29:42 PM PST 24
Peak memory 199516 kb
Host smart-7b2c89a1-e5a9-4ef8-a86f-f43421fbc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686773435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.686773435
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.965479356
Short name T227
Test name
Test status
Simulation time 20660201151 ps
CPU time 17.65 seconds
Started Mar 03 01:28:54 PM PST 24
Finished Mar 03 01:29:12 PM PST 24
Peak memory 199492 kb
Host smart-5d390caa-5197-4a91-a17c-af5bc571b0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965479356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.965479356
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3522041992
Short name T656
Test name
Test status
Simulation time 55259982608 ps
CPU time 25.81 seconds
Started Mar 03 01:28:58 PM PST 24
Finished Mar 03 01:29:23 PM PST 24
Peak memory 199668 kb
Host smart-edaf00d2-bb10-4fee-a907-fd4cf6d943e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522041992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3522041992
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3979470125
Short name T390
Test name
Test status
Simulation time 56456959285 ps
CPU time 21.9 seconds
Started Mar 03 01:29:01 PM PST 24
Finished Mar 03 01:29:23 PM PST 24
Peak memory 199696 kb
Host smart-e43733e3-ab49-4d61-84f5-53e52d32dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979470125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3979470125
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2458825478
Short name T632
Test name
Test status
Simulation time 14579386211 ps
CPU time 12.95 seconds
Started Mar 03 01:28:55 PM PST 24
Finished Mar 03 01:29:08 PM PST 24
Peak memory 199588 kb
Host smart-5202eddd-f76e-4fb4-adcf-eb6bc33c9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458825478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2458825478
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.722370809
Short name T684
Test name
Test status
Simulation time 25210763247 ps
CPU time 41.43 seconds
Started Mar 03 01:28:58 PM PST 24
Finished Mar 03 01:29:40 PM PST 24
Peak memory 199568 kb
Host smart-55075430-9df2-4abf-89ee-f8c85a64cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722370809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.722370809
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1508282320
Short name T348
Test name
Test status
Simulation time 27004943707 ps
CPU time 14.28 seconds
Started Mar 03 01:28:57 PM PST 24
Finished Mar 03 01:29:12 PM PST 24
Peak memory 199608 kb
Host smart-6ad7f910-c519-4ff9-9218-24b87025af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508282320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1508282320
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2677961912
Short name T1096
Test name
Test status
Simulation time 113310144667 ps
CPU time 200.75 seconds
Started Mar 03 01:28:56 PM PST 24
Finished Mar 03 01:32:17 PM PST 24
Peak memory 199468 kb
Host smart-ec872d35-3795-451e-8cb6-060e90fdb62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677961912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2677961912
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.148324608
Short name T587
Test name
Test status
Simulation time 16141113 ps
CPU time 0.58 seconds
Started Mar 03 01:23:46 PM PST 24
Finished Mar 03 01:23:47 PM PST 24
Peak memory 195216 kb
Host smart-97e94a77-dce2-466f-8c4a-1cd7dd2cb2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148324608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.148324608
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1104696141
Short name T476
Test name
Test status
Simulation time 76870034136 ps
CPU time 34.45 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:24:12 PM PST 24
Peak memory 199664 kb
Host smart-693c3e37-7057-45e1-b4f5-29f5d7ef80ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104696141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1104696141
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4219203138
Short name T880
Test name
Test status
Simulation time 262783781947 ps
CPU time 101.02 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:25:20 PM PST 24
Peak memory 199368 kb
Host smart-4393344c-2439-46ea-9c0b-25d1ef8ca711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219203138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4219203138
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2288993994
Short name T473
Test name
Test status
Simulation time 47679074427 ps
CPU time 273.44 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:28:17 PM PST 24
Peak memory 199704 kb
Host smart-29b5ec50-59ca-480d-b601-67c23432bb53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288993994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2288993994
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1140628467
Short name T849
Test name
Test status
Simulation time 4608028838 ps
CPU time 3.4 seconds
Started Mar 03 01:23:42 PM PST 24
Finished Mar 03 01:23:46 PM PST 24
Peak memory 198460 kb
Host smart-8637c283-9544-48b6-a5f1-a249b72d4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140628467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1140628467
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.344214449
Short name T440
Test name
Test status
Simulation time 182479675048 ps
CPU time 106.52 seconds
Started Mar 03 01:23:38 PM PST 24
Finished Mar 03 01:25:26 PM PST 24
Peak memory 207960 kb
Host smart-0c5419b5-98d9-44d1-a997-e1e7c5dc1a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344214449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.344214449
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2366978100
Short name T897
Test name
Test status
Simulation time 20968496401 ps
CPU time 489.4 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:31:53 PM PST 24
Peak memory 199688 kb
Host smart-358203ee-ef2b-4cea-8423-0f540aadcafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366978100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2366978100
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1886624598
Short name T690
Test name
Test status
Simulation time 4012161802 ps
CPU time 15.73 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:23:54 PM PST 24
Peak memory 198156 kb
Host smart-e7f6e821-9511-4bcd-9ce9-7f6581fe6f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886624598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1886624598
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2531349688
Short name T53
Test name
Test status
Simulation time 24203628981 ps
CPU time 44.45 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:24:28 PM PST 24
Peak memory 199104 kb
Host smart-3b5ec672-aa14-4fbc-9156-de2356bf99d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531349688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2531349688
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1175499739
Short name T640
Test name
Test status
Simulation time 36319455263 ps
CPU time 13.82 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:23:58 PM PST 24
Peak memory 195544 kb
Host smart-5ee74596-518c-440b-96a9-b45f4c483477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175499739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1175499739
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3092796789
Short name T895
Test name
Test status
Simulation time 272781645 ps
CPU time 1.38 seconds
Started Mar 03 01:23:37 PM PST 24
Finished Mar 03 01:23:39 PM PST 24
Peak memory 197532 kb
Host smart-ee1a4c40-2a32-4619-a5cf-ec8720a40af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092796789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3092796789
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3766146111
Short name T827
Test name
Test status
Simulation time 491138635324 ps
CPU time 518.8 seconds
Started Mar 03 01:23:45 PM PST 24
Finished Mar 03 01:32:24 PM PST 24
Peak memory 199744 kb
Host smart-6783aaa0-fd93-4f89-bad4-e7a0f0f95ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766146111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3766146111
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.133012898
Short name T659
Test name
Test status
Simulation time 1283783640 ps
CPU time 2.2 seconds
Started Mar 03 01:23:47 PM PST 24
Finished Mar 03 01:23:49 PM PST 24
Peak memory 197344 kb
Host smart-7aa1b790-e94b-464e-b965-d2751b82d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133012898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.133012898
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4108935454
Short name T889
Test name
Test status
Simulation time 26602612957 ps
CPU time 44.46 seconds
Started Mar 03 01:23:36 PM PST 24
Finished Mar 03 01:24:21 PM PST 24
Peak memory 199684 kb
Host smart-6c9c7ec2-01a8-4a70-96f0-8cbc61a3eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108935454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4108935454
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2741184977
Short name T202
Test name
Test status
Simulation time 18954053260 ps
CPU time 45.64 seconds
Started Mar 03 01:29:03 PM PST 24
Finished Mar 03 01:29:49 PM PST 24
Peak memory 199676 kb
Host smart-0326a4bb-8934-465e-9ac6-9238887b21db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741184977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2741184977
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.260206864
Short name T180
Test name
Test status
Simulation time 16636819416 ps
CPU time 14.24 seconds
Started Mar 03 01:29:04 PM PST 24
Finished Mar 03 01:29:18 PM PST 24
Peak memory 199164 kb
Host smart-ad2296ab-edab-4791-bad6-783adfcf9b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260206864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.260206864
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.339958094
Short name T825
Test name
Test status
Simulation time 81168954392 ps
CPU time 29.57 seconds
Started Mar 03 01:29:04 PM PST 24
Finished Mar 03 01:29:34 PM PST 24
Peak memory 199596 kb
Host smart-317f54cd-539e-4bbb-9bc6-a83312ccb8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339958094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.339958094
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3026786129
Short name T199
Test name
Test status
Simulation time 19458591908 ps
CPU time 16.52 seconds
Started Mar 03 01:29:01 PM PST 24
Finished Mar 03 01:29:18 PM PST 24
Peak memory 199696 kb
Host smart-d8054fbd-7ee1-4783-9f6f-c6180bc9944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026786129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3026786129
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2013895601
Short name T264
Test name
Test status
Simulation time 118061823712 ps
CPU time 46.15 seconds
Started Mar 03 01:29:03 PM PST 24
Finished Mar 03 01:29:49 PM PST 24
Peak memory 199520 kb
Host smart-f1ff2eda-18ea-4307-a9d2-4cc94f8c0c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013895601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2013895601
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.535571180
Short name T691
Test name
Test status
Simulation time 13703220 ps
CPU time 0.6 seconds
Started Mar 03 01:23:53 PM PST 24
Finished Mar 03 01:23:53 PM PST 24
Peak memory 195116 kb
Host smart-52382f8b-01e9-4215-abc0-8158a57c2552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535571180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.535571180
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2588290134
Short name T780
Test name
Test status
Simulation time 19978919028 ps
CPU time 32.43 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:24:17 PM PST 24
Peak memory 199728 kb
Host smart-fbb8636d-07f7-4965-8582-a706df861973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588290134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2588290134
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2869860304
Short name T642
Test name
Test status
Simulation time 101592029303 ps
CPU time 75.43 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:25:00 PM PST 24
Peak memory 198592 kb
Host smart-ac6861ff-999f-4ea1-82c0-245ed3ab7914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869860304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2869860304
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4019954539
Short name T1035
Test name
Test status
Simulation time 40330982416 ps
CPU time 19.61 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:24:03 PM PST 24
Peak memory 199724 kb
Host smart-72047cf3-6c83-46c5-bc25-2585906e3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019954539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4019954539
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.689326857
Short name T812
Test name
Test status
Simulation time 175673506161 ps
CPU time 51.84 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:24:36 PM PST 24
Peak memory 199624 kb
Host smart-f2d786fc-fd5d-4a67-bf26-877472ff9a77
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689326857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.689326857
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2701487427
Short name T126
Test name
Test status
Simulation time 78418033904 ps
CPU time 102.21 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:25:34 PM PST 24
Peak memory 199636 kb
Host smart-5dfd1529-974a-4051-b26e-720617793389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701487427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2701487427
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3326694266
Short name T943
Test name
Test status
Simulation time 116214123 ps
CPU time 0.84 seconds
Started Mar 03 01:23:48 PM PST 24
Finished Mar 03 01:23:49 PM PST 24
Peak memory 195220 kb
Host smart-7232a272-47d9-41be-bd5a-992de000199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326694266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3326694266
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1968636646
Short name T595
Test name
Test status
Simulation time 68223987342 ps
CPU time 64.14 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:24:47 PM PST 24
Peak memory 198996 kb
Host smart-d769abb8-261c-4bd5-8d21-05e43bbac8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968636646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1968636646
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2667697215
Short name T569
Test name
Test status
Simulation time 16852595102 ps
CPU time 144.19 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:26:16 PM PST 24
Peak memory 199672 kb
Host smart-2a88d8ed-0d65-4da8-a7d2-3819dce5695c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667697215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2667697215
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.918595425
Short name T1074
Test name
Test status
Simulation time 3405817206 ps
CPU time 22.58 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:24:07 PM PST 24
Peak memory 197656 kb
Host smart-47ec4062-4bde-42cf-b332-25c3bc5a83b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918595425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.918595425
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2515302504
Short name T900
Test name
Test status
Simulation time 147637136165 ps
CPU time 115.75 seconds
Started Mar 03 01:23:46 PM PST 24
Finished Mar 03 01:25:42 PM PST 24
Peak memory 199640 kb
Host smart-17dac224-dd8c-46a7-a397-0cf71a3d231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515302504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2515302504
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1736365109
Short name T580
Test name
Test status
Simulation time 36588761343 ps
CPU time 18.1 seconds
Started Mar 03 01:23:43 PM PST 24
Finished Mar 03 01:24:01 PM PST 24
Peak memory 195284 kb
Host smart-9a3712a3-7894-4e2f-891c-684304d012c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736365109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1736365109
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1481965412
Short name T490
Test name
Test status
Simulation time 725906986 ps
CPU time 1.93 seconds
Started Mar 03 01:23:45 PM PST 24
Finished Mar 03 01:23:47 PM PST 24
Peak memory 199052 kb
Host smart-25aebc4d-6ed3-4ab3-a525-78631ad30f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481965412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1481965412
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3752558197
Short name T704
Test name
Test status
Simulation time 1018066763 ps
CPU time 3.81 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:23:48 PM PST 24
Peak memory 198964 kb
Host smart-2bd3d047-5f9d-4b3e-a6a4-3def3dce8e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752558197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3752558197
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3091866369
Short name T740
Test name
Test status
Simulation time 32510751420 ps
CPU time 14.55 seconds
Started Mar 03 01:23:44 PM PST 24
Finished Mar 03 01:23:59 PM PST 24
Peak memory 196548 kb
Host smart-cf91d10a-48ea-4f0d-8c33-1196c280fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091866369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3091866369
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.322701286
Short name T39
Test name
Test status
Simulation time 31482964377 ps
CPU time 17.65 seconds
Started Mar 03 01:29:01 PM PST 24
Finished Mar 03 01:29:19 PM PST 24
Peak memory 198360 kb
Host smart-65216dfc-2418-47e0-9ed9-2a054b7f3b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322701286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.322701286
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2894257254
Short name T285
Test name
Test status
Simulation time 25252253442 ps
CPU time 41.75 seconds
Started Mar 03 01:29:02 PM PST 24
Finished Mar 03 01:29:44 PM PST 24
Peak memory 199280 kb
Host smart-0242ce7f-7775-4b72-861c-e80b8688e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894257254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2894257254
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1212012190
Short name T1009
Test name
Test status
Simulation time 60757822501 ps
CPU time 88.31 seconds
Started Mar 03 01:29:09 PM PST 24
Finished Mar 03 01:30:37 PM PST 24
Peak memory 199664 kb
Host smart-d12655d4-437f-4136-8213-bd06e3ebe5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212012190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1212012190
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2759434856
Short name T256
Test name
Test status
Simulation time 306824917946 ps
CPU time 252.8 seconds
Started Mar 03 01:29:13 PM PST 24
Finished Mar 03 01:33:26 PM PST 24
Peak memory 199624 kb
Host smart-ad050d7b-c963-44ee-a5b1-eb0e6b616e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759434856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2759434856
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1546178604
Short name T216
Test name
Test status
Simulation time 101348166256 ps
CPU time 191.71 seconds
Started Mar 03 01:29:10 PM PST 24
Finished Mar 03 01:32:22 PM PST 24
Peak memory 199672 kb
Host smart-735a39a3-43f9-4b4e-9bef-152db06b9a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546178604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1546178604
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2768796458
Short name T211
Test name
Test status
Simulation time 34958436294 ps
CPU time 24.06 seconds
Started Mar 03 01:29:11 PM PST 24
Finished Mar 03 01:29:35 PM PST 24
Peak memory 199668 kb
Host smart-baa9b3fc-d435-49b7-b3d6-3264f64c531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768796458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2768796458
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.843972800
Short name T596
Test name
Test status
Simulation time 12633712 ps
CPU time 0.58 seconds
Started Mar 03 01:24:00 PM PST 24
Finished Mar 03 01:24:02 PM PST 24
Peak memory 195276 kb
Host smart-9c367888-fa89-4d96-890d-812a4c85fa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843972800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.843972800
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.463048888
Short name T215
Test name
Test status
Simulation time 120141033139 ps
CPU time 204.77 seconds
Started Mar 03 01:23:50 PM PST 24
Finished Mar 03 01:27:16 PM PST 24
Peak memory 199728 kb
Host smart-7adcd872-d21c-480e-969e-afd72999722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463048888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.463048888
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.609847702
Short name T669
Test name
Test status
Simulation time 42900035636 ps
CPU time 17.82 seconds
Started Mar 03 01:23:51 PM PST 24
Finished Mar 03 01:24:09 PM PST 24
Peak memory 199404 kb
Host smart-5e0d759b-86c9-42be-9893-583ef20a2984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609847702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.609847702
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2538341403
Short name T220
Test name
Test status
Simulation time 42871320290 ps
CPU time 17.91 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:24:10 PM PST 24
Peak memory 199556 kb
Host smart-96c315cb-fa79-4f2e-8ec5-fe5ea207a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538341403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2538341403
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2059624194
Short name T833
Test name
Test status
Simulation time 550270846856 ps
CPU time 423.15 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:30:55 PM PST 24
Peak memory 198764 kb
Host smart-15c2a266-a5a9-4549-88e4-9c84203d7f80
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059624194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2059624194
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4125937448
Short name T890
Test name
Test status
Simulation time 97896663789 ps
CPU time 238.02 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:27:57 PM PST 24
Peak memory 199764 kb
Host smart-51db7c15-b9c1-44fd-990e-57aef49f0449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125937448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4125937448
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2016804766
Short name T563
Test name
Test status
Simulation time 9447671262 ps
CPU time 13.72 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:24:06 PM PST 24
Peak memory 198948 kb
Host smart-394b796a-e08a-474b-b789-28a7f82d599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016804766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2016804766
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.635680606
Short name T928
Test name
Test status
Simulation time 161720982227 ps
CPU time 45.89 seconds
Started Mar 03 01:23:51 PM PST 24
Finished Mar 03 01:24:37 PM PST 24
Peak memory 199660 kb
Host smart-258a0def-a297-4d47-8c48-1d8761512e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635680606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.635680606
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4219906219
Short name T430
Test name
Test status
Simulation time 15542981024 ps
CPU time 416.97 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:30:49 PM PST 24
Peak memory 199640 kb
Host smart-60562170-f8f8-4cf3-948f-cb774b96d6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219906219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4219906219
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.477090089
Short name T987
Test name
Test status
Simulation time 103521971721 ps
CPU time 75.11 seconds
Started Mar 03 01:23:54 PM PST 24
Finished Mar 03 01:25:09 PM PST 24
Peak memory 199680 kb
Host smart-1b8a80bc-b082-4304-b1a7-9faa9ea8e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477090089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.477090089
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2999348786
Short name T749
Test name
Test status
Simulation time 2852102021 ps
CPU time 1.94 seconds
Started Mar 03 01:23:51 PM PST 24
Finished Mar 03 01:23:54 PM PST 24
Peak memory 195248 kb
Host smart-0372c2d3-fb8e-45f6-bc60-a987f433323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999348786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2999348786
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1651463474
Short name T956
Test name
Test status
Simulation time 447140584 ps
CPU time 1.97 seconds
Started Mar 03 01:23:52 PM PST 24
Finished Mar 03 01:23:54 PM PST 24
Peak memory 197364 kb
Host smart-9dc9f35b-2472-4c2f-ab33-b473610e52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651463474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1651463474
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3055888961
Short name T754
Test name
Test status
Simulation time 1367943508037 ps
CPU time 252.03 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:28:11 PM PST 24
Peak memory 216012 kb
Host smart-a607d8f1-51eb-450a-99d8-1df4a451b141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055888961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3055888961
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2686421942
Short name T798
Test name
Test status
Simulation time 6810927066 ps
CPU time 8.22 seconds
Started Mar 03 01:23:51 PM PST 24
Finished Mar 03 01:23:59 PM PST 24
Peak memory 199004 kb
Host smart-1c924812-936d-4b7c-8cb3-bc9486a1f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686421942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2686421942
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.906398510
Short name T808
Test name
Test status
Simulation time 131305434740 ps
CPU time 322.25 seconds
Started Mar 03 01:23:51 PM PST 24
Finished Mar 03 01:29:14 PM PST 24
Peak memory 199656 kb
Host smart-187dad3c-5f45-4f89-8793-5f5820a5c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906398510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.906398510
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.451511079
Short name T230
Test name
Test status
Simulation time 64569965571 ps
CPU time 27.29 seconds
Started Mar 03 01:29:13 PM PST 24
Finished Mar 03 01:29:40 PM PST 24
Peak memory 199480 kb
Host smart-f9aaf9f6-4de0-4bf5-afc2-c23f67e530dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451511079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.451511079
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1197886696
Short name T572
Test name
Test status
Simulation time 117712368550 ps
CPU time 41.57 seconds
Started Mar 03 01:29:13 PM PST 24
Finished Mar 03 01:29:54 PM PST 24
Peak memory 199600 kb
Host smart-ec654b18-4514-4731-b00a-ef17041c6f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197886696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1197886696
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3943570356
Short name T322
Test name
Test status
Simulation time 8633978024 ps
CPU time 8.62 seconds
Started Mar 03 01:29:12 PM PST 24
Finished Mar 03 01:29:21 PM PST 24
Peak memory 199764 kb
Host smart-7c64a15f-4eb1-4363-bc15-8990ad013034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943570356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3943570356
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1912832304
Short name T140
Test name
Test status
Simulation time 19829241592 ps
CPU time 35.01 seconds
Started Mar 03 01:29:09 PM PST 24
Finished Mar 03 01:29:44 PM PST 24
Peak memory 199532 kb
Host smart-6260d116-62bb-4c3a-a54c-c2517f5184e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912832304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1912832304
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1352299269
Short name T637
Test name
Test status
Simulation time 111843203472 ps
CPU time 50.7 seconds
Started Mar 03 01:29:09 PM PST 24
Finished Mar 03 01:30:00 PM PST 24
Peak memory 199672 kb
Host smart-2b6e4952-59fb-4e3d-a2d5-f8a460716f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352299269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1352299269
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1429351313
Short name T1090
Test name
Test status
Simulation time 44680353487 ps
CPU time 87.51 seconds
Started Mar 03 01:29:19 PM PST 24
Finished Mar 03 01:30:47 PM PST 24
Peak memory 199652 kb
Host smart-3043136e-69d4-4ef2-98db-70b274dd519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429351313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1429351313
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1044469232
Short name T660
Test name
Test status
Simulation time 100969970285 ps
CPU time 16.47 seconds
Started Mar 03 01:29:17 PM PST 24
Finished Mar 03 01:29:34 PM PST 24
Peak memory 197756 kb
Host smart-895677e0-4f0b-4f5c-ad24-abfdde415fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044469232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1044469232
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.499452649
Short name T336
Test name
Test status
Simulation time 35295177519 ps
CPU time 29.54 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:29:48 PM PST 24
Peak memory 199112 kb
Host smart-0a71675a-2eaf-4640-b712-eb7b18d409ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499452649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.499452649
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1794762194
Short name T662
Test name
Test status
Simulation time 45609631804 ps
CPU time 35.86 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:29:54 PM PST 24
Peak memory 199680 kb
Host smart-b837235f-17a0-40d6-a146-109b202953d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794762194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1794762194
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.800292775
Short name T689
Test name
Test status
Simulation time 13847835 ps
CPU time 0.55 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:24:00 PM PST 24
Peak memory 194180 kb
Host smart-4b7b46c0-5e30-4c89-8be3-5fbad6559311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800292775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.800292775
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3591391906
Short name T583
Test name
Test status
Simulation time 44144493932 ps
CPU time 38.93 seconds
Started Mar 03 01:24:01 PM PST 24
Finished Mar 03 01:24:41 PM PST 24
Peak memory 199712 kb
Host smart-c9539b93-d633-4d73-a8e5-91f2e3f68ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591391906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3591391906
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.413022403
Short name T424
Test name
Test status
Simulation time 85424304046 ps
CPU time 122.97 seconds
Started Mar 03 01:24:03 PM PST 24
Finished Mar 03 01:26:07 PM PST 24
Peak memory 199596 kb
Host smart-8ea27f29-a5e8-40af-92be-4c96c03b539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413022403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.413022403
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1455482234
Short name T819
Test name
Test status
Simulation time 21178607169 ps
CPU time 35.28 seconds
Started Mar 03 01:24:00 PM PST 24
Finished Mar 03 01:24:36 PM PST 24
Peak memory 199400 kb
Host smart-510e01f1-9b75-4e85-bcdc-55c1aa78ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455482234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1455482234
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2086306191
Short name T588
Test name
Test status
Simulation time 257952949113 ps
CPU time 166.85 seconds
Started Mar 03 01:24:01 PM PST 24
Finished Mar 03 01:26:49 PM PST 24
Peak memory 198464 kb
Host smart-ebb7567c-6328-4e2b-ab11-c29e6b634255
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086306191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2086306191
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1302623235
Short name T675
Test name
Test status
Simulation time 209044272740 ps
CPU time 676.58 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:35:15 PM PST 24
Peak memory 199676 kb
Host smart-c4579d0b-705c-4129-9f25-b40d1be8d345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302623235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1302623235
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3357700737
Short name T179
Test name
Test status
Simulation time 90827205348 ps
CPU time 156.45 seconds
Started Mar 03 01:24:01 PM PST 24
Finished Mar 03 01:26:39 PM PST 24
Peak memory 198448 kb
Host smart-30ffe2bf-6d35-4420-8314-3a180330188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357700737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3357700737
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3186723636
Short name T933
Test name
Test status
Simulation time 45357324771 ps
CPU time 209.36 seconds
Started Mar 03 01:24:01 PM PST 24
Finished Mar 03 01:27:32 PM PST 24
Peak memory 199540 kb
Host smart-7b96cf7a-9fd0-4ce6-b3b3-5b7c113e2d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186723636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3186723636
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.786642063
Short name T325
Test name
Test status
Simulation time 196493211196 ps
CPU time 54.86 seconds
Started Mar 03 01:24:02 PM PST 24
Finished Mar 03 01:24:58 PM PST 24
Peak memory 199600 kb
Host smart-c507e1c7-e6ac-4ce5-9441-d39f9ba1e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786642063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.786642063
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1019945542
Short name T810
Test name
Test status
Simulation time 3046155296 ps
CPU time 2.24 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:24:01 PM PST 24
Peak memory 195116 kb
Host smart-c96c3d9d-6643-4ba0-a7d5-0795dced9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019945542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1019945542
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3845786351
Short name T680
Test name
Test status
Simulation time 276649600 ps
CPU time 1.36 seconds
Started Mar 03 01:24:01 PM PST 24
Finished Mar 03 01:24:03 PM PST 24
Peak memory 197940 kb
Host smart-a0b30189-cad8-46ad-92bd-29bec348b83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845786351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3845786351
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1744962972
Short name T449
Test name
Test status
Simulation time 1825900193490 ps
CPU time 1451.82 seconds
Started Mar 03 01:23:59 PM PST 24
Finished Mar 03 01:48:12 PM PST 24
Peak memory 225588 kb
Host smart-32c1a93c-6edc-4c0a-979a-3e9f362efe0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744962972 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1744962972
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1631619882
Short name T854
Test name
Test status
Simulation time 875916185 ps
CPU time 1.89 seconds
Started Mar 03 01:24:00 PM PST 24
Finished Mar 03 01:24:02 PM PST 24
Peak memory 197936 kb
Host smart-b75efd23-86ed-4baa-8fb5-68611794bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631619882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1631619882
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3366711755
Short name T845
Test name
Test status
Simulation time 72972406356 ps
CPU time 123.5 seconds
Started Mar 03 01:24:00 PM PST 24
Finished Mar 03 01:26:05 PM PST 24
Peak memory 199728 kb
Host smart-3cd2d33e-a7ac-4b28-8341-608006305027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366711755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3366711755
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3792664575
Short name T194
Test name
Test status
Simulation time 222241069534 ps
CPU time 38.66 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:29:57 PM PST 24
Peak memory 199664 kb
Host smart-6f1d7c9a-24ec-4bbd-b008-f85675c13296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792664575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3792664575
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2836578052
Short name T382
Test name
Test status
Simulation time 39566861298 ps
CPU time 40.57 seconds
Started Mar 03 01:29:18 PM PST 24
Finished Mar 03 01:29:59 PM PST 24
Peak memory 199664 kb
Host smart-542b1e05-b173-4073-bce8-b80167344958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836578052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2836578052
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3989865104
Short name T770
Test name
Test status
Simulation time 65508920790 ps
CPU time 16.05 seconds
Started Mar 03 01:29:17 PM PST 24
Finished Mar 03 01:29:34 PM PST 24
Peak memory 199236 kb
Host smart-e4d51882-0ad3-4c9f-9590-85857e57f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989865104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3989865104
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3536124031
Short name T254
Test name
Test status
Simulation time 13922839783 ps
CPU time 10.62 seconds
Started Mar 03 01:29:24 PM PST 24
Finished Mar 03 01:29:35 PM PST 24
Peak memory 197980 kb
Host smart-9d11329c-f8c2-4ef9-ae88-227d01cf7f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536124031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3536124031
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3112700303
Short name T465
Test name
Test status
Simulation time 30184538 ps
CPU time 0.59 seconds
Started Mar 03 01:24:08 PM PST 24
Finished Mar 03 01:24:09 PM PST 24
Peak memory 195264 kb
Host smart-cfeeeeee-78eb-411a-b83c-8046b95a6727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112700303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3112700303
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2459477854
Short name T818
Test name
Test status
Simulation time 222953703490 ps
CPU time 299.38 seconds
Started Mar 03 01:24:06 PM PST 24
Finished Mar 03 01:29:07 PM PST 24
Peak memory 199660 kb
Host smart-f22023a0-83c1-423f-b59e-f9561e124f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459477854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2459477854
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.871205972
Short name T732
Test name
Test status
Simulation time 27403560518 ps
CPU time 38.12 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:46 PM PST 24
Peak memory 198304 kb
Host smart-7bfbfa53-338e-475e-9c89-6501b60acaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871205972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.871205972
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.2234846823
Short name T246
Test name
Test status
Simulation time 55607423825 ps
CPU time 46.8 seconds
Started Mar 03 01:24:08 PM PST 24
Finished Mar 03 01:24:55 PM PST 24
Peak memory 199376 kb
Host smart-229e99c8-4efb-47d9-bd2b-9c84da40a231
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234846823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2234846823
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3804204553
Short name T403
Test name
Test status
Simulation time 175330712739 ps
CPU time 382.05 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:30:30 PM PST 24
Peak memory 199752 kb
Host smart-0913c8cb-d203-4bc9-b204-9e1ec70067a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804204553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3804204553
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.32363485
Short name T467
Test name
Test status
Simulation time 11419955132 ps
CPU time 3 seconds
Started Mar 03 01:24:09 PM PST 24
Finished Mar 03 01:24:12 PM PST 24
Peak memory 198384 kb
Host smart-b2c48102-96b7-429a-b00e-c0eec67a3dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32363485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.32363485
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1875290624
Short name T413
Test name
Test status
Simulation time 12255111998 ps
CPU time 5.32 seconds
Started Mar 03 01:24:10 PM PST 24
Finished Mar 03 01:24:16 PM PST 24
Peak memory 194380 kb
Host smart-fdd47c52-f7a6-4252-ba16-4767e2e2a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875290624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1875290624
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1764956014
Short name T149
Test name
Test status
Simulation time 16871601536 ps
CPU time 876.53 seconds
Started Mar 03 01:24:10 PM PST 24
Finished Mar 03 01:38:47 PM PST 24
Peak memory 199604 kb
Host smart-57839669-bd3c-4d93-a4f4-cf2845e39aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764956014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1764956014
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1434896547
Short name T471
Test name
Test status
Simulation time 3114899503 ps
CPU time 12.07 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:20 PM PST 24
Peak memory 198384 kb
Host smart-2c4a35a1-79bc-4697-8beb-e5e05d7f5518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434896547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1434896547
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3275458577
Short name T564
Test name
Test status
Simulation time 27487859177 ps
CPU time 11.98 seconds
Started Mar 03 01:24:05 PM PST 24
Finished Mar 03 01:24:18 PM PST 24
Peak memory 195600 kb
Host smart-35825d07-1a23-4c50-b687-835cf9f062a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275458577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3275458577
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1482313116
Short name T600
Test name
Test status
Simulation time 5625904895 ps
CPU time 17.77 seconds
Started Mar 03 01:24:00 PM PST 24
Finished Mar 03 01:24:18 PM PST 24
Peak memory 198896 kb
Host smart-5d54ec05-48f7-4ff7-9d5c-3a2e01b8146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482313116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1482313116
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1035430522
Short name T113
Test name
Test status
Simulation time 32091899817 ps
CPU time 167.74 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:26:55 PM PST 24
Peak memory 210600 kb
Host smart-907e75c4-7576-4f7a-bf04-9a1d8218d9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035430522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1035430522
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2808076088
Short name T871
Test name
Test status
Simulation time 1210618476 ps
CPU time 2.03 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:10 PM PST 24
Peak memory 198032 kb
Host smart-e1cfcf2a-b03f-4134-851d-9eed1c2388ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808076088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2808076088
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.761598983
Short name T873
Test name
Test status
Simulation time 57997601357 ps
CPU time 47.44 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:55 PM PST 24
Peak memory 199548 kb
Host smart-8e5906b0-a759-44d6-a96d-8c652f92074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761598983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.761598983
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1040111366
Short name T259
Test name
Test status
Simulation time 37938242069 ps
CPU time 29.34 seconds
Started Mar 03 01:29:26 PM PST 24
Finished Mar 03 01:29:56 PM PST 24
Peak memory 199704 kb
Host smart-8af72190-5221-4c4e-a85c-f738364fea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040111366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1040111366
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.932997315
Short name T743
Test name
Test status
Simulation time 29625078181 ps
CPU time 15.09 seconds
Started Mar 03 01:29:33 PM PST 24
Finished Mar 03 01:29:48 PM PST 24
Peak memory 199656 kb
Host smart-4137e214-a45b-4a37-b9cf-f8e2d6e81487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932997315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.932997315
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1104638821
Short name T915
Test name
Test status
Simulation time 18661318869 ps
CPU time 41.29 seconds
Started Mar 03 01:29:33 PM PST 24
Finished Mar 03 01:30:14 PM PST 24
Peak memory 199608 kb
Host smart-9d2648bd-6fdc-4d62-bef1-b0b61957c236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104638821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1104638821
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2415234138
Short name T210
Test name
Test status
Simulation time 45566484127 ps
CPU time 43.7 seconds
Started Mar 03 01:29:35 PM PST 24
Finished Mar 03 01:30:18 PM PST 24
Peak memory 199460 kb
Host smart-579236bb-32c4-44db-a3ac-d8c073f217cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415234138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2415234138
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1641886775
Short name T692
Test name
Test status
Simulation time 133728692412 ps
CPU time 230.29 seconds
Started Mar 03 01:29:40 PM PST 24
Finished Mar 03 01:33:30 PM PST 24
Peak memory 199720 kb
Host smart-3ac3e728-e13c-4fb1-b59d-8b62f15dab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641886775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1641886775
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.645398165
Short name T165
Test name
Test status
Simulation time 125322983293 ps
CPU time 55.64 seconds
Started Mar 03 01:29:40 PM PST 24
Finished Mar 03 01:30:35 PM PST 24
Peak memory 199680 kb
Host smart-3cf55f79-1ffe-4170-a91f-60d0ecc60f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645398165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.645398165
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2516739088
Short name T1026
Test name
Test status
Simulation time 135782472589 ps
CPU time 203.57 seconds
Started Mar 03 01:29:40 PM PST 24
Finished Mar 03 01:33:03 PM PST 24
Peak memory 199460 kb
Host smart-30ea1d9c-ea8a-492d-b6bf-63deb8c76b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516739088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2516739088
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1345409662
Short name T785
Test name
Test status
Simulation time 13175947 ps
CPU time 0.54 seconds
Started Mar 03 01:24:13 PM PST 24
Finished Mar 03 01:24:14 PM PST 24
Peak memory 195136 kb
Host smart-78f13b6d-d04d-436e-b26a-e75db9067ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345409662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1345409662
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.495264467
Short name T277
Test name
Test status
Simulation time 68610910254 ps
CPU time 48.35 seconds
Started Mar 03 01:24:08 PM PST 24
Finished Mar 03 01:24:57 PM PST 24
Peak memory 199604 kb
Host smart-125a8b69-7780-465f-b259-c06f77eec277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495264467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.495264467
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2887772350
Short name T927
Test name
Test status
Simulation time 31211319310 ps
CPU time 53.25 seconds
Started Mar 03 01:24:10 PM PST 24
Finished Mar 03 01:25:04 PM PST 24
Peak memory 199724 kb
Host smart-385c033c-a456-4be4-bf37-b110bf0c3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887772350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2887772350
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.322428690
Short name T736
Test name
Test status
Simulation time 37554054992 ps
CPU time 30.48 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:39 PM PST 24
Peak memory 197508 kb
Host smart-a245f7d8-c37c-4e2b-81d1-7deb6c3c26c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322428690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.322428690
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2504870049
Short name T1069
Test name
Test status
Simulation time 31967351928 ps
CPU time 21.03 seconds
Started Mar 03 01:24:13 PM PST 24
Finished Mar 03 01:24:34 PM PST 24
Peak memory 199688 kb
Host smart-4dea9024-6d75-4ab6-90aa-481023c6b4e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504870049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2504870049
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3407605932
Short name T404
Test name
Test status
Simulation time 50256156096 ps
CPU time 185.68 seconds
Started Mar 03 01:24:13 PM PST 24
Finished Mar 03 01:27:19 PM PST 24
Peak memory 199700 kb
Host smart-9dc1e93f-615c-4c27-ab13-c2b51803ee9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407605932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3407605932
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3809825365
Short name T543
Test name
Test status
Simulation time 1730716647 ps
CPU time 1.69 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:24:15 PM PST 24
Peak memory 196844 kb
Host smart-f9c2810d-a0f6-407b-8074-d6a49ea51903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809825365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3809825365
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.763518083
Short name T1015
Test name
Test status
Simulation time 44308483019 ps
CPU time 61.19 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:25:15 PM PST 24
Peak memory 198400 kb
Host smart-3a972d94-5548-4ae0-8dda-dbc735a9c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763518083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.763518083
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.278732673
Short name T43
Test name
Test status
Simulation time 7758802384 ps
CPU time 213.24 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:27:47 PM PST 24
Peak memory 199660 kb
Host smart-ed250686-96e1-434c-8d6b-79d14d9c73b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278732673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.278732673
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1728835216
Short name T628
Test name
Test status
Simulation time 2579549761 ps
CPU time 6.82 seconds
Started Mar 03 01:24:13 PM PST 24
Finished Mar 03 01:24:20 PM PST 24
Peak memory 197912 kb
Host smart-040c3783-f824-4284-a4a6-b733a6cd7df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728835216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1728835216
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.308946030
Short name T407
Test name
Test status
Simulation time 3245446103 ps
CPU time 6.12 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:24:21 PM PST 24
Peak memory 195512 kb
Host smart-ec9d04bf-edcf-4235-ae88-876074b01c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308946030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.308946030
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2314007598
Short name T809
Test name
Test status
Simulation time 128908540 ps
CPU time 0.79 seconds
Started Mar 03 01:24:07 PM PST 24
Finished Mar 03 01:24:08 PM PST 24
Peak memory 196588 kb
Host smart-fba1956f-a313-45fa-b10f-1156ac2cf141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314007598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2314007598
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.66886637
Short name T125
Test name
Test status
Simulation time 296183275648 ps
CPU time 272.43 seconds
Started Mar 03 01:24:16 PM PST 24
Finished Mar 03 01:28:49 PM PST 24
Peak memory 199676 kb
Host smart-3b83596c-9140-40e4-8a4b-5359d7865a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66886637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.66886637
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4152638590
Short name T104
Test name
Test status
Simulation time 6579303151 ps
CPU time 14 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:24:28 PM PST 24
Peak memory 199144 kb
Host smart-518d78e1-8884-44cd-904b-60739fa98e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152638590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4152638590
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.986326113
Short name T647
Test name
Test status
Simulation time 40074417016 ps
CPU time 13.03 seconds
Started Mar 03 01:24:08 PM PST 24
Finished Mar 03 01:24:22 PM PST 24
Peak memory 199740 kb
Host smart-6d847933-397e-4237-93bb-01c2361ae735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986326113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.986326113
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3285727805
Short name T168
Test name
Test status
Simulation time 30986858574 ps
CPU time 28.3 seconds
Started Mar 03 01:29:41 PM PST 24
Finished Mar 03 01:30:10 PM PST 24
Peak memory 199636 kb
Host smart-4b09a13b-c899-45ef-bc32-d95bc0cfb1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285727805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3285727805
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1087244094
Short name T965
Test name
Test status
Simulation time 50468165332 ps
CPU time 33.97 seconds
Started Mar 03 01:29:42 PM PST 24
Finished Mar 03 01:30:16 PM PST 24
Peak memory 199524 kb
Host smart-7ff42138-9e2c-4ba6-99f9-cb76a93902a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087244094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1087244094
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3431353252
Short name T8
Test name
Test status
Simulation time 97041588626 ps
CPU time 75.39 seconds
Started Mar 03 01:29:42 PM PST 24
Finished Mar 03 01:30:58 PM PST 24
Peak memory 199656 kb
Host smart-2b99d8c0-4dbf-47e1-beec-7de51c7fdeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431353252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3431353252
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1510964502
Short name T700
Test name
Test status
Simulation time 17833666276 ps
CPU time 8.88 seconds
Started Mar 03 01:29:44 PM PST 24
Finished Mar 03 01:29:53 PM PST 24
Peak memory 199660 kb
Host smart-13e28a61-d73f-40ad-8774-071926edbbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510964502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1510964502
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2680200240
Short name T590
Test name
Test status
Simulation time 37823246299 ps
CPU time 14.46 seconds
Started Mar 03 01:29:41 PM PST 24
Finished Mar 03 01:29:55 PM PST 24
Peak memory 199528 kb
Host smart-97524b9b-eb6d-4d98-94d7-f2ea3191cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680200240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2680200240
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3260503177
Short name T143
Test name
Test status
Simulation time 75246091610 ps
CPU time 59.18 seconds
Started Mar 03 01:29:44 PM PST 24
Finished Mar 03 01:30:43 PM PST 24
Peak memory 199624 kb
Host smart-e4eb684a-351b-4928-bd63-b202d9b4b0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260503177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3260503177
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.553140569
Short name T910
Test name
Test status
Simulation time 20239346041 ps
CPU time 33.72 seconds
Started Mar 03 01:29:42 PM PST 24
Finished Mar 03 01:30:16 PM PST 24
Peak memory 198772 kb
Host smart-50b20611-0fb0-4614-b9fc-4b6cb5f01aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553140569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.553140569
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.457968937
Short name T27
Test name
Test status
Simulation time 142830598 ps
CPU time 0.53 seconds
Started Mar 03 01:24:22 PM PST 24
Finished Mar 03 01:24:23 PM PST 24
Peak memory 195272 kb
Host smart-48f98fd7-24bc-4ae1-8c59-0faa684de0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457968937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.457968937
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2074231877
Short name T377
Test name
Test status
Simulation time 65659549810 ps
CPU time 30.36 seconds
Started Mar 03 01:24:16 PM PST 24
Finished Mar 03 01:24:47 PM PST 24
Peak memory 199636 kb
Host smart-e9062973-7c90-47a1-8e33-5708f8fb2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074231877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2074231877
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1552192660
Short name T708
Test name
Test status
Simulation time 112697925667 ps
CPU time 137.43 seconds
Started Mar 03 01:24:14 PM PST 24
Finished Mar 03 01:26:32 PM PST 24
Peak memory 199004 kb
Host smart-db9548e9-29ca-444c-b08c-11cfc28b3884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552192660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1552192660
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.519606835
Short name T802
Test name
Test status
Simulation time 327682070250 ps
CPU time 1269.79 seconds
Started Mar 03 01:24:20 PM PST 24
Finished Mar 03 01:45:30 PM PST 24
Peak memory 199576 kb
Host smart-24c10ce8-4bd9-4c8d-ab3e-01b04bace845
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519606835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.519606835
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2676421520
Short name T653
Test name
Test status
Simulation time 195347419678 ps
CPU time 431.42 seconds
Started Mar 03 01:24:21 PM PST 24
Finished Mar 03 01:31:33 PM PST 24
Peak memory 199680 kb
Host smart-e01e68b7-53f5-4d2a-bb61-abc11590c1db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676421520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2676421520
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2491385751
Short name T870
Test name
Test status
Simulation time 3518710089 ps
CPU time 4.97 seconds
Started Mar 03 01:24:20 PM PST 24
Finished Mar 03 01:24:25 PM PST 24
Peak memory 198020 kb
Host smart-8add9be2-04d0-40e6-b6dd-7562a1cdd31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491385751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2491385751
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3383905978
Short name T414
Test name
Test status
Simulation time 71613984319 ps
CPU time 44.57 seconds
Started Mar 03 01:24:20 PM PST 24
Finished Mar 03 01:25:05 PM PST 24
Peak memory 199016 kb
Host smart-49454198-3775-46d6-9cc0-fc8e8980bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383905978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3383905978
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1078689817
Short name T725
Test name
Test status
Simulation time 28760017452 ps
CPU time 354.31 seconds
Started Mar 03 01:24:22 PM PST 24
Finished Mar 03 01:30:16 PM PST 24
Peak memory 199656 kb
Host smart-0af5d3ca-bd63-4591-9ecc-f2b5ddba86a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078689817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1078689817
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.392372215
Short name T383
Test name
Test status
Simulation time 31724993843 ps
CPU time 18.21 seconds
Started Mar 03 01:24:21 PM PST 24
Finished Mar 03 01:24:40 PM PST 24
Peak memory 198552 kb
Host smart-84c28fed-ba2e-4997-91b4-6bb4dd3ccc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392372215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.392372215
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.272858966
Short name T835
Test name
Test status
Simulation time 2773220153 ps
CPU time 1.7 seconds
Started Mar 03 01:24:22 PM PST 24
Finished Mar 03 01:24:23 PM PST 24
Peak memory 195200 kb
Host smart-46f6f1b3-961a-4413-b2e0-76a003dfe812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272858966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.272858966
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4014665853
Short name T839
Test name
Test status
Simulation time 295390772 ps
CPU time 1.02 seconds
Started Mar 03 01:24:18 PM PST 24
Finished Mar 03 01:24:19 PM PST 24
Peak memory 197884 kb
Host smart-25f240aa-3cda-41f4-a04c-7827f9348977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014665853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4014665853
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1191680209
Short name T177
Test name
Test status
Simulation time 31291275890 ps
CPU time 550.83 seconds
Started Mar 03 01:24:23 PM PST 24
Finished Mar 03 01:33:34 PM PST 24
Peak memory 199788 kb
Host smart-0ea1de46-8518-49ad-beb7-e28bafe7ef16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191680209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1191680209
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1344173325
Short name T918
Test name
Test status
Simulation time 93292697497 ps
CPU time 545.21 seconds
Started Mar 03 01:24:22 PM PST 24
Finished Mar 03 01:33:28 PM PST 24
Peak memory 215420 kb
Host smart-3f1902e4-3a7f-451a-a91b-9b302ec1f8f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344173325 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1344173325
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4132946669
Short name T913
Test name
Test status
Simulation time 9212868154 ps
CPU time 6.65 seconds
Started Mar 03 01:24:20 PM PST 24
Finished Mar 03 01:24:27 PM PST 24
Peak memory 199400 kb
Host smart-947b7f85-3b8c-4f89-a83b-dd7d8d912899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132946669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4132946669
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3433876921
Short name T586
Test name
Test status
Simulation time 51652277142 ps
CPU time 12.1 seconds
Started Mar 03 01:24:18 PM PST 24
Finished Mar 03 01:24:30 PM PST 24
Peak memory 199744 kb
Host smart-504b2e36-7edb-4b13-ab55-e3a704ecd6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433876921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3433876921
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3419821450
Short name T972
Test name
Test status
Simulation time 6824240063 ps
CPU time 6.61 seconds
Started Mar 03 01:29:40 PM PST 24
Finished Mar 03 01:29:47 PM PST 24
Peak memory 198648 kb
Host smart-828f0549-7a47-4e64-ad03-c26e551be3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419821450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3419821450
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2633078738
Short name T687
Test name
Test status
Simulation time 82663194778 ps
CPU time 37.56 seconds
Started Mar 03 01:29:42 PM PST 24
Finished Mar 03 01:30:20 PM PST 24
Peak memory 199380 kb
Host smart-fb7d7dcf-dea9-4220-a4a7-d353c97022b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633078738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2633078738
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1737656222
Short name T121
Test name
Test status
Simulation time 85203963137 ps
CPU time 126.34 seconds
Started Mar 03 01:29:39 PM PST 24
Finished Mar 03 01:31:46 PM PST 24
Peak memory 199744 kb
Host smart-4f5ae2a2-aa13-4362-a93b-e2a35d668bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737656222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1737656222
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1942641061
Short name T263
Test name
Test status
Simulation time 93596912558 ps
CPU time 12.84 seconds
Started Mar 03 01:29:41 PM PST 24
Finished Mar 03 01:29:54 PM PST 24
Peak memory 199636 kb
Host smart-15d17c50-c6c0-4c3c-8222-85a3bc9b39df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942641061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1942641061
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.46495274
Short name T314
Test name
Test status
Simulation time 117546436634 ps
CPU time 49.05 seconds
Started Mar 03 01:29:43 PM PST 24
Finished Mar 03 01:30:32 PM PST 24
Peak memory 199704 kb
Host smart-7e143bb7-3118-4542-8f47-fde3579a43ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46495274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.46495274
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3456998293
Short name T800
Test name
Test status
Simulation time 39621688326 ps
CPU time 61.98 seconds
Started Mar 03 01:29:47 PM PST 24
Finished Mar 03 01:30:50 PM PST 24
Peak memory 199524 kb
Host smart-020f4e8a-b653-4e75-a66a-f37db0dc7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456998293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3456998293
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1213161541
Short name T260
Test name
Test status
Simulation time 180559372086 ps
CPU time 119.02 seconds
Started Mar 03 01:29:48 PM PST 24
Finished Mar 03 01:31:47 PM PST 24
Peak memory 199632 kb
Host smart-faa91af9-95d5-4f30-820e-10fa14686a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213161541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1213161541
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.807084468
Short name T1059
Test name
Test status
Simulation time 20575691103 ps
CPU time 40 seconds
Started Mar 03 01:29:47 PM PST 24
Finished Mar 03 01:30:27 PM PST 24
Peak memory 199576 kb
Host smart-d0f568d2-4320-4023-bf29-c1073b9ba3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807084468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.807084468
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3917607446
Short name T751
Test name
Test status
Simulation time 14607400 ps
CPU time 0.58 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:24:30 PM PST 24
Peak memory 195196 kb
Host smart-07c0bd84-78bc-41e0-8206-dc5e8313334a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917607446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3917607446
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3632286221
Short name T1092
Test name
Test status
Simulation time 62783128172 ps
CPU time 48.2 seconds
Started Mar 03 01:24:21 PM PST 24
Finished Mar 03 01:25:09 PM PST 24
Peak memory 199648 kb
Host smart-236c37ed-4bee-44d2-b1e9-7d75a226a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632286221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3632286221
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1195051625
Short name T1033
Test name
Test status
Simulation time 48912664142 ps
CPU time 36.08 seconds
Started Mar 03 01:24:27 PM PST 24
Finished Mar 03 01:25:04 PM PST 24
Peak memory 199556 kb
Host smart-6149db24-c7bd-44cf-8381-e80bc4bcda74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195051625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1195051625
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1074211824
Short name T1007
Test name
Test status
Simulation time 18220071406 ps
CPU time 28.73 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:24:58 PM PST 24
Peak memory 199268 kb
Host smart-1442933d-ee7a-45a3-8777-9bc250d6f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074211824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1074211824
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4080231341
Short name T828
Test name
Test status
Simulation time 198926804043 ps
CPU time 173.69 seconds
Started Mar 03 01:24:28 PM PST 24
Finished Mar 03 01:27:22 PM PST 24
Peak memory 199732 kb
Host smart-64ba1514-5eba-4c17-bed1-7f472ab5e127
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080231341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4080231341
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3793447347
Short name T1020
Test name
Test status
Simulation time 138739419737 ps
CPU time 537.98 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:33:27 PM PST 24
Peak memory 199756 kb
Host smart-370c75e0-4fd2-43fa-bd55-04e7476d6e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793447347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3793447347
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2272903805
Short name T466
Test name
Test status
Simulation time 3680789329 ps
CPU time 6.73 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:24:36 PM PST 24
Peak memory 196904 kb
Host smart-776ed69f-a326-422f-8565-9160ff39879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272903805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2272903805
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.345925014
Short name T555
Test name
Test status
Simulation time 86667216798 ps
CPU time 143.06 seconds
Started Mar 03 01:24:27 PM PST 24
Finished Mar 03 01:26:50 PM PST 24
Peak memory 198396 kb
Host smart-d719bf72-0717-4396-b166-672bafdd8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345925014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.345925014
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3182206248
Short name T155
Test name
Test status
Simulation time 14268357028 ps
CPU time 739.78 seconds
Started Mar 03 01:24:28 PM PST 24
Finished Mar 03 01:36:48 PM PST 24
Peak memory 199636 kb
Host smart-07474756-7c5b-4398-9b64-5cf445688922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182206248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3182206248
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.328123468
Short name T454
Test name
Test status
Simulation time 132676188 ps
CPU time 0.99 seconds
Started Mar 03 01:24:28 PM PST 24
Finished Mar 03 01:24:29 PM PST 24
Peak memory 197388 kb
Host smart-b308c599-24f9-45ae-9d8b-af8c0ea1a51c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328123468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.328123468
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.485926523
Short name T485
Test name
Test status
Simulation time 131868782608 ps
CPU time 219.68 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 199636 kb
Host smart-b620f4be-1633-47d4-90a2-be912568bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485926523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.485926523
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2341442611
Short name T1041
Test name
Test status
Simulation time 1440012324 ps
CPU time 1.12 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:24:30 PM PST 24
Peak memory 195228 kb
Host smart-b7e8ea29-e04e-4968-ab37-75d7e261cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341442611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2341442611
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1968251505
Short name T419
Test name
Test status
Simulation time 915318018 ps
CPU time 2.1 seconds
Started Mar 03 01:24:19 PM PST 24
Finished Mar 03 01:24:21 PM PST 24
Peak memory 197576 kb
Host smart-76810dc1-d11d-4478-af20-9d551d422114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968251505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1968251505
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.884696036
Short name T368
Test name
Test status
Simulation time 329173767795 ps
CPU time 1034.34 seconds
Started Mar 03 01:24:28 PM PST 24
Finished Mar 03 01:41:43 PM PST 24
Peak memory 199700 kb
Host smart-d842c529-f259-485d-8926-ff1165b504a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884696036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.884696036
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2863369615
Short name T55
Test name
Test status
Simulation time 36789191588 ps
CPU time 83.37 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:25:52 PM PST 24
Peak memory 208008 kb
Host smart-10af809b-1b34-4f74-bb31-ad494fbe2e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863369615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2863369615
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1478077017
Short name T23
Test name
Test status
Simulation time 1071875768 ps
CPU time 3.36 seconds
Started Mar 03 01:24:27 PM PST 24
Finished Mar 03 01:24:31 PM PST 24
Peak memory 197996 kb
Host smart-fa69bf6f-e498-4dcf-9aea-e0c605ed1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478077017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1478077017
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1822681959
Short name T530
Test name
Test status
Simulation time 92039877559 ps
CPU time 46.54 seconds
Started Mar 03 01:24:20 PM PST 24
Finished Mar 03 01:25:07 PM PST 24
Peak memory 199748 kb
Host smart-545c7f5f-2bb2-4b62-a0be-6bff10ee4c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822681959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1822681959
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1218710723
Short name T217
Test name
Test status
Simulation time 14609949136 ps
CPU time 23.53 seconds
Started Mar 03 01:29:49 PM PST 24
Finished Mar 03 01:30:13 PM PST 24
Peak memory 198360 kb
Host smart-38e9e406-47dc-4bf8-ab4b-7ab3716e94f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218710723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1218710723
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1031857843
Short name T357
Test name
Test status
Simulation time 16777423184 ps
CPU time 14.84 seconds
Started Mar 03 01:29:50 PM PST 24
Finished Mar 03 01:30:05 PM PST 24
Peak memory 199652 kb
Host smart-b2887034-948b-463c-87c6-9d6987403743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031857843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1031857843
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4113069815
Short name T228
Test name
Test status
Simulation time 17730940506 ps
CPU time 32.13 seconds
Started Mar 03 01:29:49 PM PST 24
Finished Mar 03 01:30:21 PM PST 24
Peak memory 199312 kb
Host smart-b822e47f-fc16-4996-9006-c2d193cc476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113069815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4113069815
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1722044538
Short name T172
Test name
Test status
Simulation time 138525461734 ps
CPU time 57.76 seconds
Started Mar 03 01:29:49 PM PST 24
Finished Mar 03 01:30:47 PM PST 24
Peak memory 199352 kb
Host smart-90cd7465-5678-43d0-8db8-ecf9a864c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722044538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1722044538
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2629658781
Short name T198
Test name
Test status
Simulation time 124379693141 ps
CPU time 21.27 seconds
Started Mar 03 01:29:50 PM PST 24
Finished Mar 03 01:30:11 PM PST 24
Peak memory 199492 kb
Host smart-627af8a5-5093-47ca-b1b4-b1672bf0158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629658781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2629658781
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1859353744
Short name T782
Test name
Test status
Simulation time 52015879377 ps
CPU time 23.78 seconds
Started Mar 03 01:29:47 PM PST 24
Finished Mar 03 01:30:11 PM PST 24
Peak memory 199520 kb
Host smart-ed9ab6c7-5bc9-4a45-88f3-caab29efcdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859353744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1859353744
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3878078694
Short name T1091
Test name
Test status
Simulation time 89891952333 ps
CPU time 35.77 seconds
Started Mar 03 01:29:48 PM PST 24
Finished Mar 03 01:30:24 PM PST 24
Peak memory 199340 kb
Host smart-2e77f835-710e-4cbb-91f1-f49bfbf31d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878078694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3878078694
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1166895565
Short name T250
Test name
Test status
Simulation time 16058250382 ps
CPU time 13.38 seconds
Started Mar 03 01:29:50 PM PST 24
Finished Mar 03 01:30:03 PM PST 24
Peak memory 199608 kb
Host smart-1aecb684-0255-4d67-8926-590b3da5ce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166895565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1166895565
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.828641360
Short name T645
Test name
Test status
Simulation time 43297721 ps
CPU time 0.55 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:24:40 PM PST 24
Peak memory 195280 kb
Host smart-86c4296f-7d3b-434f-ab8d-539dcb8af7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828641360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.828641360
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2952749238
Short name T867
Test name
Test status
Simulation time 180179134199 ps
CPU time 27.97 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:25:06 PM PST 24
Peak memory 199640 kb
Host smart-6bec13c2-25a5-4a02-9a91-004129b7c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952749238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2952749238
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.3721972724
Short name T764
Test name
Test status
Simulation time 1171805886580 ps
CPU time 1822.87 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:55:01 PM PST 24
Peak memory 198404 kb
Host smart-85bac351-86d5-4267-aff1-8c2bb9bac0ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721972724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3721972724
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.288513990
Short name T859
Test name
Test status
Simulation time 55609880884 ps
CPU time 218.76 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:28:17 PM PST 24
Peak memory 199704 kb
Host smart-83c93ae2-90f4-445a-9bfa-45587747b003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288513990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.288513990
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2940233848
Short name T452
Test name
Test status
Simulation time 12894475885 ps
CPU time 28.67 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:25:08 PM PST 24
Peak memory 199548 kb
Host smart-3e771828-b060-4dc6-8f37-aa4ce23eafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940233848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2940233848
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.480175758
Short name T151
Test name
Test status
Simulation time 109943841097 ps
CPU time 173.94 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:27:32 PM PST 24
Peak memory 208008 kb
Host smart-0736cebc-b66e-4991-9992-dc0c28809ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480175758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.480175758
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1003233705
Short name T505
Test name
Test status
Simulation time 9990610803 ps
CPU time 111.8 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:26:31 PM PST 24
Peak memory 199624 kb
Host smart-c20dfb9f-aa9c-4974-8bd4-b384ec9377db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003233705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1003233705
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2315203164
Short name T777
Test name
Test status
Simulation time 2752522006 ps
CPU time 8.29 seconds
Started Mar 03 01:24:40 PM PST 24
Finished Mar 03 01:24:48 PM PST 24
Peak memory 198136 kb
Host smart-e44cae41-dc60-435a-ac18-c9bf9c159a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2315203164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2315203164
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4188762764
Short name T1085
Test name
Test status
Simulation time 140708929641 ps
CPU time 50.47 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:25:29 PM PST 24
Peak memory 199728 kb
Host smart-e1a7a6c8-6304-4dc0-a23d-059a9babba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188762764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4188762764
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2949481411
Short name T1003
Test name
Test status
Simulation time 44604645885 ps
CPU time 22.14 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:25:01 PM PST 24
Peak memory 195252 kb
Host smart-9fa0d26e-8f2d-4b8f-8468-6cef8663b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949481411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2949481411
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1056616072
Short name T548
Test name
Test status
Simulation time 572742346 ps
CPU time 1.72 seconds
Started Mar 03 01:24:29 PM PST 24
Finished Mar 03 01:24:31 PM PST 24
Peak memory 199616 kb
Host smart-df22c5ef-097f-407d-98cc-4f6e51a9179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056616072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1056616072
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4207371361
Short name T122
Test name
Test status
Simulation time 392471073103 ps
CPU time 179.22 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:27:37 PM PST 24
Peak memory 199668 kb
Host smart-d479fa47-845c-464a-a432-9a2a119d8803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207371361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4207371361
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1009398136
Short name T117
Test name
Test status
Simulation time 30548973513 ps
CPU time 338.81 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:30:18 PM PST 24
Peak memory 216256 kb
Host smart-fdb85324-fb3b-4863-8cdf-9eeed77df099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009398136 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1009398136
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1967945242
Short name T513
Test name
Test status
Simulation time 895826251 ps
CPU time 2.93 seconds
Started Mar 03 01:24:38 PM PST 24
Finished Mar 03 01:24:41 PM PST 24
Peak memory 198056 kb
Host smart-95092eb3-9b30-45ca-b2e6-9713995f69bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967945242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1967945242
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.101929864
Short name T484
Test name
Test status
Simulation time 64100148813 ps
CPU time 125.94 seconds
Started Mar 03 01:24:27 PM PST 24
Finished Mar 03 01:26:33 PM PST 24
Peak memory 199600 kb
Host smart-c9703064-2064-458e-a2f5-45ef5598bb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101929864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.101929864
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3327189344
Short name T187
Test name
Test status
Simulation time 181558891006 ps
CPU time 148.01 seconds
Started Mar 03 01:29:56 PM PST 24
Finished Mar 03 01:32:25 PM PST 24
Peak memory 199692 kb
Host smart-dda2fcdd-1de2-4fc1-823f-2928fdb2f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327189344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3327189344
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1760403967
Short name T270
Test name
Test status
Simulation time 15926888997 ps
CPU time 13.82 seconds
Started Mar 03 01:29:55 PM PST 24
Finished Mar 03 01:30:10 PM PST 24
Peak memory 199736 kb
Host smart-9e745420-3c30-49a1-9309-0640cea8f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760403967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1760403967
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3180795994
Short name T274
Test name
Test status
Simulation time 95375408229 ps
CPU time 77.35 seconds
Started Mar 03 01:29:55 PM PST 24
Finished Mar 03 01:31:14 PM PST 24
Peak memory 199468 kb
Host smart-41fe8367-3918-4cd8-897e-dcdf806c129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180795994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3180795994
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2196802911
Short name T159
Test name
Test status
Simulation time 13299603155 ps
CPU time 22.54 seconds
Started Mar 03 01:29:55 PM PST 24
Finished Mar 03 01:30:19 PM PST 24
Peak memory 199624 kb
Host smart-dc79ae03-b1b4-4487-9775-88b7516e08b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196802911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2196802911
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1010225852
Short name T144
Test name
Test status
Simulation time 16674738477 ps
CPU time 19.52 seconds
Started Mar 03 01:29:56 PM PST 24
Finished Mar 03 01:30:16 PM PST 24
Peak memory 199744 kb
Host smart-c64b19f9-c382-4dc2-b339-d55be8dd581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010225852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1010225852
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3657497458
Short name T477
Test name
Test status
Simulation time 10967355 ps
CPU time 0.53 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:22:43 PM PST 24
Peak memory 194316 kb
Host smart-21e06cfa-f3cd-4b36-80bb-eb05238f9c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657497458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3657497458
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.234906037
Short name T385
Test name
Test status
Simulation time 56486638091 ps
CPU time 30.64 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:23:04 PM PST 24
Peak memory 199592 kb
Host smart-aeb9d6e5-3c9f-4862-b663-e80bae703c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234906037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.234906037
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2765324916
Short name T156
Test name
Test status
Simulation time 94362558242 ps
CPU time 131.95 seconds
Started Mar 03 01:22:34 PM PST 24
Finished Mar 03 01:24:46 PM PST 24
Peak memory 199104 kb
Host smart-cf54df3c-5afc-4c76-a1cf-c8ad67a8d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765324916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2765324916
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2208736739
Short name T623
Test name
Test status
Simulation time 224349367658 ps
CPU time 39.53 seconds
Started Mar 03 01:22:40 PM PST 24
Finished Mar 03 01:23:20 PM PST 24
Peak memory 198980 kb
Host smart-788e7114-965e-4ae2-9ab3-f54a924dcd40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208736739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2208736739
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2557409427
Short name T310
Test name
Test status
Simulation time 295862691133 ps
CPU time 550.73 seconds
Started Mar 03 01:22:40 PM PST 24
Finished Mar 03 01:31:53 PM PST 24
Peak memory 199692 kb
Host smart-9481d984-e9ae-406a-977b-545a060e570d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557409427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2557409427
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1637324820
Short name T667
Test name
Test status
Simulation time 6078729833 ps
CPU time 12.44 seconds
Started Mar 03 01:22:43 PM PST 24
Finished Mar 03 01:22:56 PM PST 24
Peak memory 199680 kb
Host smart-b03f0a80-2c5b-4977-8d34-4fa28f61a026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637324820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1637324820
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3951851614
Short name T610
Test name
Test status
Simulation time 44480851906 ps
CPU time 49.28 seconds
Started Mar 03 01:22:42 PM PST 24
Finished Mar 03 01:23:32 PM PST 24
Peak memory 197752 kb
Host smart-47dae952-64fc-467a-a3d0-67fc12c1e66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951851614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3951851614
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2925779769
Short name T1004
Test name
Test status
Simulation time 12601989149 ps
CPU time 165.98 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:25:28 PM PST 24
Peak memory 199604 kb
Host smart-78ed9df1-83cd-4dfa-b27b-f2056d78c6d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925779769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2925779769
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.247824855
Short name T988
Test name
Test status
Simulation time 2327926308 ps
CPU time 13.51 seconds
Started Mar 03 01:22:37 PM PST 24
Finished Mar 03 01:22:51 PM PST 24
Peak memory 198352 kb
Host smart-2b215014-b53f-4422-8e13-94a4864bbd1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247824855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.247824855
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1743699147
Short name T836
Test name
Test status
Simulation time 49019060311 ps
CPU time 84.94 seconds
Started Mar 03 01:22:42 PM PST 24
Finished Mar 03 01:24:07 PM PST 24
Peak memory 199668 kb
Host smart-dbccb2d3-d437-4b8c-be16-a75edc242b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743699147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1743699147
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1169978984
Short name T1008
Test name
Test status
Simulation time 57167120416 ps
CPU time 8.77 seconds
Started Mar 03 01:22:42 PM PST 24
Finished Mar 03 01:22:52 PM PST 24
Peak memory 195380 kb
Host smart-46030d42-51ee-4ad5-9650-dba4b64b1c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169978984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1169978984
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.984495128
Short name T822
Test name
Test status
Simulation time 295213044 ps
CPU time 0.97 seconds
Started Mar 03 01:22:33 PM PST 24
Finished Mar 03 01:22:34 PM PST 24
Peak memory 197140 kb
Host smart-69397fb8-0564-4d6e-b65a-2a6fbd3a25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984495128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.984495128
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3015191535
Short name T197
Test name
Test status
Simulation time 112470367267 ps
CPU time 51.43 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:23:39 PM PST 24
Peak memory 199756 kb
Host smart-39a70162-81c0-4bfe-a31f-59462e0ed3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015191535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3015191535
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.147370413
Short name T405
Test name
Test status
Simulation time 2211792498 ps
CPU time 3.2 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:22:45 PM PST 24
Peak memory 198248 kb
Host smart-dc857795-c166-4a6f-8053-02e9bf3ffbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147370413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.147370413
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1099426094
Short name T630
Test name
Test status
Simulation time 161389251976 ps
CPU time 128.3 seconds
Started Mar 03 01:22:36 PM PST 24
Finished Mar 03 01:24:44 PM PST 24
Peak memory 199520 kb
Host smart-d0923087-6fde-4954-a4e1-343ea046e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099426094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1099426094
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4173362633
Short name T506
Test name
Test status
Simulation time 40916494 ps
CPU time 0.57 seconds
Started Mar 03 01:24:52 PM PST 24
Finished Mar 03 01:24:53 PM PST 24
Peak memory 195124 kb
Host smart-563d45c0-eab3-4e64-859d-d53571d538cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173362633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4173362633
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4256500597
Short name T966
Test name
Test status
Simulation time 43101658103 ps
CPU time 33.7 seconds
Started Mar 03 01:24:45 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 199664 kb
Host smart-d1e03681-c3ab-44b2-b24b-cf49220c0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256500597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4256500597
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1408404948
Short name T1098
Test name
Test status
Simulation time 107082508002 ps
CPU time 30.83 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 198956 kb
Host smart-26129e7e-85e9-4026-89ec-ba657aab1c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408404948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1408404948
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1460556234
Short name T789
Test name
Test status
Simulation time 173078751954 ps
CPU time 26.84 seconds
Started Mar 03 01:24:52 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 199572 kb
Host smart-d0348dcf-e48e-4749-8826-2186484ec3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460556234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1460556234
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.168111412
Short name T694
Test name
Test status
Simulation time 81879506537 ps
CPU time 67.59 seconds
Started Mar 03 01:24:47 PM PST 24
Finished Mar 03 01:25:55 PM PST 24
Peak memory 199632 kb
Host smart-432b4acb-ffae-4753-b78e-040b9aa8a777
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168111412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.168111412
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3665595913
Short name T908
Test name
Test status
Simulation time 50367184145 ps
CPU time 164.83 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:27:33 PM PST 24
Peak memory 199744 kb
Host smart-01b707e8-a7aa-4235-a97d-04155df965d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665595913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3665595913
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2107553568
Short name T498
Test name
Test status
Simulation time 9854952231 ps
CPU time 22.88 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:25:11 PM PST 24
Peak memory 197860 kb
Host smart-f925c0a2-4acb-41c4-8403-c4516ec4022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107553568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2107553568
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1216237084
Short name T996
Test name
Test status
Simulation time 63948521222 ps
CPU time 106.61 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:26:35 PM PST 24
Peak memory 207624 kb
Host smart-b94d93ec-1766-4678-96b4-d527a05ca39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216237084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1216237084
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4011001890
Short name T775
Test name
Test status
Simulation time 23739145885 ps
CPU time 1228.82 seconds
Started Mar 03 01:24:46 PM PST 24
Finished Mar 03 01:45:15 PM PST 24
Peak memory 199668 kb
Host smart-cb237ae8-a804-46ec-ad53-b6b271f7b077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011001890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4011001890
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2591178490
Short name T909
Test name
Test status
Simulation time 4720634839 ps
CPU time 10.69 seconds
Started Mar 03 01:24:46 PM PST 24
Finished Mar 03 01:24:57 PM PST 24
Peak memory 198360 kb
Host smart-c13676e6-1f81-4260-8a98-0df9de31ccaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591178490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2591178490
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2747707150
Short name T333
Test name
Test status
Simulation time 31608033854 ps
CPU time 33.62 seconds
Started Mar 03 01:24:49 PM PST 24
Finished Mar 03 01:25:22 PM PST 24
Peak memory 199168 kb
Host smart-8deecac0-e9fd-4f91-966a-b2ab9b8c456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747707150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2747707150
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3482563077
Short name T527
Test name
Test status
Simulation time 6115728344 ps
CPU time 1.81 seconds
Started Mar 03 01:24:44 PM PST 24
Finished Mar 03 01:24:46 PM PST 24
Peak memory 195580 kb
Host smart-44c58896-1741-4ee2-932b-06b258d6fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482563077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3482563077
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2847951688
Short name T1101
Test name
Test status
Simulation time 976473597 ps
CPU time 3.33 seconds
Started Mar 03 01:24:39 PM PST 24
Finished Mar 03 01:24:43 PM PST 24
Peak memory 198820 kb
Host smart-5c0d5c59-ceb2-4421-8d19-4536ca509ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847951688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2847951688
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.436282008
Short name T245
Test name
Test status
Simulation time 458568233033 ps
CPU time 1413.95 seconds
Started Mar 03 01:24:52 PM PST 24
Finished Mar 03 01:48:26 PM PST 24
Peak memory 199540 kb
Host smart-7d10ab0b-5c91-46ef-be31-0cc685d73986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436282008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.436282008
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3730388557
Short name T940
Test name
Test status
Simulation time 662446032 ps
CPU time 2.22 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:24:51 PM PST 24
Peak memory 197720 kb
Host smart-2adc20b2-8508-42ea-a157-02208e652279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730388557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3730388557
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1139050543
Short name T747
Test name
Test status
Simulation time 54332002510 ps
CPU time 40.7 seconds
Started Mar 03 01:24:40 PM PST 24
Finished Mar 03 01:25:21 PM PST 24
Peak memory 199768 kb
Host smart-a3845e79-0eb8-42fa-8218-fdedaf5f1ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139050543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1139050543
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2842673656
Short name T1006
Test name
Test status
Simulation time 96416995240 ps
CPU time 150.03 seconds
Started Mar 03 01:29:57 PM PST 24
Finished Mar 03 01:32:28 PM PST 24
Peak memory 198432 kb
Host smart-40983bf6-9232-4cd1-a3a8-68c073f20203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842673656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2842673656
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.757712817
Short name T262
Test name
Test status
Simulation time 17980221704 ps
CPU time 27.81 seconds
Started Mar 03 01:29:53 PM PST 24
Finished Mar 03 01:30:21 PM PST 24
Peak memory 199692 kb
Host smart-5eeb0214-07f7-41ca-9b05-f60b20852221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757712817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.757712817
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3989637702
Short name T317
Test name
Test status
Simulation time 12701424419 ps
CPU time 18.81 seconds
Started Mar 03 01:29:54 PM PST 24
Finished Mar 03 01:30:14 PM PST 24
Peak memory 199408 kb
Host smart-41de2eb8-e651-474c-ba27-1e553a7ce8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989637702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3989637702
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3910711066
Short name T1067
Test name
Test status
Simulation time 165458003400 ps
CPU time 63.69 seconds
Started Mar 03 01:29:56 PM PST 24
Finished Mar 03 01:31:01 PM PST 24
Peak memory 199680 kb
Host smart-2d7d329e-11d4-4780-b679-927bd569f6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910711066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3910711066
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1550786245
Short name T1089
Test name
Test status
Simulation time 20423824139 ps
CPU time 20.45 seconds
Started Mar 03 01:30:00 PM PST 24
Finished Mar 03 01:30:23 PM PST 24
Peak memory 199672 kb
Host smart-d40333e0-aa97-4878-9aed-73aa55506f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550786245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1550786245
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2651929791
Short name T535
Test name
Test status
Simulation time 95776526032 ps
CPU time 41.21 seconds
Started Mar 03 01:30:05 PM PST 24
Finished Mar 03 01:30:46 PM PST 24
Peak memory 199404 kb
Host smart-a02843df-b458-4a8c-be4a-3fcc81f69c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651929791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2651929791
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.728585487
Short name T757
Test name
Test status
Simulation time 119730277876 ps
CPU time 18.17 seconds
Started Mar 03 01:30:02 PM PST 24
Finished Mar 03 01:30:21 PM PST 24
Peak memory 199228 kb
Host smart-c9a9e709-b6ac-436e-985a-ad549be02ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728585487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.728585487
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2764480311
Short name T1047
Test name
Test status
Simulation time 124409004995 ps
CPU time 15.59 seconds
Started Mar 03 01:30:04 PM PST 24
Finished Mar 03 01:30:20 PM PST 24
Peak memory 199608 kb
Host smart-a54ba029-c336-4d08-9450-fbe3ab40cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764480311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2764480311
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1368256618
Short name T946
Test name
Test status
Simulation time 87176747715 ps
CPU time 358.26 seconds
Started Mar 03 01:30:00 PM PST 24
Finished Mar 03 01:36:01 PM PST 24
Peak memory 199648 kb
Host smart-f9474c00-955e-4316-ba53-ac26029b7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368256618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1368256618
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2973719378
Short name T658
Test name
Test status
Simulation time 13411316 ps
CPU time 0.57 seconds
Started Mar 03 01:24:53 PM PST 24
Finished Mar 03 01:24:53 PM PST 24
Peak memory 195140 kb
Host smart-89cc457e-65bc-486a-b61b-f8a60f6bad69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973719378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2973719378
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1840824286
Short name T881
Test name
Test status
Simulation time 153200980530 ps
CPU time 124.49 seconds
Started Mar 03 01:24:44 PM PST 24
Finished Mar 03 01:26:49 PM PST 24
Peak memory 199728 kb
Host smart-c5a664a9-3b6f-4487-be5e-428545cc57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840824286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1840824286
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1758573183
Short name T688
Test name
Test status
Simulation time 64466796783 ps
CPU time 69.56 seconds
Started Mar 03 01:24:46 PM PST 24
Finished Mar 03 01:25:56 PM PST 24
Peak memory 199112 kb
Host smart-f409bbf5-01e4-4d45-8a11-1a5d823f135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758573183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1758573183
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.3349650018
Short name T395
Test name
Test status
Simulation time 1178670209811 ps
CPU time 2341.86 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 02:03:50 PM PST 24
Peak memory 199540 kb
Host smart-f919c7dd-db48-4b4d-8096-46bcf77a7a1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349650018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3349650018
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3109663957
Short name T998
Test name
Test status
Simulation time 102007370039 ps
CPU time 424.28 seconds
Started Mar 03 01:24:55 PM PST 24
Finished Mar 03 01:31:59 PM PST 24
Peak memory 199640 kb
Host smart-ac9c44af-7995-40ec-ad1b-b5897b2ab75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109663957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3109663957
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.885667646
Short name T714
Test name
Test status
Simulation time 7490223011 ps
CPU time 15.75 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:25:10 PM PST 24
Peak memory 197652 kb
Host smart-fd0c4c93-558e-4f3e-be51-2fb3cae0ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885667646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.885667646
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1457346734
Short name T602
Test name
Test status
Simulation time 21390620313 ps
CPU time 17.49 seconds
Started Mar 03 01:24:48 PM PST 24
Finished Mar 03 01:25:06 PM PST 24
Peak memory 194708 kb
Host smart-f00ca21a-d684-4c43-a85c-137d3cb58950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457346734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1457346734
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3218251939
Short name T437
Test name
Test status
Simulation time 12484144431 ps
CPU time 193.93 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 199672 kb
Host smart-cc08bc6f-89f7-414b-ba71-a82f3df933c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218251939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3218251939
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.499399931
Short name T816
Test name
Test status
Simulation time 1511726202 ps
CPU time 6.52 seconds
Started Mar 03 01:24:45 PM PST 24
Finished Mar 03 01:24:52 PM PST 24
Peak memory 197348 kb
Host smart-098134a9-6048-487d-8aed-38b46e3f0689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499399931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.499399931
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2268009055
Short name T482
Test name
Test status
Simulation time 3944027357 ps
CPU time 1.45 seconds
Started Mar 03 01:24:44 PM PST 24
Finished Mar 03 01:24:46 PM PST 24
Peak memory 195644 kb
Host smart-b70518b3-1c5c-4a0e-bc14-f172c7718639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268009055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2268009055
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.309158269
Short name T606
Test name
Test status
Simulation time 885777195 ps
CPU time 3.26 seconds
Started Mar 03 01:24:47 PM PST 24
Finished Mar 03 01:24:50 PM PST 24
Peak memory 199064 kb
Host smart-78cea68e-73e1-4a7c-9c82-22c2a91d220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309158269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.309158269
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4271087587
Short name T489
Test name
Test status
Simulation time 1716254940 ps
CPU time 1.9 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:24:56 PM PST 24
Peak memory 197536 kb
Host smart-68484711-9db5-438a-8163-3873ebbe22af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271087587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4271087587
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3147740524
Short name T422
Test name
Test status
Simulation time 50590986397 ps
CPU time 45.97 seconds
Started Mar 03 01:24:45 PM PST 24
Finished Mar 03 01:25:31 PM PST 24
Peak memory 199700 kb
Host smart-4f5c9125-3afd-4de1-a168-2cdd4d29d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147740524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3147740524
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3288516679
Short name T316
Test name
Test status
Simulation time 104378794634 ps
CPU time 205.47 seconds
Started Mar 03 01:30:02 PM PST 24
Finished Mar 03 01:33:28 PM PST 24
Peak memory 199708 kb
Host smart-5b1007ba-3ad2-40a7-8711-5d3812fe9dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288516679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3288516679
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2491603200
Short name T991
Test name
Test status
Simulation time 72790119789 ps
CPU time 31.43 seconds
Started Mar 03 01:30:02 PM PST 24
Finished Mar 03 01:30:34 PM PST 24
Peak memory 199700 kb
Host smart-d7f0b38b-45b9-4600-bc2f-26c0429c4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491603200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2491603200
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.442038001
Short name T1058
Test name
Test status
Simulation time 82303429185 ps
CPU time 161.84 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:32:44 PM PST 24
Peak memory 199600 kb
Host smart-0812f9c9-99cb-451b-84f5-d9157da8528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442038001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.442038001
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2593101635
Short name T729
Test name
Test status
Simulation time 178835979087 ps
CPU time 133.44 seconds
Started Mar 03 01:30:00 PM PST 24
Finished Mar 03 01:32:14 PM PST 24
Peak memory 199604 kb
Host smart-85cffa34-d8fe-474e-9a1e-3aae98e228da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593101635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2593101635
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4136226383
Short name T824
Test name
Test status
Simulation time 10584971374 ps
CPU time 10.77 seconds
Started Mar 03 01:30:02 PM PST 24
Finished Mar 03 01:30:14 PM PST 24
Peak memory 199688 kb
Host smart-270fe9f3-03a8-4b10-baf6-bb2804fc7068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136226383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4136226383
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.155704278
Short name T464
Test name
Test status
Simulation time 16725377 ps
CPU time 0.54 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:06 PM PST 24
Peak memory 194236 kb
Host smart-4c79cbba-bb13-444d-b86c-b982816963c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155704278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.155704278
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4082925848
Short name T577
Test name
Test status
Simulation time 56712003016 ps
CPU time 105.67 seconds
Started Mar 03 01:24:52 PM PST 24
Finished Mar 03 01:26:38 PM PST 24
Peak memory 199580 kb
Host smart-21fefbc8-c176-4fea-89a5-3b8db6b16b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082925848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4082925848
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3022958570
Short name T615
Test name
Test status
Simulation time 174687272536 ps
CPU time 112.63 seconds
Started Mar 03 01:24:55 PM PST 24
Finished Mar 03 01:26:48 PM PST 24
Peak memory 198272 kb
Host smart-76206ec3-ce83-4169-aa5c-d555ff9b403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022958570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3022958570
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3141898732
Short name T804
Test name
Test status
Simulation time 95840354103 ps
CPU time 166.88 seconds
Started Mar 03 01:24:53 PM PST 24
Finished Mar 03 01:27:40 PM PST 24
Peak memory 199672 kb
Host smart-96b09d6d-4e15-4c3b-8d9f-499865a7729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141898732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3141898732
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2434091104
Short name T558
Test name
Test status
Simulation time 10150173595 ps
CPU time 48.16 seconds
Started Mar 03 01:24:55 PM PST 24
Finished Mar 03 01:25:43 PM PST 24
Peak memory 198500 kb
Host smart-268d75db-9eee-47ce-82e8-5ff9f4860a26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434091104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2434091104
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1423470225
Short name T521
Test name
Test status
Simulation time 137626768966 ps
CPU time 273.44 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:29:37 PM PST 24
Peak memory 199600 kb
Host smart-00b8334a-a08a-433e-a6d5-5602d2d1474d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423470225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1423470225
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3043532713
Short name T924
Test name
Test status
Simulation time 8940755335 ps
CPU time 3.25 seconds
Started Mar 03 01:25:07 PM PST 24
Finished Mar 03 01:25:10 PM PST 24
Peak memory 197648 kb
Host smart-2b327ad2-ec7c-44c8-ac61-1d79a5205ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043532713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3043532713
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3406195861
Short name T415
Test name
Test status
Simulation time 47064941642 ps
CPU time 81.13 seconds
Started Mar 03 01:24:53 PM PST 24
Finished Mar 03 01:26:14 PM PST 24
Peak memory 199752 kb
Host smart-0f9779ce-8074-4859-8f00-8693fb250699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406195861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3406195861
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1243824475
Short name T693
Test name
Test status
Simulation time 23265877429 ps
CPU time 322.61 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:30:26 PM PST 24
Peak memory 199688 kb
Host smart-b5893506-cfda-4ce1-aa58-a198fcb40062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243824475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1243824475
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3258599648
Short name T1076
Test name
Test status
Simulation time 3710933906 ps
CPU time 7.04 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:25:01 PM PST 24
Peak memory 197552 kb
Host smart-f35f4196-6aa5-4d96-8e9e-1c75ecec86c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258599648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3258599648
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2506335332
Short name T1060
Test name
Test status
Simulation time 26936638338 ps
CPU time 42.09 seconds
Started Mar 03 01:24:53 PM PST 24
Finished Mar 03 01:25:36 PM PST 24
Peak memory 199176 kb
Host smart-465bafcb-4cc9-4aa7-990d-74f71d864701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506335332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2506335332
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1847275915
Short name T556
Test name
Test status
Simulation time 4496917329 ps
CPU time 2.54 seconds
Started Mar 03 01:24:55 PM PST 24
Finished Mar 03 01:24:57 PM PST 24
Peak memory 195536 kb
Host smart-3c576393-7de8-49d8-af75-3afa8bd0788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847275915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1847275915
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3513270715
Short name T1073
Test name
Test status
Simulation time 5683273867 ps
CPU time 8.24 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:25:02 PM PST 24
Peak memory 199016 kb
Host smart-aee9bd74-0e85-4980-bb8b-c46941d3c6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513270715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3513270715
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3652637814
Short name T826
Test name
Test status
Simulation time 827348598 ps
CPU time 2.57 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:08 PM PST 24
Peak memory 198888 kb
Host smart-dc01a2bb-3759-492e-8f2f-990b2685cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652637814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3652637814
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2519858220
Short name T408
Test name
Test status
Simulation time 74601075755 ps
CPU time 66.22 seconds
Started Mar 03 01:24:54 PM PST 24
Finished Mar 03 01:26:01 PM PST 24
Peak memory 199604 kb
Host smart-11f71898-a250-4b80-be91-79356df71a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519858220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2519858220
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3338057112
Short name T620
Test name
Test status
Simulation time 109630168091 ps
CPU time 191.47 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:33:14 PM PST 24
Peak memory 199484 kb
Host smart-ded8c071-85b4-48c3-b1b8-51c06471dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338057112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3338057112
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2839974780
Short name T207
Test name
Test status
Simulation time 20444436170 ps
CPU time 37.98 seconds
Started Mar 03 01:30:01 PM PST 24
Finished Mar 03 01:30:40 PM PST 24
Peak memory 199668 kb
Host smart-e500bbea-2e4c-4192-834c-d473e45adfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839974780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2839974780
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3995996753
Short name T1052
Test name
Test status
Simulation time 25351722504 ps
CPU time 40.72 seconds
Started Mar 03 01:30:09 PM PST 24
Finished Mar 03 01:30:50 PM PST 24
Peak memory 197584 kb
Host smart-86bfef52-b495-40f6-8e65-05b4430c73d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995996753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3995996753
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3366657629
Short name T153
Test name
Test status
Simulation time 74997240113 ps
CPU time 30 seconds
Started Mar 03 01:30:08 PM PST 24
Finished Mar 03 01:30:38 PM PST 24
Peak memory 199396 kb
Host smart-3fd6de02-0290-4d30-a6f7-12e72e18d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366657629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3366657629
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3926324009
Short name T189
Test name
Test status
Simulation time 101646043125 ps
CPU time 231.05 seconds
Started Mar 03 01:30:10 PM PST 24
Finished Mar 03 01:34:01 PM PST 24
Peak memory 199720 kb
Host smart-68e18603-70cd-4371-9ecb-bb73caab6052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926324009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3926324009
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.597306049
Short name T574
Test name
Test status
Simulation time 14362707838 ps
CPU time 15.17 seconds
Started Mar 03 01:30:10 PM PST 24
Finished Mar 03 01:30:25 PM PST 24
Peak memory 199444 kb
Host smart-3876b480-ab7e-4053-a371-256ed90a8422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597306049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.597306049
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1861083894
Short name T268
Test name
Test status
Simulation time 29103029269 ps
CPU time 46.62 seconds
Started Mar 03 01:30:10 PM PST 24
Finished Mar 03 01:30:57 PM PST 24
Peak memory 199648 kb
Host smart-f50938b8-1cbf-48c7-9b0c-738c77a4b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861083894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1861083894
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.600925136
Short name T858
Test name
Test status
Simulation time 41843938 ps
CPU time 0.55 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:06 PM PST 24
Peak memory 194336 kb
Host smart-a1f4589b-9fef-468f-903b-11a98fc86d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600925136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.600925136
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3227021751
Short name T829
Test name
Test status
Simulation time 162651583159 ps
CPU time 82.31 seconds
Started Mar 03 01:25:01 PM PST 24
Finished Mar 03 01:26:23 PM PST 24
Peak memory 199676 kb
Host smart-b46d8885-fb54-4ae0-9539-e093aa9f1764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227021751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3227021751
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.447476207
Short name T378
Test name
Test status
Simulation time 57485847973 ps
CPU time 28.56 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:34 PM PST 24
Peak memory 199512 kb
Host smart-8888c26a-644a-4414-b4cf-944c6dcd9434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447476207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.447476207
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2535961492
Short name T622
Test name
Test status
Simulation time 83163300631 ps
CPU time 443.09 seconds
Started Mar 03 01:25:05 PM PST 24
Finished Mar 03 01:32:29 PM PST 24
Peak memory 199656 kb
Host smart-e436bfc5-cca5-49e1-9707-84f13e304dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535961492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2535961492
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.437701659
Short name T533
Test name
Test status
Simulation time 707221498 ps
CPU time 2.16 seconds
Started Mar 03 01:25:05 PM PST 24
Finished Mar 03 01:25:08 PM PST 24
Peak memory 197676 kb
Host smart-9b667e4f-705b-4ed8-9fa1-5888ea0c3184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437701659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.437701659
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1336057847
Short name T807
Test name
Test status
Simulation time 35247306375 ps
CPU time 22.8 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:27 PM PST 24
Peak memory 197360 kb
Host smart-8565b9a8-5c96-4a81-8d8b-3b42e896fdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336057847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1336057847
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1064239218
Short name T292
Test name
Test status
Simulation time 19370310588 ps
CPU time 212.53 seconds
Started Mar 03 01:25:02 PM PST 24
Finished Mar 03 01:28:35 PM PST 24
Peak memory 199664 kb
Host smart-55750453-63b0-4c2f-b732-cf9df477e1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064239218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1064239218
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.870701073
Short name T76
Test name
Test status
Simulation time 3136108048 ps
CPU time 24.43 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:25:28 PM PST 24
Peak memory 198412 kb
Host smart-cd820357-5d9c-4830-95f1-0ca6e7102317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870701073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.870701073
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2295757917
Short name T1043
Test name
Test status
Simulation time 4127337333 ps
CPU time 7.08 seconds
Started Mar 03 01:25:01 PM PST 24
Finished Mar 03 01:25:09 PM PST 24
Peak memory 195540 kb
Host smart-8ef8e62d-f2c2-4334-a2f4-02a90174a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295757917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2295757917
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3457463564
Short name T676
Test name
Test status
Simulation time 932827691 ps
CPU time 3.7 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:25:07 PM PST 24
Peak memory 198084 kb
Host smart-7307b60b-0877-47a2-93ef-25f6cb12c9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457463564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3457463564
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1858941770
Short name T296
Test name
Test status
Simulation time 2293865690065 ps
CPU time 3576.23 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 02:24:41 PM PST 24
Peak memory 199660 kb
Host smart-e0992185-6a47-4592-afeb-f89b69209f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858941770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1858941770
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2287816511
Short name T748
Test name
Test status
Simulation time 428477317 ps
CPU time 1.49 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:25:04 PM PST 24
Peak memory 196416 kb
Host smart-f69ba8b2-406b-4331-92d8-1fc3a1d4d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287816511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2287816511
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1209789143
Short name T1025
Test name
Test status
Simulation time 15875958519 ps
CPU time 32.56 seconds
Started Mar 03 01:25:04 PM PST 24
Finished Mar 03 01:25:38 PM PST 24
Peak memory 199680 kb
Host smart-3a7944b2-e970-4ff5-9c40-3addd1b9bbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209789143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1209789143
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.929245624
Short name T319
Test name
Test status
Simulation time 299694323337 ps
CPU time 145.56 seconds
Started Mar 03 01:30:09 PM PST 24
Finished Mar 03 01:32:35 PM PST 24
Peak memory 199728 kb
Host smart-b622fa9a-c4ce-4047-9e53-160c55fca8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929245624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.929245624
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.197366107
Short name T275
Test name
Test status
Simulation time 111417980820 ps
CPU time 51.46 seconds
Started Mar 03 01:30:11 PM PST 24
Finished Mar 03 01:31:03 PM PST 24
Peak memory 199408 kb
Host smart-087bd8c0-2819-4cf9-8b3a-21b0a4a46e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197366107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.197366107
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3808425485
Short name T594
Test name
Test status
Simulation time 39458692842 ps
CPU time 140.44 seconds
Started Mar 03 01:30:09 PM PST 24
Finished Mar 03 01:32:29 PM PST 24
Peak memory 199708 kb
Host smart-c3b44d07-7fa6-469f-b582-c5c866ac8dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808425485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3808425485
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.773545083
Short name T727
Test name
Test status
Simulation time 30834886303 ps
CPU time 13.68 seconds
Started Mar 03 01:30:10 PM PST 24
Finished Mar 03 01:30:24 PM PST 24
Peak memory 199588 kb
Host smart-36347606-f12a-4847-a7b4-d516b7360e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773545083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.773545083
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3097637111
Short name T773
Test name
Test status
Simulation time 34172988742 ps
CPU time 18.54 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:30:36 PM PST 24
Peak memory 199748 kb
Host smart-68b10fae-47fb-46ba-b1e4-914ef4491376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097637111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3097637111
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4183759746
Short name T1087
Test name
Test status
Simulation time 123223680709 ps
CPU time 22.51 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:30:39 PM PST 24
Peak memory 199588 kb
Host smart-55891aaf-72bc-4ecb-b22c-396284f6c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183759746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4183759746
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1295126854
Short name T592
Test name
Test status
Simulation time 13962199202 ps
CPU time 11.47 seconds
Started Mar 03 01:30:17 PM PST 24
Finished Mar 03 01:30:29 PM PST 24
Peak memory 199400 kb
Host smart-a81a60e0-e9f1-46f0-83ee-e234c1510a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295126854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1295126854
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1288116227
Short name T455
Test name
Test status
Simulation time 34046743 ps
CPU time 0.57 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:25:07 PM PST 24
Peak memory 195216 kb
Host smart-fa0055f8-537b-4685-a000-0175ea2a62b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288116227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1288116227
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2561754385
Short name T366
Test name
Test status
Simulation time 119516238762 ps
CPU time 53.07 seconds
Started Mar 03 01:25:01 PM PST 24
Finished Mar 03 01:25:54 PM PST 24
Peak memory 199652 kb
Host smart-ddd79317-4f7b-472e-84a3-ba533202eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561754385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2561754385
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1256018473
Short name T731
Test name
Test status
Simulation time 47700419055 ps
CPU time 145.1 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:27:32 PM PST 24
Peak memory 199668 kb
Host smart-84172bc0-1231-4312-abe4-35cf934dc10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256018473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1256018473
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2282024845
Short name T507
Test name
Test status
Simulation time 13962837562 ps
CPU time 14.11 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:25:23 PM PST 24
Peak memory 198864 kb
Host smart-0a91a6ac-0f53-4dc3-8df6-d978a5f7e895
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282024845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2282024845
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.834671066
Short name T495
Test name
Test status
Simulation time 81676161287 ps
CPU time 665.13 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:36:12 PM PST 24
Peak memory 199748 kb
Host smart-d8e20b96-0ea8-4cf9-9580-cb7db18889f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834671066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.834671066
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1016971361
Short name T986
Test name
Test status
Simulation time 7328325348 ps
CPU time 9.91 seconds
Started Mar 03 01:25:09 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 198604 kb
Host smart-304f5a1d-b2bc-47a0-b1fe-e2a7528a28dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016971361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1016971361
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3455774172
Short name T976
Test name
Test status
Simulation time 97882079126 ps
CPU time 48.29 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:25:57 PM PST 24
Peak memory 199764 kb
Host smart-bc52ce6f-601f-4eee-b64f-5e72a4bf521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455774172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3455774172
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1860850686
Short name T45
Test name
Test status
Simulation time 22784496663 ps
CPU time 260.87 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:29:27 PM PST 24
Peak memory 199712 kb
Host smart-7fb03593-f2bd-4893-ac0d-e95c66292173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860850686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1860850686
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3628996257
Short name T514
Test name
Test status
Simulation time 79660457016 ps
CPU time 34.58 seconds
Started Mar 03 01:25:07 PM PST 24
Finished Mar 03 01:25:42 PM PST 24
Peak memory 195212 kb
Host smart-ed4acf5f-e2e7-480e-bf4a-efe792169705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628996257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3628996257
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.353934010
Short name T981
Test name
Test status
Simulation time 509915593 ps
CPU time 1.93 seconds
Started Mar 03 01:25:01 PM PST 24
Finished Mar 03 01:25:04 PM PST 24
Peak memory 198028 kb
Host smart-99f44d6c-00b3-4cda-94dd-29a554721a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353934010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.353934010
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1678594155
Short name T267
Test name
Test status
Simulation time 316265174036 ps
CPU time 147.75 seconds
Started Mar 03 01:25:09 PM PST 24
Finished Mar 03 01:27:37 PM PST 24
Peak memory 199692 kb
Host smart-76bc7b93-b8df-42d1-b0ed-c49782c69919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678594155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1678594155
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3175464201
Short name T483
Test name
Test status
Simulation time 945732143 ps
CPU time 2.57 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:25:11 PM PST 24
Peak memory 197572 kb
Host smart-efa43fe3-7a0a-4382-b835-2d2ccff25a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175464201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3175464201
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1644093775
Short name T884
Test name
Test status
Simulation time 136260846281 ps
CPU time 81.99 seconds
Started Mar 03 01:25:03 PM PST 24
Finished Mar 03 01:26:26 PM PST 24
Peak memory 199640 kb
Host smart-d50540b2-ff68-4c1d-ac10-942263bcc376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644093775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1644093775
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2805565162
Short name T435
Test name
Test status
Simulation time 160595865011 ps
CPU time 78.66 seconds
Started Mar 03 01:30:16 PM PST 24
Finished Mar 03 01:31:35 PM PST 24
Peak memory 199592 kb
Host smart-9c623b21-8abc-4fcd-966b-b79f27693a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805565162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2805565162
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1532923510
Short name T154
Test name
Test status
Simulation time 24462926213 ps
CPU time 36.32 seconds
Started Mar 03 01:30:15 PM PST 24
Finished Mar 03 01:30:52 PM PST 24
Peak memory 199408 kb
Host smart-0d1c5ad7-a46d-46a2-8482-a64037963d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532923510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1532923510
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2746507321
Short name T922
Test name
Test status
Simulation time 18216843539 ps
CPU time 8.66 seconds
Started Mar 03 01:30:15 PM PST 24
Finished Mar 03 01:30:24 PM PST 24
Peak memory 198964 kb
Host smart-ee86bdd5-8cf5-4b30-92c2-0c0c47079383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746507321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2746507321
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3296675727
Short name T224
Test name
Test status
Simulation time 17147099534 ps
CPU time 32.62 seconds
Started Mar 03 01:30:16 PM PST 24
Finished Mar 03 01:30:49 PM PST 24
Peak memory 199540 kb
Host smart-feba077d-de33-4f5c-b8ed-48bf7d6deaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296675727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3296675727
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.389618873
Short name T1081
Test name
Test status
Simulation time 42309714293 ps
CPU time 76.23 seconds
Started Mar 03 01:30:23 PM PST 24
Finished Mar 03 01:31:39 PM PST 24
Peak memory 199544 kb
Host smart-129f3fd9-e0f6-4e6d-a608-6fbaf2a1feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389618873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.389618873
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3641456322
Short name T131
Test name
Test status
Simulation time 37528274431 ps
CPU time 14.78 seconds
Started Mar 03 01:30:22 PM PST 24
Finished Mar 03 01:30:37 PM PST 24
Peak memory 199276 kb
Host smart-0fead0e7-7320-4bbc-817e-852a90334b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641456322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3641456322
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.979144164
Short name T760
Test name
Test status
Simulation time 14135667 ps
CPU time 0.56 seconds
Started Mar 03 01:25:19 PM PST 24
Finished Mar 03 01:25:20 PM PST 24
Peak memory 194296 kb
Host smart-341ec5e9-3947-47d0-8838-5ac04d4ff855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979144164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.979144164
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3502171708
Short name T975
Test name
Test status
Simulation time 85268623214 ps
CPU time 34.17 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:25:40 PM PST 24
Peak memory 199624 kb
Host smart-faf699b8-1dc5-41e4-8345-511ae968f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502171708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3502171708
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2397866325
Short name T350
Test name
Test status
Simulation time 111641517355 ps
CPU time 48.18 seconds
Started Mar 03 01:25:08 PM PST 24
Finished Mar 03 01:25:56 PM PST 24
Peak memory 199672 kb
Host smart-0109dbc3-a3cf-49c4-991e-9b68b6284789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397866325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2397866325
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.388829261
Short name T283
Test name
Test status
Simulation time 42652723860 ps
CPU time 21.66 seconds
Started Mar 03 01:25:09 PM PST 24
Finished Mar 03 01:25:31 PM PST 24
Peak memory 199656 kb
Host smart-a551522a-0f7f-485a-b45c-b4c2699660ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388829261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.388829261
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.285071250
Short name T1021
Test name
Test status
Simulation time 220713766283 ps
CPU time 323.37 seconds
Started Mar 03 01:25:06 PM PST 24
Finished Mar 03 01:30:29 PM PST 24
Peak memory 199548 kb
Host smart-51b1dd91-d160-4c8a-a4b2-a61471815713
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285071250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.285071250
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1920853271
Short name T633
Test name
Test status
Simulation time 179467761124 ps
CPU time 510.15 seconds
Started Mar 03 01:25:14 PM PST 24
Finished Mar 03 01:33:45 PM PST 24
Peak memory 199612 kb
Host smart-73fd0d5f-3ca8-4da7-be98-87a55c0995d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920853271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1920853271
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.77227258
Short name T496
Test name
Test status
Simulation time 4148011803 ps
CPU time 2.69 seconds
Started Mar 03 01:25:16 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 198044 kb
Host smart-9cd6958a-a460-4f3c-a9de-7ab5af1a3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77227258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.77227258
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3490368663
Short name T844
Test name
Test status
Simulation time 135334030013 ps
CPU time 61.16 seconds
Started Mar 03 01:25:19 PM PST 24
Finished Mar 03 01:26:21 PM PST 24
Peak memory 207992 kb
Host smart-82a97ed7-fd63-4f80-a320-f832a4fe370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490368663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3490368663
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2252730969
Short name T601
Test name
Test status
Simulation time 16414240048 ps
CPU time 63.56 seconds
Started Mar 03 01:25:16 PM PST 24
Finished Mar 03 01:26:20 PM PST 24
Peak memory 199624 kb
Host smart-65a52c48-a199-40e7-b7af-965d9c642ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252730969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2252730969
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3193640041
Short name T750
Test name
Test status
Simulation time 1790465859 ps
CPU time 10.21 seconds
Started Mar 03 01:25:07 PM PST 24
Finished Mar 03 01:25:18 PM PST 24
Peak memory 197852 kb
Host smart-bc8087b8-93e5-4668-ab5c-84121f3d0fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193640041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3193640041
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2000191727
Short name T1084
Test name
Test status
Simulation time 18777173408 ps
CPU time 34 seconds
Started Mar 03 01:25:17 PM PST 24
Finished Mar 03 01:25:51 PM PST 24
Peak memory 199648 kb
Host smart-23ea1ddc-0674-4222-992f-78cecfdefac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000191727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2000191727
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3602023420
Short name T107
Test name
Test status
Simulation time 5054594805 ps
CPU time 2.87 seconds
Started Mar 03 01:25:16 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 195476 kb
Host smart-b5a26b1f-9c3f-4e3d-8799-bbec4081d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602023420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3602023420
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1320212835
Short name T1082
Test name
Test status
Simulation time 844171725 ps
CPU time 5.52 seconds
Started Mar 03 01:25:07 PM PST 24
Finished Mar 03 01:25:13 PM PST 24
Peak memory 197536 kb
Host smart-e44b0834-d81a-4b96-a663-9330eb932bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320212835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1320212835
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3038369079
Short name T571
Test name
Test status
Simulation time 51300567825 ps
CPU time 153.48 seconds
Started Mar 03 01:25:19 PM PST 24
Finished Mar 03 01:27:52 PM PST 24
Peak memory 216152 kb
Host smart-3a5ece94-db3f-4561-bfee-c12e4dc45c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038369079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3038369079
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1455102507
Short name T709
Test name
Test status
Simulation time 1175636026 ps
CPU time 1.87 seconds
Started Mar 03 01:25:15 PM PST 24
Finished Mar 03 01:25:17 PM PST 24
Peak memory 197528 kb
Host smart-04029e6e-d51b-4df8-9278-40725129e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455102507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1455102507
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.443910464
Short name T882
Test name
Test status
Simulation time 156881260993 ps
CPU time 125.16 seconds
Started Mar 03 01:25:07 PM PST 24
Finished Mar 03 01:27:13 PM PST 24
Peak memory 199688 kb
Host smart-04ab9aba-3a70-4a3c-8df4-54b07ed8776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443910464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.443910464
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.350511988
Short name T562
Test name
Test status
Simulation time 52786823004 ps
CPU time 29.71 seconds
Started Mar 03 01:30:20 PM PST 24
Finished Mar 03 01:30:50 PM PST 24
Peak memory 199612 kb
Host smart-b04d0008-ecfd-4b04-a2fe-bb3667f4dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350511988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.350511988
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3416138811
Short name T178
Test name
Test status
Simulation time 29009009158 ps
CPU time 12.57 seconds
Started Mar 03 01:30:21 PM PST 24
Finished Mar 03 01:30:34 PM PST 24
Peak memory 199612 kb
Host smart-2e6e18cc-1187-489d-9b72-2350478ea0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416138811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3416138811
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4119953682
Short name T603
Test name
Test status
Simulation time 102298152827 ps
CPU time 24.72 seconds
Started Mar 03 01:30:24 PM PST 24
Finished Mar 03 01:30:49 PM PST 24
Peak memory 199604 kb
Host smart-4d4eb12a-6be9-49b0-8f1d-515de7c9c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119953682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4119953682
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1427362833
Short name T221
Test name
Test status
Simulation time 22215312756 ps
CPU time 36.38 seconds
Started Mar 03 01:30:21 PM PST 24
Finished Mar 03 01:30:57 PM PST 24
Peak memory 199492 kb
Host smart-1587a823-470a-433f-8c01-e413b9d7aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427362833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1427362833
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3386432889
Short name T173
Test name
Test status
Simulation time 75036703623 ps
CPU time 104.94 seconds
Started Mar 03 01:30:21 PM PST 24
Finished Mar 03 01:32:06 PM PST 24
Peak memory 199664 kb
Host smart-3d250bc6-5124-4053-92f3-98d907cbb133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386432889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3386432889
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.28347016
Short name T1075
Test name
Test status
Simulation time 20218211099 ps
CPU time 30.62 seconds
Started Mar 03 01:30:20 PM PST 24
Finished Mar 03 01:30:51 PM PST 24
Peak memory 199724 kb
Host smart-b8d2dc27-47a5-49fd-840e-287ae1b2379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28347016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.28347016
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.650960822
Short name T984
Test name
Test status
Simulation time 85460226772 ps
CPU time 37.24 seconds
Started Mar 03 01:30:23 PM PST 24
Finished Mar 03 01:31:01 PM PST 24
Peak memory 199664 kb
Host smart-078f402c-c3a8-4f4f-a133-db939db1bea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650960822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.650960822
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3238240728
Short name T589
Test name
Test status
Simulation time 15414582594 ps
CPU time 25.7 seconds
Started Mar 03 01:30:23 PM PST 24
Finished Mar 03 01:30:49 PM PST 24
Peak memory 199248 kb
Host smart-72fe1999-0200-4ca6-be83-425478ec4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238240728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3238240728
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.309303052
Short name T1077
Test name
Test status
Simulation time 101041444356 ps
CPU time 26.18 seconds
Started Mar 03 01:30:22 PM PST 24
Finished Mar 03 01:30:48 PM PST 24
Peak memory 199572 kb
Host smart-6e5c45a8-0597-408d-9253-d9cd0c2fd6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309303052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.309303052
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2128770147
Short name T542
Test name
Test status
Simulation time 13228492 ps
CPU time 0.54 seconds
Started Mar 03 01:25:23 PM PST 24
Finished Mar 03 01:25:23 PM PST 24
Peak memory 195264 kb
Host smart-5a39e6c4-0c1d-41b9-a44f-d221a4422a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128770147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2128770147
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.732933934
Short name T945
Test name
Test status
Simulation time 29798822183 ps
CPU time 46.88 seconds
Started Mar 03 01:25:15 PM PST 24
Finished Mar 03 01:26:02 PM PST 24
Peak memory 199648 kb
Host smart-699ff2b5-a8e8-4415-a65d-c6efd1e2ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732933934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.732933934
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.564649309
Short name T941
Test name
Test status
Simulation time 86387446070 ps
CPU time 146.74 seconds
Started Mar 03 01:25:18 PM PST 24
Finished Mar 03 01:27:45 PM PST 24
Peak memory 198732 kb
Host smart-2f97f5c0-1c87-4cb1-b46f-7f5dedb66c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564649309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.564649309
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2738440474
Short name T164
Test name
Test status
Simulation time 126802152096 ps
CPU time 49.01 seconds
Started Mar 03 01:25:21 PM PST 24
Finished Mar 03 01:26:10 PM PST 24
Peak memory 199376 kb
Host smart-72b10ac7-7207-4713-8bac-e150a1dabfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738440474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2738440474
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1448869269
Short name T607
Test name
Test status
Simulation time 48118880486 ps
CPU time 6.01 seconds
Started Mar 03 01:25:25 PM PST 24
Finished Mar 03 01:25:32 PM PST 24
Peak memory 198256 kb
Host smart-657e560a-b5b4-4214-9b03-78446da0f440
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448869269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1448869269
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2414977626
Short name T469
Test name
Test status
Simulation time 76747678266 ps
CPU time 414.07 seconds
Started Mar 03 01:25:24 PM PST 24
Finished Mar 03 01:32:18 PM PST 24
Peak memory 199720 kb
Host smart-c9cfa973-e5ef-4621-9a49-8c46e1d2244f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414977626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2414977626
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4162680756
Short name T492
Test name
Test status
Simulation time 9689605349 ps
CPU time 9.78 seconds
Started Mar 03 01:25:20 PM PST 24
Finished Mar 03 01:25:30 PM PST 24
Peak memory 198652 kb
Host smart-033f9175-8c3a-490a-babe-3bf364931d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162680756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4162680756
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3776835051
Short name T157
Test name
Test status
Simulation time 514778206808 ps
CPU time 61.22 seconds
Started Mar 03 01:25:22 PM PST 24
Finished Mar 03 01:26:24 PM PST 24
Peak memory 199832 kb
Host smart-9a8828d2-3f5f-4031-b35c-a93c45b6af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776835051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3776835051
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.72307371
Short name T992
Test name
Test status
Simulation time 15020234366 ps
CPU time 179.78 seconds
Started Mar 03 01:25:25 PM PST 24
Finished Mar 03 01:28:25 PM PST 24
Peak memory 199508 kb
Host smart-422370c4-b123-4727-a563-3bbd35893b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72307371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.72307371
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3660130152
Short name T460
Test name
Test status
Simulation time 1861368508 ps
CPU time 1.96 seconds
Started Mar 03 01:25:15 PM PST 24
Finished Mar 03 01:25:17 PM PST 24
Peak memory 197396 kb
Host smart-90677711-41bb-455e-9a02-11969e0ba427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660130152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3660130152
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1629034961
Short name T1024
Test name
Test status
Simulation time 85662196281 ps
CPU time 38.98 seconds
Started Mar 03 01:25:22 PM PST 24
Finished Mar 03 01:26:01 PM PST 24
Peak memory 199736 kb
Host smart-67541a92-b4fb-4d64-892f-36a67ef99c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629034961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1629034961
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3178986340
Short name T613
Test name
Test status
Simulation time 54367941455 ps
CPU time 13.46 seconds
Started Mar 03 01:25:22 PM PST 24
Finished Mar 03 01:25:36 PM PST 24
Peak memory 195252 kb
Host smart-9a83a24a-e5bd-4f7e-91d9-6241d74cc1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178986340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3178986340
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3086789001
Short name T954
Test name
Test status
Simulation time 475010133 ps
CPU time 1.58 seconds
Started Mar 03 01:25:17 PM PST 24
Finished Mar 03 01:25:19 PM PST 24
Peak memory 198856 kb
Host smart-40ccca77-f6c7-4710-8664-ac8be72e9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086789001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3086789001
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.609266794
Short name T1034
Test name
Test status
Simulation time 1007367839045 ps
CPU time 883 seconds
Started Mar 03 01:25:22 PM PST 24
Finished Mar 03 01:40:05 PM PST 24
Peak memory 199648 kb
Host smart-d2ce024c-d858-4747-aa03-935643c99368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609266794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.609266794
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.294547699
Short name T247
Test name
Test status
Simulation time 246016596578 ps
CPU time 567.68 seconds
Started Mar 03 01:25:21 PM PST 24
Finished Mar 03 01:34:49 PM PST 24
Peak memory 216092 kb
Host smart-1423dea7-bd39-4a18-a679-067e24d439a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294547699 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.294547699
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3330027692
Short name T436
Test name
Test status
Simulation time 2397731592 ps
CPU time 3.4 seconds
Started Mar 03 01:25:23 PM PST 24
Finished Mar 03 01:25:26 PM PST 24
Peak memory 198164 kb
Host smart-4e420078-3838-4d9a-877d-dcf908fbb501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330027692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3330027692
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3592845827
Short name T517
Test name
Test status
Simulation time 23703898456 ps
CPU time 43.09 seconds
Started Mar 03 01:25:16 PM PST 24
Finished Mar 03 01:25:59 PM PST 24
Peak memory 199568 kb
Host smart-d3c8c858-340c-4520-a9b2-a26b58dd1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592845827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3592845827
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3981625347
Short name T815
Test name
Test status
Simulation time 132078728065 ps
CPU time 50.86 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:31:20 PM PST 24
Peak memory 199652 kb
Host smart-ce3f1b75-b0a3-4724-b368-157b1c43a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981625347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3981625347
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1346838404
Short name T861
Test name
Test status
Simulation time 36758985402 ps
CPU time 17.51 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:30:47 PM PST 24
Peak memory 197856 kb
Host smart-3723b02d-59be-4eaf-a087-746b1a2bd75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346838404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1346838404
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.894877415
Short name T953
Test name
Test status
Simulation time 109968569917 ps
CPU time 175.62 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:33:25 PM PST 24
Peak memory 199652 kb
Host smart-99d09d8d-d594-452f-b1d1-68d1dd1f6135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894877415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.894877415
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.985152150
Short name T698
Test name
Test status
Simulation time 57021686387 ps
CPU time 22.58 seconds
Started Mar 03 01:30:30 PM PST 24
Finished Mar 03 01:30:52 PM PST 24
Peak memory 199584 kb
Host smart-9710b66c-14d6-4040-9a0c-3c529b0541c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985152150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.985152150
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.671659372
Short name T345
Test name
Test status
Simulation time 20488980474 ps
CPU time 8.77 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:30:39 PM PST 24
Peak memory 198908 kb
Host smart-77b77ccf-08a2-4304-afb0-65c85c7a23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671659372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.671659372
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.262413231
Short name T374
Test name
Test status
Simulation time 125115597000 ps
CPU time 120.22 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:32:30 PM PST 24
Peak memory 199652 kb
Host smart-12a7bd94-6cba-4b1b-a87f-78643b124a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262413231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.262413231
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.102408753
Short name T683
Test name
Test status
Simulation time 48677834256 ps
CPU time 35.25 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:31:04 PM PST 24
Peak memory 199648 kb
Host smart-a6a6b8b0-3023-4769-9d4a-b85e3afde220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102408753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.102408753
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1570353327
Short name T342
Test name
Test status
Simulation time 40419060484 ps
CPU time 18.61 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:30:48 PM PST 24
Peak memory 198976 kb
Host smart-dca7ce0c-55a2-41c1-bb9a-a8199a80bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570353327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1570353327
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2785921765
Short name T462
Test name
Test status
Simulation time 26206007 ps
CPU time 0.55 seconds
Started Mar 03 01:25:31 PM PST 24
Finished Mar 03 01:25:32 PM PST 24
Peak memory 195124 kb
Host smart-c372704d-230b-4892-8fa9-83ebbe5b1cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785921765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2785921765
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4008504410
Short name T617
Test name
Test status
Simulation time 35345562712 ps
CPU time 15.42 seconds
Started Mar 03 01:25:23 PM PST 24
Finished Mar 03 01:25:38 PM PST 24
Peak memory 199332 kb
Host smart-770abca4-7f2e-47b6-b6bf-76676265d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008504410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4008504410
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3199080078
Short name T926
Test name
Test status
Simulation time 10822800911 ps
CPU time 19.36 seconds
Started Mar 03 01:25:23 PM PST 24
Finished Mar 03 01:25:42 PM PST 24
Peak memory 199392 kb
Host smart-73da4729-df1d-45c3-b27b-a48ba57fe414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199080078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3199080078
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3916951730
Short name T17
Test name
Test status
Simulation time 390491663412 ps
CPU time 500.28 seconds
Started Mar 03 01:25:29 PM PST 24
Finished Mar 03 01:33:50 PM PST 24
Peak memory 199752 kb
Host smart-f002be08-a6d5-4f16-a3f2-993e1e129783
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916951730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3916951730
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1411534079
Short name T851
Test name
Test status
Simulation time 213244379923 ps
CPU time 613.35 seconds
Started Mar 03 01:25:30 PM PST 24
Finished Mar 03 01:35:44 PM PST 24
Peak memory 199756 kb
Host smart-1274da90-4c29-4eb3-9966-3b9f6f624d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411534079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1411534079
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.4176037437
Short name T779
Test name
Test status
Simulation time 13282096710 ps
CPU time 4.24 seconds
Started Mar 03 01:25:28 PM PST 24
Finished Mar 03 01:25:33 PM PST 24
Peak memory 197840 kb
Host smart-77a94370-5ff8-4730-9b90-073a2de93df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176037437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4176037437
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.93005777
Short name T625
Test name
Test status
Simulation time 38200025285 ps
CPU time 15.12 seconds
Started Mar 03 01:25:29 PM PST 24
Finished Mar 03 01:25:45 PM PST 24
Peak memory 196388 kb
Host smart-e524ea8b-0170-4440-bb0d-bb992258cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93005777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.93005777
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.708047222
Short name T531
Test name
Test status
Simulation time 26600872967 ps
CPU time 318.03 seconds
Started Mar 03 01:25:29 PM PST 24
Finished Mar 03 01:30:48 PM PST 24
Peak memory 199708 kb
Host smart-e86374f4-c512-4dec-b96e-594ea8a1d47b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708047222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.708047222
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1955217725
Short name T993
Test name
Test status
Simulation time 2282088536 ps
CPU time 6.4 seconds
Started Mar 03 01:25:24 PM PST 24
Finished Mar 03 01:25:30 PM PST 24
Peak memory 197932 kb
Host smart-9a18c88d-7b83-4d1d-80da-094534c1cf96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955217725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1955217725
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3350241231
Short name T823
Test name
Test status
Simulation time 3186455379 ps
CPU time 1.95 seconds
Started Mar 03 01:25:31 PM PST 24
Finished Mar 03 01:25:33 PM PST 24
Peak memory 195316 kb
Host smart-e981c6d7-31d7-445b-a260-cdc32b165e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350241231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3350241231
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3632087307
Short name T983
Test name
Test status
Simulation time 556580424 ps
CPU time 1.68 seconds
Started Mar 03 01:25:21 PM PST 24
Finished Mar 03 01:25:23 PM PST 24
Peak memory 198708 kb
Host smart-99ad231e-6419-46a4-8516-2474a0d46017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632087307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3632087307
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3301639787
Short name T761
Test name
Test status
Simulation time 22761868812 ps
CPU time 260.89 seconds
Started Mar 03 01:25:31 PM PST 24
Finished Mar 03 01:29:52 PM PST 24
Peak memory 199776 kb
Host smart-d8e8d88d-c239-4983-8f81-9cca02eacf21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301639787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3301639787
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1364502881
Short name T925
Test name
Test status
Simulation time 9492383063 ps
CPU time 6.48 seconds
Started Mar 03 01:25:30 PM PST 24
Finished Mar 03 01:25:37 PM PST 24
Peak memory 199632 kb
Host smart-ed6e1ec7-aac9-4830-b620-50acf843d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364502881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1364502881
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.788394000
Short name T406
Test name
Test status
Simulation time 169577930951 ps
CPU time 74.16 seconds
Started Mar 03 01:25:25 PM PST 24
Finished Mar 03 01:26:39 PM PST 24
Peak memory 199692 kb
Host smart-a90d46d1-f342-4a6e-b37e-8869ebafa88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788394000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.788394000
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4276558101
Short name T162
Test name
Test status
Simulation time 115060128364 ps
CPU time 53.54 seconds
Started Mar 03 01:30:29 PM PST 24
Finished Mar 03 01:31:22 PM PST 24
Peak memory 199652 kb
Host smart-6864e55c-78b8-4da5-8d88-2036a814d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276558101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4276558101
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3788058216
Short name T329
Test name
Test status
Simulation time 27780542034 ps
CPU time 44.14 seconds
Started Mar 03 01:30:28 PM PST 24
Finished Mar 03 01:31:12 PM PST 24
Peak memory 199680 kb
Host smart-802f171c-d54d-419f-91e9-5ed6540627e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788058216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3788058216
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.184133650
Short name T855
Test name
Test status
Simulation time 25701461169 ps
CPU time 45.74 seconds
Started Mar 03 01:30:36 PM PST 24
Finished Mar 03 01:31:22 PM PST 24
Peak memory 199632 kb
Host smart-a1cd5bc7-b75f-42b2-a1a0-63924940e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184133650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.184133650
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.251605186
Short name T705
Test name
Test status
Simulation time 27695508759 ps
CPU time 14.37 seconds
Started Mar 03 01:30:37 PM PST 24
Finished Mar 03 01:30:51 PM PST 24
Peak memory 199720 kb
Host smart-ff32808a-f529-4495-b7eb-f4919f2bfbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251605186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.251605186
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3050439709
Short name T147
Test name
Test status
Simulation time 21441908649 ps
CPU time 20.42 seconds
Started Mar 03 01:30:35 PM PST 24
Finished Mar 03 01:30:55 PM PST 24
Peak memory 199664 kb
Host smart-eebb002b-d9a6-4be5-a057-0f0cb8a63c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050439709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3050439709
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1710524356
Short name T1032
Test name
Test status
Simulation time 95037888478 ps
CPU time 42.88 seconds
Started Mar 03 01:30:36 PM PST 24
Finished Mar 03 01:31:19 PM PST 24
Peak memory 199676 kb
Host smart-c950aae8-3ae0-4307-8e5e-e713b649a90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710524356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1710524356
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.445465453
Short name T1023
Test name
Test status
Simulation time 189156149672 ps
CPU time 108.09 seconds
Started Mar 03 01:30:36 PM PST 24
Finished Mar 03 01:32:25 PM PST 24
Peak memory 199668 kb
Host smart-693da8aa-5262-47ce-9b42-1cf5eccc703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445465453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.445465453
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.834393012
Short name T103
Test name
Test status
Simulation time 44901201598 ps
CPU time 24.4 seconds
Started Mar 03 01:30:34 PM PST 24
Finished Mar 03 01:30:58 PM PST 24
Peak memory 199652 kb
Host smart-010381ab-d196-4781-a28a-12127e83f815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834393012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.834393012
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.105473185
Short name T573
Test name
Test status
Simulation time 46747580 ps
CPU time 0.55 seconds
Started Mar 03 01:25:42 PM PST 24
Finished Mar 03 01:25:42 PM PST 24
Peak memory 194184 kb
Host smart-1624a189-d94c-4ac8-b935-f593cae9b7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105473185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.105473185
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2222387617
Short name T597
Test name
Test status
Simulation time 84556660141 ps
CPU time 142.56 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:27:59 PM PST 24
Peak memory 199608 kb
Host smart-3ddf184a-e8d4-4f1a-9db4-e61a53cdeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222387617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2222387617
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.636087023
Short name T778
Test name
Test status
Simulation time 162195371027 ps
CPU time 55.8 seconds
Started Mar 03 01:25:34 PM PST 24
Finished Mar 03 01:26:31 PM PST 24
Peak memory 199696 kb
Host smart-8562c132-aee6-4e8d-8c81-eb14d8df3ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636087023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.636087023
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.537520347
Short name T160
Test name
Test status
Simulation time 41860259804 ps
CPU time 21.63 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:25:58 PM PST 24
Peak memory 199672 kb
Host smart-bc466fa1-706c-412b-b32e-d153f4078f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537520347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.537520347
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1277249804
Short name T443
Test name
Test status
Simulation time 308498308837 ps
CPU time 491.19 seconds
Started Mar 03 01:25:35 PM PST 24
Finished Mar 03 01:33:47 PM PST 24
Peak memory 197376 kb
Host smart-25011800-7290-45ff-96ee-3b76f380df64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277249804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1277249804
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1049554315
Short name T421
Test name
Test status
Simulation time 117812680229 ps
CPU time 407.93 seconds
Started Mar 03 01:25:37 PM PST 24
Finished Mar 03 01:32:25 PM PST 24
Peak memory 199644 kb
Host smart-485e7856-79b9-4301-9375-fc7ebebf5eda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049554315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1049554315
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1371402120
Short name T552
Test name
Test status
Simulation time 9513055115 ps
CPU time 10.41 seconds
Started Mar 03 01:25:35 PM PST 24
Finished Mar 03 01:25:46 PM PST 24
Peak memory 199364 kb
Host smart-1673f70b-f0a8-4315-abba-7606c078e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371402120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1371402120
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2424967240
Short name T508
Test name
Test status
Simulation time 166789104680 ps
CPU time 281.49 seconds
Started Mar 03 01:25:37 PM PST 24
Finished Mar 03 01:30:19 PM PST 24
Peak memory 198700 kb
Host smart-6178c911-600f-4d95-a89a-aaa0afe5c664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424967240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2424967240
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.361201525
Short name T426
Test name
Test status
Simulation time 7303758346 ps
CPU time 380.46 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:31:57 PM PST 24
Peak memory 199652 kb
Host smart-d4196adf-1f2f-4541-a5a3-3ff5d139020e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361201525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.361201525
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1884102356
Short name T522
Test name
Test status
Simulation time 4341921500 ps
CPU time 11.4 seconds
Started Mar 03 01:25:35 PM PST 24
Finished Mar 03 01:25:47 PM PST 24
Peak memory 198456 kb
Host smart-70830b00-bf17-4089-9cd2-d579d2a17450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884102356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1884102356
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1205299466
Short name T745
Test name
Test status
Simulation time 34614820926 ps
CPU time 22.16 seconds
Started Mar 03 01:25:34 PM PST 24
Finished Mar 03 01:25:57 PM PST 24
Peak memory 198680 kb
Host smart-15c93af0-00bf-4da0-b4b0-0457ae1205f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205299466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1205299466
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.35836687
Short name T964
Test name
Test status
Simulation time 42366512017 ps
CPU time 30.55 seconds
Started Mar 03 01:25:35 PM PST 24
Finished Mar 03 01:26:06 PM PST 24
Peak memory 195272 kb
Host smart-b60bd34b-a80c-4dea-8a01-3349127e0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35836687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.35836687
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1679836630
Short name T962
Test name
Test status
Simulation time 5643493032 ps
CPU time 24.46 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:26:01 PM PST 24
Peak memory 199560 kb
Host smart-855c74cc-8149-4e48-82df-4c88c7dc29c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679836630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1679836630
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3219312325
Short name T997
Test name
Test status
Simulation time 348926117514 ps
CPU time 845.27 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:39:42 PM PST 24
Peak memory 199732 kb
Host smart-951f70b2-ce82-4af1-9a44-43976168230f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219312325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3219312325
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3097258151
Short name T832
Test name
Test status
Simulation time 12562140431 ps
CPU time 42.07 seconds
Started Mar 03 01:25:38 PM PST 24
Finished Mar 03 01:26:20 PM PST 24
Peak memory 199288 kb
Host smart-dbf057cb-5337-41f4-b4ff-b13bc88dea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097258151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3097258151
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2612122177
Short name T629
Test name
Test status
Simulation time 9145961814 ps
CPU time 15.53 seconds
Started Mar 03 01:25:36 PM PST 24
Finished Mar 03 01:25:51 PM PST 24
Peak memory 198908 kb
Host smart-eb36d26a-10b0-4367-9034-258e08ff4fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612122177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2612122177
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1605077835
Short name T337
Test name
Test status
Simulation time 19329371443 ps
CPU time 31.16 seconds
Started Mar 03 01:30:36 PM PST 24
Finished Mar 03 01:31:08 PM PST 24
Peak memory 199664 kb
Host smart-633100f4-9261-4e72-ab2d-af7fc6627513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605077835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1605077835
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2747102488
Short name T841
Test name
Test status
Simulation time 23212986844 ps
CPU time 47.62 seconds
Started Mar 03 01:30:35 PM PST 24
Finished Mar 03 01:31:23 PM PST 24
Peak memory 199712 kb
Host smart-259e525a-eab9-4b9e-a4f7-26ffd76bc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747102488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2747102488
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3882150311
Short name T213
Test name
Test status
Simulation time 270023488773 ps
CPU time 127.98 seconds
Started Mar 03 01:30:45 PM PST 24
Finished Mar 03 01:32:54 PM PST 24
Peak memory 199644 kb
Host smart-70429917-29db-4e66-b54c-273be54d6a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882150311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3882150311
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.80996066
Short name T763
Test name
Test status
Simulation time 133758174247 ps
CPU time 114.55 seconds
Started Mar 03 01:30:44 PM PST 24
Finished Mar 03 01:32:39 PM PST 24
Peak memory 199508 kb
Host smart-0ac4d78c-768e-4caa-bd35-115c21236e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80996066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.80996066
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2586993228
Short name T192
Test name
Test status
Simulation time 160673016294 ps
CPU time 362.36 seconds
Started Mar 03 01:30:45 PM PST 24
Finished Mar 03 01:36:48 PM PST 24
Peak memory 199668 kb
Host smart-d1e1f898-9a81-450c-978f-02d46286a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586993228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2586993228
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2220338691
Short name T204
Test name
Test status
Simulation time 76289853904 ps
CPU time 32.13 seconds
Started Mar 03 01:30:44 PM PST 24
Finished Mar 03 01:31:16 PM PST 24
Peak memory 199612 kb
Host smart-3a11963d-6ba1-4b0f-9ad8-3e92b5b135b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220338691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2220338691
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3116206797
Short name T295
Test name
Test status
Simulation time 13804126918 ps
CPU time 11.04 seconds
Started Mar 03 01:30:43 PM PST 24
Finished Mar 03 01:30:54 PM PST 24
Peak memory 199552 kb
Host smart-2b2eb873-2f0e-4deb-b090-4b236a142f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116206797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3116206797
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.18472952
Short name T821
Test name
Test status
Simulation time 43056482722 ps
CPU time 59.72 seconds
Started Mar 03 01:30:45 PM PST 24
Finished Mar 03 01:31:44 PM PST 24
Peak memory 199176 kb
Host smart-1f35ef5c-b26e-442b-9a31-a3e7adcbb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18472952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.18472952
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1574912552
Short name T951
Test name
Test status
Simulation time 34901062869 ps
CPU time 16.16 seconds
Started Mar 03 01:30:53 PM PST 24
Finished Mar 03 01:31:10 PM PST 24
Peak memory 197980 kb
Host smart-f0ef67ff-8efa-4e0b-835f-8e7b8863cd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574912552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1574912552
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2942998254
Short name T515
Test name
Test status
Simulation time 14732300 ps
CPU time 0.58 seconds
Started Mar 03 01:25:51 PM PST 24
Finished Mar 03 01:25:51 PM PST 24
Peak memory 194320 kb
Host smart-372dd083-3a0a-4725-ad62-2c9c05a320ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942998254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2942998254
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3573122678
Short name T225
Test name
Test status
Simulation time 13850867706 ps
CPU time 25.58 seconds
Started Mar 03 01:25:45 PM PST 24
Finished Mar 03 01:26:10 PM PST 24
Peak memory 199584 kb
Host smart-dbacf45a-446f-4440-9f7f-ca010a6fedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573122678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3573122678
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1782769441
Short name T781
Test name
Test status
Simulation time 53238461386 ps
CPU time 23.03 seconds
Started Mar 03 01:25:41 PM PST 24
Finished Mar 03 01:26:04 PM PST 24
Peak memory 198820 kb
Host smart-33de0562-f4e4-4f11-8129-e83350e2b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782769441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1782769441
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3982103390
Short name T1062
Test name
Test status
Simulation time 19187550430 ps
CPU time 15.53 seconds
Started Mar 03 01:25:42 PM PST 24
Finished Mar 03 01:25:57 PM PST 24
Peak memory 199616 kb
Host smart-62e4d841-5180-4111-8716-8db7435ba211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982103390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3982103390
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.61593890
Short name T585
Test name
Test status
Simulation time 224216657137 ps
CPU time 131.61 seconds
Started Mar 03 01:25:41 PM PST 24
Finished Mar 03 01:27:53 PM PST 24
Peak memory 199744 kb
Host smart-397fcc27-1c3b-4317-be7e-b1bd30012db9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61593890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.61593890
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.41359479
Short name T1010
Test name
Test status
Simulation time 166036928785 ps
CPU time 941.5 seconds
Started Mar 03 01:25:42 PM PST 24
Finished Mar 03 01:41:24 PM PST 24
Peak memory 199696 kb
Host smart-631c5669-ac54-42fa-8817-68f6f15432fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41359479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.41359479
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2517245429
Short name T2
Test name
Test status
Simulation time 2377698692 ps
CPU time 3.99 seconds
Started Mar 03 01:25:43 PM PST 24
Finished Mar 03 01:25:47 PM PST 24
Peak memory 198000 kb
Host smart-c399d4f3-5dca-4ff7-874e-0c5d356676f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517245429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2517245429
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2030600169
Short name T1017
Test name
Test status
Simulation time 39002135909 ps
CPU time 36.09 seconds
Started Mar 03 01:25:41 PM PST 24
Finished Mar 03 01:26:17 PM PST 24
Peak memory 197216 kb
Host smart-e9d5a6ca-a39e-4be1-b6af-0e246b9c6bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030600169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2030600169
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2659619393
Short name T919
Test name
Test status
Simulation time 15470607294 ps
CPU time 107.26 seconds
Started Mar 03 01:25:41 PM PST 24
Finished Mar 03 01:27:29 PM PST 24
Peak memory 199628 kb
Host smart-89516cca-54c4-4a63-ab0b-c20e44053416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659619393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2659619393
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3798095642
Short name T544
Test name
Test status
Simulation time 3127639613 ps
CPU time 6.11 seconds
Started Mar 03 01:25:44 PM PST 24
Finished Mar 03 01:25:51 PM PST 24
Peak memory 197612 kb
Host smart-77ffc806-93bc-49ae-af5d-55b4324d4601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798095642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3798095642
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1547787447
Short name T1014
Test name
Test status
Simulation time 64890384884 ps
CPU time 106.24 seconds
Started Mar 03 01:25:42 PM PST 24
Finished Mar 03 01:27:29 PM PST 24
Peak memory 199696 kb
Host smart-70e57d99-9fd3-4819-bf38-86625bc45e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547787447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1547787447
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1276381172
Short name T1022
Test name
Test status
Simulation time 3264897225 ps
CPU time 5.39 seconds
Started Mar 03 01:25:44 PM PST 24
Finished Mar 03 01:25:49 PM PST 24
Peak memory 195528 kb
Host smart-a5db739b-15a4-4a8a-b6c7-bc913b0c4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276381172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1276381172
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3810385384
Short name T504
Test name
Test status
Simulation time 890755438 ps
CPU time 1.4 seconds
Started Mar 03 01:25:43 PM PST 24
Finished Mar 03 01:25:44 PM PST 24
Peak memory 198204 kb
Host smart-ce5b4c40-60f3-4386-814e-6d266000deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810385384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3810385384
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3348623602
Short name T813
Test name
Test status
Simulation time 530966609837 ps
CPU time 137.7 seconds
Started Mar 03 01:25:50 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 199664 kb
Host smart-9f668463-6cc2-4938-b963-01094858f95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348623602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3348623602
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.791135860
Short name T831
Test name
Test status
Simulation time 112221695343 ps
CPU time 602.07 seconds
Started Mar 03 01:25:43 PM PST 24
Finished Mar 03 01:35:45 PM PST 24
Peak memory 224516 kb
Host smart-0ce1f4e0-41bf-4f10-8ba2-c884081b23db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791135860 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.791135860
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1002949416
Short name T470
Test name
Test status
Simulation time 6927082738 ps
CPU time 11.12 seconds
Started Mar 03 01:25:41 PM PST 24
Finished Mar 03 01:25:52 PM PST 24
Peak memory 199196 kb
Host smart-6c36937f-a11e-4303-9d70-c86ca78a356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002949416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1002949416
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1023429048
Short name T733
Test name
Test status
Simulation time 57471042852 ps
CPU time 116.63 seconds
Started Mar 03 01:25:43 PM PST 24
Finished Mar 03 01:27:40 PM PST 24
Peak memory 199624 kb
Host smart-e12ee8e3-0ba7-4608-899b-2e6ae511231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023429048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1023429048
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1980980660
Short name T289
Test name
Test status
Simulation time 25434932778 ps
CPU time 24.18 seconds
Started Mar 03 01:30:52 PM PST 24
Finished Mar 03 01:31:17 PM PST 24
Peak memory 199692 kb
Host smart-8e3f6a4f-3279-4276-8c65-111cbb343be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980980660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1980980660
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.53527576
Short name T786
Test name
Test status
Simulation time 13824681522 ps
CPU time 13.88 seconds
Started Mar 03 01:30:51 PM PST 24
Finished Mar 03 01:31:05 PM PST 24
Peak memory 199248 kb
Host smart-f4ac052d-a629-4aed-b476-1614fc5645f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53527576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.53527576
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3208202624
Short name T244
Test name
Test status
Simulation time 88893589848 ps
CPU time 37.43 seconds
Started Mar 03 01:30:55 PM PST 24
Finished Mar 03 01:31:33 PM PST 24
Peak memory 199524 kb
Host smart-c7059ea3-58d0-4d37-8159-6c4b6a1ea725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208202624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3208202624
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1064696701
Short name T306
Test name
Test status
Simulation time 30117099193 ps
CPU time 53.7 seconds
Started Mar 03 01:30:56 PM PST 24
Finished Mar 03 01:31:50 PM PST 24
Peak memory 199448 kb
Host smart-05531a60-f435-4336-a85b-7a6bb7a93d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064696701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1064696701
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2036087741
Short name T820
Test name
Test status
Simulation time 79869603660 ps
CPU time 74.1 seconds
Started Mar 03 01:30:54 PM PST 24
Finished Mar 03 01:32:08 PM PST 24
Peak memory 199656 kb
Host smart-f7324da0-4778-434d-868c-1a2897aac1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036087741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2036087741
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.807320917
Short name T239
Test name
Test status
Simulation time 58112079975 ps
CPU time 27.32 seconds
Started Mar 03 01:30:56 PM PST 24
Finished Mar 03 01:31:23 PM PST 24
Peak memory 199172 kb
Host smart-00f92521-496d-4ad9-872d-bbe951b9c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807320917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.807320917
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.914545147
Short name T963
Test name
Test status
Simulation time 15697268 ps
CPU time 0.56 seconds
Started Mar 03 01:22:52 PM PST 24
Finished Mar 03 01:22:52 PM PST 24
Peak memory 195240 kb
Host smart-bc57cb6a-cf4d-4f8a-9b4d-dcf6a55b4010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914545147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.914545147
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2277137649
Short name T339
Test name
Test status
Simulation time 28602498386 ps
CPU time 26.58 seconds
Started Mar 03 01:22:42 PM PST 24
Finished Mar 03 01:23:09 PM PST 24
Peak memory 199592 kb
Host smart-b83bdbec-11ab-433d-be94-d09a89c2757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277137649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2277137649
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3804362488
Short name T557
Test name
Test status
Simulation time 136521865101 ps
CPU time 224 seconds
Started Mar 03 01:22:43 PM PST 24
Finished Mar 03 01:26:29 PM PST 24
Peak memory 198804 kb
Host smart-2e18b85f-d8cc-484c-b8d8-7756c8488a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804362488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3804362488
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.2526759843
Short name T1066
Test name
Test status
Simulation time 62352962417 ps
CPU time 166.86 seconds
Started Mar 03 01:22:40 PM PST 24
Finished Mar 03 01:25:29 PM PST 24
Peak memory 199484 kb
Host smart-f46dc874-2b84-409e-a4e7-7872658331d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526759843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2526759843
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1881514518
Short name T739
Test name
Test status
Simulation time 80545352106 ps
CPU time 148.83 seconds
Started Mar 03 01:22:52 PM PST 24
Finished Mar 03 01:25:20 PM PST 24
Peak memory 199740 kb
Host smart-d306c12f-437f-409c-a905-855ab4d61b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881514518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1881514518
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2929975357
Short name T487
Test name
Test status
Simulation time 7836026117 ps
CPU time 19.77 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:23:02 PM PST 24
Peak memory 199664 kb
Host smart-b2e0390d-905a-47c0-9aca-8dc4a9f0755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929975357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2929975357
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.704931658
Short name T401
Test name
Test status
Simulation time 76596631219 ps
CPU time 155.73 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:25:24 PM PST 24
Peak memory 199700 kb
Host smart-c92f98fb-3082-4c0e-95d0-75c4d093ee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704931658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.704931658
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2605029881
Short name T793
Test name
Test status
Simulation time 34027336528 ps
CPU time 132.91 seconds
Started Mar 03 01:22:42 PM PST 24
Finished Mar 03 01:24:56 PM PST 24
Peak memory 199636 kb
Host smart-b695331b-51f6-4d3b-bf2f-1f6b76d4cd36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605029881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2605029881
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3775494732
Short name T801
Test name
Test status
Simulation time 2473347697 ps
CPU time 4.44 seconds
Started Mar 03 01:22:43 PM PST 24
Finished Mar 03 01:22:49 PM PST 24
Peak memory 197536 kb
Host smart-491aa35f-0d8d-4913-89e0-58c5c2f6cd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775494732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3775494732
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2806435489
Short name T1080
Test name
Test status
Simulation time 45738708788 ps
CPU time 71.68 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:23:59 PM PST 24
Peak memory 199652 kb
Host smart-ad6015da-4962-49f2-80cf-590e4526f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806435489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2806435489
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2892911265
Short name T929
Test name
Test status
Simulation time 6415691429 ps
CPU time 3.22 seconds
Started Mar 03 01:22:40 PM PST 24
Finished Mar 03 01:22:45 PM PST 24
Peak memory 195536 kb
Host smart-d1d615a2-6f2b-4718-b14e-6b45bb6a3879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892911265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2892911265
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3387555882
Short name T102
Test name
Test status
Simulation time 67197674 ps
CPU time 0.9 seconds
Started Mar 03 01:22:50 PM PST 24
Finished Mar 03 01:22:51 PM PST 24
Peak memory 217168 kb
Host smart-13d92ac1-7f19-47f8-a6df-97981b5b9bce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387555882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3387555882
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.117130070
Short name T553
Test name
Test status
Simulation time 296479821 ps
CPU time 1.03 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:22:49 PM PST 24
Peak memory 197696 kb
Host smart-ebc74fd5-fa0a-485d-9eaf-6d1baa03cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117130070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.117130070
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.748128761
Short name T281
Test name
Test status
Simulation time 1016727082683 ps
CPU time 167.88 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:25:37 PM PST 24
Peak memory 208032 kb
Host smart-66e6798d-d194-4d4b-a2cc-254dc27a3bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748128761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.748128761
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2146861704
Short name T584
Test name
Test status
Simulation time 2002897640 ps
CPU time 1.82 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:22:44 PM PST 24
Peak memory 197572 kb
Host smart-427e1bb0-a57a-4c72-b99e-6b6b644b1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146861704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2146861704
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3227630971
Short name T665
Test name
Test status
Simulation time 32304053806 ps
CPU time 61.3 seconds
Started Mar 03 01:22:41 PM PST 24
Finished Mar 03 01:23:44 PM PST 24
Peak memory 199704 kb
Host smart-4a960774-e6e1-4a90-8201-717aecffd5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227630971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3227630971
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.570525102
Short name T478
Test name
Test status
Simulation time 41670175 ps
CPU time 0.55 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:26:00 PM PST 24
Peak memory 194336 kb
Host smart-12f6d731-f3eb-47f1-9e04-7f3b857791ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570525102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.570525102
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.930841264
Short name T233
Test name
Test status
Simulation time 64444584209 ps
CPU time 10.78 seconds
Started Mar 03 01:25:49 PM PST 24
Finished Mar 03 01:26:00 PM PST 24
Peak memory 199684 kb
Host smart-1a31d578-ab5e-40bf-95f1-7fc55c18cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930841264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.930841264
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1558993694
Short name T384
Test name
Test status
Simulation time 427752436454 ps
CPU time 479.38 seconds
Started Mar 03 01:25:51 PM PST 24
Finished Mar 03 01:33:51 PM PST 24
Peak memory 199620 kb
Host smart-1a542e6d-48dc-4532-833f-068f6b3cfbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558993694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1558993694
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3951138645
Short name T605
Test name
Test status
Simulation time 23533326173 ps
CPU time 17.28 seconds
Started Mar 03 01:25:52 PM PST 24
Finished Mar 03 01:26:09 PM PST 24
Peak memory 199560 kb
Host smart-9534e18b-51a7-401d-8126-60412c4f5088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951138645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3951138645
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4176053053
Short name T939
Test name
Test status
Simulation time 16885318477 ps
CPU time 4.7 seconds
Started Mar 03 01:25:50 PM PST 24
Finished Mar 03 01:25:55 PM PST 24
Peak memory 198460 kb
Host smart-30846095-9c14-4095-a1aa-9949f1c668b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176053053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4176053053
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1063993676
Short name T549
Test name
Test status
Simulation time 73151587879 ps
CPU time 403.99 seconds
Started Mar 03 01:26:00 PM PST 24
Finished Mar 03 01:32:44 PM PST 24
Peak memory 199668 kb
Host smart-7628e4fe-a31c-4f45-80a2-1440181ce55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063993676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1063993676
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1879931
Short name T519
Test name
Test status
Simulation time 1146865027 ps
CPU time 2.56 seconds
Started Mar 03 01:25:58 PM PST 24
Finished Mar 03 01:26:00 PM PST 24
Peak memory 195296 kb
Host smart-894c135a-0366-448e-906e-b53854ad132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1879931
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3756057225
Short name T885
Test name
Test status
Simulation time 39008450927 ps
CPU time 22.05 seconds
Started Mar 03 01:25:49 PM PST 24
Finished Mar 03 01:26:11 PM PST 24
Peak memory 197812 kb
Host smart-864cfa3b-2721-44fa-8f71-af30b7eb3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756057225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3756057225
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.47465270
Short name T668
Test name
Test status
Simulation time 38955752392 ps
CPU time 285.6 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:30:44 PM PST 24
Peak memory 199668 kb
Host smart-06c68e56-fbf5-4e87-937f-dfe0981e0401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47465270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.47465270
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.854245061
Short name T649
Test name
Test status
Simulation time 3961044736 ps
CPU time 20.69 seconds
Started Mar 03 01:25:50 PM PST 24
Finished Mar 03 01:26:11 PM PST 24
Peak memory 197576 kb
Host smart-5f2b3ae8-fec7-4cd5-8b6a-759ff5d1e0e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854245061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.854245061
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1096609852
Short name T1011
Test name
Test status
Simulation time 162905989699 ps
CPU time 241.23 seconds
Started Mar 03 01:25:49 PM PST 24
Finished Mar 03 01:29:50 PM PST 24
Peak memory 199396 kb
Host smart-8dc974b5-3cb7-4963-a20b-8a711f2ef9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096609852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1096609852
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2753199211
Short name T510
Test name
Test status
Simulation time 648555304 ps
CPU time 1.64 seconds
Started Mar 03 01:25:49 PM PST 24
Finished Mar 03 01:25:51 PM PST 24
Peak memory 195188 kb
Host smart-cfcd0f24-b978-4a6a-978f-382c955e6b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753199211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2753199211
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1845886578
Short name T746
Test name
Test status
Simulation time 487981829 ps
CPU time 1.31 seconds
Started Mar 03 01:25:51 PM PST 24
Finished Mar 03 01:25:52 PM PST 24
Peak memory 197696 kb
Host smart-a25d3a55-326e-4a26-ad14-b279272714a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845886578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1845886578
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2309361020
Short name T279
Test name
Test status
Simulation time 313469228058 ps
CPU time 158.65 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:28:35 PM PST 24
Peak memory 199708 kb
Host smart-e02bd568-fe7f-4a6d-ab8d-b4efbde9bdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309361020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2309361020
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3550299903
Short name T445
Test name
Test status
Simulation time 387251260101 ps
CPU time 1466.01 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:50:24 PM PST 24
Peak memory 224640 kb
Host smart-33caf0d0-0bab-4472-aaff-f1109fc75363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550299903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3550299903
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1131820401
Short name T581
Test name
Test status
Simulation time 389295264 ps
CPU time 1.62 seconds
Started Mar 03 01:25:50 PM PST 24
Finished Mar 03 01:25:52 PM PST 24
Peak memory 197856 kb
Host smart-addbf59c-0f48-4f9c-956c-13baa55df849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131820401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1131820401
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1203398086
Short name T666
Test name
Test status
Simulation time 147643863423 ps
CPU time 733.04 seconds
Started Mar 03 01:25:51 PM PST 24
Finished Mar 03 01:38:04 PM PST 24
Peak memory 199768 kb
Host smart-c2d4909c-36ce-43b1-85d3-3f801334ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203398086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1203398086
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2181288719
Short name T935
Test name
Test status
Simulation time 38480413 ps
CPU time 0.54 seconds
Started Mar 03 01:25:58 PM PST 24
Finished Mar 03 01:25:59 PM PST 24
Peak memory 195300 kb
Host smart-bae2d005-05f9-427e-849d-a05294ed9261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181288719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2181288719
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.360296
Short name T1097
Test name
Test status
Simulation time 40647504215 ps
CPU time 32.9 seconds
Started Mar 03 01:26:01 PM PST 24
Finished Mar 03 01:26:34 PM PST 24
Peak memory 199736 kb
Host smart-d2742c1b-e4a1-49ad-8775-6503ac78fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.360296
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1541213360
Short name T916
Test name
Test status
Simulation time 51852276740 ps
CPU time 82.65 seconds
Started Mar 03 01:25:58 PM PST 24
Finished Mar 03 01:27:21 PM PST 24
Peak memory 199700 kb
Host smart-b201db48-e3c6-4587-8b45-35ba70ac742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541213360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1541213360
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1353134600
Short name T1048
Test name
Test status
Simulation time 48283440342 ps
CPU time 22.41 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:26:20 PM PST 24
Peak memory 199296 kb
Host smart-42e75c16-5039-429c-88de-bc2e7d725afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353134600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1353134600
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1601027755
Short name T651
Test name
Test status
Simulation time 1444683125554 ps
CPU time 2236.59 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 198976 kb
Host smart-71ce4cad-d642-4d80-89fa-19062bbacd05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601027755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1601027755
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.733846387
Short name T896
Test name
Test status
Simulation time 95831287316 ps
CPU time 574.53 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:35:33 PM PST 24
Peak memory 199680 kb
Host smart-2f38b142-3415-4700-919c-99c558094296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733846387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.733846387
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2068524382
Short name T707
Test name
Test status
Simulation time 20606994716 ps
CPU time 18.97 seconds
Started Mar 03 01:25:58 PM PST 24
Finished Mar 03 01:26:17 PM PST 24
Peak memory 196792 kb
Host smart-ad04c403-bc5f-48b1-9649-475c528ce759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068524382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2068524382
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2320743477
Short name T811
Test name
Test status
Simulation time 8894313848 ps
CPU time 137.08 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:28:16 PM PST 24
Peak memory 199688 kb
Host smart-d3e0b0e9-8d7c-440d-9c48-2bdd1c78db3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320743477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2320743477
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1759737635
Short name T290
Test name
Test status
Simulation time 67014158089 ps
CPU time 16.14 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:26:14 PM PST 24
Peak memory 199656 kb
Host smart-bf683bd4-730d-4580-a6e1-68e4b2cf2b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759737635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1759737635
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4218490627
Short name T872
Test name
Test status
Simulation time 2746639073 ps
CPU time 1.39 seconds
Started Mar 03 01:26:00 PM PST 24
Finished Mar 03 01:26:02 PM PST 24
Peak memory 195124 kb
Host smart-fa519b0f-c8ae-488b-a607-f1b8ad0ea3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218490627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4218490627
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.747855548
Short name T442
Test name
Test status
Simulation time 662642089 ps
CPU time 3.86 seconds
Started Mar 03 01:25:58 PM PST 24
Finished Mar 03 01:26:02 PM PST 24
Peak memory 197684 kb
Host smart-b7adfe35-6415-4cda-9799-5da1137ee4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747855548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.747855548
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1819891740
Short name T287
Test name
Test status
Simulation time 254411315672 ps
CPU time 1202.76 seconds
Started Mar 03 01:26:00 PM PST 24
Finished Mar 03 01:46:03 PM PST 24
Peak memory 199652 kb
Host smart-ff037677-bd06-4bb6-b13a-1c262b5a8cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819891740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1819891740
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1269040757
Short name T261
Test name
Test status
Simulation time 56719433810 ps
CPU time 1750 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:55:07 PM PST 24
Peak memory 216016 kb
Host smart-94d7da71-b9e2-4753-9f58-b0dd6416589e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269040757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1269040757
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1268105585
Short name T532
Test name
Test status
Simulation time 1419090801 ps
CPU time 1.42 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:26:00 PM PST 24
Peak memory 197912 kb
Host smart-eccc2821-6eee-4d04-96ec-443573ff1b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268105585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1268105585
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.471352757
Short name T762
Test name
Test status
Simulation time 56587930727 ps
CPU time 235.22 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:29:54 PM PST 24
Peak memory 199636 kb
Host smart-7aba0571-6b70-4001-aba5-bc472fb075e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471352757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.471352757
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.12902748
Short name T912
Test name
Test status
Simulation time 30699477 ps
CPU time 0.58 seconds
Started Mar 03 01:26:06 PM PST 24
Finished Mar 03 01:26:07 PM PST 24
Peak memory 195236 kb
Host smart-61407e13-6d08-4b5b-b68c-17746f2e5ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.12902748
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.92967994
Short name T883
Test name
Test status
Simulation time 31690236374 ps
CPU time 43.83 seconds
Started Mar 03 01:26:02 PM PST 24
Finished Mar 03 01:26:46 PM PST 24
Peak memory 199648 kb
Host smart-41bb93cd-35f5-4c4d-aae5-a9e98aa5bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92967994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.92967994
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3281769631
Short name T195
Test name
Test status
Simulation time 35960727185 ps
CPU time 51.54 seconds
Started Mar 03 01:26:01 PM PST 24
Finished Mar 03 01:26:53 PM PST 24
Peak memory 199668 kb
Host smart-5b837e90-dd8c-4063-b470-f799365dc45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281769631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3281769631
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2950345518
Short name T255
Test name
Test status
Simulation time 19001978087 ps
CPU time 33.95 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:26:33 PM PST 24
Peak memory 199740 kb
Host smart-966662f3-ac53-40a4-9fee-0d3ac4bcd3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950345518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2950345518
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.913507837
Short name T834
Test name
Test status
Simulation time 956382584192 ps
CPU time 1734.15 seconds
Started Mar 03 01:26:00 PM PST 24
Finished Mar 03 01:54:55 PM PST 24
Peak memory 199604 kb
Host smart-4c522a1a-3cce-42d7-b9df-14d9f6431353
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913507837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.913507837
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1679293068
Short name T509
Test name
Test status
Simulation time 66892067817 ps
CPU time 263.01 seconds
Started Mar 03 01:26:09 PM PST 24
Finished Mar 03 01:30:32 PM PST 24
Peak memory 199688 kb
Host smart-207db00d-045a-45f2-8238-4048c77b7045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679293068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1679293068
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3647596307
Short name T599
Test name
Test status
Simulation time 5142877559 ps
CPU time 1.89 seconds
Started Mar 03 01:26:09 PM PST 24
Finished Mar 03 01:26:11 PM PST 24
Peak memory 196888 kb
Host smart-357d8422-3b7f-4a48-9d37-6560d12cfdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647596307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3647596307
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2531772643
Short name T961
Test name
Test status
Simulation time 108468060224 ps
CPU time 64.18 seconds
Started Mar 03 01:26:07 PM PST 24
Finished Mar 03 01:27:11 PM PST 24
Peak memory 199116 kb
Host smart-0cd92ca4-34f9-4073-b0dd-7be007131874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531772643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2531772643
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2528027986
Short name T551
Test name
Test status
Simulation time 14184771322 ps
CPU time 491.33 seconds
Started Mar 03 01:26:07 PM PST 24
Finished Mar 03 01:34:19 PM PST 24
Peak memory 199732 kb
Host smart-af7bc273-f3ef-42ae-8ae7-584cde11f8c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528027986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2528027986
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3394686640
Short name T570
Test name
Test status
Simulation time 1657726571 ps
CPU time 2.09 seconds
Started Mar 03 01:25:57 PM PST 24
Finished Mar 03 01:25:59 PM PST 24
Peak memory 197772 kb
Host smart-1f2d76b0-8760-4872-a87e-b673616a097d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394686640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3394686640
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.441219504
Short name T363
Test name
Test status
Simulation time 25731971518 ps
CPU time 44.21 seconds
Started Mar 03 01:26:05 PM PST 24
Finished Mar 03 01:26:50 PM PST 24
Peak memory 199672 kb
Host smart-4c7cad23-89a6-4ec0-9aa6-9bfb1855323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441219504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.441219504
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1288028691
Short name T938
Test name
Test status
Simulation time 3840768057 ps
CPU time 3.61 seconds
Started Mar 03 01:26:06 PM PST 24
Finished Mar 03 01:26:10 PM PST 24
Peak memory 195560 kb
Host smart-43cc18da-1f78-45cb-84a3-24c814825c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288028691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1288028691
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.291899485
Short name T1030
Test name
Test status
Simulation time 251988220 ps
CPU time 1.51 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:26:01 PM PST 24
Peak memory 197460 kb
Host smart-21cdbd0f-81e6-4c9e-8dcc-01ffc77d0bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291899485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.291899485
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1520878716
Short name T387
Test name
Test status
Simulation time 1646337573337 ps
CPU time 927.23 seconds
Started Mar 03 01:26:06 PM PST 24
Finished Mar 03 01:41:33 PM PST 24
Peak memory 215792 kb
Host smart-82c781f9-5334-42f1-b935-615cb49e24e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520878716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1520878716
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3146779664
Short name T448
Test name
Test status
Simulation time 22556203183 ps
CPU time 369.91 seconds
Started Mar 03 01:26:05 PM PST 24
Finished Mar 03 01:32:15 PM PST 24
Peak memory 214780 kb
Host smart-238c9a42-19b2-4fe1-8443-511e5ef0f7cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146779664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3146779664
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2595610805
Short name T1005
Test name
Test status
Simulation time 6109391815 ps
CPU time 1.94 seconds
Started Mar 03 01:26:09 PM PST 24
Finished Mar 03 01:26:11 PM PST 24
Peak memory 197792 kb
Host smart-61d7b19f-f2c9-42c9-b665-3ca6ddd95aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595610805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2595610805
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2361952596
Short name T990
Test name
Test status
Simulation time 38935423996 ps
CPU time 31.09 seconds
Started Mar 03 01:25:59 PM PST 24
Finished Mar 03 01:26:30 PM PST 24
Peak memory 199680 kb
Host smart-fed5447d-062f-435e-9952-675aea2d70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361952596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2361952596
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2163598721
Short name T702
Test name
Test status
Simulation time 19851390 ps
CPU time 0.53 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:26:15 PM PST 24
Peak memory 195216 kb
Host smart-9af0caaa-4a0f-45ba-bc47-1a49ca6de9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163598721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2163598721
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3475543698
Short name T982
Test name
Test status
Simulation time 58861678476 ps
CPU time 23.27 seconds
Started Mar 03 01:26:08 PM PST 24
Finished Mar 03 01:26:31 PM PST 24
Peak memory 199580 kb
Host smart-ef920ae1-86f6-40b4-bcc3-edb8b6e8dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475543698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3475543698
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2597139009
Short name T15
Test name
Test status
Simulation time 64723341284 ps
CPU time 25.89 seconds
Started Mar 03 01:26:08 PM PST 24
Finished Mar 03 01:26:34 PM PST 24
Peak memory 198912 kb
Host smart-cd13bfd8-14d0-4d51-a215-084df9857a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597139009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2597139009
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.55233308
Short name T182
Test name
Test status
Simulation time 10447801583 ps
CPU time 11.47 seconds
Started Mar 03 01:26:07 PM PST 24
Finished Mar 03 01:26:18 PM PST 24
Peak memory 197888 kb
Host smart-bfb7ed1d-b401-41b6-9140-0ca667130a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55233308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.55233308
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.611180837
Short name T79
Test name
Test status
Simulation time 576923394430 ps
CPU time 228.32 seconds
Started Mar 03 01:26:05 PM PST 24
Finished Mar 03 01:29:54 PM PST 24
Peak memory 198364 kb
Host smart-bd060483-41d5-488c-a1d2-537ecf50f497
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611180837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.611180837
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2156799607
Short name T947
Test name
Test status
Simulation time 111740641725 ps
CPU time 896.07 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:41:10 PM PST 24
Peak memory 199776 kb
Host smart-4458a1b8-9f20-4a75-b8e3-b4a0c8511d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156799607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2156799607
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.978251586
Short name T457
Test name
Test status
Simulation time 8408680167 ps
CPU time 5.72 seconds
Started Mar 03 01:26:15 PM PST 24
Finished Mar 03 01:26:21 PM PST 24
Peak memory 198836 kb
Host smart-19277240-34c5-4004-ab6a-9c52e5a86bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978251586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.978251586
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2118125520
Short name T1070
Test name
Test status
Simulation time 44912915629 ps
CPU time 22.2 seconds
Started Mar 03 01:26:12 PM PST 24
Finished Mar 03 01:26:35 PM PST 24
Peak memory 197748 kb
Host smart-e90268ac-794d-4d06-9fe8-ede7522e584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118125520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2118125520
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2559263116
Short name T432
Test name
Test status
Simulation time 11172090555 ps
CPU time 464.62 seconds
Started Mar 03 01:26:18 PM PST 24
Finished Mar 03 01:34:02 PM PST 24
Peak memory 199672 kb
Host smart-dc7d6906-f3e2-48b7-b9a2-672bbe02a1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559263116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2559263116
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3024291377
Short name T1050
Test name
Test status
Simulation time 3504839640 ps
CPU time 29.83 seconds
Started Mar 03 01:26:07 PM PST 24
Finished Mar 03 01:26:37 PM PST 24
Peak memory 198116 kb
Host smart-43af343e-3eca-4df9-a049-fe052236f697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024291377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3024291377
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1594875711
Short name T638
Test name
Test status
Simulation time 305175940974 ps
CPU time 238.04 seconds
Started Mar 03 01:26:12 PM PST 24
Finished Mar 03 01:30:11 PM PST 24
Peak memory 199632 kb
Host smart-7c83a1e1-61cc-42f8-963a-58711a7f9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594875711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1594875711
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3623119932
Short name T618
Test name
Test status
Simulation time 4784747031 ps
CPU time 5.07 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:26:18 PM PST 24
Peak memory 195480 kb
Host smart-561cee9f-ace1-44fe-921a-555e526ec56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623119932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3623119932
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.258070534
Short name T38
Test name
Test status
Simulation time 489274133 ps
CPU time 2.43 seconds
Started Mar 03 01:26:07 PM PST 24
Finished Mar 03 01:26:10 PM PST 24
Peak memory 197436 kb
Host smart-4894af67-c946-426e-8e17-d7338db32715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258070534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.258070534
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3100051360
Short name T846
Test name
Test status
Simulation time 58386656902 ps
CPU time 113.41 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 199704 kb
Host smart-750f0f3d-a5e5-4286-a7b9-49898e2544c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100051360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3100051360
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.204918410
Short name T967
Test name
Test status
Simulation time 357427709 ps
CPU time 1.4 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:26:16 PM PST 24
Peak memory 197948 kb
Host smart-742c331e-ac06-457f-829d-850943cc9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204918410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.204918410
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3992013119
Short name T720
Test name
Test status
Simulation time 62913265735 ps
CPU time 30.04 seconds
Started Mar 03 01:26:04 PM PST 24
Finished Mar 03 01:26:34 PM PST 24
Peak memory 199696 kb
Host smart-84908f60-6be6-4dd4-a385-f3a3a310e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992013119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3992013119
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1445106831
Short name T797
Test name
Test status
Simulation time 32065664 ps
CPU time 0.58 seconds
Started Mar 03 01:26:24 PM PST 24
Finished Mar 03 01:26:24 PM PST 24
Peak memory 195260 kb
Host smart-1b77090a-c9a3-4885-8e73-4350d99ff7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445106831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1445106831
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1486467403
Short name T203
Test name
Test status
Simulation time 17630088718 ps
CPU time 30.32 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:26:44 PM PST 24
Peak memory 199604 kb
Host smart-e5a29893-90f3-4d61-a2d3-d66d98c4a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486467403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1486467403
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3746704561
Short name T47
Test name
Test status
Simulation time 214320203905 ps
CPU time 38.9 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:26:52 PM PST 24
Peak memory 199624 kb
Host smart-fdea2323-268a-42a6-90fe-645b164b3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746704561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3746704561
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.916781887
Short name T716
Test name
Test status
Simulation time 115018318492 ps
CPU time 77.79 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:27:32 PM PST 24
Peak memory 199640 kb
Host smart-a2ba9201-d9c1-465f-8ba6-c281706619bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916781887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.916781887
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3338701542
Short name T511
Test name
Test status
Simulation time 83441830503 ps
CPU time 194.91 seconds
Started Mar 03 01:26:20 PM PST 24
Finished Mar 03 01:29:35 PM PST 24
Peak memory 199704 kb
Host smart-f1cc5f41-e99d-4de4-9fff-91db89c5c6ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338701542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3338701542
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3358355884
Short name T1019
Test name
Test status
Simulation time 223192789 ps
CPU time 1.02 seconds
Started Mar 03 01:26:21 PM PST 24
Finished Mar 03 01:26:22 PM PST 24
Peak memory 196696 kb
Host smart-eb4af38b-aedc-4829-8c02-63dde956dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358355884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3358355884
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.933346071
Short name T792
Test name
Test status
Simulation time 337945240314 ps
CPU time 106.6 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:28:00 PM PST 24
Peak memory 208016 kb
Host smart-ef3415ef-065a-46cd-9237-5f6675ed2c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933346071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.933346071
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.393833905
Short name T758
Test name
Test status
Simulation time 25524822045 ps
CPU time 1455.37 seconds
Started Mar 03 01:26:22 PM PST 24
Finished Mar 03 01:50:37 PM PST 24
Peak memory 199688 kb
Host smart-a1a20650-cbc3-4a04-b9c1-1b793d3c61ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393833905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.393833905
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.312143588
Short name T491
Test name
Test status
Simulation time 2489462183 ps
CPU time 2.08 seconds
Started Mar 03 01:26:17 PM PST 24
Finished Mar 03 01:26:20 PM PST 24
Peak memory 198208 kb
Host smart-3f289a3c-f21b-4e59-8b8b-67e2add3ec23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312143588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.312143588
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.467812155
Short name T167
Test name
Test status
Simulation time 137354691954 ps
CPU time 16.71 seconds
Started Mar 03 01:26:20 PM PST 24
Finished Mar 03 01:26:37 PM PST 24
Peak memory 199448 kb
Host smart-3d8055f2-a928-48d3-9418-bd7401cd1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467812155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.467812155
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3986583096
Short name T566
Test name
Test status
Simulation time 4747457379 ps
CPU time 4.83 seconds
Started Mar 03 01:26:14 PM PST 24
Finished Mar 03 01:26:19 PM PST 24
Peak memory 195412 kb
Host smart-479a26f8-eedb-46e0-bf61-bffa8f3dab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986583096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3986583096
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.855175289
Short name T500
Test name
Test status
Simulation time 6095562312 ps
CPU time 10.78 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:26:23 PM PST 24
Peak memory 199212 kb
Host smart-62476da5-50aa-40ca-a41b-38082fa95c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855175289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.855175289
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2215300479
Short name T1040
Test name
Test status
Simulation time 1618938491 ps
CPU time 1.52 seconds
Started Mar 03 01:26:20 PM PST 24
Finished Mar 03 01:26:22 PM PST 24
Peak memory 197936 kb
Host smart-6f5da7a9-dade-4146-90a2-ae7c299aadff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215300479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2215300479
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3387561323
Short name T529
Test name
Test status
Simulation time 48371330061 ps
CPU time 88.62 seconds
Started Mar 03 01:26:13 PM PST 24
Finished Mar 03 01:27:42 PM PST 24
Peak memory 199720 kb
Host smart-452af12f-4896-4e11-b6b3-5562f982e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387561323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3387561323
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1530406623
Short name T26
Test name
Test status
Simulation time 32574875 ps
CPU time 0.56 seconds
Started Mar 03 01:26:26 PM PST 24
Finished Mar 03 01:26:27 PM PST 24
Peak memory 195268 kb
Host smart-c404b3d5-7582-48f3-b725-78cbffb73417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530406623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1530406623
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3633886615
Short name T362
Test name
Test status
Simulation time 142213201066 ps
CPU time 65.4 seconds
Started Mar 03 01:26:21 PM PST 24
Finished Mar 03 01:27:27 PM PST 24
Peak memory 199668 kb
Host smart-8f6c0d3b-56a0-469a-89af-3fee72c5093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633886615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3633886615
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4104794663
Short name T767
Test name
Test status
Simulation time 203742762898 ps
CPU time 76.87 seconds
Started Mar 03 01:26:21 PM PST 24
Finished Mar 03 01:27:38 PM PST 24
Peak memory 199348 kb
Host smart-c71cf3f6-eef4-4b17-a7c2-6c42634e0f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104794663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4104794663
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.65125598
Short name T320
Test name
Test status
Simulation time 84964706595 ps
CPU time 71.78 seconds
Started Mar 03 01:26:19 PM PST 24
Finished Mar 03 01:27:31 PM PST 24
Peak memory 198976 kb
Host smart-4ef5c9d5-f315-4b72-be2e-09f66021db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65125598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.65125598
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.253791939
Short name T547
Test name
Test status
Simulation time 738398827374 ps
CPU time 330.85 seconds
Started Mar 03 01:26:27 PM PST 24
Finished Mar 03 01:31:58 PM PST 24
Peak memory 198984 kb
Host smart-cf542ebb-0135-476b-82ca-5639e6239c7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253791939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.253791939
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.673419666
Short name T765
Test name
Test status
Simulation time 153049739234 ps
CPU time 298.66 seconds
Started Mar 03 01:26:26 PM PST 24
Finished Mar 03 01:31:26 PM PST 24
Peak memory 199688 kb
Host smart-74ab8398-8316-415c-8fc5-bf9636728187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673419666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.673419666
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1184732271
Short name T903
Test name
Test status
Simulation time 8205647733 ps
CPU time 14.04 seconds
Started Mar 03 01:26:30 PM PST 24
Finished Mar 03 01:26:44 PM PST 24
Peak memory 198192 kb
Host smart-05d0fafd-b211-4b12-9ac9-be04719c4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184732271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1184732271
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1708808653
Short name T394
Test name
Test status
Simulation time 51771454852 ps
CPU time 92.6 seconds
Started Mar 03 01:26:30 PM PST 24
Finished Mar 03 01:28:03 PM PST 24
Peak memory 208156 kb
Host smart-f4812b72-cc82-4a0b-bfe7-9e66b4945793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708808653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1708808653
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2587760056
Short name T417
Test name
Test status
Simulation time 17720161609 ps
CPU time 125.85 seconds
Started Mar 03 01:26:27 PM PST 24
Finished Mar 03 01:28:34 PM PST 24
Peak memory 199748 kb
Host smart-416bc2f8-049e-4d50-b24c-df0883d2552e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587760056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2587760056
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.221887140
Short name T886
Test name
Test status
Simulation time 3009962107 ps
CPU time 6.32 seconds
Started Mar 03 01:26:20 PM PST 24
Finished Mar 03 01:26:27 PM PST 24
Peak memory 198112 kb
Host smart-ca16d018-6f15-4787-aa76-380d5f01e010
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221887140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.221887140
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3375907708
Short name T944
Test name
Test status
Simulation time 40542061774 ps
CPU time 65.39 seconds
Started Mar 03 01:26:25 PM PST 24
Finished Mar 03 01:27:31 PM PST 24
Peak memory 199748 kb
Host smart-53563e54-b6b0-4a9b-8d54-9d211583da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375907708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3375907708
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.302497663
Short name T787
Test name
Test status
Simulation time 2220876078 ps
CPU time 1.47 seconds
Started Mar 03 01:26:26 PM PST 24
Finished Mar 03 01:26:28 PM PST 24
Peak memory 195248 kb
Host smart-1d4a5193-5afa-44f8-9a0b-88706a072fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302497663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.302497663
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4182808108
Short name T1093
Test name
Test status
Simulation time 279372276 ps
CPU time 1.41 seconds
Started Mar 03 01:26:21 PM PST 24
Finished Mar 03 01:26:23 PM PST 24
Peak memory 198036 kb
Host smart-535c1dca-7e1a-43eb-9c16-629c4cb8da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182808108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4182808108
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1903578425
Short name T769
Test name
Test status
Simulation time 6723170440 ps
CPU time 11.59 seconds
Started Mar 03 01:26:26 PM PST 24
Finished Mar 03 01:26:38 PM PST 24
Peak memory 198708 kb
Host smart-ad7c90f9-4c55-4091-a536-eeaaf66137d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903578425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1903578425
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.338516856
Short name T161
Test name
Test status
Simulation time 62149608231 ps
CPU time 14.4 seconds
Started Mar 03 01:26:20 PM PST 24
Finished Mar 03 01:26:34 PM PST 24
Peak memory 199540 kb
Host smart-c846ff7c-f36f-425f-a0fc-a312d2b90bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338516856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.338516856
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3496781935
Short name T78
Test name
Test status
Simulation time 20755377 ps
CPU time 0.57 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:26:35 PM PST 24
Peak memory 195120 kb
Host smart-7e0e53cf-a498-4726-af5f-084c1996ee12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496781935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3496781935
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1505948687
Short name T127
Test name
Test status
Simulation time 301022472602 ps
CPU time 81.78 seconds
Started Mar 03 01:26:26 PM PST 24
Finished Mar 03 01:27:48 PM PST 24
Peak memory 199644 kb
Host smart-f4f956a6-5fc0-416f-b139-f119f192b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505948687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1505948687
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3124370065
Short name T341
Test name
Test status
Simulation time 63523826346 ps
CPU time 100.39 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:28:15 PM PST 24
Peak memory 199752 kb
Host smart-eebdef62-00d0-48e5-b6cb-7c75e094e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124370065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3124370065
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2043765006
Short name T516
Test name
Test status
Simulation time 18308680883 ps
CPU time 27.71 seconds
Started Mar 03 01:26:36 PM PST 24
Finished Mar 03 01:27:04 PM PST 24
Peak memory 199036 kb
Host smart-e5bbcab3-9536-4512-be2d-60e06114f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043765006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2043765006
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2121544395
Short name T444
Test name
Test status
Simulation time 644140109556 ps
CPU time 194.67 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:29:49 PM PST 24
Peak memory 199064 kb
Host smart-43982261-b0c1-49b4-8164-e6bf4fc334f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121544395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2121544395
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2148155112
Short name T686
Test name
Test status
Simulation time 90708827296 ps
CPU time 504.09 seconds
Started Mar 03 01:26:33 PM PST 24
Finished Mar 03 01:34:58 PM PST 24
Peak memory 199688 kb
Host smart-4335e26f-ecdf-40ee-94fe-55a49f076226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148155112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2148155112
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1948503353
Short name T768
Test name
Test status
Simulation time 8014605247 ps
CPU time 18.92 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:26:53 PM PST 24
Peak memory 198652 kb
Host smart-30eae89c-0bd8-4c56-8ae2-d073b61a1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948503353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1948503353
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3270626001
Short name T756
Test name
Test status
Simulation time 48545962392 ps
CPU time 20.43 seconds
Started Mar 03 01:26:35 PM PST 24
Finished Mar 03 01:26:56 PM PST 24
Peak memory 198432 kb
Host smart-a679bfd2-eb81-4f61-adcb-a31b0f83bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270626001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3270626001
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3887848208
Short name T1078
Test name
Test status
Simulation time 5372364189 ps
CPU time 143.79 seconds
Started Mar 03 01:26:36 PM PST 24
Finished Mar 03 01:28:59 PM PST 24
Peak memory 199676 kb
Host smart-401d6c58-283e-4512-a500-f9cabcfbf0bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887848208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3887848208
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.458178725
Short name T719
Test name
Test status
Simulation time 9596789019 ps
CPU time 14.73 seconds
Started Mar 03 01:26:37 PM PST 24
Finished Mar 03 01:26:52 PM PST 24
Peak memory 197396 kb
Host smart-e1ccaeb2-acf8-4e8f-9835-7a289a5b4b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458178725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.458178725
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2020051458
Short name T411
Test name
Test status
Simulation time 6403964641 ps
CPU time 11.2 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:26:46 PM PST 24
Peak memory 195440 kb
Host smart-035cca26-b492-4376-9d6a-a1237a7fa460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020051458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2020051458
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2368341997
Short name T497
Test name
Test status
Simulation time 5771856356 ps
CPU time 15.41 seconds
Started Mar 03 01:26:29 PM PST 24
Finished Mar 03 01:26:45 PM PST 24
Peak memory 199672 kb
Host smart-a8e89cff-12d5-4940-9da1-7b68d7bddaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368341997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2368341997
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.263902788
Short name T364
Test name
Test status
Simulation time 438823920322 ps
CPU time 167.39 seconds
Started Mar 03 01:26:35 PM PST 24
Finished Mar 03 01:29:23 PM PST 24
Peak memory 208020 kb
Host smart-2f1ffad3-45d6-4c95-b90f-201785db44e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263902788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.263902788
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3528445706
Short name T456
Test name
Test status
Simulation time 2001395865 ps
CPU time 1.99 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:26:37 PM PST 24
Peak memory 197992 kb
Host smart-cb3331c0-30fe-4897-8785-f595793680b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528445706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3528445706
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4104921612
Short name T575
Test name
Test status
Simulation time 24196466839 ps
CPU time 19.23 seconds
Started Mar 03 01:26:29 PM PST 24
Finished Mar 03 01:26:49 PM PST 24
Peak memory 199704 kb
Host smart-e9780fee-8466-46e8-9284-a906d6af02a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104921612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4104921612
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1816176861
Short name T614
Test name
Test status
Simulation time 14946133 ps
CPU time 0.56 seconds
Started Mar 03 01:26:48 PM PST 24
Finished Mar 03 01:26:49 PM PST 24
Peak memory 195236 kb
Host smart-c30aaf66-cf62-4203-ad4b-e437d99c2292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816176861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1816176861
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3387792164
Short name T223
Test name
Test status
Simulation time 105731564959 ps
CPU time 149.21 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:29:03 PM PST 24
Peak memory 199664 kb
Host smart-26362051-a585-44c7-a90e-b1fb69a62687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387792164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3387792164
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.32520879
Short name T19
Test name
Test status
Simulation time 312987194278 ps
CPU time 515.15 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:35:17 PM PST 24
Peak memory 199444 kb
Host smart-7eb2f5b9-b4e6-43b0-bd80-0aa534c8188d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.32520879
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1364921113
Short name T520
Test name
Test status
Simulation time 53742811313 ps
CPU time 161.64 seconds
Started Mar 03 01:26:46 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199676 kb
Host smart-aad17fa4-41bc-47d9-bba4-b8b7d0ece268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364921113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1364921113
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4220165284
Short name T759
Test name
Test status
Simulation time 2161449681 ps
CPU time 1.64 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:26:44 PM PST 24
Peak memory 195324 kb
Host smart-f7a83d92-0f4f-4861-be3c-e09df2db5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220165284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4220165284
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.215497372
Short name T441
Test name
Test status
Simulation time 110486492147 ps
CPU time 53.15 seconds
Started Mar 03 01:26:41 PM PST 24
Finished Mar 03 01:27:34 PM PST 24
Peak memory 197880 kb
Host smart-4210451d-47d2-4d48-a7f9-3c554484fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215497372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.215497372
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2606664273
Short name T236
Test name
Test status
Simulation time 4864636447 ps
CPU time 65.59 seconds
Started Mar 03 01:26:48 PM PST 24
Finished Mar 03 01:27:54 PM PST 24
Peak memory 199248 kb
Host smart-0fa984b8-c0c1-404a-8ac1-09251f167f44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606664273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2606664273
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1960520088
Short name T391
Test name
Test status
Simulation time 92506233861 ps
CPU time 68.72 seconds
Started Mar 03 01:26:45 PM PST 24
Finished Mar 03 01:27:53 PM PST 24
Peak memory 199584 kb
Host smart-c58e434d-0053-419c-964a-78193ce7fc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960520088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1960520088
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2382598197
Short name T950
Test name
Test status
Simulation time 2716546415 ps
CPU time 1.62 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:26:44 PM PST 24
Peak memory 195176 kb
Host smart-77561380-7358-46eb-899c-51d87ce5ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382598197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2382598197
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1072378012
Short name T461
Test name
Test status
Simulation time 5467473656 ps
CPU time 17.49 seconds
Started Mar 03 01:26:36 PM PST 24
Finished Mar 03 01:26:54 PM PST 24
Peak memory 198976 kb
Host smart-0fd8aef7-1236-4b44-a17b-9b464f5a4b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072378012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1072378012
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2701348178
Short name T958
Test name
Test status
Simulation time 678427887210 ps
CPU time 986.65 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:43:09 PM PST 24
Peak memory 199564 kb
Host smart-6c920519-2410-4cee-94ec-c0586e976429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701348178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2701348178
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3049118717
Short name T429
Test name
Test status
Simulation time 736916634 ps
CPU time 2.67 seconds
Started Mar 03 01:26:48 PM PST 24
Finished Mar 03 01:26:51 PM PST 24
Peak memory 198160 kb
Host smart-6a32184d-e321-474c-ac65-a788521c7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049118717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3049118717
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1335926812
Short name T887
Test name
Test status
Simulation time 34158376563 ps
CPU time 23.91 seconds
Started Mar 03 01:26:34 PM PST 24
Finished Mar 03 01:26:58 PM PST 24
Peak memory 199252 kb
Host smart-ba6f3087-92a1-40b1-8456-8499f61d5361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335926812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1335926812
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1692107221
Short name T1046
Test name
Test status
Simulation time 116235769 ps
CPU time 0.54 seconds
Started Mar 03 01:26:49 PM PST 24
Finished Mar 03 01:26:51 PM PST 24
Peak memory 195280 kb
Host smart-9c181120-443b-4496-9118-b884c53b877c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692107221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1692107221
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1818141798
Short name T18
Test name
Test status
Simulation time 26063932424 ps
CPU time 41.53 seconds
Started Mar 03 01:26:45 PM PST 24
Finished Mar 03 01:27:27 PM PST 24
Peak memory 199520 kb
Host smart-9b85963a-acb5-44fc-a200-c284a2a9827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818141798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1818141798
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.10514685
Short name T609
Test name
Test status
Simulation time 281576900278 ps
CPU time 331.17 seconds
Started Mar 03 01:26:43 PM PST 24
Finished Mar 03 01:32:14 PM PST 24
Peak memory 199664 kb
Host smart-974ebaa2-891b-4874-af25-e43b2eb910bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10514685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.10514685
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2056788879
Short name T219
Test name
Test status
Simulation time 93304581738 ps
CPU time 12.56 seconds
Started Mar 03 01:26:44 PM PST 24
Finished Mar 03 01:26:57 PM PST 24
Peak memory 198756 kb
Host smart-3bf8bb17-c431-4cc4-885f-5dda6d3ada20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056788879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2056788879
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1445247731
Short name T902
Test name
Test status
Simulation time 562470753063 ps
CPU time 197.88 seconds
Started Mar 03 01:26:43 PM PST 24
Finished Mar 03 01:30:01 PM PST 24
Peak memory 198044 kb
Host smart-00c45d2f-5eb6-4f87-8c15-d9d7cd2f19e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445247731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1445247731
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3117398413
Short name T539
Test name
Test status
Simulation time 123593668842 ps
CPU time 871.69 seconds
Started Mar 03 01:26:48 PM PST 24
Finished Mar 03 01:41:21 PM PST 24
Peak memory 199764 kb
Host smart-22329171-925a-4d58-9788-dd6708ecb0e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117398413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3117398413
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1209459558
Short name T784
Test name
Test status
Simulation time 8069378040 ps
CPU time 11.8 seconds
Started Mar 03 01:26:51 PM PST 24
Finished Mar 03 01:27:05 PM PST 24
Peak memory 199684 kb
Host smart-4ec65999-dd36-473f-a5e8-b8031b671a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209459558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1209459558
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1441271770
Short name T134
Test name
Test status
Simulation time 292246575 ps
CPU time 0.77 seconds
Started Mar 03 01:26:41 PM PST 24
Finished Mar 03 01:26:42 PM PST 24
Peak memory 193276 kb
Host smart-32c04007-e5e8-44cd-aa24-bc480db998c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441271770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1441271770
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2437031335
Short name T699
Test name
Test status
Simulation time 8352085532 ps
CPU time 358.82 seconds
Started Mar 03 01:26:51 PM PST 24
Finished Mar 03 01:32:50 PM PST 24
Peak memory 199736 kb
Host smart-16f18f99-740b-4345-82c9-cf9d986757bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437031335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2437031335
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1657423383
Short name T817
Test name
Test status
Simulation time 3097329238 ps
CPU time 25.64 seconds
Started Mar 03 01:26:43 PM PST 24
Finished Mar 03 01:27:08 PM PST 24
Peak memory 198088 kb
Host smart-8c4dfae3-ca61-45d1-9a1e-b6eab10ba142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657423383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1657423383
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1333953511
Short name T1
Test name
Test status
Simulation time 152494238403 ps
CPU time 47.34 seconds
Started Mar 03 01:26:49 PM PST 24
Finished Mar 03 01:27:37 PM PST 24
Peak memory 199464 kb
Host smart-a7eae0ae-569f-4f80-ba77-77b5e3981b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333953511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1333953511
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3606218635
Short name T724
Test name
Test status
Simulation time 5065628997 ps
CPU time 4.52 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:26:47 PM PST 24
Peak memory 195556 kb
Host smart-238b9319-3b4f-4ae2-a7c0-29f674c23115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606218635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3606218635
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2776123340
Short name T545
Test name
Test status
Simulation time 409573026 ps
CPU time 1.88 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:26:44 PM PST 24
Peak memory 197868 kb
Host smart-aee4d834-c07c-4895-896f-7ff9988bb367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776123340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2776123340
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.238105910
Short name T438
Test name
Test status
Simulation time 48049105941 ps
CPU time 62.71 seconds
Started Mar 03 01:26:50 PM PST 24
Finished Mar 03 01:27:53 PM PST 24
Peak memory 199584 kb
Host smart-1daf407c-7874-446b-ad4b-cc63d56eb7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238105910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.238105910
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2156485568
Short name T582
Test name
Test status
Simulation time 401347084 ps
CPU time 1.31 seconds
Started Mar 03 01:26:49 PM PST 24
Finished Mar 03 01:26:52 PM PST 24
Peak memory 197660 kb
Host smart-570486b8-f0b2-49b0-bac4-9f2ab3967609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156485568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2156485568
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3416656061
Short name T591
Test name
Test status
Simulation time 70670759033 ps
CPU time 29.27 seconds
Started Mar 03 01:26:42 PM PST 24
Finished Mar 03 01:27:12 PM PST 24
Peak memory 199704 kb
Host smart-f99a7eba-683b-4122-9b0d-300d8a4ae5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416656061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3416656061
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.706306138
Short name T459
Test name
Test status
Simulation time 29324608 ps
CPU time 0.61 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:26:58 PM PST 24
Peak memory 195260 kb
Host smart-e3493b1d-3323-4c0f-8c09-2aa6718a214f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706306138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.706306138
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3627823235
Short name T877
Test name
Test status
Simulation time 241987170959 ps
CPU time 135.51 seconds
Started Mar 03 01:26:52 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199712 kb
Host smart-e757f4aa-424f-4eff-9eb8-561e3730a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627823235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3627823235
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2485684948
Short name T783
Test name
Test status
Simulation time 19692259902 ps
CPU time 34.45 seconds
Started Mar 03 01:26:50 PM PST 24
Finished Mar 03 01:27:25 PM PST 24
Peak memory 198748 kb
Host smart-a86228dc-b052-4ba5-8220-6511cdfa9b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485684948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2485684948
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3236954558
Short name T379
Test name
Test status
Simulation time 122014416763 ps
CPU time 135.17 seconds
Started Mar 03 01:26:50 PM PST 24
Finished Mar 03 01:29:06 PM PST 24
Peak memory 199340 kb
Host smart-75bd6dd4-3ff1-4cb5-b5e6-67c6b8b95f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236954558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3236954558
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.4108520244
Short name T856
Test name
Test status
Simulation time 500692796145 ps
CPU time 340.85 seconds
Started Mar 03 01:26:56 PM PST 24
Finished Mar 03 01:32:38 PM PST 24
Peak memory 199556 kb
Host smart-fed4021f-f83c-4a47-a2ff-ac2bbdfc731d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108520244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4108520244
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2270938124
Short name T957
Test name
Test status
Simulation time 77060850388 ps
CPU time 185.96 seconds
Started Mar 03 01:26:55 PM PST 24
Finished Mar 03 01:30:02 PM PST 24
Peak memory 199760 kb
Host smart-ccdd33a7-4edb-45bf-a0f8-7070cc26ee68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270938124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2270938124
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1315157847
Short name T1056
Test name
Test status
Simulation time 9436204668 ps
CPU time 6.51 seconds
Started Mar 03 01:26:56 PM PST 24
Finished Mar 03 01:27:04 PM PST 24
Peak memory 198036 kb
Host smart-186ef791-111d-4d82-8d99-0af700865852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315157847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1315157847
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2396827118
Short name T1031
Test name
Test status
Simulation time 21638880954 ps
CPU time 42.49 seconds
Started Mar 03 01:26:56 PM PST 24
Finished Mar 03 01:27:39 PM PST 24
Peak memory 198236 kb
Host smart-21382a9d-74d9-4375-9fac-500f8efbd2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396827118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2396827118
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2235806157
Short name T176
Test name
Test status
Simulation time 35418633939 ps
CPU time 326.49 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:32:24 PM PST 24
Peak memory 199628 kb
Host smart-062de96d-295f-4148-b680-a814b0dd00ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235806157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2235806157
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1360389964
Short name T612
Test name
Test status
Simulation time 159841663 ps
CPU time 1.29 seconds
Started Mar 03 01:26:56 PM PST 24
Finished Mar 03 01:26:58 PM PST 24
Peak memory 197644 kb
Host smart-15d04266-01ad-4180-88d7-a779facc7092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360389964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1360389964
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2956166389
Short name T266
Test name
Test status
Simulation time 32068372362 ps
CPU time 26.77 seconds
Started Mar 03 01:26:58 PM PST 24
Finished Mar 03 01:27:25 PM PST 24
Peak memory 199424 kb
Host smart-78c664b1-ddf7-4933-9b1c-7b5888b496c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956166389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2956166389
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.4275390954
Short name T479
Test name
Test status
Simulation time 4223475207 ps
CPU time 1.64 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:26:59 PM PST 24
Peak memory 195648 kb
Host smart-460b4114-be4d-4f8b-985f-571ebf0d5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275390954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4275390954
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3590531344
Short name T559
Test name
Test status
Simulation time 264994241 ps
CPU time 1.29 seconds
Started Mar 03 01:26:55 PM PST 24
Finished Mar 03 01:26:57 PM PST 24
Peak memory 197932 kb
Host smart-49df1012-119d-4b95-b177-d5bda3cf9af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590531344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3590531344
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.296246676
Short name T124
Test name
Test status
Simulation time 866363958475 ps
CPU time 373.16 seconds
Started Mar 03 01:26:55 PM PST 24
Finished Mar 03 01:33:10 PM PST 24
Peak memory 199604 kb
Host smart-b579c24b-f0cf-4765-943b-430e1079f894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296246676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.296246676
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1481368770
Short name T488
Test name
Test status
Simulation time 7250523112 ps
CPU time 11.54 seconds
Started Mar 03 01:27:01 PM PST 24
Finished Mar 03 01:27:12 PM PST 24
Peak memory 199172 kb
Host smart-935476e8-f6e8-43de-9543-2e0270f343ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481368770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1481368770
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1993211417
Short name T138
Test name
Test status
Simulation time 28119148353 ps
CPU time 39.41 seconds
Started Mar 03 01:26:51 PM PST 24
Finished Mar 03 01:27:33 PM PST 24
Peak memory 199684 kb
Host smart-8f625b7a-f169-478c-a6dd-4952c5bf1b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993211417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1993211417
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1267784424
Short name T696
Test name
Test status
Simulation time 22372288 ps
CPU time 0.57 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:22:58 PM PST 24
Peak memory 194184 kb
Host smart-c19effbb-e02b-41bb-86a7-24aec8d6cd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267784424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1267784424
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2481864479
Short name T803
Test name
Test status
Simulation time 152107859493 ps
CPU time 224.47 seconds
Started Mar 03 01:22:50 PM PST 24
Finished Mar 03 01:26:35 PM PST 24
Peak memory 199760 kb
Host smart-29c51633-e8f5-4b3c-a3b4-b2b9c48d8275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481864479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2481864479
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1246784927
Short name T1079
Test name
Test status
Simulation time 359195294503 ps
CPU time 365.7 seconds
Started Mar 03 01:22:51 PM PST 24
Finished Mar 03 01:28:57 PM PST 24
Peak memory 199740 kb
Host smart-5d9d5864-cc64-4c70-a8ce-5194a9a6c1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246784927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1246784927
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1509649153
Short name T1039
Test name
Test status
Simulation time 20705889821 ps
CPU time 31.36 seconds
Started Mar 03 01:22:50 PM PST 24
Finished Mar 03 01:23:22 PM PST 24
Peak memory 199632 kb
Host smart-0c32a1f1-116b-4d9e-9545-f1a0264b44d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509649153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1509649153
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.301486465
Short name T980
Test name
Test status
Simulation time 54215906261 ps
CPU time 44.25 seconds
Started Mar 03 01:22:51 PM PST 24
Finished Mar 03 01:23:35 PM PST 24
Peak memory 196768 kb
Host smart-6a62eadb-94e0-4c81-a8c5-b4b3d88b3820
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301486465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.301486465
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1840337346
Short name T875
Test name
Test status
Simulation time 125021692881 ps
CPU time 121.24 seconds
Started Mar 03 01:22:54 PM PST 24
Finished Mar 03 01:24:55 PM PST 24
Peak memory 199696 kb
Host smart-54bb3b1d-90b1-4f6f-b67c-25003cb97e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840337346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1840337346
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2155911317
Short name T1099
Test name
Test status
Simulation time 10054402705 ps
CPU time 21.54 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:23:11 PM PST 24
Peak memory 199340 kb
Host smart-dd47a8b1-bf7c-433c-8e17-33173a94189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155911317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2155911317
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1054629272
Short name T735
Test name
Test status
Simulation time 121893636465 ps
CPU time 76.51 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:24:06 PM PST 24
Peak memory 199612 kb
Host smart-f52e601b-7973-44d5-900a-1b265de2009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054629272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1054629272
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3688553450
Short name T518
Test name
Test status
Simulation time 18983147810 ps
CPU time 248.79 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:26:57 PM PST 24
Peak memory 199604 kb
Host smart-6dd049fe-c2b6-4e6d-b72e-7c6692a6fe3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688553450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3688553450
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.827439650
Short name T670
Test name
Test status
Simulation time 685569683 ps
CPU time 4.79 seconds
Started Mar 03 01:22:48 PM PST 24
Finished Mar 03 01:22:53 PM PST 24
Peak memory 197868 kb
Host smart-c9d793bf-99d1-460f-b9f9-f2aa912f6fa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827439650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.827439650
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2547922819
Short name T703
Test name
Test status
Simulation time 106362012504 ps
CPU time 19.57 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:23:09 PM PST 24
Peak memory 197356 kb
Host smart-8da93c10-c7f7-4d0d-aae0-f827afed8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547922819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2547922819
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2110403546
Short name T755
Test name
Test status
Simulation time 2913005266 ps
CPU time 1.78 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:22:51 PM PST 24
Peak memory 195232 kb
Host smart-f80e5bab-8dce-4361-8ca7-820cba1030cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110403546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2110403546
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3945750341
Short name T101
Test name
Test status
Simulation time 274509829 ps
CPU time 0.76 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:03 PM PST 24
Peak memory 216932 kb
Host smart-b2836652-b9e5-4765-95a0-c676754c23e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945750341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3945750341
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3257161341
Short name T1012
Test name
Test status
Simulation time 694546437 ps
CPU time 1.56 seconds
Started Mar 03 01:22:51 PM PST 24
Finished Mar 03 01:22:52 PM PST 24
Peak memory 197520 kb
Host smart-78d48a5d-30a3-4df0-a726-666541122299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257161341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3257161341
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1395102542
Short name T717
Test name
Test status
Simulation time 168795065366 ps
CPU time 78.49 seconds
Started Mar 03 01:22:56 PM PST 24
Finished Mar 03 01:24:15 PM PST 24
Peak memory 199732 kb
Host smart-56438c36-326c-4bc5-94cc-92b5ac9cc3a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395102542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1395102542
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3592418187
Short name T427
Test name
Test status
Simulation time 192282918766 ps
CPU time 877.03 seconds
Started Mar 03 01:22:59 PM PST 24
Finished Mar 03 01:37:36 PM PST 24
Peak memory 213340 kb
Host smart-c7f8637d-9d6e-4f3a-946e-6cd9983e6665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592418187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3592418187
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2920612744
Short name T468
Test name
Test status
Simulation time 836673681 ps
CPU time 2.64 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:22:52 PM PST 24
Peak memory 197628 kb
Host smart-d0695a6f-a83b-4b3f-9163-da89a5f9d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920612744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2920612744
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.246814016
Short name T1057
Test name
Test status
Simulation time 278488722114 ps
CPU time 31.21 seconds
Started Mar 03 01:22:49 PM PST 24
Finished Mar 03 01:23:20 PM PST 24
Peak memory 199724 kb
Host smart-f76d44f9-a23a-41f5-9c89-62e412123d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246814016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.246814016
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2851917490
Short name T874
Test name
Test status
Simulation time 45651836 ps
CPU time 0.58 seconds
Started Mar 03 01:27:04 PM PST 24
Finished Mar 03 01:27:05 PM PST 24
Peak memory 195268 kb
Host smart-9d5e45a1-a39e-434d-8e6c-0476e9e01b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851917490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2851917490
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2250016981
Short name T375
Test name
Test status
Simulation time 34394702616 ps
CPU time 29.79 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:27:27 PM PST 24
Peak memory 199336 kb
Host smart-200f1827-1b34-4973-928a-0489f80834d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250016981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2250016981
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.128199969
Short name T554
Test name
Test status
Simulation time 25573329287 ps
CPU time 27.91 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:27:25 PM PST 24
Peak memory 199580 kb
Host smart-9555d766-bbf5-43e4-a44e-0052863493d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128199969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.128199969
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.343763453
Short name T978
Test name
Test status
Simulation time 697688891489 ps
CPU time 496.45 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:35:14 PM PST 24
Peak memory 199740 kb
Host smart-06089c72-aa1e-4828-a760-56031987b8e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343763453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.343763453
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3387687300
Short name T995
Test name
Test status
Simulation time 99718829402 ps
CPU time 218.54 seconds
Started Mar 03 01:27:08 PM PST 24
Finished Mar 03 01:30:46 PM PST 24
Peak memory 199636 kb
Host smart-a291fbbf-a908-4409-ba19-fada644a5f39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387687300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3387687300
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_noise_filter.831590302
Short name T119
Test name
Test status
Simulation time 1626457164 ps
CPU time 1.51 seconds
Started Mar 03 01:27:01 PM PST 24
Finished Mar 03 01:27:02 PM PST 24
Peak memory 194072 kb
Host smart-ccd86430-c07a-4ac3-a20a-8934d4a57943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831590302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.831590302
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3497221769
Short name T923
Test name
Test status
Simulation time 17062775807 ps
CPU time 221.27 seconds
Started Mar 03 01:27:04 PM PST 24
Finished Mar 03 01:30:45 PM PST 24
Peak memory 199520 kb
Host smart-2f9da5e4-7c1e-4743-83c9-b8d13c81ac11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497221769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3497221769
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3196340973
Short name T901
Test name
Test status
Simulation time 2052351736 ps
CPU time 6.84 seconds
Started Mar 03 01:26:56 PM PST 24
Finished Mar 03 01:27:04 PM PST 24
Peak memory 197684 kb
Host smart-dfe81c6a-f2bd-42ae-97c5-5f0b2c617d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196340973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3196340973
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3023169129
Short name T974
Test name
Test status
Simulation time 138220120846 ps
CPU time 232.9 seconds
Started Mar 03 01:27:05 PM PST 24
Finished Mar 03 01:30:58 PM PST 24
Peak memory 199640 kb
Host smart-0981c7e2-a36e-47b5-b9dc-e141e87aa14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023169129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3023169129
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1506959866
Short name T931
Test name
Test status
Simulation time 33121245285 ps
CPU time 14.96 seconds
Started Mar 03 01:27:05 PM PST 24
Finished Mar 03 01:27:20 PM PST 24
Peak memory 195252 kb
Host smart-6c8e7219-478b-40ea-beb2-e57d0be49037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506959866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1506959866
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.4028020439
Short name T540
Test name
Test status
Simulation time 469554871 ps
CPU time 1.92 seconds
Started Mar 03 01:26:57 PM PST 24
Finished Mar 03 01:26:59 PM PST 24
Peak memory 198804 kb
Host smart-07c7968e-1c01-415d-a828-d546867721fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028020439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.4028020439
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4212661683
Short name T446
Test name
Test status
Simulation time 72597650249 ps
CPU time 220.05 seconds
Started Mar 03 01:27:06 PM PST 24
Finished Mar 03 01:30:46 PM PST 24
Peak memory 200224 kb
Host smart-1380d119-02dd-423f-89c0-c084e85605eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212661683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4212661683
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2749609088
Short name T523
Test name
Test status
Simulation time 8254253641 ps
CPU time 12.07 seconds
Started Mar 03 01:27:05 PM PST 24
Finished Mar 03 01:27:17 PM PST 24
Peak memory 198612 kb
Host smart-97d213cf-011d-4824-9799-c6bbc471ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749609088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2749609088
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1922621056
Short name T393
Test name
Test status
Simulation time 70116216297 ps
CPU time 59.67 seconds
Started Mar 03 01:26:55 PM PST 24
Finished Mar 03 01:27:56 PM PST 24
Peak memory 199628 kb
Host smart-152c2a6d-2ea0-44fd-be98-b30e8dd403e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922621056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1922621056
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3523527055
Short name T985
Test name
Test status
Simulation time 23001528 ps
CPU time 0.56 seconds
Started Mar 03 01:27:13 PM PST 24
Finished Mar 03 01:27:14 PM PST 24
Peak memory 195200 kb
Host smart-1e32dee9-dcce-43d8-9e88-d3f2f1c30ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523527055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3523527055
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2423689622
Short name T906
Test name
Test status
Simulation time 204657372124 ps
CPU time 202.09 seconds
Started Mar 03 01:27:04 PM PST 24
Finished Mar 03 01:30:26 PM PST 24
Peak memory 199712 kb
Host smart-1c9564fa-382b-4db9-8b5f-7532b1583299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423689622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2423689622
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2544768869
Short name T579
Test name
Test status
Simulation time 181606796502 ps
CPU time 49.42 seconds
Started Mar 03 01:27:06 PM PST 24
Finished Mar 03 01:27:55 PM PST 24
Peak memory 199696 kb
Host smart-f8911883-6d07-482d-b16f-8f6d293a041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544768869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2544768869
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.678347364
Short name T118
Test name
Test status
Simulation time 11898388666 ps
CPU time 17.29 seconds
Started Mar 03 01:27:13 PM PST 24
Finished Mar 03 01:27:30 PM PST 24
Peak memory 195588 kb
Host smart-3c47dace-e4d3-460c-8734-5c219e9821e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678347364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.678347364
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3740738888
Short name T936
Test name
Test status
Simulation time 73471903932 ps
CPU time 180.79 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:30:13 PM PST 24
Peak memory 199712 kb
Host smart-b2f9c948-a063-45dd-ba1a-b51b43685042
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740738888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3740738888
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.496507328
Short name T863
Test name
Test status
Simulation time 2015931040 ps
CPU time 1.26 seconds
Started Mar 03 01:27:15 PM PST 24
Finished Mar 03 01:27:16 PM PST 24
Peak memory 197852 kb
Host smart-6939995f-4b27-47fc-a8a9-de0b359daa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496507328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.496507328
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3732129703
Short name T74
Test name
Test status
Simulation time 62522113836 ps
CPU time 110.51 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:29:03 PM PST 24
Peak memory 197296 kb
Host smart-baa54b5c-6313-40a0-9699-d16d59cc4f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732129703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3732129703
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3605940548
Short name T911
Test name
Test status
Simulation time 28669617959 ps
CPU time 757.57 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:39:49 PM PST 24
Peak memory 199676 kb
Host smart-6daf7824-a011-4891-9201-b2d926250d1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605940548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3605940548
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.803755135
Short name T578
Test name
Test status
Simulation time 156389525460 ps
CPU time 320.29 seconds
Started Mar 03 01:27:10 PM PST 24
Finished Mar 03 01:32:31 PM PST 24
Peak memory 199648 kb
Host smart-b8e38577-9c5c-416d-bb00-fb438c007447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803755135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.803755135
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4288989257
Short name T1100
Test name
Test status
Simulation time 27530600845 ps
CPU time 2.73 seconds
Started Mar 03 01:27:14 PM PST 24
Finished Mar 03 01:27:17 PM PST 24
Peak memory 195256 kb
Host smart-c4c80efa-b9ea-4209-87a6-426ee93152fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288989257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4288989257
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4163173723
Short name T619
Test name
Test status
Simulation time 6252219345 ps
CPU time 18.49 seconds
Started Mar 03 01:27:04 PM PST 24
Finished Mar 03 01:27:23 PM PST 24
Peak memory 199588 kb
Host smart-06558c60-4659-4a8a-914f-3be2ba1abd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163173723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4163173723
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.794511710
Short name T790
Test name
Test status
Simulation time 7338947086 ps
CPU time 10.96 seconds
Started Mar 03 01:27:16 PM PST 24
Finished Mar 03 01:27:27 PM PST 24
Peak memory 199024 kb
Host smart-c1163442-5764-4bd2-84cf-288f58df881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794511710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.794511710
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2944260076
Short name T398
Test name
Test status
Simulation time 216070874389 ps
CPU time 89.93 seconds
Started Mar 03 01:27:05 PM PST 24
Finished Mar 03 01:28:35 PM PST 24
Peak memory 199756 kb
Host smart-2170a81f-5af1-4690-838f-e54346861587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944260076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2944260076
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1793399554
Short name T876
Test name
Test status
Simulation time 22576301 ps
CPU time 0.57 seconds
Started Mar 03 01:27:14 PM PST 24
Finished Mar 03 01:27:15 PM PST 24
Peak memory 195224 kb
Host smart-c858aea4-9349-469a-8b43-c1c2c269888b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793399554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1793399554
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.929341191
Short name T621
Test name
Test status
Simulation time 139232604090 ps
CPU time 336.28 seconds
Started Mar 03 01:27:13 PM PST 24
Finished Mar 03 01:32:49 PM PST 24
Peak memory 199664 kb
Host smart-fba416aa-7d52-4613-b9e4-4948c3a00290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929341191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.929341191
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3991315300
Short name T308
Test name
Test status
Simulation time 82163984281 ps
CPU time 38.13 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:49 PM PST 24
Peak memory 199568 kb
Host smart-a661dcfd-f290-4af0-9f8b-eca9b114fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991315300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3991315300
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3020205189
Short name T776
Test name
Test status
Simulation time 7679946940 ps
CPU time 11.28 seconds
Started Mar 03 01:27:15 PM PST 24
Finished Mar 03 01:27:27 PM PST 24
Peak memory 199664 kb
Host smart-55daa34b-6f73-48c1-9343-c284665f7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020205189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3020205189
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2187237791
Short name T486
Test name
Test status
Simulation time 605258190260 ps
CPU time 1480.45 seconds
Started Mar 03 01:27:13 PM PST 24
Finished Mar 03 01:51:53 PM PST 24
Peak memory 199700 kb
Host smart-7d19f16a-41f6-4859-8387-37c4882c9fcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187237791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2187237791
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.753353304
Short name T663
Test name
Test status
Simulation time 99937433636 ps
CPU time 476.67 seconds
Started Mar 03 01:27:15 PM PST 24
Finished Mar 03 01:35:12 PM PST 24
Peak memory 199700 kb
Host smart-02f142e2-bfaa-4e26-a087-d6dde47ba766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753353304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.753353304
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3888758258
Short name T463
Test name
Test status
Simulation time 1097822304 ps
CPU time 1.18 seconds
Started Mar 03 01:27:14 PM PST 24
Finished Mar 03 01:27:15 PM PST 24
Peak memory 196136 kb
Host smart-109f4224-f356-4ae0-9344-00fd93f307e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888758258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3888758258
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3796412919
Short name T627
Test name
Test status
Simulation time 37782475519 ps
CPU time 16.53 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:28 PM PST 24
Peak memory 198280 kb
Host smart-2c34d5a2-24c2-4ffc-92dd-c664432230dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796412919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3796412919
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1002347296
Short name T299
Test name
Test status
Simulation time 11600228302 ps
CPU time 557.8 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:36:30 PM PST 24
Peak memory 199704 kb
Host smart-2ba65eec-b9b5-4e08-8766-8a9e43d213c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002347296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1002347296
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.963856801
Short name T451
Test name
Test status
Simulation time 2533711950 ps
CPU time 6.85 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:18 PM PST 24
Peak memory 198216 kb
Host smart-da73b5d6-2498-4586-b2a7-71fe589ba34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963856801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.963856801
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1084193844
Short name T369
Test name
Test status
Simulation time 21386983832 ps
CPU time 17.6 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:29 PM PST 24
Peak memory 198224 kb
Host smart-818c1aae-d650-481c-a7bb-0b56d4347978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084193844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1084193844
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1076280453
Short name T425
Test name
Test status
Simulation time 2380009384 ps
CPU time 0.93 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:12 PM PST 24
Peak memory 195252 kb
Host smart-dc1b2bd1-a221-45de-b639-e585e8279782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076280453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1076280453
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4003057200
Short name T914
Test name
Test status
Simulation time 674183530 ps
CPU time 1.87 seconds
Started Mar 03 01:27:16 PM PST 24
Finished Mar 03 01:27:18 PM PST 24
Peak memory 199552 kb
Host smart-515f5476-fb00-483b-984f-b1dfa2533918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003057200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4003057200
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3210854218
Short name T115
Test name
Test status
Simulation time 335136779598 ps
CPU time 845.72 seconds
Started Mar 03 01:27:15 PM PST 24
Finished Mar 03 01:41:21 PM PST 24
Peak memory 216000 kb
Host smart-ffef2ce0-0dbc-4a61-b7a7-ae4fad8b9b59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210854218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3210854218
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1992269032
Short name T546
Test name
Test status
Simulation time 1184352123 ps
CPU time 3.71 seconds
Started Mar 03 01:27:13 PM PST 24
Finished Mar 03 01:27:17 PM PST 24
Peak memory 198156 kb
Host smart-709a7a10-941e-4c7d-b56f-c435c6cbdb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992269032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1992269032
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.425095038
Short name T969
Test name
Test status
Simulation time 35041163858 ps
CPU time 31.78 seconds
Started Mar 03 01:27:11 PM PST 24
Finished Mar 03 01:27:43 PM PST 24
Peak memory 199620 kb
Host smart-0f629e03-9975-48f4-a83d-a7f144d88794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425095038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.425095038
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.4044157383
Short name T650
Test name
Test status
Simulation time 17435384 ps
CPU time 0.55 seconds
Started Mar 03 01:27:27 PM PST 24
Finished Mar 03 01:27:28 PM PST 24
Peak memory 194276 kb
Host smart-4e580031-156f-49b6-8015-940ce779aadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044157383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.4044157383
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4279060921
Short name T412
Test name
Test status
Simulation time 188468395679 ps
CPU time 306.51 seconds
Started Mar 03 01:27:17 PM PST 24
Finished Mar 03 01:32:24 PM PST 24
Peak memory 199684 kb
Host smart-f550ba9b-30ec-42a2-aa5f-d40d6622d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279060921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4279060921
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.893616219
Short name T565
Test name
Test status
Simulation time 24568580296 ps
CPU time 39.64 seconds
Started Mar 03 01:27:18 PM PST 24
Finished Mar 03 01:27:58 PM PST 24
Peak memory 199636 kb
Host smart-106e3da9-9d0d-48c3-9483-21e9e8041cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893616219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.893616219
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.865980577
Short name T952
Test name
Test status
Simulation time 52125537161 ps
CPU time 21.35 seconds
Started Mar 03 01:27:28 PM PST 24
Finished Mar 03 01:27:50 PM PST 24
Peak memory 199592 kb
Host smart-6aba1ce8-257c-466b-9264-00fd669d7afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865980577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.865980577
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1735714812
Short name T678
Test name
Test status
Simulation time 657098092202 ps
CPU time 967.6 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 01:43:40 PM PST 24
Peak memory 198968 kb
Host smart-ac0e6e57-ff1d-4a5f-821b-adb821bab07a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735714812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1735714812
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_loopback.3979599498
Short name T501
Test name
Test status
Simulation time 9556981642 ps
CPU time 6.96 seconds
Started Mar 03 01:27:22 PM PST 24
Finished Mar 03 01:27:29 PM PST 24
Peak memory 198780 kb
Host smart-a1fda1e3-6ded-491e-94cc-e87b8105c36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979599498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3979599498
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.540913534
Short name T869
Test name
Test status
Simulation time 138102635763 ps
CPU time 75.34 seconds
Started Mar 03 01:27:27 PM PST 24
Finished Mar 03 01:28:43 PM PST 24
Peak memory 199764 kb
Host smart-fc3b2bcc-62cb-44e3-ae59-dee73ee856d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540913534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.540913534
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.4283508328
Short name T48
Test name
Test status
Simulation time 13829752904 ps
CPU time 753.29 seconds
Started Mar 03 01:27:18 PM PST 24
Finished Mar 03 01:39:52 PM PST 24
Peak memory 199752 kb
Host smart-18b5e2f1-6733-40a0-8dfc-52ca299c58c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283508328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4283508328
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.135616687
Short name T737
Test name
Test status
Simulation time 1849629643 ps
CPU time 2.74 seconds
Started Mar 03 01:27:27 PM PST 24
Finished Mar 03 01:27:30 PM PST 24
Peak memory 197864 kb
Host smart-3a2d61d5-5834-4593-86b1-25cba4f05129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135616687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.135616687
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1065109055
Short name T524
Test name
Test status
Simulation time 9178849088 ps
CPU time 16.78 seconds
Started Mar 03 01:27:28 PM PST 24
Finished Mar 03 01:27:45 PM PST 24
Peak memory 199668 kb
Host smart-4d2194b6-b680-4bc4-bd3b-e84db2a948be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065109055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1065109055
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3602394173
Short name T942
Test name
Test status
Simulation time 27523866097 ps
CPU time 11.35 seconds
Started Mar 03 01:27:17 PM PST 24
Finished Mar 03 01:27:29 PM PST 24
Peak memory 195104 kb
Host smart-dd948f08-7662-4c88-9121-65d75eac17eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602394173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3602394173
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.404976911
Short name T420
Test name
Test status
Simulation time 6337056208 ps
CPU time 27.11 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:27:39 PM PST 24
Peak memory 199128 kb
Host smart-1d52f12c-b533-498d-8d26-6b9529fec9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404976911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.404976911
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.212804948
Short name T145
Test name
Test status
Simulation time 384257985289 ps
CPU time 771.66 seconds
Started Mar 03 01:27:27 PM PST 24
Finished Mar 03 01:40:19 PM PST 24
Peak memory 199612 kb
Host smart-8858b3f4-338b-49ac-a6fa-ff41bef44f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212804948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.212804948
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3535244393
Short name T682
Test name
Test status
Simulation time 1274697432 ps
CPU time 4.52 seconds
Started Mar 03 01:27:28 PM PST 24
Finished Mar 03 01:27:32 PM PST 24
Peak memory 198648 kb
Host smart-3a3ac035-0e33-4c37-9ef1-dd82dc3ee1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535244393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3535244393
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3871848308
Short name T1063
Test name
Test status
Simulation time 27297264732 ps
CPU time 56.13 seconds
Started Mar 03 01:27:12 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 199684 kb
Host smart-659fa703-d2d0-4b02-91a8-6b7a0290a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871848308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3871848308
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1475796183
Short name T499
Test name
Test status
Simulation time 11229323 ps
CPU time 0.56 seconds
Started Mar 03 01:27:33 PM PST 24
Finished Mar 03 01:27:33 PM PST 24
Peak memory 195196 kb
Host smart-6b2fe965-3717-46a9-841a-929df45bfbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475796183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1475796183
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1512131975
Short name T864
Test name
Test status
Simulation time 124804656924 ps
CPU time 261.43 seconds
Started Mar 03 01:27:20 PM PST 24
Finished Mar 03 01:31:42 PM PST 24
Peak memory 199544 kb
Host smart-30ddec55-563c-401c-be4e-b47d74caf64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512131975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1512131975
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3796370340
Short name T842
Test name
Test status
Simulation time 136537430239 ps
CPU time 116.38 seconds
Started Mar 03 01:27:24 PM PST 24
Finished Mar 03 01:29:21 PM PST 24
Peak memory 199696 kb
Host smart-82b31681-1bf0-4c9f-b0e5-43ff72a49fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796370340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3796370340
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.114158138
Short name T1002
Test name
Test status
Simulation time 68224634268 ps
CPU time 106.21 seconds
Started Mar 03 01:27:24 PM PST 24
Finished Mar 03 01:29:10 PM PST 24
Peak memory 199656 kb
Host smart-b775e004-7e32-41f2-a577-b52e128f424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114158138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.114158138
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1373616238
Short name T862
Test name
Test status
Simulation time 119292814674 ps
CPU time 94.82 seconds
Started Mar 03 01:27:25 PM PST 24
Finished Mar 03 01:29:00 PM PST 24
Peak memory 199656 kb
Host smart-674c3928-4d1d-4cc8-8deb-9313a27f4255
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373616238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1373616238
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3238458689
Short name T428
Test name
Test status
Simulation time 109895810131 ps
CPU time 478.94 seconds
Started Mar 03 01:27:24 PM PST 24
Finished Mar 03 01:35:23 PM PST 24
Peak memory 199708 kb
Host smart-4b23c032-2715-42be-a97b-bb517b338ae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238458689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3238458689
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2460840896
Short name T671
Test name
Test status
Simulation time 94765096790 ps
CPU time 21.46 seconds
Started Mar 03 01:27:24 PM PST 24
Finished Mar 03 01:27:46 PM PST 24
Peak memory 196528 kb
Host smart-c41c54b7-5e0b-4e74-ad28-19be94c1e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460840896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2460840896
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2878882380
Short name T528
Test name
Test status
Simulation time 8446285136 ps
CPU time 112.81 seconds
Started Mar 03 01:27:27 PM PST 24
Finished Mar 03 01:29:20 PM PST 24
Peak memory 199428 kb
Host smart-8eb35d3e-05f9-4f4d-9751-66d84652aaed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878882380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2878882380
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2660235007
Short name T1094
Test name
Test status
Simulation time 4339242398 ps
CPU time 32.09 seconds
Started Mar 03 01:27:24 PM PST 24
Finished Mar 03 01:27:57 PM PST 24
Peak memory 198644 kb
Host smart-f8bff7e9-58e4-43b8-a8dd-0049c840d530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660235007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2660235007
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4131365249
Short name T128
Test name
Test status
Simulation time 39796604486 ps
CPU time 73.68 seconds
Started Mar 03 01:27:26 PM PST 24
Finished Mar 03 01:28:40 PM PST 24
Peak memory 199660 kb
Host smart-460fdf96-e6ab-4acf-b795-9fd7ce11181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131365249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4131365249
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1055667863
Short name T608
Test name
Test status
Simulation time 28349019474 ps
CPU time 47.07 seconds
Started Mar 03 01:27:25 PM PST 24
Finished Mar 03 01:28:12 PM PST 24
Peak memory 195628 kb
Host smart-06bff9ee-e509-438f-baef-4b74c7d63046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055667863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1055667863
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4197536201
Short name T110
Test name
Test status
Simulation time 5884567271 ps
CPU time 9.68 seconds
Started Mar 03 01:27:17 PM PST 24
Finished Mar 03 01:27:26 PM PST 24
Peak memory 199580 kb
Host smart-b01701cd-c177-439b-9cff-5d5e3542a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197536201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4197536201
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3480980332
Short name T791
Test name
Test status
Simulation time 869563571089 ps
CPU time 2364.26 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 199700 kb
Host smart-31bf8a60-3851-4676-b6c1-08589110c441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480980332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3480980332
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3207321391
Short name T416
Test name
Test status
Simulation time 6759412534 ps
CPU time 21.26 seconds
Started Mar 03 01:27:25 PM PST 24
Finished Mar 03 01:27:46 PM PST 24
Peak memory 199332 kb
Host smart-7bb88541-e9ed-46ff-9649-4287da009d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207321391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3207321391
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3942786757
Short name T989
Test name
Test status
Simulation time 53743451307 ps
CPU time 43.35 seconds
Started Mar 03 01:27:21 PM PST 24
Finished Mar 03 01:28:05 PM PST 24
Peak memory 199544 kb
Host smart-7cdf2341-4973-4299-a920-9f4a14b1aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942786757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3942786757
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3040563499
Short name T674
Test name
Test status
Simulation time 24039405 ps
CPU time 0.52 seconds
Started Mar 03 01:27:39 PM PST 24
Finished Mar 03 01:27:39 PM PST 24
Peak memory 195136 kb
Host smart-b35217d2-c910-4d40-8c60-b152af884887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040563499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3040563499
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3050319653
Short name T657
Test name
Test status
Simulation time 352238779030 ps
CPU time 46.95 seconds
Started Mar 03 01:27:34 PM PST 24
Finished Mar 03 01:28:21 PM PST 24
Peak memory 199640 kb
Host smart-dc9187b1-b807-4dc6-894a-0f5246d02ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050319653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3050319653
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1741570588
Short name T36
Test name
Test status
Simulation time 62973659700 ps
CPU time 31.32 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 01:28:03 PM PST 24
Peak memory 199656 kb
Host smart-2112dbf3-4f2d-4a10-9da5-10469d9b1e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741570588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1741570588
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3689875113
Short name T738
Test name
Test status
Simulation time 601829150234 ps
CPU time 836.08 seconds
Started Mar 03 01:27:33 PM PST 24
Finished Mar 03 01:41:29 PM PST 24
Peak memory 199504 kb
Host smart-b64c4861-728b-49e1-b0fa-124211c10243
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689875113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3689875113
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3288445008
Short name T494
Test name
Test status
Simulation time 161386010729 ps
CPU time 183.51 seconds
Started Mar 03 01:27:41 PM PST 24
Finished Mar 03 01:30:45 PM PST 24
Peak memory 199700 kb
Host smart-595084ba-c080-44ce-aa34-074d4d403456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288445008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3288445008
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1191193893
Short name T22
Test name
Test status
Simulation time 1926817742 ps
CPU time 1.7 seconds
Started Mar 03 01:27:33 PM PST 24
Finished Mar 03 01:27:35 PM PST 24
Peak memory 196560 kb
Host smart-41564fd7-225c-41c2-89d7-a368ef1eb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191193893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1191193893
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4124940368
Short name T652
Test name
Test status
Simulation time 72676765443 ps
CPU time 124.65 seconds
Started Mar 03 01:27:30 PM PST 24
Finished Mar 03 01:29:35 PM PST 24
Peak memory 197532 kb
Host smart-6ac31d50-d96c-40d2-87bb-9cd2bc50d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124940368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4124940368
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1026704777
Short name T288
Test name
Test status
Simulation time 33515083470 ps
CPU time 354.56 seconds
Started Mar 03 01:27:41 PM PST 24
Finished Mar 03 01:33:36 PM PST 24
Peak memory 199580 kb
Host smart-f9a8ce73-7d82-4acb-952a-9497f9ed9087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026704777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1026704777
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3482260098
Short name T453
Test name
Test status
Simulation time 4762034465 ps
CPU time 17.99 seconds
Started Mar 03 01:27:31 PM PST 24
Finished Mar 03 01:27:49 PM PST 24
Peak memory 197936 kb
Host smart-4ff9106f-983a-4fe2-8c14-2fbe2546be72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482260098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3482260098
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4211427677
Short name T344
Test name
Test status
Simulation time 153958381388 ps
CPU time 117.39 seconds
Started Mar 03 01:27:31 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199092 kb
Host smart-bb37c140-6ab7-4b3e-b464-a53a8c61d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211427677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4211427677
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1116814672
Short name T474
Test name
Test status
Simulation time 2156950031 ps
CPU time 1.6 seconds
Started Mar 03 01:27:34 PM PST 24
Finished Mar 03 01:27:36 PM PST 24
Peak memory 195268 kb
Host smart-a36e2654-53e4-4ced-90b4-2e1f0b5d95c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116814672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1116814672
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2086390095
Short name T837
Test name
Test status
Simulation time 625873383 ps
CPU time 2.36 seconds
Started Mar 03 01:27:33 PM PST 24
Finished Mar 03 01:27:35 PM PST 24
Peak memory 197952 kb
Host smart-c031f335-b3a4-4a92-926b-f4b02fc66159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086390095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2086390095
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4276893857
Short name T634
Test name
Test status
Simulation time 183734006764 ps
CPU time 792.32 seconds
Started Mar 03 01:27:40 PM PST 24
Finished Mar 03 01:40:52 PM PST 24
Peak memory 199920 kb
Host smart-c0c9969d-e4f4-4b64-a1b9-f6ba308e0690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276893857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4276893857
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3188169700
Short name T1083
Test name
Test status
Simulation time 7239859957 ps
CPU time 12.8 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 01:27:45 PM PST 24
Peak memory 198556 kb
Host smart-9f4bee6c-e061-471f-9b57-1e520e1b87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188169700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3188169700
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2548071628
Short name T661
Test name
Test status
Simulation time 13237240164 ps
CPU time 5.96 seconds
Started Mar 03 01:27:32 PM PST 24
Finished Mar 03 01:27:38 PM PST 24
Peak memory 199628 kb
Host smart-52abc379-0e77-4f9d-ba06-bbf279930590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548071628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2548071628
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2232041682
Short name T1027
Test name
Test status
Simulation time 11233987 ps
CPU time 0.59 seconds
Started Mar 03 01:27:46 PM PST 24
Finished Mar 03 01:27:47 PM PST 24
Peak memory 195272 kb
Host smart-02951f26-db3a-4d24-9015-e510e15a3978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232041682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2232041682
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.242807799
Short name T721
Test name
Test status
Simulation time 160581408970 ps
CPU time 172.24 seconds
Started Mar 03 01:27:41 PM PST 24
Finished Mar 03 01:30:34 PM PST 24
Peak memory 199744 kb
Host smart-15846e59-7b46-46b8-8acd-7a5d9b647079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242807799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.242807799
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2783594802
Short name T196
Test name
Test status
Simulation time 14572713723 ps
CPU time 21.98 seconds
Started Mar 03 01:27:43 PM PST 24
Finished Mar 03 01:28:05 PM PST 24
Peak memory 199732 kb
Host smart-6d4014b5-826d-48f9-ac16-2e372990af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783594802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2783594802
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4266754572
Short name T971
Test name
Test status
Simulation time 140269357357 ps
CPU time 114.14 seconds
Started Mar 03 01:27:41 PM PST 24
Finished Mar 03 01:29:35 PM PST 24
Peak memory 199748 kb
Host smart-e7f193a8-2b5e-4f29-bfe3-bb8749c76baa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266754572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4266754572
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1986436179
Short name T400
Test name
Test status
Simulation time 55758963048 ps
CPU time 478.33 seconds
Started Mar 03 01:27:45 PM PST 24
Finished Mar 03 01:35:44 PM PST 24
Peak memory 199732 kb
Host smart-d90c3ef3-be92-4501-8133-507f1ed53a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986436179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1986436179
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2591309199
Short name T458
Test name
Test status
Simulation time 2599284633 ps
CPU time 5.02 seconds
Started Mar 03 01:27:49 PM PST 24
Finished Mar 03 01:27:54 PM PST 24
Peak memory 195540 kb
Host smart-33feb894-4083-42b1-9e06-d90f6889d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591309199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2591309199
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2181275608
Short name T41
Test name
Test status
Simulation time 24819690030 ps
CPU time 20.73 seconds
Started Mar 03 01:27:48 PM PST 24
Finished Mar 03 01:28:09 PM PST 24
Peak memory 197496 kb
Host smart-4aeabd2c-297a-46b6-b909-65d6fbd75f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181275608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2181275608
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.22934912
Short name T1053
Test name
Test status
Simulation time 11649939138 ps
CPU time 181.93 seconds
Started Mar 03 01:27:49 PM PST 24
Finished Mar 03 01:30:51 PM PST 24
Peak memory 199728 kb
Host smart-28ca9df3-1cb2-415b-91e5-d37b9b6bbbdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22934912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.22934912
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1540846504
Short name T654
Test name
Test status
Simulation time 686903438 ps
CPU time 7.96 seconds
Started Mar 03 01:27:41 PM PST 24
Finished Mar 03 01:27:50 PM PST 24
Peak memory 197452 kb
Host smart-bf3ed3d5-48c5-48bc-aed0-efb510316df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540846504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1540846504
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1397749472
Short name T848
Test name
Test status
Simulation time 40750726583 ps
CPU time 33.85 seconds
Started Mar 03 01:27:46 PM PST 24
Finished Mar 03 01:28:20 PM PST 24
Peak memory 199680 kb
Host smart-4eba50fb-2579-4eab-a3f5-639f934da426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397749472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1397749472
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3083636609
Short name T917
Test name
Test status
Simulation time 46447519371 ps
CPU time 9.63 seconds
Started Mar 03 01:27:48 PM PST 24
Finished Mar 03 01:27:58 PM PST 24
Peak memory 195272 kb
Host smart-531b827a-c488-4ead-90d1-5dc7435a6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083636609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3083636609
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.196341132
Short name T538
Test name
Test status
Simulation time 461575607 ps
CPU time 1.78 seconds
Started Mar 03 01:27:40 PM PST 24
Finished Mar 03 01:27:42 PM PST 24
Peak memory 197944 kb
Host smart-e6484770-9616-4627-b500-c27ad4294e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196341132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.196341132
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1472503190
Short name T537
Test name
Test status
Simulation time 74681565376 ps
CPU time 97.63 seconds
Started Mar 03 01:27:46 PM PST 24
Finished Mar 03 01:29:23 PM PST 24
Peak memory 199700 kb
Host smart-0ff5bc19-b9af-42e2-ae1d-0f5b2a2176b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472503190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1472503190
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3900264779
Short name T111
Test name
Test status
Simulation time 6177624036 ps
CPU time 14.91 seconds
Started Mar 03 01:27:50 PM PST 24
Finished Mar 03 01:28:05 PM PST 24
Peak memory 198992 kb
Host smart-9ccffc66-34c3-4fa0-863e-d7dfd08fc06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900264779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3900264779
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2762331001
Short name T905
Test name
Test status
Simulation time 114034025642 ps
CPU time 45.71 seconds
Started Mar 03 01:27:42 PM PST 24
Finished Mar 03 01:28:28 PM PST 24
Peak memory 199676 kb
Host smart-d866ab65-d082-45a2-8cd0-20fbd56c6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762331001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2762331001
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1013268790
Short name T949
Test name
Test status
Simulation time 17386467 ps
CPU time 0.57 seconds
Started Mar 03 01:27:54 PM PST 24
Finished Mar 03 01:27:54 PM PST 24
Peak memory 195280 kb
Host smart-1e527ed1-3140-470a-9b0f-c261010bdbdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013268790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1013268790
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1999218452
Short name T774
Test name
Test status
Simulation time 35729235446 ps
CPU time 28.26 seconds
Started Mar 03 01:27:44 PM PST 24
Finished Mar 03 01:28:13 PM PST 24
Peak memory 199108 kb
Host smart-06e0fdcb-09e6-4aa6-9662-372f647d8e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999218452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1999218452
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1941478155
Short name T282
Test name
Test status
Simulation time 92252236334 ps
CPU time 19.73 seconds
Started Mar 03 01:27:52 PM PST 24
Finished Mar 03 01:28:13 PM PST 24
Peak memory 199712 kb
Host smart-cd0765a6-8b9f-4bdb-9899-a4f043df2d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941478155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1941478155
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1501125171
Short name T894
Test name
Test status
Simulation time 2026163132698 ps
CPU time 1431.41 seconds
Started Mar 03 01:27:55 PM PST 24
Finished Mar 03 01:51:47 PM PST 24
Peak memory 199664 kb
Host smart-de1c0525-d58a-47f5-b6c8-6a8b6be97a63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501125171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1501125171
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2577617422
Short name T541
Test name
Test status
Simulation time 289019701142 ps
CPU time 324.46 seconds
Started Mar 03 01:27:52 PM PST 24
Finished Mar 03 01:33:17 PM PST 24
Peak memory 199720 kb
Host smart-d6dda898-ed73-4cb1-896b-d03688edfcf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577617422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2577617422
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1928153221
Short name T893
Test name
Test status
Simulation time 13226323785 ps
CPU time 8.28 seconds
Started Mar 03 01:27:55 PM PST 24
Finished Mar 03 01:28:03 PM PST 24
Peak memory 198704 kb
Host smart-cb07fc4c-8cdd-4bb9-9138-db9cc5469b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928153221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1928153221
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2581643173
Short name T968
Test name
Test status
Simulation time 25896995982 ps
CPU time 37.21 seconds
Started Mar 03 01:27:55 PM PST 24
Finished Mar 03 01:28:33 PM PST 24
Peak memory 196792 kb
Host smart-bea4b69a-5531-431f-878e-475b8e084e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581643173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2581643173
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3127282194
Short name T795
Test name
Test status
Simulation time 7432774577 ps
CPU time 437.15 seconds
Started Mar 03 01:27:53 PM PST 24
Finished Mar 03 01:35:11 PM PST 24
Peak memory 199656 kb
Host smart-88a8bd2f-445f-4d27-8ce8-6d781f1bae83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127282194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3127282194
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4220291825
Short name T1038
Test name
Test status
Simulation time 300097633471 ps
CPU time 75.16 seconds
Started Mar 03 01:27:52 PM PST 24
Finished Mar 03 01:29:08 PM PST 24
Peak memory 199432 kb
Host smart-8dae501a-4d1f-4e05-a026-1960fdf4e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220291825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4220291825
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1918392671
Short name T418
Test name
Test status
Simulation time 467743349 ps
CPU time 1.37 seconds
Started Mar 03 01:27:54 PM PST 24
Finished Mar 03 01:27:55 PM PST 24
Peak memory 195204 kb
Host smart-3e28422e-d165-4969-ac92-bde291a342ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918392671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1918392671
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3768691535
Short name T664
Test name
Test status
Simulation time 725870059 ps
CPU time 1.65 seconds
Started Mar 03 01:27:46 PM PST 24
Finished Mar 03 01:27:47 PM PST 24
Peak memory 198212 kb
Host smart-c1bae81c-77e0-4fc6-b82f-3574d6e175bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768691535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3768691535
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1742293883
Short name T150
Test name
Test status
Simulation time 505146510071 ps
CPU time 816.44 seconds
Started Mar 03 01:27:52 PM PST 24
Finished Mar 03 01:41:28 PM PST 24
Peak memory 208440 kb
Host smart-39664813-68d9-4b28-92ee-b069c6d87376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742293883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1742293883
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2145398792
Short name T899
Test name
Test status
Simulation time 6587379280 ps
CPU time 35.53 seconds
Started Mar 03 01:27:55 PM PST 24
Finished Mar 03 01:28:31 PM PST 24
Peak memory 199056 kb
Host smart-0debfba6-c871-48c5-8f02-db4216e94b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145398792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2145398792
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1807292757
Short name T920
Test name
Test status
Simulation time 22967926891 ps
CPU time 34.3 seconds
Started Mar 03 01:27:45 PM PST 24
Finished Mar 03 01:28:19 PM PST 24
Peak memory 199644 kb
Host smart-1bc4bbba-55c0-401e-b7d4-007b5f0a2eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807292757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1807292757
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1646306030
Short name T892
Test name
Test status
Simulation time 33896705 ps
CPU time 0.57 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 195156 kb
Host smart-9d1522bf-b18f-4f1c-9fc3-3de80f947584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646306030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1646306030
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.287384968
Short name T838
Test name
Test status
Simulation time 137860013924 ps
CPU time 64.79 seconds
Started Mar 03 01:27:59 PM PST 24
Finished Mar 03 01:29:04 PM PST 24
Peak memory 199704 kb
Host smart-6dddcba6-b603-4cf7-93ea-c218f42fbd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287384968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.287384968
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2558413121
Short name T109
Test name
Test status
Simulation time 29700392063 ps
CPU time 33.46 seconds
Started Mar 03 01:28:01 PM PST 24
Finished Mar 03 01:28:35 PM PST 24
Peak memory 198796 kb
Host smart-af18e10a-412c-4cfb-95c2-0a75ea9d55b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558413121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2558413121
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1409101443
Short name T46
Test name
Test status
Simulation time 9987669817 ps
CPU time 15.77 seconds
Started Mar 03 01:28:03 PM PST 24
Finished Mar 03 01:28:19 PM PST 24
Peak memory 197984 kb
Host smart-00b0db73-760f-4579-9307-cdfbd8baa2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409101443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1409101443
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.94636943
Short name T723
Test name
Test status
Simulation time 144901961868 ps
CPU time 268.36 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:32:35 PM PST 24
Peak memory 199628 kb
Host smart-303e5602-5e73-4093-8598-a0e44c11293b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94636943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.94636943
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3654005440
Short name T679
Test name
Test status
Simulation time 91372016 ps
CPU time 0.62 seconds
Started Mar 03 01:28:01 PM PST 24
Finished Mar 03 01:28:01 PM PST 24
Peak memory 195280 kb
Host smart-8d6c2b88-4040-4bcd-ba8a-11fa88721df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654005440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3654005440
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.785046630
Short name T772
Test name
Test status
Simulation time 86810036246 ps
CPU time 69.04 seconds
Started Mar 03 01:28:00 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199832 kb
Host smart-2b11ef04-f471-40c7-977e-53f2537f39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785046630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.785046630
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2924295991
Short name T977
Test name
Test status
Simulation time 24882934279 ps
CPU time 691.6 seconds
Started Mar 03 01:27:58 PM PST 24
Finished Mar 03 01:39:30 PM PST 24
Peak memory 199696 kb
Host smart-f9166376-6547-4a6d-bacc-0814159e1511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924295991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2924295991
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.40580582
Short name T10
Test name
Test status
Simulation time 21925129688 ps
CPU time 63.4 seconds
Started Mar 03 01:27:58 PM PST 24
Finished Mar 03 01:29:02 PM PST 24
Peak memory 199624 kb
Host smart-13246358-cdf1-46e6-8b5f-cfda42803d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40580582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.40580582
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1162657094
Short name T1088
Test name
Test status
Simulation time 4078140137 ps
CPU time 7.79 seconds
Started Mar 03 01:28:03 PM PST 24
Finished Mar 03 01:28:11 PM PST 24
Peak memory 195496 kb
Host smart-c42e9714-37a5-44b4-b545-60dab4da4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162657094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1162657094
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.428535771
Short name T681
Test name
Test status
Simulation time 11558341507 ps
CPU time 21.94 seconds
Started Mar 03 01:28:01 PM PST 24
Finished Mar 03 01:28:23 PM PST 24
Peak memory 199292 kb
Host smart-8226ed13-89f3-4ae8-bf96-677dd65077fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428535771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.428535771
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.294076946
Short name T1064
Test name
Test status
Simulation time 318800415073 ps
CPU time 738.13 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:40:26 PM PST 24
Peak memory 208044 kb
Host smart-66bb1a53-302b-4c27-8df5-195de3fca0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294076946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.294076946
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4236421428
Short name T114
Test name
Test status
Simulation time 114604453107 ps
CPU time 333.76 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:33:41 PM PST 24
Peak memory 210360 kb
Host smart-20e8427e-65f7-4538-955f-af74705e5bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236421428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4236421428
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1675307631
Short name T904
Test name
Test status
Simulation time 13352706781 ps
CPU time 20.6 seconds
Started Mar 03 01:27:59 PM PST 24
Finished Mar 03 01:28:20 PM PST 24
Peak memory 199444 kb
Host smart-7b5de86f-ada1-4cd0-9f11-81e4ae3c1634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675307631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1675307631
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4240300811
Short name T561
Test name
Test status
Simulation time 92295900600 ps
CPU time 267.23 seconds
Started Mar 03 01:28:03 PM PST 24
Finished Mar 03 01:32:30 PM PST 24
Peak memory 199652 kb
Host smart-364947e9-decd-4ca8-8292-7fb5861e614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240300811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4240300811
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.662138160
Short name T948
Test name
Test status
Simulation time 13521846 ps
CPU time 0.57 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:28:08 PM PST 24
Peak memory 194328 kb
Host smart-4b57e322-f46b-4412-ba29-93262ca701c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662138160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.662138160
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4117950789
Short name T713
Test name
Test status
Simulation time 62697453823 ps
CPU time 25.78 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:28:33 PM PST 24
Peak memory 199640 kb
Host smart-9f41154b-0e60-423d-a7ad-88cccd9bd43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117950789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4117950789
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_intr.4129179101
Short name T1072
Test name
Test status
Simulation time 622069393217 ps
CPU time 309.43 seconds
Started Mar 03 01:28:05 PM PST 24
Finished Mar 03 01:33:14 PM PST 24
Peak memory 198096 kb
Host smart-695e9726-56eb-45bb-80b3-74451c1b4a09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129179101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4129179101
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1172497652
Short name T930
Test name
Test status
Simulation time 61838652944 ps
CPU time 205.08 seconds
Started Mar 03 01:28:05 PM PST 24
Finished Mar 03 01:31:30 PM PST 24
Peak memory 199608 kb
Host smart-da8cc38b-4293-46c3-8019-0e20390d4681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172497652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1172497652
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1724009862
Short name T921
Test name
Test status
Simulation time 3854440425 ps
CPU time 8.2 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:28:15 PM PST 24
Peak memory 198492 kb
Host smart-d69ae31e-3478-47cc-99dd-d3c92722fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724009862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1724009862
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3281254513
Short name T898
Test name
Test status
Simulation time 95753881515 ps
CPU time 35 seconds
Started Mar 03 01:28:05 PM PST 24
Finished Mar 03 01:28:40 PM PST 24
Peak memory 196552 kb
Host smart-15ceffdd-8ced-4b12-a24b-bf82ccc28424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281254513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3281254513
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.524408908
Short name T639
Test name
Test status
Simulation time 6685060792 ps
CPU time 181.56 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:31:09 PM PST 24
Peak memory 199676 kb
Host smart-b784d23b-7b5e-46e7-a036-ec7e47227bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524408908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.524408908
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2530826093
Short name T868
Test name
Test status
Simulation time 124581540225 ps
CPU time 46.53 seconds
Started Mar 03 01:28:09 PM PST 24
Finished Mar 03 01:28:55 PM PST 24
Peak memory 199676 kb
Host smart-5878d17e-917c-4523-b6c1-b94944dc43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530826093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2530826093
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2370946180
Short name T1061
Test name
Test status
Simulation time 4334579094 ps
CPU time 2.68 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:28:09 PM PST 24
Peak memory 195420 kb
Host smart-071c67d3-fd04-48d3-b850-e5f407b388cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370946180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2370946180
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2537007931
Short name T71
Test name
Test status
Simulation time 508878758 ps
CPU time 1.8 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:28:09 PM PST 24
Peak memory 197464 kb
Host smart-e2e2b2ca-852a-4ba6-bf60-71619f667a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537007931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2537007931
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2645911055
Short name T1042
Test name
Test status
Simulation time 149321860718 ps
CPU time 619.95 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:38:27 PM PST 24
Peak memory 199752 kb
Host smart-dc648f6a-aec4-4768-80d2-0515b2b97ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645911055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2645911055
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.667432850
Short name T447
Test name
Test status
Simulation time 16980624078 ps
CPU time 265.9 seconds
Started Mar 03 01:28:07 PM PST 24
Finished Mar 03 01:32:33 PM PST 24
Peak memory 215504 kb
Host smart-09e11183-dd5c-4d4a-8c24-6087e65388c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667432850 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.667432850
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2421007534
Short name T75
Test name
Test status
Simulation time 1286043696 ps
CPU time 1.36 seconds
Started Mar 03 01:28:09 PM PST 24
Finished Mar 03 01:28:11 PM PST 24
Peak memory 197536 kb
Host smart-cae543f1-d81d-4912-83c2-12e08aeb6f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421007534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2421007534
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1184951726
Short name T493
Test name
Test status
Simulation time 53325027669 ps
CPU time 16.82 seconds
Started Mar 03 01:28:06 PM PST 24
Finished Mar 03 01:28:23 PM PST 24
Peak memory 199616 kb
Host smart-602fa127-8e76-41f4-80fa-d97f9de35c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184951726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1184951726
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.94590040
Short name T512
Test name
Test status
Simulation time 12661757 ps
CPU time 0.56 seconds
Started Mar 03 01:22:58 PM PST 24
Finished Mar 03 01:22:59 PM PST 24
Peak memory 195064 kb
Host smart-baf4d0aa-562d-4763-b297-4c329956beac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94590040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.94590040
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1538070479
Short name T722
Test name
Test status
Simulation time 27863978107 ps
CPU time 40.81 seconds
Started Mar 03 01:22:58 PM PST 24
Finished Mar 03 01:23:39 PM PST 24
Peak memory 199688 kb
Host smart-3faa688a-bcd2-4ce6-8b37-534637aef1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538070479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1538070479
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3151261873
Short name T852
Test name
Test status
Simulation time 221549715208 ps
CPU time 81.01 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:24:18 PM PST 24
Peak memory 199596 kb
Host smart-8c8c53cb-95fe-4494-b891-b42e0b219be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151261873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3151261873
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3172390087
Short name T433
Test name
Test status
Simulation time 7862489941 ps
CPU time 14.99 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:23:13 PM PST 24
Peak memory 199540 kb
Host smart-3690b5ac-5121-426c-ae4a-61618dcf5c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172390087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3172390087
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2122769262
Short name T726
Test name
Test status
Simulation time 30583112785 ps
CPU time 11.46 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:23:08 PM PST 24
Peak memory 196308 kb
Host smart-48ee5a63-7db6-4930-b661-316b75959eed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122769262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2122769262
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1630741905
Short name T728
Test name
Test status
Simulation time 146510326256 ps
CPU time 366.2 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:29:03 PM PST 24
Peak memory 199680 kb
Host smart-385ce3a4-f0cb-43ff-8a68-5a1595de0498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630741905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1630741905
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1395572503
Short name T643
Test name
Test status
Simulation time 1118732739 ps
CPU time 2.49 seconds
Started Mar 03 01:22:55 PM PST 24
Finished Mar 03 01:22:58 PM PST 24
Peak memory 197728 kb
Host smart-7118afaf-4afb-4de4-b946-4f2c904781d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395572503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1395572503
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3094243190
Short name T1095
Test name
Test status
Simulation time 112583216664 ps
CPU time 95.92 seconds
Started Mar 03 01:22:55 PM PST 24
Finished Mar 03 01:24:31 PM PST 24
Peak memory 207916 kb
Host smart-b571c3f4-b41a-436d-8c98-041d90228d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094243190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3094243190
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4276466721
Short name T1013
Test name
Test status
Simulation time 28188258333 ps
CPU time 43.05 seconds
Started Mar 03 01:22:56 PM PST 24
Finished Mar 03 01:23:39 PM PST 24
Peak memory 199652 kb
Host smart-60fd4b13-a5b1-4527-ac50-d0677662448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276466721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4276466721
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4047384687
Short name T853
Test name
Test status
Simulation time 41713745990 ps
CPU time 35.06 seconds
Started Mar 03 01:22:56 PM PST 24
Finished Mar 03 01:23:31 PM PST 24
Peak memory 195608 kb
Host smart-fd994406-22f6-44f3-abe8-d126fe6a3e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047384687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4047384687
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2825374336
Short name T766
Test name
Test status
Simulation time 712184609 ps
CPU time 1.52 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:22:59 PM PST 24
Peak memory 197900 kb
Host smart-1a326d03-68c7-48b3-a155-9c8ed9ed8e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825374336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2825374336
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1087032494
Short name T56
Test name
Test status
Simulation time 29080054751 ps
CPU time 316.18 seconds
Started Mar 03 01:22:57 PM PST 24
Finished Mar 03 01:28:13 PM PST 24
Peak memory 215484 kb
Host smart-85c1969e-25a4-4020-abef-6b85ab8837ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087032494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1087032494
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3322339139
Short name T534
Test name
Test status
Simulation time 5080163206 ps
CPU time 2.17 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:05 PM PST 24
Peak memory 198356 kb
Host smart-36dee228-8320-43e4-8e91-32bd67b30214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322339139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3322339139
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4073734755
Short name T170
Test name
Test status
Simulation time 19320432947 ps
CPU time 18.35 seconds
Started Mar 03 01:22:56 PM PST 24
Finished Mar 03 01:23:14 PM PST 24
Peak memory 199664 kb
Host smart-6bc16668-88bc-4cc3-82ad-4bf197d87eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073734755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4073734755
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2992007796
Short name T771
Test name
Test status
Simulation time 19341853229 ps
CPU time 32.06 seconds
Started Mar 03 01:28:08 PM PST 24
Finished Mar 03 01:28:40 PM PST 24
Peak memory 199292 kb
Host smart-613c4c62-09f8-4579-82ce-7b8f4a01f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992007796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2992007796
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.175455666
Short name T1001
Test name
Test status
Simulation time 55216206206 ps
CPU time 12.86 seconds
Started Mar 03 01:28:13 PM PST 24
Finished Mar 03 01:28:26 PM PST 24
Peak memory 199648 kb
Host smart-4b8f4a00-534d-4ffa-832f-3fc2b3348caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175455666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.175455666
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1662230326
Short name T25
Test name
Test status
Simulation time 24680087103 ps
CPU time 224.83 seconds
Started Mar 03 01:28:13 PM PST 24
Finished Mar 03 01:31:58 PM PST 24
Peak memory 216048 kb
Host smart-4b35027e-6c36-4d2c-b0ca-e99b9c200ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662230326 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1662230326
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2711000915
Short name T711
Test name
Test status
Simulation time 46623948964 ps
CPU time 21.03 seconds
Started Mar 03 01:28:19 PM PST 24
Finished Mar 03 01:28:40 PM PST 24
Peak memory 199672 kb
Host smart-1155692f-b548-41d6-adc6-0abb14741851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711000915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2711000915
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2382592650
Short name T734
Test name
Test status
Simulation time 45705224960 ps
CPU time 235.14 seconds
Started Mar 03 01:28:19 PM PST 24
Finished Mar 03 01:32:15 PM PST 24
Peak memory 208016 kb
Host smart-88182b78-f1d2-442d-9bbf-8cb5fde83912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382592650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2382592650
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2537672248
Short name T330
Test name
Test status
Simulation time 51571963138 ps
CPU time 45.87 seconds
Started Mar 03 01:28:13 PM PST 24
Finished Mar 03 01:28:59 PM PST 24
Peak memory 199656 kb
Host smart-e638faa3-2015-46eb-840b-e19fc2334a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537672248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2537672248
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1705313240
Short name T1086
Test name
Test status
Simulation time 21797431042 ps
CPU time 30.61 seconds
Started Mar 03 01:28:13 PM PST 24
Finished Mar 03 01:28:44 PM PST 24
Peak memory 199696 kb
Host smart-3c9bccca-08a9-4c18-a5f8-0628e0ebe1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705313240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1705313240
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2189225172
Short name T3
Test name
Test status
Simulation time 23442196013 ps
CPU time 42.15 seconds
Started Mar 03 01:28:12 PM PST 24
Finished Mar 03 01:28:55 PM PST 24
Peak memory 199408 kb
Host smart-47264538-c215-40dc-96b5-b352bf63a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189225172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2189225172
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3058901112
Short name T120
Test name
Test status
Simulation time 42321833230 ps
CPU time 54.12 seconds
Started Mar 03 01:28:13 PM PST 24
Finished Mar 03 01:29:07 PM PST 24
Peak memory 199696 kb
Host smart-9dfef809-0a02-4f03-8974-6910e69f2e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058901112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3058901112
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1877309835
Short name T888
Test name
Test status
Simulation time 14129844469 ps
CPU time 12.28 seconds
Started Mar 03 01:28:14 PM PST 24
Finished Mar 03 01:28:27 PM PST 24
Peak memory 199700 kb
Host smart-f2e16865-44ad-442e-ab54-b193627c4ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877309835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1877309835
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1721589207
Short name T677
Test name
Test status
Simulation time 11503657 ps
CPU time 0.55 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:23:05 PM PST 24
Peak memory 194316 kb
Host smart-f8feebb8-6aad-4196-91cc-02915df3a366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721589207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1721589207
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1131399265
Short name T635
Test name
Test status
Simulation time 103852386290 ps
CPU time 149.07 seconds
Started Mar 03 01:23:00 PM PST 24
Finished Mar 03 01:25:29 PM PST 24
Peak memory 199216 kb
Host smart-45f0a6a7-a994-45d1-b150-9b37de7c1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131399265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1131399265
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1007479476
Short name T365
Test name
Test status
Simulation time 29376067396 ps
CPU time 26.09 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:28 PM PST 24
Peak memory 199668 kb
Host smart-457a4cf5-f137-4698-a775-6a9f29c7872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007479476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1007479476
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4181904099
Short name T648
Test name
Test status
Simulation time 630470779813 ps
CPU time 508.32 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:31:30 PM PST 24
Peak memory 199748 kb
Host smart-d1f76bcb-8582-465f-bc1a-e2c028b474a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181904099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4181904099
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_loopback.2499896772
Short name T52
Test name
Test status
Simulation time 8022202255 ps
CPU time 16.6 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:23:21 PM PST 24
Peak memory 198452 kb
Host smart-e4ef38b1-98d7-468b-af26-a4cb4d4c1e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499896772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2499896772
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4225305609
Short name T576
Test name
Test status
Simulation time 161145018195 ps
CPU time 74.49 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:24:20 PM PST 24
Peak memory 199704 kb
Host smart-b17ce93f-fc4f-4f51-8921-5258790b5fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225305609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4225305609
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4013509916
Short name T598
Test name
Test status
Simulation time 40597727621 ps
CPU time 245.19 seconds
Started Mar 03 01:23:03 PM PST 24
Finished Mar 03 01:27:08 PM PST 24
Peak memory 199732 kb
Host smart-4b6f0e21-4d77-410a-931c-4076a7dec3fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013509916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4013509916
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.164678815
Short name T805
Test name
Test status
Simulation time 2376850178 ps
CPU time 5 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:23:10 PM PST 24
Peak memory 198168 kb
Host smart-2d1f534c-2eee-4b65-a10f-5c6c48bd32c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164678815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.164678815
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2181010764
Short name T568
Test name
Test status
Simulation time 278117053556 ps
CPU time 130.27 seconds
Started Mar 03 01:23:03 PM PST 24
Finished Mar 03 01:25:13 PM PST 24
Peak memory 198968 kb
Host smart-0406216f-0121-4ea0-85e9-dc8cebccae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181010764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2181010764
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.146654117
Short name T560
Test name
Test status
Simulation time 33836802232 ps
CPU time 9.74 seconds
Started Mar 03 01:23:01 PM PST 24
Finished Mar 03 01:23:11 PM PST 24
Peak memory 195520 kb
Host smart-9ef94361-864c-44ab-95b7-bccab9dcc281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146654117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.146654117
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3325986126
Short name T860
Test name
Test status
Simulation time 770255882 ps
CPU time 1.58 seconds
Started Mar 03 01:22:55 PM PST 24
Finished Mar 03 01:22:57 PM PST 24
Peak memory 197624 kb
Host smart-3a05588c-eb6c-43bc-aca3-8ef42ede37b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325986126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3325986126
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1934113455
Short name T169
Test name
Test status
Simulation time 58526557793 ps
CPU time 68.1 seconds
Started Mar 03 01:23:01 PM PST 24
Finished Mar 03 01:24:09 PM PST 24
Peak memory 199704 kb
Host smart-c1e1e157-8c81-4f6c-82bb-985208c7bd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934113455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1934113455
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.839638619
Short name T830
Test name
Test status
Simulation time 9811084475 ps
CPU time 8.76 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:11 PM PST 24
Peak memory 199200 kb
Host smart-563ad6ee-a129-4a7c-9e77-66d0c22f1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839638619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.839638619
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2988652685
Short name T402
Test name
Test status
Simulation time 24600441396 ps
CPU time 41.28 seconds
Started Mar 03 01:22:59 PM PST 24
Finished Mar 03 01:23:40 PM PST 24
Peak memory 199668 kb
Host smart-cfa88ef6-6396-445e-a162-1e680fabcba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988652685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2988652685
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1984005944
Short name T200
Test name
Test status
Simulation time 37570416750 ps
CPU time 17.19 seconds
Started Mar 03 01:28:20 PM PST 24
Finished Mar 03 01:28:38 PM PST 24
Peak memory 198964 kb
Host smart-afd0831c-12b4-48f9-84d8-334baed651ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984005944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1984005944
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1403232369
Short name T973
Test name
Test status
Simulation time 248749627578 ps
CPU time 85.14 seconds
Started Mar 03 01:28:19 PM PST 24
Finished Mar 03 01:29:45 PM PST 24
Peak memory 199620 kb
Host smart-91475fb0-b982-49cb-b3e2-e6c2fb340baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403232369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1403232369
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1558560579
Short name T970
Test name
Test status
Simulation time 7593006051 ps
CPU time 13.19 seconds
Started Mar 03 01:28:19 PM PST 24
Finished Mar 03 01:28:33 PM PST 24
Peak memory 198960 kb
Host smart-1a0db97b-b0bc-4285-8879-cd92de302c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558560579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1558560579
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2228972792
Short name T141
Test name
Test status
Simulation time 17848403579 ps
CPU time 24.21 seconds
Started Mar 03 01:28:20 PM PST 24
Finished Mar 03 01:28:46 PM PST 24
Peak memory 198232 kb
Host smart-4c9e9180-973c-462f-a3cd-6605413fd7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228972792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2228972792
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2325177860
Short name T72
Test name
Test status
Simulation time 18368729313 ps
CPU time 8.52 seconds
Started Mar 03 01:28:27 PM PST 24
Finished Mar 03 01:28:37 PM PST 24
Peak memory 199656 kb
Host smart-ac3d27be-a24f-4bac-905e-3cc1210e2797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325177860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2325177860
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.871970262
Short name T32
Test name
Test status
Simulation time 31138526477 ps
CPU time 363.19 seconds
Started Mar 03 01:28:25 PM PST 24
Finished Mar 03 01:34:30 PM PST 24
Peak memory 216116 kb
Host smart-a8155eb8-8f7b-4b3d-9e27-388f257f277e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871970262 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.871970262
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3400693452
Short name T315
Test name
Test status
Simulation time 7787049308 ps
CPU time 16.15 seconds
Started Mar 03 01:28:26 PM PST 24
Finished Mar 03 01:28:44 PM PST 24
Peak memory 199604 kb
Host smart-dda3477c-e338-499a-a5ae-2a6e3a8e0c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400693452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3400693452
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3243123524
Short name T214
Test name
Test status
Simulation time 28038421650 ps
CPU time 16.91 seconds
Started Mar 03 01:28:26 PM PST 24
Finished Mar 03 01:28:45 PM PST 24
Peak memory 198960 kb
Host smart-6dd605ee-d6e0-424d-b03c-f43fafec3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243123524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3243123524
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.715063104
Short name T331
Test name
Test status
Simulation time 10165174657 ps
CPU time 5.61 seconds
Started Mar 03 01:28:24 PM PST 24
Finished Mar 03 01:28:31 PM PST 24
Peak memory 199344 kb
Host smart-52dbcd1d-5ca7-4732-83e4-a9e22ba41bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715063104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.715063104
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1719634975
Short name T191
Test name
Test status
Simulation time 28985228386 ps
CPU time 52.11 seconds
Started Mar 03 01:28:26 PM PST 24
Finished Mar 03 01:29:20 PM PST 24
Peak memory 199592 kb
Host smart-10064e4c-d9b3-4d80-9be6-86dcd485d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719634975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1719634975
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2322213872
Short name T54
Test name
Test status
Simulation time 70091771112 ps
CPU time 348.92 seconds
Started Mar 03 01:28:27 PM PST 24
Finished Mar 03 01:34:18 PM PST 24
Peak memory 215984 kb
Host smart-558f96af-36f4-4428-8002-c47bc91f53af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322213872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2322213872
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.864488736
Short name T857
Test name
Test status
Simulation time 34729783 ps
CPU time 0.57 seconds
Started Mar 03 01:23:11 PM PST 24
Finished Mar 03 01:23:12 PM PST 24
Peak memory 194244 kb
Host smart-4da856ea-1b0d-477d-a116-d52bd6fbfeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864488736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.864488736
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1754466048
Short name T624
Test name
Test status
Simulation time 42522880225 ps
CPU time 78.95 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:24:24 PM PST 24
Peak memory 199748 kb
Host smart-f7cf6d44-9527-4d2f-97a2-8e7890f9983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754466048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1754466048
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1164017442
Short name T710
Test name
Test status
Simulation time 53021026465 ps
CPU time 20.94 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:23:26 PM PST 24
Peak memory 198660 kb
Host smart-55d94044-2f3b-4f85-af85-08f1b474b14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164017442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1164017442
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3607514326
Short name T356
Test name
Test status
Simulation time 49299150196 ps
CPU time 14.27 seconds
Started Mar 03 01:23:03 PM PST 24
Finished Mar 03 01:23:18 PM PST 24
Peak memory 199648 kb
Host smart-ebc516d8-9ce5-4a65-805c-b6bae8d216a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607514326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3607514326
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1272838684
Short name T879
Test name
Test status
Simulation time 159882469400 ps
CPU time 43.73 seconds
Started Mar 03 01:23:05 PM PST 24
Finished Mar 03 01:23:49 PM PST 24
Peak memory 199748 kb
Host smart-80c91855-ed8a-4b30-9f4d-c7dddc32574a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272838684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1272838684
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3394484135
Short name T480
Test name
Test status
Simulation time 51067449357 ps
CPU time 245.75 seconds
Started Mar 03 01:23:09 PM PST 24
Finished Mar 03 01:27:14 PM PST 24
Peak memory 199688 kb
Host smart-37f52efe-e61e-4ae7-bccc-8cedf142ab0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394484135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3394484135
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.837597966
Short name T641
Test name
Test status
Simulation time 3628058407 ps
CPU time 4.35 seconds
Started Mar 03 01:23:09 PM PST 24
Finished Mar 03 01:23:13 PM PST 24
Peak memory 198152 kb
Host smart-30a7910c-d8c9-46a3-ac21-b237cac918a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837597966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.837597966
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2409372493
Short name T907
Test name
Test status
Simulation time 24728589215 ps
CPU time 46.25 seconds
Started Mar 03 01:23:12 PM PST 24
Finished Mar 03 01:23:59 PM PST 24
Peak memory 198304 kb
Host smart-fb00d757-d331-4160-9dee-9df9d562a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409372493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2409372493
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3207208633
Short name T20
Test name
Test status
Simulation time 2921745443 ps
CPU time 13.47 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:15 PM PST 24
Peak memory 197660 kb
Host smart-b9a774f2-cc48-408b-83da-57678b8c92f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207208633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3207208633
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1340244940
Short name T1068
Test name
Test status
Simulation time 137294843482 ps
CPU time 360.71 seconds
Started Mar 03 01:23:08 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199700 kb
Host smart-51843006-7447-4cfe-92f6-cd8e02e18176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340244940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1340244940
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1145446492
Short name T503
Test name
Test status
Simulation time 4513945997 ps
CPU time 1.65 seconds
Started Mar 03 01:23:09 PM PST 24
Finished Mar 03 01:23:11 PM PST 24
Peak memory 195468 kb
Host smart-b929825c-d853-40a8-8d72-4ea77b155b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145446492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1145446492
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4067215903
Short name T697
Test name
Test status
Simulation time 776733283 ps
CPU time 1.29 seconds
Started Mar 03 01:23:03 PM PST 24
Finished Mar 03 01:23:04 PM PST 24
Peak memory 198596 kb
Host smart-e54874f3-28d8-43dd-af78-f96f0e0d931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067215903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4067215903
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3166803865
Short name T1102
Test name
Test status
Simulation time 1886676705634 ps
CPU time 1591.6 seconds
Started Mar 03 01:23:09 PM PST 24
Finished Mar 03 01:49:40 PM PST 24
Peak memory 199764 kb
Host smart-61407e69-481a-437f-bc32-38c438309274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166803865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3166803865
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4053020805
Short name T626
Test name
Test status
Simulation time 7576571164 ps
CPU time 12.84 seconds
Started Mar 03 01:23:10 PM PST 24
Finished Mar 03 01:23:23 PM PST 24
Peak memory 199116 kb
Host smart-908aaf4e-b5cb-4940-a8a1-2a071b89f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053020805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4053020805
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.4229605310
Short name T794
Test name
Test status
Simulation time 32613813297 ps
CPU time 15.67 seconds
Started Mar 03 01:23:02 PM PST 24
Finished Mar 03 01:23:18 PM PST 24
Peak memory 199680 kb
Host smart-9499a842-6264-49b3-90cf-b71726bd9765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229605310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4229605310
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.484521158
Short name T932
Test name
Test status
Simulation time 205927007418 ps
CPU time 304.28 seconds
Started Mar 03 01:28:26 PM PST 24
Finished Mar 03 01:33:32 PM PST 24
Peak memory 199680 kb
Host smart-50e410d6-c8e6-47dc-8882-d2e17d4a6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484521158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.484521158
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3149321726
Short name T269
Test name
Test status
Simulation time 32873751435 ps
CPU time 59.04 seconds
Started Mar 03 01:28:27 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199544 kb
Host smart-ca2c1fd6-303c-4dd2-a5a5-882efe120d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149321726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3149321726
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.828594146
Short name T450
Test name
Test status
Simulation time 32844800185 ps
CPU time 386.9 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:35:01 PM PST 24
Peak memory 212812 kb
Host smart-fa7ed659-48b9-4299-98b3-f1b9690d9cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828594146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.828594146
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2687063808
Short name T752
Test name
Test status
Simulation time 110541904591 ps
CPU time 61.66 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:29:36 PM PST 24
Peak memory 199760 kb
Host smart-29ed2696-cf2e-4972-aa7a-1047c5206bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687063808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2687063808
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2031760870
Short name T241
Test name
Test status
Simulation time 172754305426 ps
CPU time 279.37 seconds
Started Mar 03 01:28:33 PM PST 24
Finished Mar 03 01:33:13 PM PST 24
Peak memory 199596 kb
Host smart-85a70474-4ec7-48e8-a8bf-e428aecc4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031760870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2031760870
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.4053537509
Short name T1016
Test name
Test status
Simulation time 53308434423 ps
CPU time 161.18 seconds
Started Mar 03 01:28:33 PM PST 24
Finished Mar 03 01:31:14 PM PST 24
Peak memory 199536 kb
Host smart-5f8dc68f-a907-4bab-9763-b3aa5c4c0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053537509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4053537509
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1402783571
Short name T937
Test name
Test status
Simulation time 47679454663 ps
CPU time 70.86 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:29:45 PM PST 24
Peak memory 199656 kb
Host smart-b4422923-ed05-42f1-bf59-c89122c28b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402783571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1402783571
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1873064513
Short name T174
Test name
Test status
Simulation time 17354305684 ps
CPU time 38.24 seconds
Started Mar 03 01:28:32 PM PST 24
Finished Mar 03 01:29:10 PM PST 24
Peak memory 199620 kb
Host smart-d6f5ab88-0f7a-43b0-8bc6-af8c7f1fb968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873064513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1873064513
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.684083139
Short name T351
Test name
Test status
Simulation time 6673669050 ps
CPU time 6.63 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:28:41 PM PST 24
Peak memory 199644 kb
Host smart-f99c02cb-58d8-4a0b-b7c6-b1ab549c6bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684083139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.684083139
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.696884101
Short name T788
Test name
Test status
Simulation time 20723805117 ps
CPU time 41.95 seconds
Started Mar 03 01:28:33 PM PST 24
Finished Mar 03 01:29:15 PM PST 24
Peak memory 199664 kb
Host smart-f845d45d-6b6a-4eca-b4a3-720e273295a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696884101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.696884101
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1068152264
Short name T502
Test name
Test status
Simulation time 37420153 ps
CPU time 0.57 seconds
Started Mar 03 01:23:22 PM PST 24
Finished Mar 03 01:23:22 PM PST 24
Peak memory 194120 kb
Host smart-7ab06cbb-e4ae-450a-8eeb-3531a46ef1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068152264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1068152264
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3432723438
Short name T431
Test name
Test status
Simulation time 91000036708 ps
CPU time 147.6 seconds
Started Mar 03 01:23:08 PM PST 24
Finished Mar 03 01:25:36 PM PST 24
Peak memory 199708 kb
Host smart-6cf4d5b4-2cf6-42b0-8c35-fe142b52cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432723438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3432723438
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3512752314
Short name T242
Test name
Test status
Simulation time 29536807847 ps
CPU time 13.64 seconds
Started Mar 03 01:23:16 PM PST 24
Finished Mar 03 01:23:29 PM PST 24
Peak memory 198100 kb
Host smart-bb961ebf-5267-4f11-9291-986fbdf22c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512752314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3512752314
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.15586139
Short name T644
Test name
Test status
Simulation time 110413938412 ps
CPU time 44.75 seconds
Started Mar 03 01:23:15 PM PST 24
Finished Mar 03 01:23:59 PM PST 24
Peak memory 199748 kb
Host smart-85576637-f31a-4cb8-b69b-a9d1a6e1f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15586139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.15586139
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3402861137
Short name T1055
Test name
Test status
Simulation time 496765169909 ps
CPU time 186.56 seconds
Started Mar 03 01:23:17 PM PST 24
Finished Mar 03 01:26:24 PM PST 24
Peak memory 199296 kb
Host smart-7bf1caf5-745b-4c5e-9962-ecd23cde2c4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402861137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3402861137
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.75161017
Short name T1037
Test name
Test status
Simulation time 98796882149 ps
CPU time 579.04 seconds
Started Mar 03 01:23:15 PM PST 24
Finished Mar 03 01:32:54 PM PST 24
Peak memory 199680 kb
Host smart-74b4f774-5623-42c5-8b46-00dd396c97a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75161017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.75161017
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1190772932
Short name T631
Test name
Test status
Simulation time 5223206552 ps
CPU time 5.47 seconds
Started Mar 03 01:23:17 PM PST 24
Finished Mar 03 01:23:23 PM PST 24
Peak memory 198796 kb
Host smart-f7e9ef24-63ad-4ced-b991-8925771aedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190772932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1190772932
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.4023504800
Short name T409
Test name
Test status
Simulation time 99474405153 ps
CPU time 63.63 seconds
Started Mar 03 01:23:14 PM PST 24
Finished Mar 03 01:24:18 PM PST 24
Peak memory 199808 kb
Host smart-089105d8-b0f7-47bc-902e-d2746390c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023504800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4023504800
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3141662509
Short name T1028
Test name
Test status
Simulation time 25439186377 ps
CPU time 1237.41 seconds
Started Mar 03 01:23:19 PM PST 24
Finished Mar 03 01:43:57 PM PST 24
Peak memory 199752 kb
Host smart-f45c3adf-4c07-4e54-93db-31f979c6bd3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141662509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3141662509
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2481411899
Short name T1036
Test name
Test status
Simulation time 2349018756 ps
CPU time 6.74 seconds
Started Mar 03 01:23:18 PM PST 24
Finished Mar 03 01:23:25 PM PST 24
Peak memory 198248 kb
Host smart-bd15b871-8dae-4fcd-8d9e-e721e0a0c730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481411899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2481411899
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3797816476
Short name T373
Test name
Test status
Simulation time 44346133805 ps
CPU time 67.3 seconds
Started Mar 03 01:23:17 PM PST 24
Finished Mar 03 01:24:25 PM PST 24
Peak memory 199660 kb
Host smart-f885f749-d47f-4f66-b2c8-4858cd62d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797816476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3797816476
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.553042082
Short name T526
Test name
Test status
Simulation time 4738136033 ps
CPU time 2.88 seconds
Started Mar 03 01:23:20 PM PST 24
Finished Mar 03 01:23:23 PM PST 24
Peak memory 195528 kb
Host smart-099d0460-8b5d-409a-a514-dbb636c626cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553042082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.553042082
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.591614316
Short name T814
Test name
Test status
Simulation time 864157188 ps
CPU time 1.78 seconds
Started Mar 03 01:23:09 PM PST 24
Finished Mar 03 01:23:11 PM PST 24
Peak memory 197492 kb
Host smart-8c4904e3-4786-4d1f-8d84-ba599c8bfadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591614316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.591614316
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2429748490
Short name T123
Test name
Test status
Simulation time 151488909406 ps
CPU time 120.56 seconds
Started Mar 03 01:23:22 PM PST 24
Finished Mar 03 01:25:23 PM PST 24
Peak memory 199360 kb
Host smart-6ea4ea26-4131-4694-a4e5-fbe706815877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429748490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2429748490
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2948568881
Short name T646
Test name
Test status
Simulation time 1471390192 ps
CPU time 2.44 seconds
Started Mar 03 01:23:15 PM PST 24
Finished Mar 03 01:23:18 PM PST 24
Peak memory 197792 kb
Host smart-2d0b39bb-cf39-43fe-bb5b-d95eb4e97520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948568881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2948568881
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2687280646
Short name T959
Test name
Test status
Simulation time 91915145884 ps
CPU time 69.27 seconds
Started Mar 03 01:23:11 PM PST 24
Finished Mar 03 01:24:21 PM PST 24
Peak memory 199672 kb
Host smart-199a612a-ab60-4828-a43c-f2cc991c6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687280646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2687280646
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4212640256
Short name T960
Test name
Test status
Simulation time 182296497674 ps
CPU time 311.13 seconds
Started Mar 03 01:28:38 PM PST 24
Finished Mar 03 01:33:50 PM PST 24
Peak memory 199712 kb
Host smart-7003825f-3f97-4e50-9ae2-2189481d68ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212640256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4212640256
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1851018831
Short name T51
Test name
Test status
Simulation time 117374948508 ps
CPU time 50.39 seconds
Started Mar 03 01:28:34 PM PST 24
Finished Mar 03 01:29:25 PM PST 24
Peak memory 199444 kb
Host smart-5e44f902-9856-4a5d-8748-6e80fa91f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851018831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1851018831
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1223864418
Short name T313
Test name
Test status
Simulation time 26433866004 ps
CPU time 46.29 seconds
Started Mar 03 01:28:42 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 199620 kb
Host smart-5fc0247f-b144-4eb4-aa59-fdc41a1eb495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223864418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1223864418
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.706419940
Short name T276
Test name
Test status
Simulation time 12975354347 ps
CPU time 23.99 seconds
Started Mar 03 01:28:42 PM PST 24
Finished Mar 03 01:29:06 PM PST 24
Peak memory 199432 kb
Host smart-c2cb0fc3-889b-424b-a3f9-c983da0f010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706419940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.706419940
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3386351621
Short name T33
Test name
Test status
Simulation time 12758000239 ps
CPU time 115.34 seconds
Started Mar 03 01:28:40 PM PST 24
Finished Mar 03 01:30:35 PM PST 24
Peak memory 208156 kb
Host smart-fcdc3a7e-1bd8-479f-a156-49a1528a94ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386351621 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3386351621
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2619361573
Short name T753
Test name
Test status
Simulation time 138949045894 ps
CPU time 62.77 seconds
Started Mar 03 01:28:41 PM PST 24
Finished Mar 03 01:29:44 PM PST 24
Peak memory 199372 kb
Host smart-1c4870b0-d630-4f65-b744-485bb8ed7e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619361573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2619361573
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2453546847
Short name T796
Test name
Test status
Simulation time 97943865089 ps
CPU time 27.08 seconds
Started Mar 03 01:28:41 PM PST 24
Finished Mar 03 01:29:09 PM PST 24
Peak memory 199672 kb
Host smart-f18aafc7-01ae-4463-872b-b7ab1ffbf283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453546847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2453546847
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1175519444
Short name T979
Test name
Test status
Simulation time 97279173913 ps
CPU time 31.13 seconds
Started Mar 03 01:28:43 PM PST 24
Finished Mar 03 01:29:14 PM PST 24
Peak memory 199740 kb
Host smart-61694d9e-9a22-41b3-9024-2210d616123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175519444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1175519444
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4132932910
Short name T1051
Test name
Test status
Simulation time 111314021624 ps
CPU time 158.02 seconds
Started Mar 03 01:28:42 PM PST 24
Finished Mar 03 01:31:21 PM PST 24
Peak memory 199620 kb
Host smart-c6847457-6f3c-447f-8720-0ffb4466f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132932910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4132932910
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2932306139
Short name T193
Test name
Test status
Simulation time 51252562239 ps
CPU time 90.24 seconds
Started Mar 03 01:28:49 PM PST 24
Finished Mar 03 01:30:19 PM PST 24
Peak memory 199428 kb
Host smart-4552c668-80b7-45d5-a078-187638bf86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932306139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2932306139
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1350223479
Short name T181
Test name
Test status
Simulation time 61616127884 ps
CPU time 18.38 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:29:08 PM PST 24
Peak memory 199640 kb
Host smart-cd41b121-8aa4-434d-a014-4d0d261ac282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350223479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1350223479
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4145387884
Short name T475
Test name
Test status
Simulation time 15844317 ps
CPU time 0.61 seconds
Started Mar 03 01:23:34 PM PST 24
Finished Mar 03 01:23:35 PM PST 24
Peak memory 195260 kb
Host smart-6e538b62-da5b-49a3-bb40-93e1253fe4d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145387884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4145387884
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3936626855
Short name T397
Test name
Test status
Simulation time 132832123387 ps
CPU time 197.61 seconds
Started Mar 03 01:23:21 PM PST 24
Finished Mar 03 01:26:38 PM PST 24
Peak memory 199496 kb
Host smart-47519fdd-283e-4b8a-8863-6ba8e298ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936626855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3936626855
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3007134748
Short name T13
Test name
Test status
Simulation time 120569616603 ps
CPU time 187.88 seconds
Started Mar 03 01:23:21 PM PST 24
Finished Mar 03 01:26:29 PM PST 24
Peak memory 199608 kb
Host smart-b3f547fc-d507-459d-8a32-3020e5f770e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007134748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3007134748
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2084020441
Short name T1044
Test name
Test status
Simulation time 63749990969 ps
CPU time 49.99 seconds
Started Mar 03 01:23:23 PM PST 24
Finished Mar 03 01:24:13 PM PST 24
Peak memory 199528 kb
Host smart-1153c245-b9a1-4cc5-9d38-3db935ccbacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084020441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2084020441
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.425648333
Short name T616
Test name
Test status
Simulation time 258221657702 ps
CPU time 184.62 seconds
Started Mar 03 01:23:22 PM PST 24
Finished Mar 03 01:26:26 PM PST 24
Peak memory 199308 kb
Host smart-888552da-e773-4182-9f06-d51b1c898884
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425648333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.425648333
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_loopback.177904012
Short name T891
Test name
Test status
Simulation time 3821843449 ps
CPU time 1.15 seconds
Started Mar 03 01:23:28 PM PST 24
Finished Mar 03 01:23:30 PM PST 24
Peak memory 195468 kb
Host smart-9f283ab7-6d9d-4f65-b716-8961a4aa6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177904012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.177904012
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1456111399
Short name T148
Test name
Test status
Simulation time 85829056885 ps
CPU time 77.77 seconds
Started Mar 03 01:23:23 PM PST 24
Finished Mar 03 01:24:41 PM PST 24
Peak memory 198680 kb
Host smart-81c9f410-b5a4-4093-8547-1d2cb631aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456111399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1456111399
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1365824231
Short name T840
Test name
Test status
Simulation time 7436698615 ps
CPU time 447.72 seconds
Started Mar 03 01:23:34 PM PST 24
Finished Mar 03 01:31:03 PM PST 24
Peak memory 199680 kb
Host smart-48faaa9e-6ddc-4af3-add4-828491bf84c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365824231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1365824231
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.847125816
Short name T636
Test name
Test status
Simulation time 2654538958 ps
CPU time 9.6 seconds
Started Mar 03 01:23:26 PM PST 24
Finished Mar 03 01:23:36 PM PST 24
Peak memory 198296 kb
Host smart-caac3d9c-e2d0-43f4-a4f3-d71a30bbe3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=847125816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.847125816
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3674899361
Short name T843
Test name
Test status
Simulation time 14723443818 ps
CPU time 21.04 seconds
Started Mar 03 01:23:30 PM PST 24
Finished Mar 03 01:23:51 PM PST 24
Peak memory 199628 kb
Host smart-fc07b234-694e-4054-a700-9990f5c9f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674899361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3674899361
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1994853749
Short name T742
Test name
Test status
Simulation time 4087492832 ps
CPU time 6.16 seconds
Started Mar 03 01:23:23 PM PST 24
Finished Mar 03 01:23:29 PM PST 24
Peak memory 195412 kb
Host smart-c966df4d-1637-4803-8b3f-2a8d89db3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994853749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1994853749
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.818227569
Short name T593
Test name
Test status
Simulation time 276017241 ps
CPU time 1.6 seconds
Started Mar 03 01:23:23 PM PST 24
Finished Mar 03 01:23:25 PM PST 24
Peak memory 197584 kb
Host smart-7406a2b7-07dd-49fc-aca8-0df38ba9eaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818227569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.818227569
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3093267899
Short name T434
Test name
Test status
Simulation time 328731332009 ps
CPU time 1331.88 seconds
Started Mar 03 01:23:32 PM PST 24
Finished Mar 03 01:45:44 PM PST 24
Peak memory 199692 kb
Host smart-0d9da6c1-6068-43d9-bc2d-7a116d6daaf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093267899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3093267899
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3036656265
Short name T1045
Test name
Test status
Simulation time 1754256928 ps
CPU time 1.65 seconds
Started Mar 03 01:23:28 PM PST 24
Finished Mar 03 01:23:30 PM PST 24
Peak memory 197728 kb
Host smart-54878ee6-f7b7-4c8f-9be1-964efa31023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036656265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3036656265
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.177786689
Short name T878
Test name
Test status
Simulation time 24302612152 ps
CPU time 11.81 seconds
Started Mar 03 01:23:21 PM PST 24
Finished Mar 03 01:23:33 PM PST 24
Peak memory 199724 kb
Host smart-0cfe4692-ea40-4e87-a2dd-5b68641ad87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177786689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.177786689
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2690456424
Short name T695
Test name
Test status
Simulation time 160627618095 ps
CPU time 42.61 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:29:33 PM PST 24
Peak memory 198992 kb
Host smart-785069f9-5251-4e1e-a9f7-77336b3c70f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690456424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2690456424
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.975460333
Short name T34
Test name
Test status
Simulation time 27420214962 ps
CPU time 204.45 seconds
Started Mar 03 01:28:49 PM PST 24
Finished Mar 03 01:32:13 PM PST 24
Peak memory 216104 kb
Host smart-70e76004-d477-40c0-8412-c731a44cf9a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975460333 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.975460333
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1860737731
Short name T850
Test name
Test status
Simulation time 59823630680 ps
CPU time 37.21 seconds
Started Mar 03 01:28:49 PM PST 24
Finished Mar 03 01:29:26 PM PST 24
Peak memory 199324 kb
Host smart-5b1205fe-6f13-452e-b79f-354387a0b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860737731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1860737731
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4292384987
Short name T744
Test name
Test status
Simulation time 42538602879 ps
CPU time 15.14 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:29:05 PM PST 24
Peak memory 199092 kb
Host smart-96f1a314-6e48-4afe-9011-5abf1920d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292384987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4292384987
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.213722213
Short name T701
Test name
Test status
Simulation time 40952449170 ps
CPU time 59.87 seconds
Started Mar 03 01:28:51 PM PST 24
Finished Mar 03 01:29:51 PM PST 24
Peak memory 199660 kb
Host smart-529f73b7-fdd2-490d-a6e2-19253064d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213722213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.213722213
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3316406
Short name T352
Test name
Test status
Simulation time 186101466470 ps
CPU time 556.85 seconds
Started Mar 03 01:28:48 PM PST 24
Finished Mar 03 01:38:05 PM PST 24
Peak memory 227376 kb
Host smart-c37fb9f8-8a83-44b2-992a-0fc4d07abb16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316406 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3316406
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3196086184
Short name T349
Test name
Test status
Simulation time 20082252507 ps
CPU time 17.12 seconds
Started Mar 03 01:28:49 PM PST 24
Finished Mar 03 01:29:07 PM PST 24
Peak memory 199264 kb
Host smart-db9b075f-e5a5-4083-bb65-a63b58d9b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196086184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3196086184
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3648902616
Short name T372
Test name
Test status
Simulation time 60805920798 ps
CPU time 254.14 seconds
Started Mar 03 01:28:48 PM PST 24
Finished Mar 03 01:33:02 PM PST 24
Peak memory 208108 kb
Host smart-edebebca-0e7f-44fb-b546-d0847ffa19cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648902616 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3648902616
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1795043330
Short name T152
Test name
Test status
Simulation time 108175913911 ps
CPU time 94.91 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:30:26 PM PST 24
Peak memory 199648 kb
Host smart-02b77538-9890-4d72-834f-8ece98c5a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795043330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1795043330
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3450533972
Short name T252
Test name
Test status
Simulation time 127685663465 ps
CPU time 50.2 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:29:40 PM PST 24
Peak memory 199668 kb
Host smart-b137f814-ea03-4814-9889-325ba9e8fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450533972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3450533972
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2888721063
Short name T311
Test name
Test status
Simulation time 147398983071 ps
CPU time 75.69 seconds
Started Mar 03 01:28:49 PM PST 24
Finished Mar 03 01:30:05 PM PST 24
Peak memory 199684 kb
Host smart-8180c5fd-115e-4253-b6f5-282c1d66b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888721063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2888721063
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3431264707
Short name T49
Test name
Test status
Simulation time 62323353452 ps
CPU time 106.95 seconds
Started Mar 03 01:28:50 PM PST 24
Finished Mar 03 01:30:37 PM PST 24
Peak memory 199620 kb
Host smart-9a53f6c2-9ec9-4dd7-81e0-0b147bd1765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431264707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3431264707
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4031854164
Short name T146
Test name
Test status
Simulation time 20337195715 ps
CPU time 85.01 seconds
Started Mar 03 01:28:55 PM PST 24
Finished Mar 03 01:30:20 PM PST 24
Peak memory 199664 kb
Host smart-dfb5c9d9-c9d0-4b8f-92dd-2a1d0f41d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031854164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4031854164
Directory /workspace/99.uart_fifo_reset/latest
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