Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99604	1			T1	1		T2	57		T3	2
all_values[1]	99604	1			T1	1		T2	57		T3	2
all_values[2]	99604	1			T1	1		T2	57		T3	2
all_values[3]	99604	1			T1	1		T2	57		T3	2
all_values[4]	99604	1			T1	1		T2	57		T3	2
all_values[5]	99604	1			T1	1		T2	57		T3	2
all_values[6]	99604	1			T1	1		T2	57		T3	2
all_values[7]	99604	1			T1	1		T2	57		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

409746

1

T1

6

T2

175

T3

16

auto[1]

387086

1

T1

2

T2

281

T5

3254

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732657

1

T1

7

T2

443

T3

13

auto[1]

64175

1

T1

1

T2

13

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24194	1			T2	2		T6	19		T9	93
all_values[0]	auto[0]	auto[1]	24831	1			T1	1		T2	5		T3	2
all_values[0]	auto[1]	auto[0]	25335	1			T2	47		T5	617		T6	8
all_values[0]	auto[1]	auto[1]	25244	1			T2	3		T5	180		T7	1
all_values[1]	auto[0]	auto[0]	51144	1			T1	1		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	4874	1			T2	1		T9	1		T207	2
all_values[1]	auto[1]	auto[0]	40640	1			T2	53		T5	111		T7	10
all_values[1]	auto[1]	auto[1]	2946	1			T9	7		T124	5		T278	1
all_values[2]	auto[0]	auto[0]	47661	1			T1	1		T2	40		T3	1
all_values[2]	auto[0]	auto[1]	2230	1			T2	4		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	47640	1			T2	13		T5	512		T6	18
all_values[2]	auto[1]	auto[1]	2073	1			T5	6		T6	2		T8	4
all_values[3]	auto[0]	auto[0]	51219	1			T1	1		T2	13		T3	2
all_values[3]	auto[0]	auto[1]	128	1			T9	1		T12	2		T41	1
all_values[3]	auto[1]	auto[0]	48083	1			T2	44		T5	453		T6	19
all_values[3]	auto[1]	auto[1]	174	1			T9	3		T11	3		T12	2
all_values[4]	auto[0]	auto[0]	52009	1			T1	1		T2	53		T3	2
all_values[4]	auto[0]	auto[1]	337	1			T9	3		T15	14		T11	6
all_values[4]	auto[1]	auto[0]	46928	1			T2	4		T5	191		T6	8
all_values[4]	auto[1]	auto[1]	330	1			T9	1		T23	9		T12	1
all_values[5]	auto[0]	auto[0]	51693	1			T2	48		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	116	1			T9	1		T11	1		T41	2
all_values[5]	auto[1]	auto[0]	47664	1			T1	1		T2	9		T5	502
all_values[5]	auto[1]	auto[1]	131	1			T9	1		T11	1		T12	3
all_values[6]	auto[0]	auto[0]	46791	1			T2	2		T3	2		T4	2
all_values[6]	auto[0]	auto[1]	114	1			T9	3		T11	1		T376	1
all_values[6]	auto[1]	auto[0]	52581	1			T1	1		T2	55		T5	204
all_values[6]	auto[1]	auto[1]	118	1			T9	4		T11	1		T41	2
all_values[7]	auto[0]	auto[0]	52160	1			T1	1		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	245	1			T9	2		T278	1		T383	11
all_values[7]	auto[1]	auto[0]	46915	1			T2	53		T5	478		T6	12
all_values[7]	auto[1]	auto[1]	284	1			T9	3		T45	1		T383	2