Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

1947

1

T1

1

T2

1

T3

1

auto[UartRx]

1947

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3724	1			T1	2		T2	2		T3	2
values[1]	20	1			T36	1		T37	1		T38	1
values[2]	13	1			T39	2		T40	1		T334	1
values[3]	10	1			T9	2		T27	2		T39	1
values[4]	14	1			T27	1		T28	1		T12	2
values[5]	20	1			T9	3		T27	2		T37	1
values[6]	15	1			T28	2		T38	1		T440	1
values[7]	12	1			T37	1		T39	2		T334	1
values[8]	20	1			T28	2		T36	1		T38	1
values[9]	13	1			T36	1		T37	1		T334	1
values[10]	23	1			T9	1		T36	1		T37	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1894	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	5	1			T39	1		T334	1		T319	1
auto[UartTx]	values[2]	5	1			T440	2		T319	2		T61	1
auto[UartTx]	values[3]	3	1			T39	1		T179	1		T109	1
auto[UartTx]	values[4]	3	1			T12	1		T381	1		T441	1
auto[UartTx]	values[5]	5	1			T27	1		T440	1		T108	1
auto[UartTx]	values[6]	4	1			T28	1		T441	1		T108	2
auto[UartTx]	values[7]	3	1			T104	1		T219	1		T442	1
auto[UartTx]	values[8]	8	1			T28	1		T38	1		T40	1
auto[UartTx]	values[9]	2	1			T382	2		-	-		-	-
auto[UartTx]	values[10]	9	1			T37	1		T104	1		T219	1
auto[UartRx]	values[0]	1830	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	15	1			T36	1		T37	1		T38	1
auto[UartRx]	values[2]	8	1			T39	2		T40	1		T334	1
auto[UartRx]	values[3]	7	1			T9	2		T27	2		T441	1
auto[UartRx]	values[4]	11	1			T27	1		T28	1		T12	1
auto[UartRx]	values[5]	15	1			T9	3		T27	1		T37	1
auto[UartRx]	values[6]	11	1			T28	1		T38	1		T440	1
auto[UartRx]	values[7]	9	1			T37	1		T39	2		T334	1
auto[UartRx]	values[8]	12	1			T28	1		T36	1		T40	1
auto[UartRx]	values[9]	11	1			T36	1		T37	1		T334	1
auto[UartRx]	values[10]	14	1			T9	1		T36	1		T40	1