Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1682	1			T2	1		T3	2		T7	2
auto[BaudRate115200]	1747	1			T5	3		T9	10		T16	3
auto[BaudRate230400]	1463	1			T5	1		T7	2		T8	3
auto[BaudRate128Kbps]	1437	1			T4	2		T5	2		T8	1
auto[BaudRate256Kbps]	1673	1			T1	3		T2	4		T6	10
auto[BaudRate1Mbps]	1457	1			T2	3		T5	2		T9	22
auto[BaudRate1p5Mbps]	982	1			T5	2		T127	1		T135	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1050	1			T3	2		T7	5		T207	7
freqs[25]	1122	1			T13	19		T17	2		T47	9
freqs[48]	401	1			T298	7		T409	5		T115	7
freqs[50]	374	1			T299	8		T128	7		T144	10
freqs[100]	1365	1			T443	54		T48	10		T156	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	149	1			T3	2		T7	2		T392	1
auto[BaudRate9600]	freqs[25]	215	1			T13	11		T47	1		T160	1
auto[BaudRate9600]	freqs[48]	38	1			T409	1		T146	1		T175	1
auto[BaudRate9600]	freqs[50]	51	1			T128	3		T144	1		T427	2
auto[BaudRate9600]	freqs[100]	201	1			T443	12		T156	2		T196	3
auto[BaudRate115200]	freqs[24]	175	1			T207	1		T278	1		T403	1
auto[BaudRate115200]	freqs[25]	204	1			T13	8		T47	1		T130	2
auto[BaudRate115200]	freqs[48]	65	1			T115	3		T146	2		T39	6
auto[BaudRate115200]	freqs[50]	66	1			T144	1		T211	2		T265	3
auto[BaudRate115200]	freqs[100]	181	1			T443	9		T48	4		T156	1
auto[BaudRate230400]	freqs[24]	160	1			T7	2		T207	2		T278	1
auto[BaudRate230400]	freqs[25]	147	1			T17	1		T160	2		T130	2
auto[BaudRate230400]	freqs[48]	40	1			T409	1		T146	2		T175	1
auto[BaudRate230400]	freqs[50]	38	1			T427	2		T211	1		T265	2
auto[BaudRate230400]	freqs[100]	198	1			T443	6		T48	2		T156	1
auto[BaudRate128Kbps]	freqs[24]	143	1			T278	1		T126	2		T399	1
auto[BaudRate128Kbps]	freqs[25]	147	1			T47	1		T130	1		T138	1
auto[BaudRate128Kbps]	freqs[48]	53	1			T409	1		T115	1		T146	2
auto[BaudRate128Kbps]	freqs[50]	51	1			T128	1		T144	3		T427	1
auto[BaudRate128Kbps]	freqs[100]	179	1			T443	9		T48	3		T156	1
auto[BaudRate256Kbps]	freqs[24]	147	1			T7	1		T278	2		T391	4
auto[BaudRate256Kbps]	freqs[25]	161	1			T17	1		T47	2		T390	3
auto[BaudRate256Kbps]	freqs[48]	59	1			T298	3		T409	1		T444	4
auto[BaudRate256Kbps]	freqs[50]	55	1			T299	2		T144	1		T113	2
auto[BaudRate256Kbps]	freqs[100]	206	1			T443	3		T148	1		T196	2
auto[BaudRate1Mbps]	freqs[24]	191	1			T207	3		T278	1		T391	2
auto[BaudRate1Mbps]	freqs[25]	167	1			T47	2		T390	2		T160	2
auto[BaudRate1Mbps]	freqs[48]	87	1			T298	2		T115	1		T444	2
auto[BaudRate1Mbps]	freqs[50]	47	1			T299	2		T128	2		T144	1
auto[BaudRate1Mbps]	freqs[100]	217	1			T443	12		T196	1		T27	16
auto[BaudRate1p5Mbps]	freqs[25]	81	1			T47	2		T390	3		T160	1
auto[BaudRate1p5Mbps]	freqs[48]	59	1			T298	2		T409	1		T115	2
auto[BaudRate1p5Mbps]	freqs[50]	66	1			T299	4		T128	1		T144	3
auto[BaudRate1p5Mbps]	freqs[100]	183	1			T443	3		T48	1		T148	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded