Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2713 1 T2 1 T9 6 T124 20
all_levels[1] 1533 1 T207 2 T160 2 T128 8
all_levels[2] 1402 1 T254 7 T37 3 T19 4
all_levels[3] 667 1 T147 2 T173 5 T318 3
all_levels[4] 621 1 T153 1 T334 1 T447 4
all_levels[5] 548 1 T278 1 T448 6 T449 6
all_levels[6] 313 1 T9 2 T450 2 T451 129
all_levels[7] 24 1 T20 12 T452 3 T453 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%