Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99604	1			T1	1		T2	57		T3	2
all_pins[1]	99604	1			T1	1		T2	57		T3	2
all_pins[2]	99604	1			T1	1		T2	57		T3	2
all_pins[3]	99604	1			T1	1		T2	57		T3	2
all_pins[4]	99604	1			T1	1		T2	57		T3	2
all_pins[5]	99604	1			T1	1		T2	57		T3	2
all_pins[6]	99604	1			T1	1		T2	57		T3	2
all_pins[7]	99604	1			T1	1		T2	57		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	764842	1			T1	8		T2	453		T3	16
values[0x1]	31990	1			T2	3		T5	186		T6	2
transitions[0x0=>0x1]	30613	1			T2	3		T5	186		T6	2
transitions[0x1=>0x0]	30201	1			T2	2		T5	185		T6	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	74317	1			T1	1		T2	54		T3	2
all_pins[0]	values[0x1]	25287	1			T2	3		T5	180		T7	1
all_pins[0]	transitions[0x0=>0x1]	24316	1			T2	3		T5	180		T7	1
all_pins[0]	transitions[0x1=>0x0]	1977	1			T9	2		T278	1		T36	4
all_pins[1]	values[0x0]	96656	1			T1	1		T2	57		T3	2
all_pins[1]	values[0x1]	2948	1			T9	7		T124	5		T278	1
all_pins[1]	transitions[0x0=>0x1]	2886	1			T9	7		T124	5		T278	1
all_pins[1]	transitions[0x1=>0x0]	2051	1			T5	6		T6	2		T8	4
all_pins[2]	values[0x0]	97491	1			T1	1		T2	57		T3	2
all_pins[2]	values[0x1]	2113	1			T5	6		T6	2		T8	4
all_pins[2]	transitions[0x0=>0x1]	2089	1			T5	6		T6	2		T8	4
all_pins[2]	transitions[0x1=>0x0]	150	1			T9	3		T11	3		T12	1
all_pins[3]	values[0x0]	99430	1			T1	1		T2	57		T3	2
all_pins[3]	values[0x1]	174	1			T9	3		T11	3		T12	2
all_pins[3]	transitions[0x0=>0x1]	130	1			T9	2		T11	3		T12	1
all_pins[3]	transitions[0x1=>0x0]	286	1			T23	9		T38	6		T20	3
all_pins[4]	values[0x0]	99274	1			T1	1		T2	57		T3	2
all_pins[4]	values[0x1]	330	1			T9	1		T23	9		T12	1
all_pins[4]	transitions[0x0=>0x1]	256	1			T23	7		T38	6		T20	3
all_pins[4]	transitions[0x1=>0x0]	102	1			T11	1		T12	2		T19	2
all_pins[5]	values[0x0]	99428	1			T1	1		T2	57		T3	2
all_pins[5]	values[0x1]	176	1			T9	1		T11	1		T23	2
all_pins[5]	transitions[0x0=>0x1]	134	1			T23	2		T12	3		T19	2
all_pins[5]	transitions[0x1=>0x0]	636	1			T9	10		T16	5		T127	1
all_pins[6]	values[0x0]	98926	1			T1	1		T2	57		T3	2
all_pins[6]	values[0x1]	678	1			T9	11		T16	5		T127	1
all_pins[6]	transitions[0x0=>0x1]	636	1			T9	9		T16	5		T127	1
all_pins[6]	transitions[0x1=>0x0]	242	1			T9	1		T45	1		T383	2
all_pins[7]	values[0x0]	99320	1			T1	1		T2	57		T3	2
all_pins[7]	values[0x1]	284	1			T9	3		T45	1		T383	2
all_pins[7]	transitions[0x0=>0x1]	166	1			T9	1		T45	1		T383	1
all_pins[7]	transitions[0x1=>0x0]	24757	1			T2	2		T5	179		T7	1