Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 0 7 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 7054 1 T3 2 T4 2 T5 15
all_levels[1] 5103 1 T7 7 T8 2 T9 22
all_levels[2] 5347 1 T2 1 T5 121 T7 1
all_levels[3] 5522 1 T1 1 T5 1 T6 1
all_levels[4] 8995 1 T2 2 T9 1 T16 2
all_levels[5] 8636 1 T5 56 T9 5 T16 1
all_levels[6] 9506 1 T2 5 T5 23 T8 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%