Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	498	1			T9	8		T11	4		T12	4
all_values[1]	498	1			T9	8		T11	4		T12	4
all_values[2]	498	1			T9	8		T11	4		T12	4
all_values[3]	498	1			T9	8		T11	4		T12	4
all_values[4]	498	1			T9	8		T11	4		T12	4
all_values[5]	498	1			T9	8		T11	4		T12	4
all_values[6]	498	1			T9	8		T11	4		T12	4
all_values[7]	498	1			T9	8		T11	4		T12	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T9

24

T11

18

T12

15

auto[1]

1909

1

T9

40

T11

14

T12

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1438

1

T9

23

T11

9

T12

10

auto[1]

2546

1

T9

41

T11

23

T12

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2339

1

T9

38

T11

22

T12

18

auto[1]

1645

1

T9

26

T11

10

T12

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	165	1			T9	1		T11	2		T12	1
all_values[0]	auto[0]	auto[1]	auto[1]	135	1			T9	3		T11	1		T41	4
all_values[0]	auto[1]	auto[0]	auto[1]	101	1			T9	3		T11	1		T12	2
all_values[0]	auto[1]	auto[1]	auto[1]	97	1			T9	1		T12	1		T41	1
all_values[1]	auto[0]	auto[0]	auto[0]	148	1			T9	2		T11	2		T381	3
all_values[1]	auto[0]	auto[1]	auto[0]	150	1			T9	3		T11	2		T12	2
all_values[1]	auto[1]	auto[0]	auto[1]	106	1			T9	2		T41	1		T376	3
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T9	1		T12	2		T41	2
all_values[2]	auto[0]	auto[0]	auto[0]	95	1			T9	1		T11	1		T12	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T9	1		T11	1		T376	2
all_values[2]	auto[0]	auto[1]	auto[0]	95	1			T9	2		T41	2		T376	2
all_values[2]	auto[0]	auto[1]	auto[1]	49	1			T9	1		T12	1		T41	1
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T9	1		T11	2		T41	2
all_values[2]	auto[1]	auto[1]	auto[1]	84	1			T9	2		T12	2		T382	2
all_values[3]	auto[0]	auto[0]	auto[0]	121	1			T9	1		T376	3		T382	5
all_values[3]	auto[0]	auto[0]	auto[1]	34	1			T12	2		T381	1		T382	1
all_values[3]	auto[0]	auto[1]	auto[0]	85	1			T9	2		T11	1		T376	1
all_values[3]	auto[0]	auto[1]	auto[1]	60	1			T9	1		T11	2		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	106	1			T9	1		T11	1		T41	2
all_values[3]	auto[1]	auto[1]	auto[1]	92	1			T9	3		T12	1		T41	3
all_values[4]	auto[0]	auto[0]	auto[0]	87	1			T9	1		T376	2		T381	2
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T9	1		T11	2		T41	1
all_values[4]	auto[0]	auto[1]	auto[0]	71	1			T9	2		T12	2		T41	2
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T9	2		T41	1		T382	1
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T9	1		T11	1		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	110	1			T9	1		T11	1		T12	1
all_values[5]	auto[0]	auto[0]	auto[0]	95	1			T9	1		T41	1		T376	3
all_values[5]	auto[0]	auto[0]	auto[1]	42	1			T11	1		T41	1		T376	1
all_values[5]	auto[0]	auto[1]	auto[0]	85	1			T9	3		T11	1		T12	1
all_values[5]	auto[0]	auto[1]	auto[1]	55	1			T9	1		T11	1		T12	1
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T41	2		T376	1		T381	3
all_values[5]	auto[1]	auto[1]	auto[1]	109	1			T9	3		T11	1		T12	2
all_values[6]	auto[0]	auto[0]	auto[0]	108	1			T9	1		T12	4		T41	1
all_values[6]	auto[0]	auto[0]	auto[1]	45	1			T9	1		T382	5		T104	1
all_values[6]	auto[0]	auto[1]	auto[0]	87	1			T11	1		T41	3		T381	2
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T9	2		T11	1		T41	1
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T9	3		T11	1		T376	1
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T9	1		T11	1		T41	2
all_values[7]	auto[0]	auto[0]	auto[0]	108	1			T41	2		T381	1		T382	2
all_values[7]	auto[0]	auto[0]	auto[1]	43	1			T11	2		T12	2		T381	1
all_values[7]	auto[0]	auto[1]	auto[0]	103	1			T9	4		T11	1		T41	2
all_values[7]	auto[0]	auto[1]	auto[1]	49	1			T9	1		T381	1		T382	2
all_values[7]	auto[1]	auto[0]	auto[1]	113	1			T9	2		T11	1		T12	2
all_values[7]	auto[1]	auto[1]	auto[1]	82	1			T9	1		T41	2		T376	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal