Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.94 99.38 97.89 100.00 98.83 100.00 97.52


Total test records in report: 1232
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T1040 /workspace/coverage/default/195.uart_fifo_reset.710947499 Mar 05 01:42:40 PM PST 24 Mar 05 01:43:39 PM PST 24 140099876449 ps
T1041 /workspace/coverage/default/37.uart_rx_oversample.4216099405 Mar 05 01:36:00 PM PST 24 Mar 05 01:36:10 PM PST 24 2670782263 ps
T1042 /workspace/coverage/default/2.uart_alert_test.2708483704 Mar 05 01:33:08 PM PST 24 Mar 05 01:33:09 PM PST 24 13559624 ps
T1043 /workspace/coverage/default/44.uart_intr.1538546155 Mar 05 01:38:13 PM PST 24 Mar 05 01:38:23 PM PST 24 20452236275 ps
T1044 /workspace/coverage/default/256.uart_fifo_reset.1750798446 Mar 05 01:43:41 PM PST 24 Mar 05 01:45:06 PM PST 24 51647497000 ps
T1045 /workspace/coverage/default/187.uart_fifo_reset.1941072621 Mar 05 01:42:30 PM PST 24 Mar 05 01:44:33 PM PST 24 72569658622 ps
T268 /workspace/coverage/default/217.uart_fifo_reset.1956569428 Mar 05 01:42:52 PM PST 24 Mar 05 01:43:39 PM PST 24 116356935997 ps
T1046 /workspace/coverage/default/6.uart_fifo_full.2744981519 Mar 05 01:33:22 PM PST 24 Mar 05 01:33:59 PM PST 24 28473269581 ps
T1047 /workspace/coverage/default/15.uart_fifo_reset.2130935852 Mar 05 01:34:03 PM PST 24 Mar 05 01:35:10 PM PST 24 29157212567 ps
T1048 /workspace/coverage/default/20.uart_fifo_reset.1922303575 Mar 05 01:34:23 PM PST 24 Mar 05 01:38:24 PM PST 24 133770615124 ps
T1049 /workspace/coverage/default/0.uart_rx_start_bit_filter.4087550907 Mar 05 01:32:59 PM PST 24 Mar 05 01:33:04 PM PST 24 1964252887 ps
T1050 /workspace/coverage/default/44.uart_tx_ovrd.2094583526 Mar 05 01:38:17 PM PST 24 Mar 05 01:38:19 PM PST 24 1643599058 ps
T324 /workspace/coverage/default/66.uart_fifo_reset.730046671 Mar 05 01:40:13 PM PST 24 Mar 05 01:40:36 PM PST 24 47932494756 ps
T1051 /workspace/coverage/default/29.uart_noise_filter.640584770 Mar 05 01:35:27 PM PST 24 Mar 05 01:36:39 PM PST 24 81268528618 ps
T1052 /workspace/coverage/default/18.uart_rx_start_bit_filter.2561487216 Mar 05 01:34:17 PM PST 24 Mar 05 01:34:19 PM PST 24 657988924 ps
T1053 /workspace/coverage/default/205.uart_fifo_reset.4228285889 Mar 05 01:42:44 PM PST 24 Mar 05 01:45:38 PM PST 24 104522322632 ps
T1054 /workspace/coverage/default/5.uart_long_xfer_wo_dly.1068028789 Mar 05 01:33:23 PM PST 24 Mar 05 01:39:49 PM PST 24 145413491009 ps
T1055 /workspace/coverage/default/32.uart_smoke.338508066 Mar 05 01:35:22 PM PST 24 Mar 05 01:35:24 PM PST 24 675937759 ps
T1056 /workspace/coverage/default/38.uart_rx_oversample.1694619201 Mar 05 01:36:23 PM PST 24 Mar 05 01:36:26 PM PST 24 1690003760 ps
T1057 /workspace/coverage/default/49.uart_rx_start_bit_filter.153118226 Mar 05 01:39:32 PM PST 24 Mar 05 01:39:40 PM PST 24 4256625990 ps
T1058 /workspace/coverage/default/11.uart_long_xfer_wo_dly.359703422 Mar 05 01:33:52 PM PST 24 Mar 05 01:46:18 PM PST 24 102373486555 ps
T1059 /workspace/coverage/default/26.uart_fifo_full.1234828545 Mar 05 01:34:51 PM PST 24 Mar 05 01:35:11 PM PST 24 58819757221 ps
T374 /workspace/coverage/default/107.uart_fifo_reset.2456319414 Mar 05 01:41:19 PM PST 24 Mar 05 01:41:37 PM PST 24 127537401652 ps
T1060 /workspace/coverage/default/40.uart_rx_start_bit_filter.3057227361 Mar 05 01:37:16 PM PST 24 Mar 05 01:37:18 PM PST 24 2881399136 ps
T284 /workspace/coverage/default/201.uart_fifo_reset.575427193 Mar 05 01:42:40 PM PST 24 Mar 05 01:45:42 PM PST 24 106705747132 ps
T1061 /workspace/coverage/default/192.uart_fifo_reset.2037386030 Mar 05 01:42:37 PM PST 24 Mar 05 01:43:06 PM PST 24 290248040906 ps
T290 /workspace/coverage/default/34.uart_fifo_full.2673957647 Mar 05 01:35:36 PM PST 24 Mar 05 01:36:22 PM PST 24 121043091344 ps
T1062 /workspace/coverage/default/41.uart_noise_filter.492665034 Mar 05 01:37:29 PM PST 24 Mar 05 01:39:12 PM PST 24 236197448348 ps
T1063 /workspace/coverage/default/20.uart_stress_all.743881118 Mar 05 01:34:22 PM PST 24 Mar 05 01:53:16 PM PST 24 156157683932 ps
T1064 /workspace/coverage/default/37.uart_fifo_overflow.2703474047 Mar 05 01:35:59 PM PST 24 Mar 05 01:36:57 PM PST 24 32377335861 ps
T338 /workspace/coverage/default/98.uart_fifo_reset.3681246683 Mar 05 01:41:10 PM PST 24 Mar 05 01:41:22 PM PST 24 56798128511 ps
T1065 /workspace/coverage/default/285.uart_fifo_reset.244560406 Mar 05 01:43:59 PM PST 24 Mar 05 01:44:19 PM PST 24 12580194766 ps
T1066 /workspace/coverage/default/13.uart_rx_oversample.1068257516 Mar 05 01:34:02 PM PST 24 Mar 05 01:34:14 PM PST 24 5709210815 ps
T1067 /workspace/coverage/default/46.uart_intr.372955699 Mar 05 01:38:51 PM PST 24 Mar 05 01:47:19 PM PST 24 369030387928 ps
T1068 /workspace/coverage/default/14.uart_rx_oversample.1278931454 Mar 05 01:34:02 PM PST 24 Mar 05 01:34:12 PM PST 24 3548347474 ps
T244 /workspace/coverage/default/234.uart_fifo_reset.319536663 Mar 05 01:43:16 PM PST 24 Mar 05 01:44:01 PM PST 24 30523965081 ps
T1069 /workspace/coverage/default/37.uart_smoke.375200450 Mar 05 01:35:50 PM PST 24 Mar 05 01:35:53 PM PST 24 647131442 ps
T1070 /workspace/coverage/default/47.uart_fifo_full.1578833461 Mar 05 01:39:03 PM PST 24 Mar 05 01:39:46 PM PST 24 397699755241 ps
T1071 /workspace/coverage/default/49.uart_rx_oversample.217398663 Mar 05 01:39:33 PM PST 24 Mar 05 01:39:34 PM PST 24 159245075 ps
T1072 /workspace/coverage/default/20.uart_tx_rx.1214467515 Mar 05 01:34:23 PM PST 24 Mar 05 01:34:35 PM PST 24 28174026063 ps
T1073 /workspace/coverage/default/36.uart_noise_filter.1203398066 Mar 05 01:35:40 PM PST 24 Mar 05 01:38:09 PM PST 24 174539739015 ps
T1074 /workspace/coverage/default/159.uart_fifo_reset.875347132 Mar 05 01:42:08 PM PST 24 Mar 05 01:42:18 PM PST 24 14832199459 ps
T1075 /workspace/coverage/default/37.uart_noise_filter.380433784 Mar 05 01:36:10 PM PST 24 Mar 05 01:38:17 PM PST 24 67778822351 ps
T1076 /workspace/coverage/default/43.uart_tx_ovrd.2821078728 Mar 05 01:38:01 PM PST 24 Mar 05 01:38:05 PM PST 24 1013340206 ps
T1077 /workspace/coverage/default/25.uart_tx_ovrd.3743429648 Mar 05 01:34:49 PM PST 24 Mar 05 01:34:51 PM PST 24 883188843 ps
T1078 /workspace/coverage/default/273.uart_fifo_reset.1699339200 Mar 05 01:43:55 PM PST 24 Mar 05 01:46:03 PM PST 24 80170779800 ps
T1079 /workspace/coverage/default/57.uart_fifo_reset.753519465 Mar 05 01:40:02 PM PST 24 Mar 05 01:40:19 PM PST 24 7619290315 ps
T1080 /workspace/coverage/default/35.uart_fifo_reset.3565383224 Mar 05 01:35:35 PM PST 24 Mar 05 01:36:45 PM PST 24 27374950679 ps
T1081 /workspace/coverage/default/36.uart_alert_test.1354000458 Mar 05 01:35:48 PM PST 24 Mar 05 01:35:49 PM PST 24 42176778 ps
T1082 /workspace/coverage/default/34.uart_long_xfer_wo_dly.835258848 Mar 05 01:35:34 PM PST 24 Mar 05 01:48:48 PM PST 24 114381375408 ps
T1083 /workspace/coverage/default/216.uart_fifo_reset.4060597873 Mar 05 01:42:57 PM PST 24 Mar 05 01:43:15 PM PST 24 153164053683 ps
T1084 /workspace/coverage/default/34.uart_tx_rx.1262908650 Mar 05 01:35:34 PM PST 24 Mar 05 01:36:16 PM PST 24 36601686614 ps
T1085 /workspace/coverage/default/25.uart_rx_parity_err.3535189011 Mar 05 01:34:49 PM PST 24 Mar 05 01:35:17 PM PST 24 91138040650 ps
T1086 /workspace/coverage/default/40.uart_fifo_full.4175706937 Mar 05 01:37:02 PM PST 24 Mar 05 01:38:01 PM PST 24 127183020302 ps
T1087 /workspace/coverage/default/27.uart_perf.3828168592 Mar 05 01:34:59 PM PST 24 Mar 05 01:40:55 PM PST 24 6532151763 ps
T316 /workspace/coverage/default/86.uart_fifo_reset.2233347603 Mar 05 01:40:55 PM PST 24 Mar 05 01:41:27 PM PST 24 24226462999 ps
T222 /workspace/coverage/default/143.uart_fifo_reset.1971782625 Mar 05 01:41:56 PM PST 24 Mar 05 01:44:33 PM PST 24 94653519757 ps
T1088 /workspace/coverage/default/28.uart_intr.3549475983 Mar 05 01:35:06 PM PST 24 Mar 05 02:30:54 PM PST 24 2143633347996 ps
T339 /workspace/coverage/default/140.uart_fifo_reset.393086038 Mar 05 01:41:44 PM PST 24 Mar 05 01:42:28 PM PST 24 49308753967 ps
T1089 /workspace/coverage/default/10.uart_fifo_reset.1319707923 Mar 05 01:33:46 PM PST 24 Mar 05 01:34:28 PM PST 24 30421260618 ps
T1090 /workspace/coverage/default/15.uart_smoke.2325265510 Mar 05 01:34:05 PM PST 24 Mar 05 01:34:13 PM PST 24 5845976075 ps
T1091 /workspace/coverage/default/254.uart_fifo_reset.3147944162 Mar 05 01:43:38 PM PST 24 Mar 05 01:44:10 PM PST 24 93659017765 ps
T1092 /workspace/coverage/default/46.uart_tx_rx.4232971100 Mar 05 01:38:50 PM PST 24 Mar 05 01:39:47 PM PST 24 24907810107 ps
T1093 /workspace/coverage/default/4.uart_fifo_overflow.2488958664 Mar 05 01:33:15 PM PST 24 Mar 05 01:45:56 PM PST 24 171305426412 ps
T1094 /workspace/coverage/default/41.uart_loopback.426702116 Mar 05 01:37:36 PM PST 24 Mar 05 01:37:47 PM PST 24 8465128547 ps
T369 /workspace/coverage/default/44.uart_rx_parity_err.997069601 Mar 05 01:38:18 PM PST 24 Mar 05 01:38:55 PM PST 24 64058790416 ps
T1095 /workspace/coverage/default/9.uart_tx_rx.3826548243 Mar 05 01:33:38 PM PST 24 Mar 05 01:33:56 PM PST 24 51050763674 ps
T1096 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1416466102 Mar 05 02:51:46 PM PST 24 Mar 05 02:51:47 PM PST 24 110901981 ps
T1097 /workspace/coverage/cover_reg_top/42.uart_intr_test.2321342991 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:51 PM PST 24 21926930 ps
T1098 /workspace/coverage/cover_reg_top/19.uart_tl_errors.179076122 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:45 PM PST 24 41978325 ps
T1099 /workspace/coverage/cover_reg_top/49.uart_intr_test.1280937847 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:50 PM PST 24 10948063 ps
T83 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3467324020 Mar 05 02:51:27 PM PST 24 Mar 05 02:51:28 PM PST 24 55403405 ps
T1100 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2481492577 Mar 05 02:51:25 PM PST 24 Mar 05 02:51:25 PM PST 24 23542407 ps
T84 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2129435675 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:43 PM PST 24 89459296 ps
T1101 /workspace/coverage/cover_reg_top/44.uart_intr_test.3990473355 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:52 PM PST 24 85800447 ps
T1102 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1502860832 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:48 PM PST 24 44085467 ps
T85 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.271860691 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 102417729 ps
T1103 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1122133896 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:27 PM PST 24 27866693 ps
T75 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4027956342 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 29128404 ps
T1104 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1902815734 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:20 PM PST 24 20191242 ps
T1105 /workspace/coverage/cover_reg_top/5.uart_tl_errors.466304364 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:28 PM PST 24 40027098 ps
T76 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3814106234 Mar 05 02:51:33 PM PST 24 Mar 05 02:51:34 PM PST 24 159319523 ps
T77 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1602978416 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:36 PM PST 24 21343976 ps
T78 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2328409823 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 203557777 ps
T1106 /workspace/coverage/cover_reg_top/33.uart_intr_test.2339621416 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:53 PM PST 24 11763763 ps
T1107 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2830179625 Mar 05 02:51:37 PM PST 24 Mar 05 02:51:39 PM PST 24 54852981 ps
T1108 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1740858373 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 80471487 ps
T1109 /workspace/coverage/cover_reg_top/19.uart_intr_test.1136719286 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 17471599 ps
T1110 /workspace/coverage/cover_reg_top/40.uart_intr_test.3842523758 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:53 PM PST 24 12045298 ps
T91 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2702029904 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 49557825 ps
T1111 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3503926677 Mar 05 02:51:37 PM PST 24 Mar 05 02:51:38 PM PST 24 28328861 ps
T1112 /workspace/coverage/cover_reg_top/23.uart_intr_test.1557308835 Mar 05 02:51:48 PM PST 24 Mar 05 02:51:48 PM PST 24 40304738 ps
T1113 /workspace/coverage/cover_reg_top/45.uart_intr_test.2263011556 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:52 PM PST 24 19001711 ps
T79 /workspace/coverage/cover_reg_top/17.uart_csr_rw.71497020 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 21369179 ps
T1114 /workspace/coverage/cover_reg_top/10.uart_intr_test.2057021274 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 14441639 ps
T80 /workspace/coverage/cover_reg_top/19.uart_csr_rw.440367527 Mar 05 02:51:48 PM PST 24 Mar 05 02:51:49 PM PST 24 16782663 ps
T1115 /workspace/coverage/cover_reg_top/24.uart_intr_test.1698751759 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:43 PM PST 24 16400214 ps
T86 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3456234916 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:20 PM PST 24 94755761 ps
T89 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1536775572 Mar 05 02:51:21 PM PST 24 Mar 05 02:51:22 PM PST 24 76839220 ps
T1116 /workspace/coverage/cover_reg_top/6.uart_intr_test.2500727710 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:26 PM PST 24 31943528 ps
T81 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2754160893 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 15153276 ps
T82 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2715765413 Mar 05 02:51:20 PM PST 24 Mar 05 02:51:20 PM PST 24 15059443 ps
T1117 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2902373625 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:28 PM PST 24 80607960 ps
T1118 /workspace/coverage/cover_reg_top/8.uart_intr_test.344025480 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:35 PM PST 24 11968333 ps
T64 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3898290564 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:43 PM PST 24 37899353 ps
T1119 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.874652672 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:43 PM PST 24 96136791 ps
T1120 /workspace/coverage/cover_reg_top/34.uart_intr_test.2622016291 Mar 05 02:51:51 PM PST 24 Mar 05 02:51:52 PM PST 24 35765150 ps
T1121 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3860444872 Mar 05 02:51:22 PM PST 24 Mar 05 02:51:23 PM PST 24 149151350 ps
T87 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3794506291 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 85016859 ps
T69 /workspace/coverage/cover_reg_top/2.uart_csr_rw.81719652 Mar 05 02:51:27 PM PST 24 Mar 05 02:51:28 PM PST 24 138530773 ps
T1122 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3417883916 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:45 PM PST 24 89774823 ps
T1123 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3640896334 Mar 05 02:51:20 PM PST 24 Mar 05 02:51:21 PM PST 24 43537244 ps
T1124 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.384569011 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:30 PM PST 24 21161590 ps
T1125 /workspace/coverage/cover_reg_top/13.uart_csr_rw.854288186 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 25604489 ps
T1126 /workspace/coverage/cover_reg_top/22.uart_intr_test.1896467599 Mar 05 02:51:48 PM PST 24 Mar 05 02:51:49 PM PST 24 14268116 ps
T65 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.545369271 Mar 05 02:51:18 PM PST 24 Mar 05 02:51:19 PM PST 24 37894105 ps
T1127 /workspace/coverage/cover_reg_top/11.uart_intr_test.1767539020 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 12948277 ps
T1128 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3409631277 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:27 PM PST 24 43226045 ps
T1129 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1982472831 Mar 05 02:51:37 PM PST 24 Mar 05 02:51:38 PM PST 24 27987101 ps
T1130 /workspace/coverage/cover_reg_top/8.uart_tl_errors.542721978 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:35 PM PST 24 48602267 ps
T90 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1898824506 Mar 05 02:51:18 PM PST 24 Mar 05 02:51:20 PM PST 24 94328226 ps
T66 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1059415012 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 41566867 ps
T88 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1554815689 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:29 PM PST 24 54700048 ps
T1131 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1923957816 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 24696258 ps
T1132 /workspace/coverage/cover_reg_top/29.uart_intr_test.2351362320 Mar 05 02:51:54 PM PST 24 Mar 05 02:51:55 PM PST 24 39409614 ps
T1133 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2786377999 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:47 PM PST 24 30570661 ps
T1134 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4269026242 Mar 05 02:51:22 PM PST 24 Mar 05 02:51:23 PM PST 24 15817159 ps
T1135 /workspace/coverage/cover_reg_top/27.uart_intr_test.3613102286 Mar 05 02:51:51 PM PST 24 Mar 05 02:51:52 PM PST 24 54113504 ps
T1136 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1643773114 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:29 PM PST 24 24954212 ps
T1137 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.572257068 Mar 05 02:51:18 PM PST 24 Mar 05 02:51:20 PM PST 24 104669493 ps
T1138 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1938648575 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 25979457 ps
T1139 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2234017369 Mar 05 02:51:25 PM PST 24 Mar 05 02:51:25 PM PST 24 14278524 ps
T1140 /workspace/coverage/cover_reg_top/6.uart_tl_errors.4122050421 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:28 PM PST 24 80122021 ps
T1141 /workspace/coverage/cover_reg_top/28.uart_intr_test.1812712632 Mar 05 02:51:54 PM PST 24 Mar 05 02:51:55 PM PST 24 95462701 ps
T1142 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3891237184 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:29 PM PST 24 26472452 ps
T1143 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2905536864 Mar 05 02:51:20 PM PST 24 Mar 05 02:51:22 PM PST 24 96243524 ps
T1144 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3333068283 Mar 05 02:51:46 PM PST 24 Mar 05 02:51:47 PM PST 24 24302612 ps
T67 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1207286133 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:30 PM PST 24 104527205 ps
T68 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2508409675 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:36 PM PST 24 14368798 ps
T1145 /workspace/coverage/cover_reg_top/13.uart_intr_test.3986265378 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 26810728 ps
T1146 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.879887669 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 270088084 ps
T1147 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3245097663 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:44 PM PST 24 29082695 ps
T1148 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.95035765 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:37 PM PST 24 302721510 ps
T1149 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2854880627 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:46 PM PST 24 351896780 ps
T1150 /workspace/coverage/cover_reg_top/1.uart_tl_errors.97613002 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:20 PM PST 24 34384770 ps
T1151 /workspace/coverage/cover_reg_top/21.uart_intr_test.4029355923 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 14835251 ps
T1152 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.344150472 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:30 PM PST 24 30620020 ps
T1153 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2083543464 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:27 PM PST 24 19816876 ps
T1154 /workspace/coverage/cover_reg_top/38.uart_intr_test.2678296367 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:51 PM PST 24 228389049 ps
T1155 /workspace/coverage/cover_reg_top/15.uart_intr_test.30535376 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 26230102 ps
T1156 /workspace/coverage/cover_reg_top/36.uart_intr_test.1168060481 Mar 05 02:51:51 PM PST 24 Mar 05 02:51:51 PM PST 24 91736967 ps
T1157 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3046945544 Mar 05 02:51:27 PM PST 24 Mar 05 02:51:28 PM PST 24 17691344 ps
T1158 /workspace/coverage/cover_reg_top/17.uart_intr_test.3840553856 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:45 PM PST 24 55841274 ps
T1159 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1235339039 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:43 PM PST 24 96595439 ps
T1160 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3092653360 Mar 05 02:51:20 PM PST 24 Mar 05 02:51:21 PM PST 24 213483772 ps
T1161 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1556681508 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:30 PM PST 24 22610759 ps
T1162 /workspace/coverage/cover_reg_top/35.uart_intr_test.3649511773 Mar 05 02:51:49 PM PST 24 Mar 05 02:51:50 PM PST 24 101037824 ps
T1163 /workspace/coverage/cover_reg_top/4.uart_intr_test.1899334906 Mar 05 02:51:25 PM PST 24 Mar 05 02:51:26 PM PST 24 21633498 ps
T1164 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1564845715 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:29 PM PST 24 171562460 ps
T1165 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1730584704 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:44 PM PST 24 72236225 ps
T1166 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1138402354 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:44 PM PST 24 56324650 ps
T1167 /workspace/coverage/cover_reg_top/2.uart_intr_test.2533977704 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:20 PM PST 24 52390114 ps
T1168 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1098241686 Mar 05 02:51:43 PM PST 24 Mar 05 02:51:44 PM PST 24 65448624 ps
T1169 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2333828813 Mar 05 02:51:27 PM PST 24 Mar 05 02:51:28 PM PST 24 33819859 ps
T1170 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1885661351 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 228313891 ps
T1171 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1007114787 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:48 PM PST 24 87364115 ps
T1172 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4058894710 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 159110788 ps
T1173 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1849676314 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:21 PM PST 24 37527668 ps
T1174 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3507279617 Mar 05 02:51:37 PM PST 24 Mar 05 02:51:39 PM PST 24 109254868 ps
T1175 /workspace/coverage/cover_reg_top/31.uart_intr_test.1838731532 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:51 PM PST 24 105014868 ps
T1176 /workspace/coverage/cover_reg_top/8.uart_csr_rw.327700388 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 58750133 ps
T1177 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2188479811 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:36 PM PST 24 41956773 ps
T70 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1269158515 Mar 05 02:51:24 PM PST 24 Mar 05 02:51:26 PM PST 24 532817104 ps
T71 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3738700575 Mar 05 02:51:21 PM PST 24 Mar 05 02:51:22 PM PST 24 40947420 ps
T1178 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.652745238 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:30 PM PST 24 61154774 ps
T1179 /workspace/coverage/cover_reg_top/5.uart_intr_test.3598180217 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:27 PM PST 24 50746354 ps
T1180 /workspace/coverage/cover_reg_top/43.uart_intr_test.778155002 Mar 05 02:51:54 PM PST 24 Mar 05 02:51:55 PM PST 24 19331867 ps
T1181 /workspace/coverage/cover_reg_top/39.uart_intr_test.365268510 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:53 PM PST 24 25183239 ps
T1182 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1899601955 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:29 PM PST 24 21187868 ps
T1183 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2995863975 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:43 PM PST 24 42057814 ps
T1184 /workspace/coverage/cover_reg_top/37.uart_intr_test.3705764444 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:50 PM PST 24 23817258 ps
T1185 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1316501888 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 36044261 ps
T1186 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2657755668 Mar 05 02:51:26 PM PST 24 Mar 05 02:51:27 PM PST 24 33120114 ps
T1187 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2228496702 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 158081221 ps
T1188 /workspace/coverage/cover_reg_top/48.uart_intr_test.371741693 Mar 05 02:51:52 PM PST 24 Mar 05 02:51:53 PM PST 24 22702486 ps
T1189 /workspace/coverage/cover_reg_top/0.uart_intr_test.2157278341 Mar 05 02:51:18 PM PST 24 Mar 05 02:51:19 PM PST 24 10596727 ps
T1190 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3163529369 Mar 05 02:51:27 PM PST 24 Mar 05 02:51:27 PM PST 24 92767421 ps
T1191 /workspace/coverage/cover_reg_top/25.uart_intr_test.4285984029 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 44598722 ps
T1192 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2488807087 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 323321322 ps
T1193 /workspace/coverage/cover_reg_top/1.uart_csr_rw.346470153 Mar 05 02:51:21 PM PST 24 Mar 05 02:51:22 PM PST 24 45855640 ps
T1194 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1777429060 Mar 05 02:51:39 PM PST 24 Mar 05 02:51:39 PM PST 24 18462834 ps
T1195 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.299824717 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:43 PM PST 24 114102117 ps
T1196 /workspace/coverage/cover_reg_top/7.uart_intr_test.360200127 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 34071147 ps
T1197 /workspace/coverage/cover_reg_top/32.uart_intr_test.2112949266 Mar 05 02:51:49 PM PST 24 Mar 05 02:51:50 PM PST 24 13936083 ps
T1198 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.101167674 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 22665795 ps
T1199 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3167324928 Mar 05 02:51:48 PM PST 24 Mar 05 02:51:49 PM PST 24 68137895 ps
T1200 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3631986380 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:48 PM PST 24 43354142 ps
T1201 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2088631571 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 12935007 ps
T1202 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3037059211 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:20 PM PST 24 46627721 ps
T1203 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3246403780 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:37 PM PST 24 183028003 ps
T1204 /workspace/coverage/cover_reg_top/18.uart_intr_test.4020595861 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:47 PM PST 24 18853872 ps
T1205 /workspace/coverage/cover_reg_top/41.uart_intr_test.725862769 Mar 05 02:51:51 PM PST 24 Mar 05 02:51:52 PM PST 24 21509450 ps
T1206 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3425426867 Mar 05 02:51:19 PM PST 24 Mar 05 02:51:22 PM PST 24 943868118 ps
T1207 /workspace/coverage/cover_reg_top/26.uart_intr_test.863480279 Mar 05 02:51:51 PM PST 24 Mar 05 02:51:51 PM PST 24 57653098 ps
T1208 /workspace/coverage/cover_reg_top/46.uart_intr_test.2979374641 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:50 PM PST 24 16994321 ps
T1209 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3721238241 Mar 05 02:51:46 PM PST 24 Mar 05 02:51:47 PM PST 24 138498589 ps
T72 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2010633078 Mar 05 02:51:29 PM PST 24 Mar 05 02:51:31 PM PST 24 58157789 ps
T1210 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.991805591 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 28341037 ps
T1211 /workspace/coverage/cover_reg_top/12.uart_intr_test.415298399 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:35 PM PST 24 38132639 ps
T1212 /workspace/coverage/cover_reg_top/47.uart_intr_test.2696706215 Mar 05 02:51:54 PM PST 24 Mar 05 02:51:54 PM PST 24 13423997 ps
T1213 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3468645132 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 95551635 ps
T73 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2150318530 Mar 05 02:51:32 PM PST 24 Mar 05 02:51:33 PM PST 24 15780394 ps
T1214 /workspace/coverage/cover_reg_top/9.uart_intr_test.2850727767 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:35 PM PST 24 18282477 ps
T1215 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4057217074 Mar 05 02:51:46 PM PST 24 Mar 05 02:51:46 PM PST 24 62917330 ps
T1216 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1249029658 Mar 05 02:51:48 PM PST 24 Mar 05 02:51:49 PM PST 24 30312135 ps
T1217 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3014888397 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 39825104 ps
T1218 /workspace/coverage/cover_reg_top/30.uart_intr_test.2592720113 Mar 05 02:51:50 PM PST 24 Mar 05 02:51:51 PM PST 24 12591787 ps
T1219 /workspace/coverage/cover_reg_top/15.uart_tl_errors.33266593 Mar 05 02:51:42 PM PST 24 Mar 05 02:51:45 PM PST 24 179264255 ps
T1220 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.293119238 Mar 05 02:51:45 PM PST 24 Mar 05 02:51:46 PM PST 24 420975990 ps
T1221 /workspace/coverage/cover_reg_top/1.uart_intr_test.1676214271 Mar 05 02:51:18 PM PST 24 Mar 05 02:51:19 PM PST 24 25643404 ps
T1222 /workspace/coverage/cover_reg_top/16.uart_intr_test.371664364 Mar 05 02:51:44 PM PST 24 Mar 05 02:51:45 PM PST 24 38873102 ps
T1223 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1440337695 Mar 05 02:51:34 PM PST 24 Mar 05 02:51:35 PM PST 24 40739941 ps
T1224 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2202284740 Mar 05 02:51:24 PM PST 24 Mar 05 02:51:25 PM PST 24 32240260 ps
T1225 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3475557183 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:30 PM PST 24 69756802 ps
T1226 /workspace/coverage/cover_reg_top/3.uart_intr_test.2793523465 Mar 05 02:51:28 PM PST 24 Mar 05 02:51:28 PM PST 24 45104771 ps
T1227 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1300487471 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 120028234 ps
T74 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3795842567 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:48 PM PST 24 20337071 ps
T1228 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1396628934 Mar 05 02:51:36 PM PST 24 Mar 05 02:51:37 PM PST 24 55720478 ps
T1229 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3424162289 Mar 05 02:51:41 PM PST 24 Mar 05 02:51:42 PM PST 24 63617217 ps
T1230 /workspace/coverage/cover_reg_top/20.uart_intr_test.3333195662 Mar 05 02:51:47 PM PST 24 Mar 05 02:51:47 PM PST 24 39120077 ps
T1231 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3835874136 Mar 05 02:51:35 PM PST 24 Mar 05 02:51:36 PM PST 24 51540078 ps
T1232 /workspace/coverage/cover_reg_top/14.uart_intr_test.3166256784 Mar 05 02:51:41 PM PST 24 Mar 05 02:51:41 PM PST 24 43798684 ps

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.939382301
Short name T9
Test name
Test status
Simulation time 560345194848 ps
CPU time 1228.86 seconds
Started Mar 05 01:33:24 PM PST 24
Finished Mar 05 01:53:53 PM PST 24
Peak memory 226436 kb
Host smart-e836b0b9-f0f2-4962-a14f-f7f085e9ca1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939382301 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.939382301
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.785002942
Short name T123
Test name
Test status
Simulation time 211710534817 ps
CPU time 367.74 seconds
Started Mar 05 01:40:55 PM PST 24
Finished Mar 05 01:47:03 PM PST 24
Peak memory 200356 kb
Host smart-ae0045fb-2942-428e-9869-6a2cd0d49de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785002942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.785002942
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3326625066
Short name T299
Test name
Test status
Simulation time 99797287461 ps
CPU time 441.54 seconds
Started Mar 05 01:39:27 PM PST 24
Finished Mar 05 01:46:49 PM PST 24
Peak memory 200372 kb
Host smart-9b561282-34d6-4592-977e-e708dbbbeed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326625066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3326625066
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_intr.1768028788
Short name T19
Test name
Test status
Simulation time 74779428476 ps
CPU time 77.85 seconds
Started Mar 05 01:34:36 PM PST 24
Finished Mar 05 01:35:54 PM PST 24
Peak memory 200348 kb
Host smart-198d1a5e-4e0c-429c-9b32-19cace648f6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768028788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1768028788
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/8.uart_stress_all.433005825
Short name T29
Test name
Test status
Simulation time 63167050472 ps
CPU time 537.43 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:42:35 PM PST 24
Peak memory 200336 kb
Host smart-27f9c2ee-ad94-4789-ad45-41a4d0920801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433005825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.433005825
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.995254685
Short name T138
Test name
Test status
Simulation time 181234004603 ps
CPU time 81.83 seconds
Started Mar 05 01:43:02 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 200352 kb
Host smart-5d644800-220e-47bc-9fc5-f7f400f9776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995254685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.995254685
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2895480639
Short name T41
Test name
Test status
Simulation time 224728441024 ps
CPU time 624.85 seconds
Started Mar 05 01:39:21 PM PST 24
Finished Mar 05 01:49:47 PM PST 24
Peak memory 216872 kb
Host smart-9c9f91ea-d589-4e1b-9807-bc5b0554e891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895480639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2895480639
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3014970304
Short name T39
Test name
Test status
Simulation time 112676824316 ps
CPU time 634.16 seconds
Started Mar 05 01:33:06 PM PST 24
Finished Mar 05 01:43:40 PM PST 24
Peak memory 225364 kb
Host smart-82093873-6200-45ef-b976-7b408002b846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014970304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3014970304
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.429489633
Short name T390
Test name
Test status
Simulation time 144757591729 ps
CPU time 267.41 seconds
Started Mar 05 01:34:12 PM PST 24
Finished Mar 05 01:38:39 PM PST 24
Peak memory 200232 kb
Host smart-2486933e-4e73-4654-a5b7-0210382a5a71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429489633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.429489633
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_stress_all.471005357
Short name T208
Test name
Test status
Simulation time 464219661000 ps
CPU time 241.6 seconds
Started Mar 05 01:38:04 PM PST 24
Finished Mar 05 01:42:06 PM PST 24
Peak memory 200356 kb
Host smart-4549c034-0522-4667-ac6b-fda88edb7406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471005357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.471005357
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all.3576281508
Short name T11
Test name
Test status
Simulation time 320058848527 ps
CPU time 131.49 seconds
Started Mar 05 01:34:56 PM PST 24
Finished Mar 05 01:37:09 PM PST 24
Peak memory 208796 kb
Host smart-0ffc7c87-cda7-4c34-b0b5-606dcaa0f9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576281508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3576281508
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_alert_test.1813906394
Short name T30
Test name
Test status
Simulation time 39555970 ps
CPU time 0.56 seconds
Started Mar 05 01:39:11 PM PST 24
Finished Mar 05 01:39:12 PM PST 24
Peak memory 195960 kb
Host smart-39a328e6-ed0c-4c4e-b555-c27643b0f0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813906394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1813906394
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3359966637
Short name T33
Test name
Test status
Simulation time 251313471 ps
CPU time 0.83 seconds
Started Mar 05 01:33:01 PM PST 24
Finished Mar 05 01:33:02 PM PST 24
Peak memory 217832 kb
Host smart-7130a183-3fcf-4a4c-a6ef-e8d411d230a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359966637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3359966637
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/16.uart_stress_all.1584343952
Short name T57
Test name
Test status
Simulation time 282439936048 ps
CPU time 447.14 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:41:32 PM PST 24
Peak memory 200336 kb
Host smart-9b073d95-8504-4a50-a802-f6c6656756fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584343952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1584343952
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.798891561
Short name T167
Test name
Test status
Simulation time 143276299969 ps
CPU time 40.92 seconds
Started Mar 05 01:43:02 PM PST 24
Finished Mar 05 01:43:44 PM PST 24
Peak memory 200360 kb
Host smart-2cf0099c-2ad4-4d0b-8e7d-a64ff227fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798891561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.798891561
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3823316608
Short name T27
Test name
Test status
Simulation time 76454575563 ps
CPU time 883.71 seconds
Started Mar 05 01:34:37 PM PST 24
Finished Mar 05 01:49:22 PM PST 24
Peak memory 225328 kb
Host smart-8914a38a-0aa0-4a3c-81c1-6a2d53857ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823316608 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3823316608
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2207192784
Short name T165
Test name
Test status
Simulation time 47363234895 ps
CPU time 79.86 seconds
Started Mar 05 01:40:49 PM PST 24
Finished Mar 05 01:42:09 PM PST 24
Peak memory 200344 kb
Host smart-a9dc93eb-2a5d-4a84-baeb-03ac9677547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207192784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2207192784
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.789092437
Short name T393
Test name
Test status
Simulation time 115450844682 ps
CPU time 265.22 seconds
Started Mar 05 01:37:29 PM PST 24
Finished Mar 05 01:41:55 PM PST 24
Peak memory 200300 kb
Host smart-ca830709-9df2-4eef-8cd9-7d976a54cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789092437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.789092437
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1536775572
Short name T89
Test name
Test status
Simulation time 76839220 ps
CPU time 1.26 seconds
Started Mar 05 02:51:21 PM PST 24
Finished Mar 05 02:51:22 PM PST 24
Peak memory 199212 kb
Host smart-a9dc64d0-59d6-4e58-aee3-9bc0662344f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536775572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1536775572
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.209130695
Short name T36
Test name
Test status
Simulation time 38486472420 ps
CPU time 489.87 seconds
Started Mar 05 01:39:58 PM PST 24
Finished Mar 05 01:48:13 PM PST 24
Peak memory 216864 kb
Host smart-4a755752-6a65-4573-95fb-e0ef8f6cbbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209130695 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.209130695
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_perf.3546761897
Short name T48
Test name
Test status
Simulation time 34508970232 ps
CPU time 1656.39 seconds
Started Mar 05 01:37:50 PM PST 24
Finished Mar 05 02:05:27 PM PST 24
Peak memory 200468 kb
Host smart-2c712f23-c1d7-41cb-b7df-33249a89b917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546761897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3546761897
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1761085938
Short name T50
Test name
Test status
Simulation time 191230353807 ps
CPU time 488.8 seconds
Started Mar 05 01:37:05 PM PST 24
Finished Mar 05 01:45:14 PM PST 24
Peak memory 200260 kb
Host smart-935b4d40-782b-4b93-9b0e-6fe0b1bf4507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761085938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1761085938
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_stress_all.1708117048
Short name T145
Test name
Test status
Simulation time 193966659314 ps
CPU time 143.74 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:35:59 PM PST 24
Peak memory 200388 kb
Host smart-db5c5dc1-f53a-4651-915d-adaf0a87632e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708117048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1708117048
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.1060823265
Short name T243
Test name
Test status
Simulation time 361064995416 ps
CPU time 840.58 seconds
Started Mar 05 01:35:53 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 208812 kb
Host smart-fc800de3-98e2-4a02-b408-a7c7daf84912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060823265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1060823265
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.627531392
Short name T37
Test name
Test status
Simulation time 59047644542 ps
CPU time 1444.54 seconds
Started Mar 05 01:40:56 PM PST 24
Finished Mar 05 02:05:01 PM PST 24
Peak memory 217044 kb
Host smart-6169be10-921f-4b9d-af5c-19dc00c8f82c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627531392 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.627531392
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3738700575
Short name T71
Test name
Test status
Simulation time 40947420 ps
CPU time 0.67 seconds
Started Mar 05 02:51:21 PM PST 24
Finished Mar 05 02:51:22 PM PST 24
Peak memory 194688 kb
Host smart-59f0d262-4e0a-4a3f-8096-71fa020acdf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738700575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3738700575
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2715765413
Short name T82
Test name
Test status
Simulation time 15059443 ps
CPU time 0.61 seconds
Started Mar 05 02:51:20 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 195508 kb
Host smart-7fbd2cf4-15d4-4b0f-858e-fa5755745e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715765413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2715765413
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2018061613
Short name T381
Test name
Test status
Simulation time 177369407590 ps
CPU time 684.6 seconds
Started Mar 05 01:34:37 PM PST 24
Finished Mar 05 01:46:02 PM PST 24
Peak memory 225308 kb
Host smart-4b7f0f68-8649-44ab-9107-02a4f1a12d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018061613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2018061613
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.603559837
Short name T161
Test name
Test status
Simulation time 89812432211 ps
CPU time 38.97 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:18 PM PST 24
Peak memory 200368 kb
Host smart-26d7df0b-7125-494a-98e4-5cb435abf740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603559837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.603559837
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2029833676
Short name T255
Test name
Test status
Simulation time 59087188340 ps
CPU time 21.05 seconds
Started Mar 05 01:42:53 PM PST 24
Finished Mar 05 01:43:14 PM PST 24
Peak memory 200176 kb
Host smart-b3891c68-598e-47f2-8dce-96de9a7a6b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029833676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2029833676
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2818950961
Short name T8
Test name
Test status
Simulation time 242689245060 ps
CPU time 34.8 seconds
Started Mar 05 01:33:21 PM PST 24
Finished Mar 05 01:33:56 PM PST 24
Peak memory 200364 kb
Host smart-e0612e96-87ff-4d01-b01d-453834f39ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818950961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2818950961
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2402498549
Short name T211
Test name
Test status
Simulation time 65160574497 ps
CPU time 62.95 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:45:03 PM PST 24
Peak memory 199988 kb
Host smart-d7a82605-fb61-4e68-80c9-f781cb7d0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402498549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2402498549
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.3838672680
Short name T120
Test name
Test status
Simulation time 304141638178 ps
CPU time 88.77 seconds
Started Mar 05 01:38:03 PM PST 24
Finished Mar 05 01:39:33 PM PST 24
Peak memory 200428 kb
Host smart-a33cc474-f3e4-4cd4-8b2a-d8c53dc3f979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838672680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3838672680
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.648431130
Short name T106
Test name
Test status
Simulation time 187529335621 ps
CPU time 494.01 seconds
Started Mar 05 01:40:31 PM PST 24
Finished Mar 05 01:48:45 PM PST 24
Peak memory 217044 kb
Host smart-20a0d872-8be5-4613-b5be-6bfd017a63ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648431130 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.648431130
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.293119238
Short name T1220
Test name
Test status
Simulation time 420975990 ps
CPU time 1.28 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 199392 kb
Host smart-4052a977-185f-4a6d-9d5a-e53a553f5dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293119238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.293119238
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1828122942
Short name T341
Test name
Test status
Simulation time 26715431599 ps
CPU time 23.57 seconds
Started Mar 05 01:41:19 PM PST 24
Finished Mar 05 01:41:42 PM PST 24
Peak memory 200404 kb
Host smart-b62220fe-ab2d-4f76-a4db-68167ee87908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828122942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1828122942
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2690089618
Short name T364
Test name
Test status
Simulation time 361707248862 ps
CPU time 155.94 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:36:44 PM PST 24
Peak memory 200148 kb
Host smart-9b5ef2fe-64b4-424c-8690-e054c7ffd25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690089618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2690089618
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.630523912
Short name T262
Test name
Test status
Simulation time 27200250493 ps
CPU time 34.34 seconds
Started Mar 05 01:43:46 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 200288 kb
Host smart-b9262247-4f46-4a8d-a450-3aeb9698ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630523912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.630523912
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1785011981
Short name T132
Test name
Test status
Simulation time 139912146652 ps
CPU time 88.34 seconds
Started Mar 05 01:41:21 PM PST 24
Finished Mar 05 01:42:49 PM PST 24
Peak memory 200304 kb
Host smart-cf1d94bb-697c-4697-9ee7-b0c2a6fcae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785011981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1785011981
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.393086038
Short name T339
Test name
Test status
Simulation time 49308753967 ps
CPU time 42.43 seconds
Started Mar 05 01:41:44 PM PST 24
Finished Mar 05 01:42:28 PM PST 24
Peak memory 200348 kb
Host smart-ec4467ad-a597-47d2-b049-6f55524b98e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393086038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.393086038
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3916238835
Short name T168
Test name
Test status
Simulation time 65304817433 ps
CPU time 17.3 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 200340 kb
Host smart-350afb33-0248-4cbc-b708-35c42339c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916238835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3916238835
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2673957647
Short name T290
Test name
Test status
Simulation time 121043091344 ps
CPU time 46.58 seconds
Started Mar 05 01:35:36 PM PST 24
Finished Mar 05 01:36:22 PM PST 24
Peak memory 200416 kb
Host smart-7b138eaa-6199-487d-b403-57cd62bd808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673957647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2673957647
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_intr.1265992676
Short name T20
Test name
Test status
Simulation time 459178613461 ps
CPU time 432.18 seconds
Started Mar 05 01:39:03 PM PST 24
Finished Mar 05 01:46:15 PM PST 24
Peak memory 200336 kb
Host smart-e3600350-940c-4a1c-8d35-99d9bcf73ab8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265992676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1265992676
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/7.uart_noise_filter.653973020
Short name T16
Test name
Test status
Simulation time 247100976645 ps
CPU time 121.56 seconds
Started Mar 05 01:33:28 PM PST 24
Finished Mar 05 01:35:30 PM PST 24
Peak memory 208560 kb
Host smart-9847699a-1d08-47f8-8b7b-0cdf866471fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653973020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.653973020
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2151642075
Short name T285
Test name
Test status
Simulation time 59591229705 ps
CPU time 38.48 seconds
Started Mar 05 01:33:43 PM PST 24
Finished Mar 05 01:34:22 PM PST 24
Peak memory 200436 kb
Host smart-7bc6a13d-d2ea-407d-8254-210651ef4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151642075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2151642075
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3505199562
Short name T210
Test name
Test status
Simulation time 29500605931 ps
CPU time 22.86 seconds
Started Mar 05 01:33:42 PM PST 24
Finished Mar 05 01:34:05 PM PST 24
Peak memory 200064 kb
Host smart-86a0d65b-cfe2-4f9c-9e3c-1617ab71f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505199562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3505199562
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3872954259
Short name T184
Test name
Test status
Simulation time 110479436067 ps
CPU time 169.74 seconds
Started Mar 05 01:42:04 PM PST 24
Finished Mar 05 01:44:54 PM PST 24
Peak memory 199632 kb
Host smart-fe7fa740-ddc1-45c7-b804-ff44c9e4d8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872954259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3872954259
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4176530182
Short name T156
Test name
Test status
Simulation time 147569933276 ps
CPU time 259.22 seconds
Started Mar 05 01:42:09 PM PST 24
Finished Mar 05 01:46:28 PM PST 24
Peak memory 199828 kb
Host smart-92533b0f-aa81-47df-8fc8-a7d0cb7b772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176530182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4176530182
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.642479076
Short name T334
Test name
Test status
Simulation time 96910007346 ps
CPU time 375.53 seconds
Started Mar 05 01:34:20 PM PST 24
Finished Mar 05 01:40:36 PM PST 24
Peak memory 217040 kb
Host smart-8b55aad0-a331-4313-943e-3f1bf08f38c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642479076 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.642479076
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.4188414731
Short name T181
Test name
Test status
Simulation time 332731878224 ps
CPU time 87.07 seconds
Started Mar 05 01:34:36 PM PST 24
Finished Mar 05 01:36:04 PM PST 24
Peak memory 200400 kb
Host smart-25bc73e4-984c-4afc-8161-3bd033c49501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188414731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4188414731
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3384940785
Short name T1011
Test name
Test status
Simulation time 23206465263 ps
CPU time 40.73 seconds
Started Mar 05 01:43:47 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 199652 kb
Host smart-6a1e329b-d2a6-40a2-917d-cb4015d35046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384940785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3384940785
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1869270122
Short name T2
Test name
Test status
Simulation time 101275728437 ps
CPU time 125.81 seconds
Started Mar 05 01:43:55 PM PST 24
Finished Mar 05 01:46:01 PM PST 24
Peak memory 200248 kb
Host smart-e556b71e-21a8-4afd-83e6-15a01e25bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869270122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1869270122
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.4166855308
Short name T363
Test name
Test status
Simulation time 268923700919 ps
CPU time 423.89 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:42:31 PM PST 24
Peak memory 200240 kb
Host smart-61d6d9f8-d892-4f72-b1e6-9ca115e0e698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166855308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4166855308
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3013678607
Short name T343
Test name
Test status
Simulation time 43238458341 ps
CPU time 75.17 seconds
Started Mar 05 01:40:18 PM PST 24
Finished Mar 05 01:41:34 PM PST 24
Peak memory 200396 kb
Host smart-4a35e6cd-ceb4-493d-bfa8-cad99212ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013678607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3013678607
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2718466488
Short name T40
Test name
Test status
Simulation time 184736734585 ps
CPU time 327.08 seconds
Started Mar 05 01:40:56 PM PST 24
Finished Mar 05 01:46:23 PM PST 24
Peak memory 216532 kb
Host smart-a61cef9e-c150-4537-8f2f-643f7a48c11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718466488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2718466488
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.4242912527
Short name T270
Test name
Test status
Simulation time 247719285727 ps
CPU time 207.91 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:36:34 PM PST 24
Peak memory 200388 kb
Host smart-e48b03d4-9e09-49c9-aed1-6236f9e54bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242912527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4242912527
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1395116716
Short name T687
Test name
Test status
Simulation time 29678352209 ps
CPU time 25.56 seconds
Started Mar 05 01:41:20 PM PST 24
Finished Mar 05 01:41:46 PM PST 24
Peak memory 200320 kb
Host smart-ccac0bfb-a6aa-49ca-8ccc-6dd5d0a01cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395116716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1395116716
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2098781868
Short name T192
Test name
Test status
Simulation time 283960434113 ps
CPU time 58.38 seconds
Started Mar 05 01:42:00 PM PST 24
Finished Mar 05 01:42:59 PM PST 24
Peak memory 199640 kb
Host smart-fae336a0-c79e-4fd9-a2f2-11834e62fb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098781868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2098781868
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2353677670
Short name T261
Test name
Test status
Simulation time 220983074915 ps
CPU time 97.96 seconds
Started Mar 05 01:38:33 PM PST 24
Finished Mar 05 01:40:11 PM PST 24
Peak memory 200324 kb
Host smart-86898ffc-d853-4549-bf08-1076e4551804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353677670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2353677670
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1927502679
Short name T372
Test name
Test status
Simulation time 46497138581 ps
CPU time 42.25 seconds
Started Mar 05 01:39:17 PM PST 24
Finished Mar 05 01:40:01 PM PST 24
Peak memory 199448 kb
Host smart-c2086d2e-3447-44c3-8657-1b59cc6fc6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927502679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1927502679
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3993453768
Short name T240
Test name
Test status
Simulation time 29329308383 ps
CPU time 25.84 seconds
Started Mar 05 01:40:15 PM PST 24
Finished Mar 05 01:40:41 PM PST 24
Peak memory 200148 kb
Host smart-14b6b919-f448-429a-922f-85a2169052ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993453768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3993453768
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1609975580
Short name T319
Test name
Test status
Simulation time 132198239853 ps
CPU time 637.29 seconds
Started Mar 05 01:40:31 PM PST 24
Finished Mar 05 01:51:09 PM PST 24
Peak memory 216928 kb
Host smart-b4241a99-c1b2-4c95-b0af-884f9e9fe138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609975580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1609975580
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1261970004
Short name T136
Test name
Test status
Simulation time 109843312165 ps
CPU time 51.36 seconds
Started Mar 05 01:32:53 PM PST 24
Finished Mar 05 01:33:44 PM PST 24
Peak memory 200304 kb
Host smart-f43fb455-18bc-4565-b784-82af637f4398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261970004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1261970004
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1319707923
Short name T1089
Test name
Test status
Simulation time 30421260618 ps
CPU time 40.96 seconds
Started Mar 05 01:33:46 PM PST 24
Finished Mar 05 01:34:28 PM PST 24
Peak memory 200320 kb
Host smart-4567f59c-21aa-455c-baa9-746259a639a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319707923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1319707923
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2456319414
Short name T374
Test name
Test status
Simulation time 127537401652 ps
CPU time 17.26 seconds
Started Mar 05 01:41:19 PM PST 24
Finished Mar 05 01:41:37 PM PST 24
Peak memory 200284 kb
Host smart-79b1133b-728d-4581-bf01-a050ce475872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456319414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2456319414
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.2189037857
Short name T376
Test name
Test status
Simulation time 87197563744 ps
CPU time 100.58 seconds
Started Mar 05 01:34:01 PM PST 24
Finished Mar 05 01:35:42 PM PST 24
Peak memory 200388 kb
Host smart-6fc84805-3cde-4de8-8110-674ba779d319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189037857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2189037857
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.228581017
Short name T289
Test name
Test status
Simulation time 54828903710 ps
CPU time 20.18 seconds
Started Mar 05 01:41:35 PM PST 24
Finished Mar 05 01:41:56 PM PST 24
Peak memory 200052 kb
Host smart-b42d9128-68e9-4d68-a57a-c9a6c465fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228581017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.228581017
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3738295475
Short name T173
Test name
Test status
Simulation time 19577649000 ps
CPU time 29.98 seconds
Started Mar 05 01:41:35 PM PST 24
Finished Mar 05 01:42:05 PM PST 24
Peak memory 200420 kb
Host smart-d92312b2-1301-4638-affc-196aa252da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738295475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3738295475
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3044453052
Short name T7
Test name
Test status
Simulation time 60472873060 ps
CPU time 22.95 seconds
Started Mar 05 01:41:54 PM PST 24
Finished Mar 05 01:42:17 PM PST 24
Peak memory 199096 kb
Host smart-71872f08-9a27-41e3-9d96-91ac0b96e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044453052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3044453052
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.511824189
Short name T314
Test name
Test status
Simulation time 171542987361 ps
CPU time 76.93 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:35:22 PM PST 24
Peak memory 200392 kb
Host smart-55ce0db2-92e0-4264-945e-07ecb6cfd45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511824189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.511824189
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3016685472
Short name T265
Test name
Test status
Simulation time 19721843621 ps
CPU time 17.66 seconds
Started Mar 05 01:42:23 PM PST 24
Finished Mar 05 01:42:41 PM PST 24
Peak memory 200184 kb
Host smart-ce3e0b05-805b-49c5-865c-e32cb6e885ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016685472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3016685472
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2848371631
Short name T892
Test name
Test status
Simulation time 47695918298 ps
CPU time 52.4 seconds
Started Mar 05 01:42:30 PM PST 24
Finished Mar 05 01:43:23 PM PST 24
Peak memory 200288 kb
Host smart-c99d6139-c12c-4d24-ba4c-ebd625f5c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848371631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2848371631
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3340939644
Short name T233
Test name
Test status
Simulation time 34299919560 ps
CPU time 31.37 seconds
Started Mar 05 01:43:09 PM PST 24
Finished Mar 05 01:43:40 PM PST 24
Peak memory 199732 kb
Host smart-5723648b-0693-4196-80bd-83625aee720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340939644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3340939644
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.1647245111
Short name T296
Test name
Test status
Simulation time 1827282456726 ps
CPU time 962.44 seconds
Started Mar 05 01:34:53 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 200340 kb
Host smart-d5d3abd5-061c-4c7f-911e-161018eceab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647245111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1647245111
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1699339200
Short name T1078
Test name
Test status
Simulation time 80170779800 ps
CPU time 127.39 seconds
Started Mar 05 01:43:55 PM PST 24
Finished Mar 05 01:46:03 PM PST 24
Peak memory 200288 kb
Host smart-fb4b1944-c889-45e1-9951-3549ed369aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699339200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1699339200
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.221909090
Short name T232
Test name
Test status
Simulation time 96306426380 ps
CPU time 122.53 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:46:03 PM PST 24
Peak memory 200260 kb
Host smart-6a72c057-8dff-4b87-b2b8-f50ee56f451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221909090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.221909090
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2743991985
Short name T253
Test name
Test status
Simulation time 152220826888 ps
CPU time 250.97 seconds
Started Mar 05 01:40:51 PM PST 24
Finished Mar 05 01:45:02 PM PST 24
Peak memory 200412 kb
Host smart-3f8bacc0-9d6e-4c2e-b873-3c3ef67ea716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743991985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2743991985
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.147978446
Short name T382
Test name
Test status
Simulation time 35182313694 ps
CPU time 630.22 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 216248 kb
Host smart-1977fe74-e65b-49a8-b397-75192585d36c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147978446 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.147978446
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2700964392
Short name T201
Test name
Test status
Simulation time 50734055064 ps
CPU time 34.53 seconds
Started Mar 05 01:41:21 PM PST 24
Finished Mar 05 01:41:56 PM PST 24
Peak memory 200240 kb
Host smart-f7cb5c17-b303-4c8c-94bb-511b9df7faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700964392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2700964392
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1863937399
Short name T218
Test name
Test status
Simulation time 86448610557 ps
CPU time 39.39 seconds
Started Mar 05 01:41:20 PM PST 24
Finished Mar 05 01:41:59 PM PST 24
Peak memory 200336 kb
Host smart-a72d1c90-6b21-4728-b13d-c96ed861a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863937399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1863937399
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4209020291
Short name T317
Test name
Test status
Simulation time 177446713208 ps
CPU time 58.08 seconds
Started Mar 05 01:41:36 PM PST 24
Finished Mar 05 01:42:35 PM PST 24
Peak memory 200196 kb
Host smart-bdf63640-0598-4acf-a0b6-d8bf907bd22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209020291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4209020291
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4122031051
Short name T171
Test name
Test status
Simulation time 31492391353 ps
CPU time 33.84 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:36 PM PST 24
Peak memory 200400 kb
Host smart-6777c237-055d-4e62-8c9a-83f14210012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122031051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4122031051
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2482823678
Short name T327
Test name
Test status
Simulation time 95979448385 ps
CPU time 42.07 seconds
Started Mar 05 01:41:56 PM PST 24
Finished Mar 05 01:42:38 PM PST 24
Peak memory 200352 kb
Host smart-6e26c688-452a-4a35-9a14-81685eaf1181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482823678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2482823678
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3062232922
Short name T380
Test name
Test status
Simulation time 34822662534 ps
CPU time 14.9 seconds
Started Mar 05 01:42:00 PM PST 24
Finished Mar 05 01:42:15 PM PST 24
Peak memory 200308 kb
Host smart-1c4fef1a-5369-469e-be8b-94a2a94fcc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062232922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3062232922
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3544766767
Short name T345
Test name
Test status
Simulation time 378819559874 ps
CPU time 49.62 seconds
Started Mar 05 01:34:12 PM PST 24
Finished Mar 05 01:35:01 PM PST 24
Peak memory 200240 kb
Host smart-2d6c66b2-513f-4a68-8dd3-a6580bbaf71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544766767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3544766767
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_perf.2745630701
Short name T297
Test name
Test status
Simulation time 15888944885 ps
CPU time 836.16 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:48:04 PM PST 24
Peak memory 200424 kb
Host smart-1a7454e4-8b36-4f2e-b76a-2962f05ca303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745630701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2745630701
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3659337629
Short name T142
Test name
Test status
Simulation time 27585927649 ps
CPU time 13.08 seconds
Started Mar 05 01:42:18 PM PST 24
Finished Mar 05 01:42:32 PM PST 24
Peak memory 200408 kb
Host smart-26ab569a-700a-4426-a7e2-1daecba4f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659337629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3659337629
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.2721095003
Short name T277
Test name
Test status
Simulation time 201701970671 ps
CPU time 481.72 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:41:09 PM PST 24
Peak memory 200304 kb
Host smart-970fc029-074e-442d-b4b7-62e8f9f3a7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721095003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2721095003
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.575427193
Short name T284
Test name
Test status
Simulation time 106705747132 ps
CPU time 181.44 seconds
Started Mar 05 01:42:40 PM PST 24
Finished Mar 05 01:45:42 PM PST 24
Peak memory 200392 kb
Host smart-15f100f6-4cc5-4a70-9c44-3442cf223ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575427193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.575427193
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3893503033
Short name T148
Test name
Test status
Simulation time 19102713595 ps
CPU time 32.89 seconds
Started Mar 05 01:42:40 PM PST 24
Finished Mar 05 01:43:14 PM PST 24
Peak memory 200312 kb
Host smart-ed6957e9-ac3a-490e-88b2-7fdf25ceea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893503033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3893503033
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4031954759
Short name T259
Test name
Test status
Simulation time 79263965527 ps
CPU time 100.65 seconds
Started Mar 05 01:42:47 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 200424 kb
Host smart-edcf068c-e0f5-4e7d-8303-0fef53a4770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031954759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4031954759
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1956569428
Short name T268
Test name
Test status
Simulation time 116356935997 ps
CPU time 46.18 seconds
Started Mar 05 01:42:52 PM PST 24
Finished Mar 05 01:43:39 PM PST 24
Peak memory 200404 kb
Host smart-996f64a3-d301-4f30-9552-4fb41a3e4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956569428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1956569428
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4209069175
Short name T292
Test name
Test status
Simulation time 110213222079 ps
CPU time 108.56 seconds
Started Mar 05 01:34:46 PM PST 24
Finished Mar 05 01:36:35 PM PST 24
Peak memory 200300 kb
Host smart-cdba03d2-465c-4094-a216-6384e2e6f340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209069175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4209069175
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_perf.2741895910
Short name T288
Test name
Test status
Simulation time 25212304713 ps
CPU time 574.34 seconds
Started Mar 05 01:34:48 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 200384 kb
Host smart-2b846cd1-baba-40b2-8628-ab2a5164910e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741895910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2741895910
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4147266692
Short name T28
Test name
Test status
Simulation time 17821449515 ps
CPU time 157.94 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:37:22 PM PST 24
Peak memory 209964 kb
Host smart-2aa9ccfa-2d48-4e53-8e30-f6fe7f9e83fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147266692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4147266692
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1923713961
Short name T242
Test name
Test status
Simulation time 122212793575 ps
CPU time 19.95 seconds
Started Mar 05 01:43:35 PM PST 24
Finished Mar 05 01:43:55 PM PST 24
Peak memory 199544 kb
Host smart-825532cb-0dcf-4a7c-8b7e-f96774c6b489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923713961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1923713961
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3523144122
Short name T300
Test name
Test status
Simulation time 115044847169 ps
CPU time 38.47 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 199840 kb
Host smart-818534d3-c0d3-4fbb-acb1-7ba26253756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523144122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3523144122
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1896219848
Short name T191
Test name
Test status
Simulation time 45666120581 ps
CPU time 61.41 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:45:01 PM PST 24
Peak memory 199988 kb
Host smart-5acde4b6-f81d-4d4f-954b-6eba089de75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896219848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1896219848
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1874859995
Short name T337
Test name
Test status
Simulation time 15221288666 ps
CPU time 39.06 seconds
Started Mar 05 01:43:57 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 200316 kb
Host smart-098b0b1e-8835-49ae-8238-8ea13dc924f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874859995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1874859995
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.1124444389
Short name T287
Test name
Test status
Simulation time 117187162684 ps
CPU time 1554.9 seconds
Started Mar 05 01:35:18 PM PST 24
Finished Mar 05 02:01:13 PM PST 24
Peak memory 208740 kb
Host smart-a02caa57-207e-40fb-b877-729a8a5ea8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124444389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1124444389
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3392658009
Short name T180
Test name
Test status
Simulation time 11861854955 ps
CPU time 18.77 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 199856 kb
Host smart-ed1d1d29-960b-41b8-ba4e-169055a57291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392658009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3392658009
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1786541699
Short name T442
Test name
Test status
Simulation time 10285184296 ps
CPU time 120.95 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:37:28 PM PST 24
Peak memory 208760 kb
Host smart-7fc2c2ae-9d01-4eb7-a16f-e69de831c04d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786541699 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1786541699
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2531641544
Short name T291
Test name
Test status
Simulation time 65710438923 ps
CPU time 107.09 seconds
Started Mar 05 01:35:42 PM PST 24
Finished Mar 05 01:37:29 PM PST 24
Peak memory 200360 kb
Host smart-e7de54d5-9750-4bd9-bde6-5e47709cfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531641544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2531641544
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3586260527
Short name T346
Test name
Test status
Simulation time 32941300935 ps
CPU time 12.94 seconds
Started Mar 05 01:35:59 PM PST 24
Finished Mar 05 01:36:13 PM PST 24
Peak memory 200296 kb
Host smart-d6b626ca-2a06-44a4-a283-5870243f57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586260527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3586260527
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3050582616
Short name T379
Test name
Test status
Simulation time 91802479222 ps
CPU time 83.27 seconds
Started Mar 05 01:36:21 PM PST 24
Finished Mar 05 01:37:45 PM PST 24
Peak memory 200304 kb
Host smart-50f4ab34-c1a6-46ab-904b-6ad7504ea257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050582616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3050582616
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1287002010
Short name T293
Test name
Test status
Simulation time 82710604826 ps
CPU time 164.74 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:36:07 PM PST 24
Peak memory 200272 kb
Host smart-f52b76e7-ece4-4546-8389-408f63daf786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287002010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1287002010
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_stress_all.3282134030
Short name T294
Test name
Test status
Simulation time 132921565232 ps
CPU time 610.67 seconds
Started Mar 05 01:37:23 PM PST 24
Finished Mar 05 01:47:34 PM PST 24
Peak memory 216140 kb
Host smart-3415a5b4-4a29-4aa5-8404-ec75808bd674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282134030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3282134030
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4220592387
Short name T371
Test name
Test status
Simulation time 69793870636 ps
CPU time 9.76 seconds
Started Mar 05 01:37:23 PM PST 24
Finished Mar 05 01:37:33 PM PST 24
Peak memory 199436 kb
Host smart-6989cc21-c5ba-491d-b5cd-45288dccc01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220592387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4220592387
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3738711971
Short name T55
Test name
Test status
Simulation time 24989365110 ps
CPU time 31.06 seconds
Started Mar 05 01:39:04 PM PST 24
Finished Mar 05 01:39:35 PM PST 24
Peak memory 200324 kb
Host smart-673dc634-1c59-4763-abf7-d5721995c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738711971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3738711971
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3446188071
Short name T375
Test name
Test status
Simulation time 87136933885 ps
CPU time 42 seconds
Started Mar 05 01:33:23 PM PST 24
Finished Mar 05 01:34:06 PM PST 24
Peak memory 200408 kb
Host smart-49262c36-e25c-4b18-8209-8f8f257a0b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446188071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3446188071
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.871591125
Short name T370
Test name
Test status
Simulation time 140206923312 ps
CPU time 56.99 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:34:17 PM PST 24
Peak memory 200336 kb
Host smart-e69ccfa1-77a5-491b-8823-afd4480779f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871591125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.871591125
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3315190622
Short name T157
Test name
Test status
Simulation time 68702685148 ps
CPU time 11.58 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:33:34 PM PST 24
Peak memory 200348 kb
Host smart-1ca02f6b-98fb-44d5-8d63-ebbf94427ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315190622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3315190622
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.730046671
Short name T324
Test name
Test status
Simulation time 47932494756 ps
CPU time 22.95 seconds
Started Mar 05 01:40:13 PM PST 24
Finished Mar 05 01:40:36 PM PST 24
Peak memory 200264 kb
Host smart-7acf4465-2b51-41ba-8774-46779e9137cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730046671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.730046671
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1103639090
Short name T170
Test name
Test status
Simulation time 178232735679 ps
CPU time 84.41 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 200380 kb
Host smart-e108396b-64bb-485f-87af-197dddc221f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103639090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1103639090
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2631600481
Short name T46
Test name
Test status
Simulation time 48905686509 ps
CPU time 38 seconds
Started Mar 05 01:41:01 PM PST 24
Finished Mar 05 01:41:39 PM PST 24
Peak memory 200244 kb
Host smart-f7098434-6b15-4480-b695-c0f3c478da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631600481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2631600481
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3425426867
Short name T1206
Test name
Test status
Simulation time 943868118 ps
CPU time 2.56 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:22 PM PST 24
Peak memory 198032 kb
Host smart-a37e5550-e180-4b30-a30f-d4cb5bcb8c1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425426867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3425426867
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4269026242
Short name T1134
Test name
Test status
Simulation time 15817159 ps
CPU time 0.63 seconds
Started Mar 05 02:51:22 PM PST 24
Finished Mar 05 02:51:23 PM PST 24
Peak memory 195536 kb
Host smart-b1e8077b-8adb-44a6-8d65-f1730389d563
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269026242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4269026242
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1849676314
Short name T1173
Test name
Test status
Simulation time 37527668 ps
CPU time 0.9 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:21 PM PST 24
Peak memory 199948 kb
Host smart-3aa007aa-a15a-4e17-be4a-ad28745095bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849676314 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1849676314
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2157278341
Short name T1189
Test name
Test status
Simulation time 10596727 ps
CPU time 0.57 seconds
Started Mar 05 02:51:18 PM PST 24
Finished Mar 05 02:51:19 PM PST 24
Peak memory 194492 kb
Host smart-3959d1b0-c928-4caf-89d4-078358535bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157278341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2157278341
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3037059211
Short name T1202
Test name
Test status
Simulation time 46627721 ps
CPU time 0.66 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 195636 kb
Host smart-56d9090a-37d0-4d96-98b9-b8cbed8604ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037059211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3037059211
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3092653360
Short name T1160
Test name
Test status
Simulation time 213483772 ps
CPU time 1.4 seconds
Started Mar 05 02:51:20 PM PST 24
Finished Mar 05 02:51:21 PM PST 24
Peak memory 200044 kb
Host smart-e68996b2-675c-41c7-ad73-13f0cd05f2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092653360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3092653360
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3456234916
Short name T86
Test name
Test status
Simulation time 94755761 ps
CPU time 1.41 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 199196 kb
Host smart-51142422-bed6-4ed9-9d3e-40374593b299
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456234916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3456234916
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.545369271
Short name T65
Test name
Test status
Simulation time 37894105 ps
CPU time 0.69 seconds
Started Mar 05 02:51:18 PM PST 24
Finished Mar 05 02:51:19 PM PST 24
Peak memory 195532 kb
Host smart-fbbd4097-56a2-4cec-9c48-2850ef8c48e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545369271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.545369271
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.572257068
Short name T1137
Test name
Test status
Simulation time 104669493 ps
CPU time 1.6 seconds
Started Mar 05 02:51:18 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 197716 kb
Host smart-4b732dfd-e0d0-46a8-bf74-cdf9a72373c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572257068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.572257068
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3640896334
Short name T1123
Test name
Test status
Simulation time 43537244 ps
CPU time 0.58 seconds
Started Mar 05 02:51:20 PM PST 24
Finished Mar 05 02:51:21 PM PST 24
Peak memory 195624 kb
Host smart-d14564b2-8b0b-4410-912a-97f26138e34c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640896334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3640896334
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1902815734
Short name T1104
Test name
Test status
Simulation time 20191242 ps
CPU time 1.03 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 199964 kb
Host smart-5315f7ce-a448-4b57-9b79-f0cba64a060e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902815734 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1902815734
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.346470153
Short name T1193
Test name
Test status
Simulation time 45855640 ps
CPU time 0.67 seconds
Started Mar 05 02:51:21 PM PST 24
Finished Mar 05 02:51:22 PM PST 24
Peak memory 195676 kb
Host smart-9e89a545-aa66-4584-be41-639385b9c3be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346470153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.346470153
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1676214271
Short name T1221
Test name
Test status
Simulation time 25643404 ps
CPU time 0.56 seconds
Started Mar 05 02:51:18 PM PST 24
Finished Mar 05 02:51:19 PM PST 24
Peak memory 194516 kb
Host smart-0a34e1d9-4bae-4458-bf60-db06ea6ac580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676214271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1676214271
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2202284740
Short name T1224
Test name
Test status
Simulation time 32240260 ps
CPU time 0.81 seconds
Started Mar 05 02:51:24 PM PST 24
Finished Mar 05 02:51:25 PM PST 24
Peak memory 195992 kb
Host smart-95f51345-ec54-4955-9fe5-4788c9da1824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202284740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2202284740
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.97613002
Short name T1150
Test name
Test status
Simulation time 34384770 ps
CPU time 0.94 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 199936 kb
Host smart-b450825f-95ad-4e9f-b421-50e209cd9939
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97613002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.97613002
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1777429060
Short name T1194
Test name
Test status
Simulation time 18462834 ps
CPU time 0.73 seconds
Started Mar 05 02:51:39 PM PST 24
Finished Mar 05 02:51:39 PM PST 24
Peak memory 197808 kb
Host smart-2af7ac57-b124-451b-95cd-ff55c1b4a30c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777429060 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1777429060
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2228496702
Short name T1187
Test name
Test status
Simulation time 158081221 ps
CPU time 0.66 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 195572 kb
Host smart-ccc0f418-9ae8-49a1-a7c4-d95594d786e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228496702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2228496702
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2057021274
Short name T1114
Test name
Test status
Simulation time 14441639 ps
CPU time 0.58 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 194516 kb
Host smart-19f8345c-29a6-4fde-a473-0ff07c4525e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057021274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2057021274
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3468645132
Short name T1213
Test name
Test status
Simulation time 95551635 ps
CPU time 0.8 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 195916 kb
Host smart-60984cc4-c43d-4525-855a-ea6a148f33c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468645132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3468645132
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3507279617
Short name T1174
Test name
Test status
Simulation time 109254868 ps
CPU time 1.94 seconds
Started Mar 05 02:51:37 PM PST 24
Finished Mar 05 02:51:39 PM PST 24
Peak memory 200192 kb
Host smart-43cb2cde-c716-4f23-b779-1b648bd278f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507279617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3507279617
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1300487471
Short name T1227
Test name
Test status
Simulation time 120028234 ps
CPU time 0.96 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 198900 kb
Host smart-bc5188d4-08c7-465f-9da1-b25b8a260244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300487471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1300487471
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3835874136
Short name T1231
Test name
Test status
Simulation time 51540078 ps
CPU time 0.74 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 198396 kb
Host smart-791b9181-e931-412d-8da6-396578cb6192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835874136 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3835874136
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2508409675
Short name T68
Test name
Test status
Simulation time 14368798 ps
CPU time 0.6 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195556 kb
Host smart-00320376-e101-41d3-bc91-cf9ee5cfb9f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508409675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2508409675
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1767539020
Short name T1127
Test name
Test status
Simulation time 12948277 ps
CPU time 0.58 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 194496 kb
Host smart-4160f12e-05d0-44d1-815e-4f786da4b448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767539020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1767539020
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1602978416
Short name T77
Test name
Test status
Simulation time 21343976 ps
CPU time 0.66 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195816 kb
Host smart-5a72164e-4c48-4615-a791-87e67d49d03b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602978416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1602978416
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2830179625
Short name T1107
Test name
Test status
Simulation time 54852981 ps
CPU time 1.49 seconds
Started Mar 05 02:51:37 PM PST 24
Finished Mar 05 02:51:39 PM PST 24
Peak memory 200128 kb
Host smart-784889d5-65a1-4b05-a3d7-a727ca155960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830179625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2830179625
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3794506291
Short name T87
Test name
Test status
Simulation time 85016859 ps
CPU time 1.29 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 199288 kb
Host smart-eee054c6-9bfe-4e54-a6f3-3b9a36b01c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794506291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3794506291
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3424162289
Short name T1229
Test name
Test status
Simulation time 63617217 ps
CPU time 0.71 seconds
Started Mar 05 02:51:41 PM PST 24
Finished Mar 05 02:51:42 PM PST 24
Peak memory 198112 kb
Host smart-665b4616-46b2-4c41-9ac1-2575cd781a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424162289 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3424162289
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3014888397
Short name T1217
Test name
Test status
Simulation time 39825104 ps
CPU time 0.6 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195536 kb
Host smart-778f521b-d66c-448f-91d1-e7efb0ed5224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014888397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3014888397
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.415298399
Short name T1211
Test name
Test status
Simulation time 38132639 ps
CPU time 0.55 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:35 PM PST 24
Peak memory 194516 kb
Host smart-8e1e15f5-9132-45aa-bc4f-1dd6d952f0e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415298399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.415298399
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1396628934
Short name T1228
Test name
Test status
Simulation time 55720478 ps
CPU time 0.71 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 195644 kb
Host smart-990ace35-3f9b-4004-9567-bb0e0a0b54bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396628934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1396628934
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3246403780
Short name T1203
Test name
Test status
Simulation time 183028003 ps
CPU time 1.88 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 200192 kb
Host smart-39bd3775-ddc9-4c2c-b6e3-db67d218e0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246403780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3246403780
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.271860691
Short name T85
Test name
Test status
Simulation time 102417729 ps
CPU time 0.99 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 198624 kb
Host smart-34d1c9ff-53fd-4c09-a365-8813d3e98471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271860691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.271860691
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1098241686
Short name T1168
Test name
Test status
Simulation time 65448624 ps
CPU time 0.92 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:44 PM PST 24
Peak memory 199988 kb
Host smart-cb2a1532-2ce1-4713-b6d0-e3d8ae5a0212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098241686 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1098241686
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.854288186
Short name T1125
Test name
Test status
Simulation time 25604489 ps
CPU time 0.59 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 195532 kb
Host smart-6a345f4a-3a2e-46fa-a03b-04a81ea897c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854288186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.854288186
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3986265378
Short name T1145
Test name
Test status
Simulation time 26810728 ps
CPU time 0.59 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194564 kb
Host smart-3b4f172f-c356-46b3-a9b5-da7f29dab63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986265378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3986265378
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4027956342
Short name T75
Test name
Test status
Simulation time 29128404 ps
CPU time 0.77 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 196952 kb
Host smart-2c4528b7-515a-4743-ba11-7479918e3ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027956342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4027956342
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3333068283
Short name T1144
Test name
Test status
Simulation time 24302612 ps
CPU time 1.21 seconds
Started Mar 05 02:51:46 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 200128 kb
Host smart-de55855c-e738-4174-9f6c-9fed642b671d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333068283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3333068283
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3721238241
Short name T1209
Test name
Test status
Simulation time 138498589 ps
CPU time 0.92 seconds
Started Mar 05 02:51:46 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 198660 kb
Host smart-83435843-12a6-48f4-9667-9d87bd58022a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721238241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3721238241
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3245097663
Short name T1147
Test name
Test status
Simulation time 29082695 ps
CPU time 0.68 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:44 PM PST 24
Peak memory 197748 kb
Host smart-27a32e04-45b7-477a-97b7-cd730e432f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245097663 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3245097663
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3898290564
Short name T64
Test name
Test status
Simulation time 37899353 ps
CPU time 0.59 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 195556 kb
Host smart-a5de486a-e689-4ca4-af8d-b53072e7e298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898290564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3898290564
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3166256784
Short name T1232
Test name
Test status
Simulation time 43798684 ps
CPU time 0.56 seconds
Started Mar 05 02:51:41 PM PST 24
Finished Mar 05 02:51:41 PM PST 24
Peak memory 194560 kb
Host smart-09607f15-d765-47bc-8fa2-b9b01ce24c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166256784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3166256784
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4057217074
Short name T1215
Test name
Test status
Simulation time 62917330 ps
CPU time 0.66 seconds
Started Mar 05 02:51:46 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 195604 kb
Host smart-793d633c-7b59-44a6-870c-ccbc1f1122ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057217074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4057217074
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1416466102
Short name T1096
Test name
Test status
Simulation time 110901981 ps
CPU time 1.23 seconds
Started Mar 05 02:51:46 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 199848 kb
Host smart-ec1965dd-a4b8-471b-ae50-5f3362d1795c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416466102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1416466102
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2129435675
Short name T84
Test name
Test status
Simulation time 89459296 ps
CPU time 0.96 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 198796 kb
Host smart-950acc82-df2c-495e-a39f-4a0e945f4b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129435675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2129435675
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.299824717
Short name T1195
Test name
Test status
Simulation time 114102117 ps
CPU time 0.84 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 199948 kb
Host smart-020b0aa2-4ced-409d-b498-ef73bbbb429d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299824717 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.299824717
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1059415012
Short name T66
Test name
Test status
Simulation time 41566867 ps
CPU time 0.59 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 195544 kb
Host smart-864b1c90-d672-413f-9e54-4d13a52337c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059415012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1059415012
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.30535376
Short name T1155
Test name
Test status
Simulation time 26230102 ps
CPU time 0.59 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194480 kb
Host smart-7c9b3048-ce4a-42cf-9957-6c38df5bd523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30535376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.30535376
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1316501888
Short name T1185
Test name
Test status
Simulation time 36044261 ps
CPU time 0.71 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194560 kb
Host smart-6a1dc8e2-ca8b-465f-bc6d-df64ae071068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316501888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1316501888
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.33266593
Short name T1219
Test name
Test status
Simulation time 179264255 ps
CPU time 2.26 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 200124 kb
Host smart-43778d63-d955-4a1c-9734-3f65e19bb179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.33266593
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.991805591
Short name T1210
Test name
Test status
Simulation time 28341037 ps
CPU time 0.87 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 199324 kb
Host smart-289b3bba-5eda-4547-a4ce-3883b914a5e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991805591 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.991805591
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1138402354
Short name T1166
Test name
Test status
Simulation time 56324650 ps
CPU time 0.59 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:44 PM PST 24
Peak memory 195632 kb
Host smart-e2831303-a372-453d-8084-c874a0ff5a20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138402354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1138402354
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.371664364
Short name T1222
Test name
Test status
Simulation time 38873102 ps
CPU time 0.55 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194520 kb
Host smart-80741f4c-bcbe-43da-8ceb-1cdddf254509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371664364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.371664364
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2786377999
Short name T1133
Test name
Test status
Simulation time 30570661 ps
CPU time 0.66 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 195588 kb
Host smart-3776cca9-3cc9-44df-9f68-30e56bb8292d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786377999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2786377999
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3417883916
Short name T1122
Test name
Test status
Simulation time 89774823 ps
CPU time 2.06 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 200124 kb
Host smart-b7ce608d-0a1e-4037-adfd-8c2ab521d628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417883916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3417883916
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1885661351
Short name T1170
Test name
Test status
Simulation time 228313891 ps
CPU time 1.39 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 199432 kb
Host smart-d18a9305-6085-46bb-a415-ba3900399b43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885661351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1885661351
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2995863975
Short name T1183
Test name
Test status
Simulation time 42057814 ps
CPU time 1.15 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 200184 kb
Host smart-05713882-09ad-43b0-8cfe-4db0dd1f2e9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995863975 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2995863975
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.71497020
Short name T79
Test name
Test status
Simulation time 21369179 ps
CPU time 0.61 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 195540 kb
Host smart-c8214971-26c6-40a3-a107-1c16319e1f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71497020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.71497020
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3840553856
Short name T1158
Test name
Test status
Simulation time 55841274 ps
CPU time 0.6 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194484 kb
Host smart-56103c2c-be69-4cc0-881c-d191e32fc88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840553856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3840553856
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3167324928
Short name T1199
Test name
Test status
Simulation time 68137895 ps
CPU time 0.64 seconds
Started Mar 05 02:51:48 PM PST 24
Finished Mar 05 02:51:49 PM PST 24
Peak memory 195604 kb
Host smart-a892fc7f-3204-486a-8a61-c30e2a3e8a1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167324928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3167324928
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1730584704
Short name T1165
Test name
Test status
Simulation time 72236225 ps
CPU time 1.24 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:44 PM PST 24
Peak memory 200180 kb
Host smart-fe757f10-f0ae-4ce7-947e-2d31d8722c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730584704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1730584704
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2854880627
Short name T1149
Test name
Test status
Simulation time 351896780 ps
CPU time 0.98 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 198968 kb
Host smart-d24e7977-5512-49c4-8d99-d3e0c8147730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854880627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2854880627
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.101167674
Short name T1198
Test name
Test status
Simulation time 22665795 ps
CPU time 1.06 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 200132 kb
Host smart-0776a5b7-0d1f-48c4-9480-18290836eb41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101167674 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.101167674
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3795842567
Short name T74
Test name
Test status
Simulation time 20337071 ps
CPU time 0.57 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:48 PM PST 24
Peak memory 195564 kb
Host smart-b020eb03-2295-4a22-b063-83e7192def7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795842567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3795842567
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4020595861
Short name T1204
Test name
Test status
Simulation time 18853872 ps
CPU time 0.55 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 194408 kb
Host smart-c4ef88b0-bd00-40db-ba34-75bf3d8c5d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020595861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4020595861
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3631986380
Short name T1200
Test name
Test status
Simulation time 43354142 ps
CPU time 0.65 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:48 PM PST 24
Peak memory 196632 kb
Host smart-41d6740e-78b8-4c70-84c5-f9869f22f5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631986380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3631986380
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1502860832
Short name T1102
Test name
Test status
Simulation time 44085467 ps
CPU time 1.19 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:48 PM PST 24
Peak memory 200064 kb
Host smart-ec445e59-6751-4698-9175-d44e75c41b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502860832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1502860832
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1007114787
Short name T1171
Test name
Test status
Simulation time 87364115 ps
CPU time 1.04 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:48 PM PST 24
Peak memory 198948 kb
Host smart-dfb6b0d0-392e-4f8f-b5b1-fbbd863a239a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007114787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1007114787
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1740858373
Short name T1108
Test name
Test status
Simulation time 80471487 ps
CPU time 0.83 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 199944 kb
Host smart-82b00b93-cf5d-44e7-b140-013662d1541f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740858373 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1740858373
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.440367527
Short name T80
Test name
Test status
Simulation time 16782663 ps
CPU time 0.65 seconds
Started Mar 05 02:51:48 PM PST 24
Finished Mar 05 02:51:49 PM PST 24
Peak memory 195552 kb
Host smart-f2a10c75-4310-4f09-aab3-1dc06123bbb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440367527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.440367527
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1136719286
Short name T1109
Test name
Test status
Simulation time 17471599 ps
CPU time 0.58 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 194528 kb
Host smart-d46ca992-2acc-4a7f-811f-387bddd4302b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136719286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1136719286
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1249029658
Short name T1216
Test name
Test status
Simulation time 30312135 ps
CPU time 0.76 seconds
Started Mar 05 02:51:48 PM PST 24
Finished Mar 05 02:51:49 PM PST 24
Peak memory 197020 kb
Host smart-a327a02f-dff1-4268-9b29-edac97734b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249029658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1249029658
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.179076122
Short name T1098
Test name
Test status
Simulation time 41978325 ps
CPU time 2.15 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 200168 kb
Host smart-8b76efba-78bb-4f03-82cc-f6043132d0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179076122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.179076122
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.874652672
Short name T1119
Test name
Test status
Simulation time 96136791 ps
CPU time 1.26 seconds
Started Mar 05 02:51:42 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 199364 kb
Host smart-acbf6993-8eb4-4b79-a886-00c4e0b2cf19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874652672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.874652672
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1207286133
Short name T67
Test name
Test status
Simulation time 104527205 ps
CPU time 0.79 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 196312 kb
Host smart-0a0e8ffe-b755-4ff6-becb-e1c6b75d60db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207286133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1207286133
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1564845715
Short name T1164
Test name
Test status
Simulation time 171562460 ps
CPU time 2.53 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:29 PM PST 24
Peak memory 197604 kb
Host smart-ddf16fb6-a8af-4b33-8782-bdd55c8eae66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564845715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1564845715
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3860444872
Short name T1121
Test name
Test status
Simulation time 149151350 ps
CPU time 0.61 seconds
Started Mar 05 02:51:22 PM PST 24
Finished Mar 05 02:51:23 PM PST 24
Peak memory 195536 kb
Host smart-0b49a503-1b75-4135-af5b-cf3490fe324a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860444872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3860444872
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1643773114
Short name T1136
Test name
Test status
Simulation time 24954212 ps
CPU time 0.81 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:29 PM PST 24
Peak memory 199048 kb
Host smart-f9ff619f-e915-4d30-8810-e9ed7b347703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643773114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1643773114
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.81719652
Short name T69
Test name
Test status
Simulation time 138530773 ps
CPU time 0.61 seconds
Started Mar 05 02:51:27 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 195524 kb
Host smart-05a90390-e2f2-46d9-ab70-2544e1deb5e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81719652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.81719652
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2533977704
Short name T1167
Test name
Test status
Simulation time 52390114 ps
CPU time 0.63 seconds
Started Mar 05 02:51:19 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 194520 kb
Host smart-cb94d4e4-8b9f-41bf-b419-d9f2bf686c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533977704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2533977704
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2657755668
Short name T1186
Test name
Test status
Simulation time 33120114 ps
CPU time 0.81 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 195744 kb
Host smart-e044454a-c8ab-4813-80e6-6daa611ab15d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657755668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2657755668
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2905536864
Short name T1143
Test name
Test status
Simulation time 96243524 ps
CPU time 1.93 seconds
Started Mar 05 02:51:20 PM PST 24
Finished Mar 05 02:51:22 PM PST 24
Peak memory 200124 kb
Host smart-7d068eda-c928-4e2c-9ee2-849c255f634e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905536864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2905536864
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1898824506
Short name T90
Test name
Test status
Simulation time 94328226 ps
CPU time 0.88 seconds
Started Mar 05 02:51:18 PM PST 24
Finished Mar 05 02:51:20 PM PST 24
Peak memory 198624 kb
Host smart-18ddb790-e34f-4001-a283-ef41bb405ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898824506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1898824506
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3333195662
Short name T1230
Test name
Test status
Simulation time 39120077 ps
CPU time 0.61 seconds
Started Mar 05 02:51:47 PM PST 24
Finished Mar 05 02:51:47 PM PST 24
Peak memory 194504 kb
Host smart-2e32790d-6585-4918-96c6-e1f7e5366c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333195662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3333195662
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4029355923
Short name T1151
Test name
Test status
Simulation time 14835251 ps
CPU time 0.61 seconds
Started Mar 05 02:51:44 PM PST 24
Finished Mar 05 02:51:45 PM PST 24
Peak memory 194484 kb
Host smart-0d9858b4-00fb-493f-b8a6-5a3af5d10920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029355923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4029355923
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1896467599
Short name T1126
Test name
Test status
Simulation time 14268116 ps
CPU time 0.57 seconds
Started Mar 05 02:51:48 PM PST 24
Finished Mar 05 02:51:49 PM PST 24
Peak memory 194516 kb
Host smart-f07a64a8-3281-4885-a6ae-d1b6adf928c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896467599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1896467599
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1557308835
Short name T1112
Test name
Test status
Simulation time 40304738 ps
CPU time 0.56 seconds
Started Mar 05 02:51:48 PM PST 24
Finished Mar 05 02:51:48 PM PST 24
Peak memory 194512 kb
Host smart-78a0991c-ee66-4ecc-b1a2-1963c8083767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557308835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1557308835
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1698751759
Short name T1115
Test name
Test status
Simulation time 16400214 ps
CPU time 0.6 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 194520 kb
Host smart-7fca37f9-6ce2-4420-a817-b97de3924ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698751759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1698751759
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4285984029
Short name T1191
Test name
Test status
Simulation time 44598722 ps
CPU time 0.58 seconds
Started Mar 05 02:51:45 PM PST 24
Finished Mar 05 02:51:46 PM PST 24
Peak memory 194528 kb
Host smart-0c416919-a9d0-40ba-b4f6-8257e92704c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285984029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4285984029
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.863480279
Short name T1207
Test name
Test status
Simulation time 57653098 ps
CPU time 0.55 seconds
Started Mar 05 02:51:51 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194496 kb
Host smart-d24a6afc-6046-4305-b539-cdcd5076b7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863480279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.863480279
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3613102286
Short name T1135
Test name
Test status
Simulation time 54113504 ps
CPU time 0.58 seconds
Started Mar 05 02:51:51 PM PST 24
Finished Mar 05 02:51:52 PM PST 24
Peak memory 194536 kb
Host smart-43b624f1-c8c1-4a97-86b3-771905bc1c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613102286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3613102286
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1812712632
Short name T1141
Test name
Test status
Simulation time 95462701 ps
CPU time 0.58 seconds
Started Mar 05 02:51:54 PM PST 24
Finished Mar 05 02:51:55 PM PST 24
Peak memory 194372 kb
Host smart-32005b98-dd59-4676-8323-ead1eb1b9154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812712632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1812712632
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2351362320
Short name T1132
Test name
Test status
Simulation time 39409614 ps
CPU time 0.55 seconds
Started Mar 05 02:51:54 PM PST 24
Finished Mar 05 02:51:55 PM PST 24
Peak memory 194540 kb
Host smart-229fa59b-b05b-409b-9dec-b3dbb5c8f2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351362320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2351362320
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.384569011
Short name T1124
Test name
Test status
Simulation time 21161590 ps
CPU time 0.7 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 194668 kb
Host smart-2a3ab9cc-58c8-48bb-af35-c0352b5ce3a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384569011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.384569011
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1269158515
Short name T70
Test name
Test status
Simulation time 532817104 ps
CPU time 1.5 seconds
Started Mar 05 02:51:24 PM PST 24
Finished Mar 05 02:51:26 PM PST 24
Peak memory 197672 kb
Host smart-f2cbeaed-05ff-43ac-a509-e3d99f20de77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269158515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1269158515
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2234017369
Short name T1139
Test name
Test status
Simulation time 14278524 ps
CPU time 0.6 seconds
Started Mar 05 02:51:25 PM PST 24
Finished Mar 05 02:51:25 PM PST 24
Peak memory 195600 kb
Host smart-a7a2bb26-f05e-4a27-8dba-aa40d066fb48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234017369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2234017369
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.344150472
Short name T1152
Test name
Test status
Simulation time 30620020 ps
CPU time 0.93 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 199984 kb
Host smart-20e8c145-0a74-48c5-a96c-5c5d8f1421e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344150472 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.344150472
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3891237184
Short name T1142
Test name
Test status
Simulation time 26472452 ps
CPU time 0.59 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:29 PM PST 24
Peak memory 195584 kb
Host smart-3e218a6c-a370-4ba4-9e2b-61f91d897dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891237184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3891237184
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2793523465
Short name T1226
Test name
Test status
Simulation time 45104771 ps
CPU time 0.6 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 194500 kb
Host smart-120f4830-9975-4029-affd-dcc774548df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793523465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2793523465
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1899601955
Short name T1182
Test name
Test status
Simulation time 21187868 ps
CPU time 0.67 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:29 PM PST 24
Peak memory 194848 kb
Host smart-a07655f7-3291-4278-9ba1-b5fdada59fbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899601955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1899601955
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3475557183
Short name T1225
Test name
Test status
Simulation time 69756802 ps
CPU time 1.79 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 200112 kb
Host smart-cf2e46da-bd2d-4e67-a241-082642f100ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475557183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3475557183
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3409631277
Short name T1128
Test name
Test status
Simulation time 43226045 ps
CPU time 0.96 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 198860 kb
Host smart-5b816b43-1e0f-4d22-8da5-c19aae722081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409631277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3409631277
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2592720113
Short name T1218
Test name
Test status
Simulation time 12591787 ps
CPU time 0.6 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194516 kb
Host smart-c7ee83df-3a27-4898-a496-a2543a6881c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592720113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2592720113
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1838731532
Short name T1175
Test name
Test status
Simulation time 105014868 ps
CPU time 0.58 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194516 kb
Host smart-6f6ba302-c81b-43b4-901f-c47a4a3026e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838731532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1838731532
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2112949266
Short name T1197
Test name
Test status
Simulation time 13936083 ps
CPU time 0.6 seconds
Started Mar 05 02:51:49 PM PST 24
Finished Mar 05 02:51:50 PM PST 24
Peak memory 194516 kb
Host smart-b1d27f82-3ca7-4e4c-a4b9-a21d5b5e6ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112949266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2112949266
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2339621416
Short name T1106
Test name
Test status
Simulation time 11763763 ps
CPU time 0.61 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:53 PM PST 24
Peak memory 194516 kb
Host smart-fc5c25ba-a025-4995-8ce1-3a9b09042a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339621416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2339621416
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2622016291
Short name T1120
Test name
Test status
Simulation time 35765150 ps
CPU time 0.63 seconds
Started Mar 05 02:51:51 PM PST 24
Finished Mar 05 02:51:52 PM PST 24
Peak memory 194476 kb
Host smart-57e82227-1b36-4739-b31e-9a8f1755ad34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622016291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2622016291
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3649511773
Short name T1162
Test name
Test status
Simulation time 101037824 ps
CPU time 0.57 seconds
Started Mar 05 02:51:49 PM PST 24
Finished Mar 05 02:51:50 PM PST 24
Peak memory 194544 kb
Host smart-1270d036-8946-4d5f-a6e7-dfa0628fea68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649511773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3649511773
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1168060481
Short name T1156
Test name
Test status
Simulation time 91736967 ps
CPU time 0.58 seconds
Started Mar 05 02:51:51 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194488 kb
Host smart-4504df5f-f5eb-4e25-b699-ad63abe71e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168060481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1168060481
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3705764444
Short name T1184
Test name
Test status
Simulation time 23817258 ps
CPU time 0.6 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:50 PM PST 24
Peak memory 194572 kb
Host smart-cf8ca6d9-c290-4678-b0fc-fa1cff581932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705764444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3705764444
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2678296367
Short name T1154
Test name
Test status
Simulation time 228389049 ps
CPU time 0.55 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194532 kb
Host smart-ac38d8c8-7c4a-4896-9218-041341a4362f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678296367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2678296367
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.365268510
Short name T1181
Test name
Test status
Simulation time 25183239 ps
CPU time 0.58 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:53 PM PST 24
Peak memory 194552 kb
Host smart-edc3983e-26c9-4e58-be82-fa09ca1cb419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365268510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.365268510
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1122133896
Short name T1103
Test name
Test status
Simulation time 27866693 ps
CPU time 0.68 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 194576 kb
Host smart-71df995f-b5a5-4f26-8b53-6607be80532b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122133896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1122133896
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2010633078
Short name T72
Test name
Test status
Simulation time 58157789 ps
CPU time 2.4 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:31 PM PST 24
Peak memory 198076 kb
Host smart-13266548-0bf1-49ab-9acd-b46bb0056ae5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010633078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2010633078
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2150318530
Short name T73
Test name
Test status
Simulation time 15780394 ps
CPU time 0.63 seconds
Started Mar 05 02:51:32 PM PST 24
Finished Mar 05 02:51:33 PM PST 24
Peak memory 195520 kb
Host smart-10ef4949-4fff-422d-9f3f-5c712137ae66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150318530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2150318530
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1556681508
Short name T1161
Test name
Test status
Simulation time 22610759 ps
CPU time 0.82 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 198352 kb
Host smart-0ea6eb81-1576-459a-a9d3-f0cddf4d790e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556681508 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1556681508
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2083543464
Short name T1153
Test name
Test status
Simulation time 19816876 ps
CPU time 0.63 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 195484 kb
Host smart-e146830e-8560-4e29-9cb0-ec5d5293490d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083543464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2083543464
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1899334906
Short name T1163
Test name
Test status
Simulation time 21633498 ps
CPU time 0.6 seconds
Started Mar 05 02:51:25 PM PST 24
Finished Mar 05 02:51:26 PM PST 24
Peak memory 194520 kb
Host smart-3cd0b852-aefd-4a35-9bf7-5ccf77414d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899334906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1899334906
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3163529369
Short name T1190
Test name
Test status
Simulation time 92767421 ps
CPU time 0.76 seconds
Started Mar 05 02:51:27 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 196920 kb
Host smart-99fc8c6c-7662-41a5-b343-c6cb79a6c60c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163529369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3163529369
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2902373625
Short name T1117
Test name
Test status
Simulation time 80607960 ps
CPU time 1.85 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 200124 kb
Host smart-fe970882-fc96-40e9-8b2b-a4c6e6a298a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902373625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2902373625
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.652745238
Short name T1178
Test name
Test status
Simulation time 61154774 ps
CPU time 0.98 seconds
Started Mar 05 02:51:29 PM PST 24
Finished Mar 05 02:51:30 PM PST 24
Peak memory 198844 kb
Host smart-556ee51b-ad7a-4cff-8c36-086fe5b3588e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652745238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.652745238
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3842523758
Short name T1110
Test name
Test status
Simulation time 12045298 ps
CPU time 0.57 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:53 PM PST 24
Peak memory 194524 kb
Host smart-6ee16483-4bff-44b4-8d5e-bbfa5ad53472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842523758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3842523758
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.725862769
Short name T1205
Test name
Test status
Simulation time 21509450 ps
CPU time 0.61 seconds
Started Mar 05 02:51:51 PM PST 24
Finished Mar 05 02:51:52 PM PST 24
Peak memory 194440 kb
Host smart-703cd766-b7ad-4d5d-b6f9-a366cca507b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725862769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.725862769
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2321342991
Short name T1097
Test name
Test status
Simulation time 21926930 ps
CPU time 0.59 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:51 PM PST 24
Peak memory 194420 kb
Host smart-11af8272-a184-416f-8723-20aae107611d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321342991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2321342991
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.778155002
Short name T1180
Test name
Test status
Simulation time 19331867 ps
CPU time 0.57 seconds
Started Mar 05 02:51:54 PM PST 24
Finished Mar 05 02:51:55 PM PST 24
Peak memory 194248 kb
Host smart-be27a966-9791-4c9e-b7f5-353c1087c6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778155002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.778155002
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3990473355
Short name T1101
Test name
Test status
Simulation time 85800447 ps
CPU time 0.57 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:52 PM PST 24
Peak memory 194520 kb
Host smart-017582ce-e70e-42f4-8e56-94b8a94ff0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990473355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3990473355
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2263011556
Short name T1113
Test name
Test status
Simulation time 19001711 ps
CPU time 0.57 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:52 PM PST 24
Peak memory 194496 kb
Host smart-442729d9-b5d6-4542-81d3-205a1e761510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263011556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2263011556
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2979374641
Short name T1208
Test name
Test status
Simulation time 16994321 ps
CPU time 0.58 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:50 PM PST 24
Peak memory 194548 kb
Host smart-738e685d-7633-4166-8d1a-4c62d248218c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979374641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2979374641
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2696706215
Short name T1212
Test name
Test status
Simulation time 13423997 ps
CPU time 0.57 seconds
Started Mar 05 02:51:54 PM PST 24
Finished Mar 05 02:51:54 PM PST 24
Peak memory 194516 kb
Host smart-95627f02-e1b0-43cb-a336-3d507c54bb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696706215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2696706215
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.371741693
Short name T1188
Test name
Test status
Simulation time 22702486 ps
CPU time 0.6 seconds
Started Mar 05 02:51:52 PM PST 24
Finished Mar 05 02:51:53 PM PST 24
Peak memory 194508 kb
Host smart-8fa734e1-8960-4de8-a9c7-3027f6eb8404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371741693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.371741693
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1280937847
Short name T1099
Test name
Test status
Simulation time 10948063 ps
CPU time 0.57 seconds
Started Mar 05 02:51:50 PM PST 24
Finished Mar 05 02:51:50 PM PST 24
Peak memory 194516 kb
Host smart-18e86f8a-2a5d-4ca7-ba1b-6b82efb0faa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280937847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1280937847
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2481492577
Short name T1100
Test name
Test status
Simulation time 23542407 ps
CPU time 0.7 seconds
Started Mar 05 02:51:25 PM PST 24
Finished Mar 05 02:51:25 PM PST 24
Peak memory 198500 kb
Host smart-f24a43fc-e4eb-42de-b704-15304f34851d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481492577 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2481492577
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3046945544
Short name T1157
Test name
Test status
Simulation time 17691344 ps
CPU time 0.63 seconds
Started Mar 05 02:51:27 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 195572 kb
Host smart-6ed831ce-7472-458e-a8d1-cb2ac66d5a1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046945544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3046945544
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3598180217
Short name T1179
Test name
Test status
Simulation time 50746354 ps
CPU time 0.58 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:27 PM PST 24
Peak memory 194456 kb
Host smart-77fd6c85-485c-409f-bb3f-b88988b5078c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598180217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3598180217
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2333828813
Short name T1169
Test name
Test status
Simulation time 33819859 ps
CPU time 0.65 seconds
Started Mar 05 02:51:27 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 195632 kb
Host smart-f3cd4ce2-db0b-4bb9-9fbc-f8e9d754e04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333828813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2333828813
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.466304364
Short name T1105
Test name
Test status
Simulation time 40027098 ps
CPU time 1.07 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 199932 kb
Host smart-cd229f9d-9dc5-46a5-b325-8901fb131ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466304364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.466304364
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1554815689
Short name T88
Test name
Test status
Simulation time 54700048 ps
CPU time 1 seconds
Started Mar 05 02:51:28 PM PST 24
Finished Mar 05 02:51:29 PM PST 24
Peak memory 198832 kb
Host smart-b1982efb-aa6e-4a00-bde9-76c821602a94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554815689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1554815689
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3503926677
Short name T1111
Test name
Test status
Simulation time 28328861 ps
CPU time 0.79 seconds
Started Mar 05 02:51:37 PM PST 24
Finished Mar 05 02:51:38 PM PST 24
Peak memory 198396 kb
Host smart-d471a090-0fa4-4e67-b2bf-5ffaaf9f7918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503926677 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3503926677
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2088631571
Short name T1201
Test name
Test status
Simulation time 12935007 ps
CPU time 0.59 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 195600 kb
Host smart-46e25512-c227-4264-81c5-46fd238510cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088631571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2088631571
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2500727710
Short name T1116
Test name
Test status
Simulation time 31943528 ps
CPU time 0.59 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:26 PM PST 24
Peak memory 194516 kb
Host smart-fb620608-e794-423c-9ebc-86edfa3d2a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500727710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2500727710
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3814106234
Short name T76
Test name
Test status
Simulation time 159319523 ps
CPU time 0.65 seconds
Started Mar 05 02:51:33 PM PST 24
Finished Mar 05 02:51:34 PM PST 24
Peak memory 195520 kb
Host smart-fed64cd7-742e-42f3-9a16-3180ae8f1767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814106234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3814106234
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4122050421
Short name T1140
Test name
Test status
Simulation time 80122021 ps
CPU time 1.08 seconds
Started Mar 05 02:51:26 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 200120 kb
Host smart-1bf0e8a9-4985-4a01-9c2d-bd2ada8e1489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122050421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4122050421
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3467324020
Short name T83
Test name
Test status
Simulation time 55403405 ps
CPU time 1.05 seconds
Started Mar 05 02:51:27 PM PST 24
Finished Mar 05 02:51:28 PM PST 24
Peak memory 199028 kb
Host smart-012db603-18ae-4e99-bb58-9823fcc82802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467324020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3467324020
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1938648575
Short name T1138
Test name
Test status
Simulation time 25979457 ps
CPU time 0.78 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 199180 kb
Host smart-53f19070-fe18-4bdf-acc2-275f2ae369b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938648575 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1938648575
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1923957816
Short name T1131
Test name
Test status
Simulation time 24696258 ps
CPU time 0.58 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195560 kb
Host smart-a33f7e17-3ec2-4ca1-b8aa-e3e38de1bd47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923957816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1923957816
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.360200127
Short name T1196
Test name
Test status
Simulation time 34071147 ps
CPU time 0.57 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 194520 kb
Host smart-4d049f9e-6438-4fac-9bef-4592384db7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360200127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.360200127
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2754160893
Short name T81
Test name
Test status
Simulation time 15153276 ps
CPU time 0.7 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 195948 kb
Host smart-dbb354f6-cecf-4e99-baf5-779ec116af8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754160893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2754160893
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2188479811
Short name T1177
Test name
Test status
Simulation time 41956773 ps
CPU time 2.04 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 200144 kb
Host smart-7d9eea63-88f9-42b0-853e-403b7e57b02f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188479811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2188479811
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.95035765
Short name T1148
Test name
Test status
Simulation time 302721510 ps
CPU time 1.44 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 199368 kb
Host smart-7c87155d-09e3-4d84-9054-ae0952ad5792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95035765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.95035765
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1235339039
Short name T1159
Test name
Test status
Simulation time 96595439 ps
CPU time 0.63 seconds
Started Mar 05 02:51:43 PM PST 24
Finished Mar 05 02:51:43 PM PST 24
Peak memory 196884 kb
Host smart-e2c5b237-2400-4fe0-a2bb-97281ea2fb6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235339039 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1235339039
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.327700388
Short name T1176
Test name
Test status
Simulation time 58750133 ps
CPU time 0.63 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195572 kb
Host smart-74bb7faa-8a8c-4035-8ac4-78ea04f5134b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327700388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.327700388
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.344025480
Short name T1118
Test name
Test status
Simulation time 11968333 ps
CPU time 0.59 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:35 PM PST 24
Peak memory 194492 kb
Host smart-f3e0882b-d528-4ba0-b024-148011304905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344025480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.344025480
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1440337695
Short name T1223
Test name
Test status
Simulation time 40739941 ps
CPU time 0.69 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:35 PM PST 24
Peak memory 194884 kb
Host smart-501012d4-4e6f-4b9f-9166-6adcbda31594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440337695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1440337695
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.542721978
Short name T1130
Test name
Test status
Simulation time 48602267 ps
CPU time 0.9 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:35 PM PST 24
Peak memory 199704 kb
Host smart-b7614d64-43c6-4c79-9298-275160fd65ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542721978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.542721978
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2702029904
Short name T91
Test name
Test status
Simulation time 49557825 ps
CPU time 1.02 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 198992 kb
Host smart-e5a77115-fd40-470e-bf59-150ec55085e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702029904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2702029904
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.879887669
Short name T1146
Test name
Test status
Simulation time 270088084 ps
CPU time 1.14 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 200140 kb
Host smart-2fbb55df-a551-4611-b1f7-eae8191cdc9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879887669 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.879887669
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2328409823
Short name T78
Test name
Test status
Simulation time 203557777 ps
CPU time 0.62 seconds
Started Mar 05 02:51:35 PM PST 24
Finished Mar 05 02:51:36 PM PST 24
Peak memory 195624 kb
Host smart-bc9f7e09-b951-424a-999d-8d7126ce81ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328409823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2328409823
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2850727767
Short name T1214
Test name
Test status
Simulation time 18282477 ps
CPU time 0.57 seconds
Started Mar 05 02:51:34 PM PST 24
Finished Mar 05 02:51:35 PM PST 24
Peak memory 194556 kb
Host smart-1fce887a-f674-428b-9f8b-e805c20ecffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850727767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2850727767
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4058894710
Short name T1172
Test name
Test status
Simulation time 159110788 ps
CPU time 0.79 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 196960 kb
Host smart-14e82a0e-b896-4d6c-9173-6bfb459166cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058894710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4058894710
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1982472831
Short name T1129
Test name
Test status
Simulation time 27987101 ps
CPU time 1.39 seconds
Started Mar 05 02:51:37 PM PST 24
Finished Mar 05 02:51:38 PM PST 24
Peak memory 200128 kb
Host smart-83eef4c8-6689-4e0e-838a-82ae76f40f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982472831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1982472831
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2488807087
Short name T1192
Test name
Test status
Simulation time 323321322 ps
CPU time 1.23 seconds
Started Mar 05 02:51:36 PM PST 24
Finished Mar 05 02:51:37 PM PST 24
Peak memory 199264 kb
Host smart-b7505293-3d6d-495e-a8c5-f70ae01877c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488807087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2488807087
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3028861789
Short name T635
Test name
Test status
Simulation time 20085686 ps
CPU time 0.57 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:33:01 PM PST 24
Peak memory 195952 kb
Host smart-ccc092db-bc7d-4304-b053-2e115aa1396f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028861789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3028861789
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1373548349
Short name T205
Test name
Test status
Simulation time 142917197440 ps
CPU time 220.1 seconds
Started Mar 05 01:32:52 PM PST 24
Finished Mar 05 01:36:33 PM PST 24
Peak memory 200372 kb
Host smart-126b05c3-fd66-4354-a0af-109ed99cc2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373548349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1373548349
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1244139845
Short name T926
Test name
Test status
Simulation time 235640526558 ps
CPU time 92.28 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 200324 kb
Host smart-0ef15ccb-532b-442b-92ae-3e88d239e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244139845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1244139845
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1552652607
Short name T426
Test name
Test status
Simulation time 404253289890 ps
CPU time 48.77 seconds
Started Mar 05 01:32:52 PM PST 24
Finished Mar 05 01:33:41 PM PST 24
Peak memory 200264 kb
Host smart-87909fd5-4d7b-4128-ac8c-f217157f413e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552652607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1552652607
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1706067312
Short name T437
Test name
Test status
Simulation time 70944046233 ps
CPU time 473.08 seconds
Started Mar 05 01:33:02 PM PST 24
Finished Mar 05 01:40:55 PM PST 24
Peak memory 200360 kb
Host smart-78b8044d-ad35-4880-a691-a29295d63c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706067312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1706067312
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3360695218
Short name T777
Test name
Test status
Simulation time 6196674202 ps
CPU time 3.55 seconds
Started Mar 05 01:32:57 PM PST 24
Finished Mar 05 01:33:01 PM PST 24
Peak memory 200276 kb
Host smart-2c6d9a6e-8564-4c0d-8e84-5fe55c78034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360695218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3360695218
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1373472106
Short name T996
Test name
Test status
Simulation time 41734130060 ps
CPU time 64.78 seconds
Started Mar 05 01:32:59 PM PST 24
Finished Mar 05 01:34:05 PM PST 24
Peak memory 199076 kb
Host smart-33c0b625-67cb-4a1b-8fa7-319c15cebce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373472106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1373472106
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1230002082
Short name T969
Test name
Test status
Simulation time 9744382936 ps
CPU time 545.81 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:42:07 PM PST 24
Peak memory 200368 kb
Host smart-c2860799-5f33-4ddd-a961-f429297d99fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230002082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1230002082
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.733959541
Short name T752
Test name
Test status
Simulation time 1197999530 ps
CPU time 11.8 seconds
Started Mar 05 01:32:55 PM PST 24
Finished Mar 05 01:33:07 PM PST 24
Peak memory 198452 kb
Host smart-5e36afbc-54d5-4543-8102-6ed958e08212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733959541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.733959541
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1187715639
Short name T814
Test name
Test status
Simulation time 30400890976 ps
CPU time 49 seconds
Started Mar 05 01:32:58 PM PST 24
Finished Mar 05 01:33:48 PM PST 24
Peak memory 199232 kb
Host smart-0e7277f1-b508-40ca-a854-0237b7f17bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187715639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1187715639
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4087550907
Short name T1049
Test name
Test status
Simulation time 1964252887 ps
CPU time 3.94 seconds
Started Mar 05 01:32:59 PM PST 24
Finished Mar 05 01:33:04 PM PST 24
Peak memory 195696 kb
Host smart-762d5553-030d-4517-b979-5098c5e9d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087550907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4087550907
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3128744270
Short name T413
Test name
Test status
Simulation time 693315525 ps
CPU time 2.75 seconds
Started Mar 05 01:32:53 PM PST 24
Finished Mar 05 01:32:56 PM PST 24
Peak memory 198752 kb
Host smart-77619e58-99b2-42a2-a4c9-b34d121fa35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128744270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3128744270
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3476111569
Short name T448
Test name
Test status
Simulation time 501112809539 ps
CPU time 431.45 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:40:12 PM PST 24
Peak memory 200408 kb
Host smart-c3c03ba5-bec4-41d7-808d-f3b2dcb9629c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476111569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3476111569
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2274509100
Short name T492
Test name
Test status
Simulation time 6523805354 ps
CPU time 14.11 seconds
Started Mar 05 01:33:02 PM PST 24
Finished Mar 05 01:33:17 PM PST 24
Peak memory 200380 kb
Host smart-66cedce9-e0ed-42e3-9b84-8859039ffca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274509100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2274509100
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2940718291
Short name T614
Test name
Test status
Simulation time 8252744941 ps
CPU time 13.85 seconds
Started Mar 05 01:32:59 PM PST 24
Finished Mar 05 01:33:13 PM PST 24
Peak memory 200324 kb
Host smart-746b309b-1efe-4f10-b172-7c849b2ec68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940718291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2940718291
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2108716745
Short name T472
Test name
Test status
Simulation time 21032395 ps
CPU time 0.56 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:33:08 PM PST 24
Peak memory 195936 kb
Host smart-600e8cf8-dabf-4619-bbb1-ad097d0b0577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108716745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2108716745
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1004910235
Short name T515
Test name
Test status
Simulation time 28414301863 ps
CPU time 50.81 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 200356 kb
Host smart-c73b50a2-0841-40f6-99a4-edc1f2224848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004910235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1004910235
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.266385655
Short name T344
Test name
Test status
Simulation time 119212741783 ps
CPU time 50.33 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 200288 kb
Host smart-cdc230e3-36ce-417e-a844-1810548ee092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266385655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.266385655
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3623494994
Short name T100
Test name
Test status
Simulation time 287773814417 ps
CPU time 114.82 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:34:56 PM PST 24
Peak memory 200108 kb
Host smart-523fd066-b630-4188-8aba-ba010c762ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623494994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3623494994
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1534979448
Short name T885
Test name
Test status
Simulation time 1511367361082 ps
CPU time 822.08 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:46:43 PM PST 24
Peak memory 200132 kb
Host smart-8b53acd8-e9d0-42aa-b77c-19a3f8452599
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534979448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1534979448
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3583803592
Short name T735
Test name
Test status
Simulation time 91539746388 ps
CPU time 305.37 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:38:14 PM PST 24
Peak memory 200292 kb
Host smart-14a68c8a-4458-44ce-9edc-8632c04988c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583803592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3583803592
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1943636512
Short name T495
Test name
Test status
Simulation time 8277082054 ps
CPU time 5.43 seconds
Started Mar 05 01:33:06 PM PST 24
Finished Mar 05 01:33:12 PM PST 24
Peak memory 199892 kb
Host smart-37b4ddb9-4946-497d-973d-de09c71621bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943636512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1943636512
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2126424622
Short name T737
Test name
Test status
Simulation time 161802611156 ps
CPU time 330.05 seconds
Started Mar 05 01:33:00 PM PST 24
Finished Mar 05 01:38:31 PM PST 24
Peak memory 200536 kb
Host smart-9f827c16-6bde-4d76-b19f-87ca5413a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126424622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2126424622
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.985863152
Short name T115
Test name
Test status
Simulation time 12898406105 ps
CPU time 361.78 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:39:10 PM PST 24
Peak memory 200404 kb
Host smart-1e82429f-6ba4-4b68-b2f7-99d768ff67b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985863152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.985863152
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3035911393
Short name T491
Test name
Test status
Simulation time 3315182103 ps
CPU time 10.11 seconds
Started Mar 05 01:33:03 PM PST 24
Finished Mar 05 01:33:13 PM PST 24
Peak memory 198844 kb
Host smart-00372424-34a2-4a7d-8fae-a7f3290d03b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035911393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3035911393
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2214662098
Short name T541
Test name
Test status
Simulation time 29815108818 ps
CPU time 13.25 seconds
Started Mar 05 01:33:09 PM PST 24
Finished Mar 05 01:33:23 PM PST 24
Peak memory 198832 kb
Host smart-9326a55d-6ec2-44b9-8fad-95ebf4a39f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214662098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2214662098
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4266240549
Short name T689
Test name
Test status
Simulation time 2909806033 ps
CPU time 3.08 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:33:09 PM PST 24
Peak memory 195872 kb
Host smart-7b034602-13a6-4ba2-9803-954f41c8afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266240549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4266240549
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4103467862
Short name T94
Test name
Test status
Simulation time 93329064 ps
CPU time 0.76 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:33:09 PM PST 24
Peak memory 217908 kb
Host smart-fcbb06d3-12d0-41be-bb3c-bb2d1f626597
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103467862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4103467862
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2529982397
Short name T906
Test name
Test status
Simulation time 5365757128 ps
CPU time 16.62 seconds
Started Mar 05 01:33:01 PM PST 24
Finished Mar 05 01:33:18 PM PST 24
Peak memory 199500 kb
Host smart-96d78d50-08cc-4e9f-af6d-6792425d39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529982397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2529982397
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3895722693
Short name T476
Test name
Test status
Simulation time 6318011237 ps
CPU time 16.68 seconds
Started Mar 05 01:33:04 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 200156 kb
Host smart-7fed35cf-7089-408d-809a-7650ced9e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895722693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3895722693
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.794378125
Short name T529
Test name
Test status
Simulation time 53541711838 ps
CPU time 79.39 seconds
Started Mar 05 01:33:01 PM PST 24
Finished Mar 05 01:34:21 PM PST 24
Peak memory 200416 kb
Host smart-dd0bf35d-f846-47a6-93ae-a9778534fa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794378125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.794378125
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3681940658
Short name T965
Test name
Test status
Simulation time 23845811 ps
CPU time 0.57 seconds
Started Mar 05 01:33:41 PM PST 24
Finished Mar 05 01:33:42 PM PST 24
Peak memory 195864 kb
Host smart-a159e299-173e-44ed-92c5-34b0157c50a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681940658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3681940658
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2040470042
Short name T340
Test name
Test status
Simulation time 30223921000 ps
CPU time 45.63 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:34:22 PM PST 24
Peak memory 200352 kb
Host smart-2c59fda7-b49a-449d-9f55-86b635fc0218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040470042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2040470042
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.21806122
Short name T855
Test name
Test status
Simulation time 146588016039 ps
CPU time 208.44 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:37:07 PM PST 24
Peak memory 200328 kb
Host smart-e0739a97-5ae9-4550-86ce-46e183e9126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21806122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.21806122
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.3944591672
Short name T815
Test name
Test status
Simulation time 196634181668 ps
CPU time 141.54 seconds
Started Mar 05 01:33:42 PM PST 24
Finished Mar 05 01:36:04 PM PST 24
Peak memory 199268 kb
Host smart-c7a35256-39c3-4ac4-a9b8-15d90a787350
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944591672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3944591672
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.126832749
Short name T859
Test name
Test status
Simulation time 116193386882 ps
CPU time 710.78 seconds
Started Mar 05 01:33:47 PM PST 24
Finished Mar 05 01:45:38 PM PST 24
Peak memory 200344 kb
Host smart-457d16e3-03dc-4f41-8637-294bc5a8da75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126832749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.126832749
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2872952154
Short name T10
Test name
Test status
Simulation time 2138200663 ps
CPU time 3.8 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:33:54 PM PST 24
Peak memory 195780 kb
Host smart-d3b49604-23ab-4ad0-9060-76860afe9d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872952154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2872952154
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.570614523
Short name T520
Test name
Test status
Simulation time 232921783568 ps
CPU time 146.36 seconds
Started Mar 05 01:33:47 PM PST 24
Finished Mar 05 01:36:14 PM PST 24
Peak memory 200596 kb
Host smart-919dd159-6d7a-4916-bd61-60fd811d2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570614523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.570614523
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.796580176
Short name T655
Test name
Test status
Simulation time 18638318593 ps
CPU time 563.95 seconds
Started Mar 05 01:33:42 PM PST 24
Finished Mar 05 01:43:06 PM PST 24
Peak memory 200344 kb
Host smart-6813dd34-ff4f-43ca-80f9-73487fce5da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796580176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.796580176
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2215616436
Short name T607
Test name
Test status
Simulation time 2429386977 ps
CPU time 6 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:33:58 PM PST 24
Peak memory 198792 kb
Host smart-b2acc462-4c98-4a9c-af59-9c6df4280952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215616436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2215616436
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1109154847
Short name T668
Test name
Test status
Simulation time 112831697564 ps
CPU time 209.46 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:37:21 PM PST 24
Peak memory 200320 kb
Host smart-f60e9247-7980-46da-9a83-02bd428f2fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109154847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1109154847
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.411531581
Short name T742
Test name
Test status
Simulation time 2631268675 ps
CPU time 0.79 seconds
Started Mar 05 01:33:43 PM PST 24
Finished Mar 05 01:33:44 PM PST 24
Peak memory 195884 kb
Host smart-c2fafc37-dea5-4fce-a64a-a1fed797ef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411531581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.411531581
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2710395678
Short name T833
Test name
Test status
Simulation time 289156288 ps
CPU time 1.4 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:33:40 PM PST 24
Peak memory 198568 kb
Host smart-1e13c8f9-309c-4c76-b40e-55d86242f69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710395678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2710395678
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4106460727
Short name T699
Test name
Test status
Simulation time 2288984554 ps
CPU time 2.73 seconds
Started Mar 05 01:33:49 PM PST 24
Finished Mar 05 01:33:52 PM PST 24
Peak memory 199444 kb
Host smart-03c821cf-f678-4277-ab11-4709496c197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106460727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4106460727
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1695402966
Short name T427
Test name
Test status
Simulation time 34719402387 ps
CPU time 28.24 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:08 PM PST 24
Peak memory 200284 kb
Host smart-2b705a73-4b27-4cac-ab90-756bc936032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695402966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1695402966
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4116575137
Short name T866
Test name
Test status
Simulation time 161947648448 ps
CPU time 147.39 seconds
Started Mar 05 01:41:09 PM PST 24
Finished Mar 05 01:43:37 PM PST 24
Peak memory 200348 kb
Host smart-e3e2fe32-5a13-4411-b57d-1e7173a48cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116575137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4116575137
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1771516504
Short name T203
Test name
Test status
Simulation time 7461527064 ps
CPU time 13.31 seconds
Started Mar 05 01:41:20 PM PST 24
Finished Mar 05 01:41:33 PM PST 24
Peak memory 199816 kb
Host smart-6671cd00-224f-4c01-9188-9e7aa7a08291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771516504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1771516504
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2448060428
Short name T1023
Test name
Test status
Simulation time 45538750813 ps
CPU time 64.43 seconds
Started Mar 05 01:41:20 PM PST 24
Finished Mar 05 01:42:25 PM PST 24
Peak memory 200112 kb
Host smart-75da6c5a-e43b-4f67-b07a-2e08b04ed1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448060428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2448060428
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1796873686
Short name T593
Test name
Test status
Simulation time 43253326793 ps
CPU time 84.32 seconds
Started Mar 05 01:41:23 PM PST 24
Finished Mar 05 01:42:47 PM PST 24
Peak memory 200420 kb
Host smart-f5d4f489-3cb2-451a-948e-007c815d465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796873686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1796873686
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3482196281
Short name T188
Test name
Test status
Simulation time 61351836518 ps
CPU time 95.85 seconds
Started Mar 05 01:41:20 PM PST 24
Finished Mar 05 01:42:56 PM PST 24
Peak memory 199004 kb
Host smart-792d3b7b-5b1d-4f86-82c2-fb2bea65235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482196281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3482196281
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2149247259
Short name T970
Test name
Test status
Simulation time 13481724 ps
CPU time 0.53 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:33:53 PM PST 24
Peak memory 195932 kb
Host smart-779a5c68-550c-425a-bb6b-193265ef3ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149247259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2149247259
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3546927516
Short name T622
Test name
Test status
Simulation time 39873681428 ps
CPU time 80.02 seconds
Started Mar 05 01:33:49 PM PST 24
Finished Mar 05 01:35:09 PM PST 24
Peak memory 200384 kb
Host smart-414c3376-14df-4232-be06-463565ddef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546927516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3546927516
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2389568461
Short name T449
Test name
Test status
Simulation time 395753014455 ps
CPU time 805.24 seconds
Started Mar 05 01:33:48 PM PST 24
Finished Mar 05 01:47:13 PM PST 24
Peak memory 200204 kb
Host smart-4c104585-8b43-47c6-a987-51e5737b6833
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389568461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2389568461
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.359703422
Short name T1058
Test name
Test status
Simulation time 102373486555 ps
CPU time 746.18 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:46:18 PM PST 24
Peak memory 200316 kb
Host smart-92086ec0-7411-4427-b5ce-38f2c920d783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359703422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.359703422
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4160303556
Short name T489
Test name
Test status
Simulation time 9601301874 ps
CPU time 6.9 seconds
Started Mar 05 01:33:43 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 198916 kb
Host smart-2185d2c0-9363-4be6-8ef9-b7bda82336a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160303556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4160303556
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1566552228
Short name T809
Test name
Test status
Simulation time 72905492474 ps
CPU time 111.63 seconds
Started Mar 05 01:33:45 PM PST 24
Finished Mar 05 01:35:37 PM PST 24
Peak memory 208632 kb
Host smart-ff4dfc04-83eb-4940-ac60-05443c562f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566552228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1566552228
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3102781775
Short name T647
Test name
Test status
Simulation time 15430732130 ps
CPU time 324.05 seconds
Started Mar 05 01:33:48 PM PST 24
Finished Mar 05 01:39:12 PM PST 24
Peak memory 200396 kb
Host smart-8d8f0964-a6c3-4071-a1ef-5470ec327488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102781775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3102781775
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3575119867
Short name T820
Test name
Test status
Simulation time 106569022981 ps
CPU time 194.83 seconds
Started Mar 05 01:33:45 PM PST 24
Finished Mar 05 01:37:00 PM PST 24
Peak memory 199952 kb
Host smart-79d0db8d-d5f7-4614-b648-1633d128f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575119867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3575119867
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4234113267
Short name T419
Test name
Test status
Simulation time 4892726218 ps
CPU time 7.39 seconds
Started Mar 05 01:33:48 PM PST 24
Finished Mar 05 01:33:55 PM PST 24
Peak memory 196152 kb
Host smart-73f3d2c1-750a-4503-a419-3557fef1e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234113267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4234113267
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2667927871
Short name T957
Test name
Test status
Simulation time 5465604597 ps
CPU time 9.01 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:00 PM PST 24
Peak memory 199624 kb
Host smart-ae59ebeb-5bff-4d0b-9132-52b27675b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667927871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2667927871
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2692989305
Short name T545
Test name
Test status
Simulation time 1938342851 ps
CPU time 1.86 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:33:54 PM PST 24
Peak memory 198656 kb
Host smart-9dced290-bee1-4b94-aaa0-811c7228c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692989305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2692989305
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2088240052
Short name T791
Test name
Test status
Simulation time 68393191213 ps
CPU time 44.03 seconds
Started Mar 05 01:33:43 PM PST 24
Finished Mar 05 01:34:27 PM PST 24
Peak memory 200388 kb
Host smart-e4ee699c-3c17-486a-90f7-fa868d66dcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088240052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2088240052
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2943785904
Short name T470
Test name
Test status
Simulation time 147033556862 ps
CPU time 50.93 seconds
Started Mar 05 01:41:27 PM PST 24
Finished Mar 05 01:42:19 PM PST 24
Peak memory 200368 kb
Host smart-0b3a8158-0750-45e6-9c66-af9d039bdc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943785904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2943785904
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3055222432
Short name T984
Test name
Test status
Simulation time 176987317066 ps
CPU time 29.09 seconds
Started Mar 05 01:41:31 PM PST 24
Finished Mar 05 01:42:00 PM PST 24
Peak memory 199992 kb
Host smart-d957efe6-3147-4eac-80a3-8d115a9bef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055222432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3055222432
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3095480352
Short name T1020
Test name
Test status
Simulation time 63216080336 ps
CPU time 47.11 seconds
Started Mar 05 01:41:29 PM PST 24
Finished Mar 05 01:42:17 PM PST 24
Peak memory 200352 kb
Host smart-c271af18-c301-4bda-8bbc-918e361a35a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095480352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3095480352
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1043300162
Short name T49
Test name
Test status
Simulation time 109577232565 ps
CPU time 252.83 seconds
Started Mar 05 01:41:29 PM PST 24
Finished Mar 05 01:45:42 PM PST 24
Peak memory 200372 kb
Host smart-457e2e65-7bd8-4256-90ae-a7637c7cbd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043300162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1043300162
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1790331453
Short name T280
Test name
Test status
Simulation time 190443651268 ps
CPU time 321.09 seconds
Started Mar 05 01:41:29 PM PST 24
Finished Mar 05 01:46:51 PM PST 24
Peak memory 200212 kb
Host smart-6e0435b7-5d65-4acc-acde-85aaa41920a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790331453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1790331453
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.479005958
Short name T129
Test name
Test status
Simulation time 132904605552 ps
CPU time 27.18 seconds
Started Mar 05 01:41:28 PM PST 24
Finished Mar 05 01:41:56 PM PST 24
Peak memory 200332 kb
Host smart-6c4d9168-01ce-40eb-9a09-d8250b85105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479005958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.479005958
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.466383352
Short name T679
Test name
Test status
Simulation time 32986451191 ps
CPU time 14.61 seconds
Started Mar 05 01:41:33 PM PST 24
Finished Mar 05 01:41:48 PM PST 24
Peak memory 199952 kb
Host smart-84c16c61-fcd4-48a5-99d6-3b00d6221b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466383352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.466383352
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3879974552
Short name T320
Test name
Test status
Simulation time 84042050823 ps
CPU time 36.23 seconds
Started Mar 05 01:41:28 PM PST 24
Finished Mar 05 01:42:05 PM PST 24
Peak memory 200220 kb
Host smart-dd67d3e9-a749-4161-9b2c-15c2ba6d033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879974552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3879974552
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3876952938
Short name T275
Test name
Test status
Simulation time 36269577047 ps
CPU time 34.15 seconds
Started Mar 05 01:41:31 PM PST 24
Finished Mar 05 01:42:05 PM PST 24
Peak memory 200340 kb
Host smart-4d0a928b-a463-4fc8-8fc6-80bc4fa40a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876952938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3876952938
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.706993496
Short name T486
Test name
Test status
Simulation time 37406879 ps
CPU time 0.57 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 195880 kb
Host smart-a1df4939-bc2c-4e0e-b508-dc5dda097ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706993496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.706993496
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.386867219
Short name T358
Test name
Test status
Simulation time 177906198733 ps
CPU time 38.05 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:30 PM PST 24
Peak memory 200400 kb
Host smart-70eb7b5f-0de8-46ce-9613-a1ab4b4099db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386867219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.386867219
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.683088486
Short name T389
Test name
Test status
Simulation time 48663229719 ps
CPU time 75.46 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:35:07 PM PST 24
Peak memory 200224 kb
Host smart-74fc3b7d-44dd-4a48-8dcf-3a99fac1e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683088486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.683088486
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3898614094
Short name T274
Test name
Test status
Simulation time 16893154244 ps
CPU time 29.67 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:21 PM PST 24
Peak memory 199756 kb
Host smart-c5b69499-5f27-4cac-9b0b-7365855b2e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898614094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3898614094
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.590625642
Short name T471
Test name
Test status
Simulation time 602829430583 ps
CPU time 991.59 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:50:22 PM PST 24
Peak memory 197492 kb
Host smart-c5b254f3-581d-4b11-9f90-e24c1b423308
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590625642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.590625642
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.975179191
Short name T612
Test name
Test status
Simulation time 66168241030 ps
CPU time 592.25 seconds
Started Mar 05 01:34:01 PM PST 24
Finished Mar 05 01:43:54 PM PST 24
Peak memory 200192 kb
Host smart-dba12a2a-4393-4986-bd20-bbafc057cf6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975179191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.975179191
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.284694834
Short name T576
Test name
Test status
Simulation time 2539306890 ps
CPU time 0.89 seconds
Started Mar 05 01:33:53 PM PST 24
Finished Mar 05 01:33:54 PM PST 24
Peak memory 195832 kb
Host smart-28b061e2-9fd5-42a9-bda2-35dbe566a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284694834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.284694834
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1510134055
Short name T438
Test name
Test status
Simulation time 481819364960 ps
CPU time 47.51 seconds
Started Mar 05 01:33:49 PM PST 24
Finished Mar 05 01:34:37 PM PST 24
Peak memory 200520 kb
Host smart-7bf94fc7-e036-4ba1-a27c-1487664d5f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510134055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1510134055
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.952748746
Short name T533
Test name
Test status
Simulation time 22933731159 ps
CPU time 113.46 seconds
Started Mar 05 01:33:53 PM PST 24
Finished Mar 05 01:35:47 PM PST 24
Peak memory 200372 kb
Host smart-5246a8ff-3ee2-4226-9a4d-8517adef12b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952748746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.952748746
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3376363402
Short name T694
Test name
Test status
Simulation time 4943840417 ps
CPU time 12.48 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:04 PM PST 24
Peak memory 199168 kb
Host smart-9829c654-5b67-48b6-8c55-4b12755626ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376363402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3376363402
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1272503269
Short name T850
Test name
Test status
Simulation time 61602677106 ps
CPU time 24.68 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:34:16 PM PST 24
Peak memory 200224 kb
Host smart-c686f17b-3f56-4d2a-bdbb-4e31fec5639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272503269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1272503269
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1410720124
Short name T428
Test name
Test status
Simulation time 5458109213 ps
CPU time 3.05 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:33:53 PM PST 24
Peak memory 196244 kb
Host smart-0246a783-141f-46d3-a448-5732c3390963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410720124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1410720124
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3458922213
Short name T903
Test name
Test status
Simulation time 5382768546 ps
CPU time 9.02 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:00 PM PST 24
Peak memory 199140 kb
Host smart-eb7d992a-7ba9-4ea3-8ed7-457a01179e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458922213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3458922213
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4193746671
Short name T785
Test name
Test status
Simulation time 142540789650 ps
CPU time 301.01 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:38:51 PM PST 24
Peak memory 216944 kb
Host smart-386111cf-dfa3-43a0-80de-49ae1df60ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193746671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4193746671
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.698523330
Short name T877
Test name
Test status
Simulation time 2266770512 ps
CPU time 1.91 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:33:53 PM PST 24
Peak memory 198724 kb
Host smart-8abad6bb-21c4-4db3-9db0-bcaccdee3cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698523330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.698523330
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4293329643
Short name T930
Test name
Test status
Simulation time 32740432931 ps
CPU time 44.1 seconds
Started Mar 05 01:33:52 PM PST 24
Finished Mar 05 01:34:36 PM PST 24
Peak memory 200264 kb
Host smart-2bca917d-9404-41a0-a332-98743d0b6027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293329643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4293329643
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.834850432
Short name T662
Test name
Test status
Simulation time 13193182753 ps
CPU time 13.56 seconds
Started Mar 05 01:41:35 PM PST 24
Finished Mar 05 01:41:49 PM PST 24
Peak memory 200340 kb
Host smart-ad900659-a63d-4fed-9a38-816c5934a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834850432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.834850432
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4216541630
Short name T150
Test name
Test status
Simulation time 45418605932 ps
CPU time 67.44 seconds
Started Mar 05 01:41:38 PM PST 24
Finished Mar 05 01:42:46 PM PST 24
Peak memory 200148 kb
Host smart-967c612f-9ea9-4feb-baaa-9e942254ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216541630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4216541630
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1286227915
Short name T677
Test name
Test status
Simulation time 101065590161 ps
CPU time 40.75 seconds
Started Mar 05 01:41:33 PM PST 24
Finished Mar 05 01:42:14 PM PST 24
Peak memory 200332 kb
Host smart-9ce6250d-9475-44d9-bb3c-7738dc33b9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286227915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1286227915
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.935159733
Short name T309
Test name
Test status
Simulation time 38751435793 ps
CPU time 50.34 seconds
Started Mar 05 01:41:38 PM PST 24
Finished Mar 05 01:42:29 PM PST 24
Peak memory 200372 kb
Host smart-46986b92-1e9b-4843-b643-8f092eb34f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935159733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.935159733
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1533192568
Short name T56
Test name
Test status
Simulation time 109809091664 ps
CPU time 40.75 seconds
Started Mar 05 01:41:36 PM PST 24
Finished Mar 05 01:42:18 PM PST 24
Peak memory 200324 kb
Host smart-430af5d6-b17b-4637-bb16-277d9223d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533192568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1533192568
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.852149237
Short name T212
Test name
Test status
Simulation time 15651678103 ps
CPU time 13.02 seconds
Started Mar 05 01:41:36 PM PST 24
Finished Mar 05 01:41:49 PM PST 24
Peak memory 199516 kb
Host smart-00d45bd6-7be8-4978-a04c-6d2810deb625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852149237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.852149237
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3556684696
Short name T388
Test name
Test status
Simulation time 15718293015 ps
CPU time 25.17 seconds
Started Mar 05 01:41:36 PM PST 24
Finished Mar 05 01:42:02 PM PST 24
Peak memory 199872 kb
Host smart-2095942a-900e-4dce-bfe4-1606db157d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556684696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3556684696
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3244291429
Short name T692
Test name
Test status
Simulation time 16168884121 ps
CPU time 7.95 seconds
Started Mar 05 01:41:36 PM PST 24
Finished Mar 05 01:41:44 PM PST 24
Peak memory 200408 kb
Host smart-d293fbad-5025-448f-be85-df7d8a9e6697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244291429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3244291429
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1212774574
Short name T643
Test name
Test status
Simulation time 22790397 ps
CPU time 0.56 seconds
Started Mar 05 01:33:56 PM PST 24
Finished Mar 05 01:33:56 PM PST 24
Peak memory 195012 kb
Host smart-0762bc08-acf2-41a9-baca-173fd0b1211c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212774574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1212774574
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3000205791
Short name T876
Test name
Test status
Simulation time 35511113069 ps
CPU time 58.11 seconds
Started Mar 05 01:33:50 PM PST 24
Finished Mar 05 01:34:48 PM PST 24
Peak memory 200424 kb
Host smart-87bb0d66-64a0-4e57-a03c-e533e5285814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000205791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3000205791
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2777566041
Short name T312
Test name
Test status
Simulation time 165096837428 ps
CPU time 252.1 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:38:03 PM PST 24
Peak memory 200388 kb
Host smart-0c1684df-7baf-4002-9061-6bf7a65a752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777566041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2777566041
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3932601861
Short name T508
Test name
Test status
Simulation time 110490412774 ps
CPU time 37.06 seconds
Started Mar 05 01:33:51 PM PST 24
Finished Mar 05 01:34:28 PM PST 24
Peak memory 200048 kb
Host smart-97d25501-e67a-499b-aaf2-b7ed65ed224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932601861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3932601861
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3867338475
Short name T966
Test name
Test status
Simulation time 67846226843 ps
CPU time 81.29 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:35:23 PM PST 24
Peak memory 200400 kb
Host smart-2d3b25b3-43fa-4ea3-a8c1-a015fc7b2fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867338475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3867338475
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3394874721
Short name T939
Test name
Test status
Simulation time 31391927 ps
CPU time 0.59 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:02 PM PST 24
Peak memory 195688 kb
Host smart-3cd7ed4d-4c73-4787-b238-243983e7a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394874721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3394874721
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.640428821
Short name T961
Test name
Test status
Simulation time 68304600589 ps
CPU time 166.91 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:36:49 PM PST 24
Peak memory 200592 kb
Host smart-f324ec07-b8d4-47c2-8b8e-2f6e1479d45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640428821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.640428821
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2879916163
Short name T1003
Test name
Test status
Simulation time 18572484511 ps
CPU time 673.48 seconds
Started Mar 05 01:34:00 PM PST 24
Finished Mar 05 01:45:14 PM PST 24
Peak memory 200348 kb
Host smart-a94b1798-c475-4e26-bbf1-981e63e80031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879916163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2879916163
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1068257516
Short name T1066
Test name
Test status
Simulation time 5709210815 ps
CPU time 11.62 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:14 PM PST 24
Peak memory 199052 kb
Host smart-0183b962-e5a6-40a3-b6e8-88efd63611ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068257516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1068257516
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.312283169
Short name T745
Test name
Test status
Simulation time 15362688538 ps
CPU time 28.3 seconds
Started Mar 05 01:34:00 PM PST 24
Finished Mar 05 01:34:28 PM PST 24
Peak memory 199968 kb
Host smart-905287dd-76e4-4ee1-8e29-1f51601433b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312283169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.312283169
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1251154925
Short name T839
Test name
Test status
Simulation time 5114375829 ps
CPU time 9.52 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:11 PM PST 24
Peak memory 196128 kb
Host smart-9b59df5d-5c6d-4fc0-91e0-ea89e29bdd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251154925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1251154925
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1492456170
Short name T952
Test name
Test status
Simulation time 647359849 ps
CPU time 1.74 seconds
Started Mar 05 01:33:49 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 198496 kb
Host smart-59e1dd78-9a9a-4613-a87a-7e2f57d20fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492456170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1492456170
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.360699702
Short name T332
Test name
Test status
Simulation time 283381525981 ps
CPU time 385.71 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:40:30 PM PST 24
Peak memory 200372 kb
Host smart-7f67027a-aa58-436d-89f2-70f206177b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360699702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.360699702
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4031974815
Short name T551
Test name
Test status
Simulation time 6508235324 ps
CPU time 26.66 seconds
Started Mar 05 01:34:03 PM PST 24
Finished Mar 05 01:34:29 PM PST 24
Peak memory 199976 kb
Host smart-58471096-7a38-4523-a139-28ec9c3d1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031974815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4031974815
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.708247569
Short name T730
Test name
Test status
Simulation time 4587751259 ps
CPU time 4.35 seconds
Started Mar 05 01:33:53 PM PST 24
Finished Mar 05 01:33:57 PM PST 24
Peak memory 196524 kb
Host smart-91dd811f-b486-4b24-8a96-02bef73115ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708247569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.708247569
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2248479747
Short name T163
Test name
Test status
Simulation time 25992077327 ps
CPU time 41.54 seconds
Started Mar 05 01:41:40 PM PST 24
Finished Mar 05 01:42:23 PM PST 24
Peak memory 200356 kb
Host smart-454745a4-90e4-4788-91ef-170bcc250354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248479747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2248479747
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3249648180
Short name T891
Test name
Test status
Simulation time 15267203471 ps
CPU time 14.85 seconds
Started Mar 05 01:41:40 PM PST 24
Finished Mar 05 01:41:55 PM PST 24
Peak memory 200360 kb
Host smart-ca11d8d8-179c-4503-9308-09691b7eb851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249648180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3249648180
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3885433579
Short name T651
Test name
Test status
Simulation time 24129990789 ps
CPU time 24.13 seconds
Started Mar 05 01:41:39 PM PST 24
Finished Mar 05 01:42:03 PM PST 24
Peak memory 200320 kb
Host smart-789ab35f-95f4-496b-b8d0-38f70c474799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885433579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3885433579
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2691030452
Short name T229
Test name
Test status
Simulation time 87927717347 ps
CPU time 154.25 seconds
Started Mar 05 01:41:43 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 200368 kb
Host smart-108abc30-673a-4814-b0fa-4ac781de7963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691030452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2691030452
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2461066182
Short name T175
Test name
Test status
Simulation time 36202458740 ps
CPU time 40.12 seconds
Started Mar 05 01:41:39 PM PST 24
Finished Mar 05 01:42:19 PM PST 24
Peak memory 200340 kb
Host smart-6a060135-f6d3-4be4-9594-94392812155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461066182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2461066182
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.373613572
Short name T182
Test name
Test status
Simulation time 223297211853 ps
CPU time 94.29 seconds
Started Mar 05 01:41:42 PM PST 24
Finished Mar 05 01:43:17 PM PST 24
Peak memory 200404 kb
Host smart-7ed885f2-3c19-435e-ad36-179ac05423da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373613572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.373613572
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.812305703
Short name T821
Test name
Test status
Simulation time 31933096549 ps
CPU time 27.41 seconds
Started Mar 05 01:41:42 PM PST 24
Finished Mar 05 01:42:10 PM PST 24
Peak memory 200292 kb
Host smart-0904467b-ebe4-49df-ba09-d61401413167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812305703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.812305703
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3989316647
Short name T224
Test name
Test status
Simulation time 56592569146 ps
CPU time 23.55 seconds
Started Mar 05 01:41:42 PM PST 24
Finished Mar 05 01:42:06 PM PST 24
Peak memory 200296 kb
Host smart-55c3265d-c5a6-44ac-8075-9605e212090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989316647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3989316647
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2624409589
Short name T693
Test name
Test status
Simulation time 125089528107 ps
CPU time 27.22 seconds
Started Mar 05 01:41:44 PM PST 24
Finished Mar 05 01:42:12 PM PST 24
Peak memory 200400 kb
Host smart-4aed6b56-9de9-457f-8bfa-81bd36c8a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624409589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2624409589
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.391378492
Short name T511
Test name
Test status
Simulation time 34762870 ps
CPU time 0.55 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:05 PM PST 24
Peak memory 195916 kb
Host smart-c6b825fc-338f-4ac6-aed6-5396a8c21053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391378492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.391378492
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2242679462
Short name T561
Test name
Test status
Simulation time 60945597580 ps
CPU time 101.34 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:35:44 PM PST 24
Peak memory 200368 kb
Host smart-79f38853-0e10-4d4b-a584-babe39ad038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242679462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2242679462
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2989259175
Short name T763
Test name
Test status
Simulation time 278378795783 ps
CPU time 493.34 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:42:16 PM PST 24
Peak memory 200332 kb
Host smart-498b7a32-276a-4765-9a07-708320fd7a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989259175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2989259175
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.2229847818
Short name T24
Test name
Test status
Simulation time 572636002913 ps
CPU time 291.82 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:38:56 PM PST 24
Peak memory 200392 kb
Host smart-93c1f4e1-63f6-45d3-8cfa-0fd6163b7f37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229847818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2229847818
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2264907602
Short name T863
Test name
Test status
Simulation time 95267606332 ps
CPU time 286.21 seconds
Started Mar 05 01:34:03 PM PST 24
Finished Mar 05 01:38:50 PM PST 24
Peak memory 200404 kb
Host smart-f2e4cf79-3585-4514-b5b4-cc1dbf4d7314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264907602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2264907602
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.938682305
Short name T800
Test name
Test status
Simulation time 6557438593 ps
CPU time 15.51 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:18 PM PST 24
Peak memory 199608 kb
Host smart-e5207104-97d0-4277-911c-8daf6dbef8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938682305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.938682305
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2760555474
Short name T112
Test name
Test status
Simulation time 228681911231 ps
CPU time 48.98 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:34:54 PM PST 24
Peak memory 208784 kb
Host smart-13cf11b9-40de-4f0d-adc3-bef4c8884acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760555474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2760555474
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2890722109
Short name T404
Test name
Test status
Simulation time 8108422048 ps
CPU time 97.69 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:35:40 PM PST 24
Peak memory 200416 kb
Host smart-a0f94da9-2cca-4a9b-89d7-9f93fb85ad0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890722109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2890722109
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1278931454
Short name T1068
Test name
Test status
Simulation time 3548347474 ps
CPU time 9.47 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:12 PM PST 24
Peak memory 199160 kb
Host smart-bc06be3a-82f7-48bb-9926-4b68d9f4213d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278931454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1278931454
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.105056681
Short name T989
Test name
Test status
Simulation time 41776383201 ps
CPU time 68.65 seconds
Started Mar 05 01:34:03 PM PST 24
Finished Mar 05 01:35:11 PM PST 24
Peak memory 200156 kb
Host smart-8f12bfaf-b8c8-42ae-8ad0-e3befd6258d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105056681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.105056681
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4202220947
Short name T937
Test name
Test status
Simulation time 39467673179 ps
CPU time 71.54 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:35:13 PM PST 24
Peak memory 196172 kb
Host smart-73cf3017-3a0b-4d1f-a852-fb694eda3576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202220947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4202220947
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1063762820
Short name T621
Test name
Test status
Simulation time 556470099 ps
CPU time 2.9 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:07 PM PST 24
Peak memory 198336 kb
Host smart-2fdc7e8a-6dc2-4191-a2bf-ec25239735e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063762820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1063762820
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.924491044
Short name T228
Test name
Test status
Simulation time 167790703363 ps
CPU time 507.34 seconds
Started Mar 05 01:34:03 PM PST 24
Finished Mar 05 01:42:32 PM PST 24
Peak memory 200336 kb
Host smart-8153704b-ae95-487b-9229-6cdb244f2a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924491044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.924491044
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.24836538
Short name T837
Test name
Test status
Simulation time 6386398817 ps
CPU time 19.55 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:24 PM PST 24
Peak memory 200352 kb
Host smart-428a37dc-c658-49f8-8911-fbb6a14b15db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24836538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.24836538
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1209715074
Short name T172
Test name
Test status
Simulation time 109169958213 ps
CPU time 28.15 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:34:30 PM PST 24
Peak memory 200284 kb
Host smart-d3f788f6-d8bb-4123-83da-566874185bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209715074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1209715074
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.940633002
Short name T818
Test name
Test status
Simulation time 20468873585 ps
CPU time 32.21 seconds
Started Mar 05 01:41:45 PM PST 24
Finished Mar 05 01:42:18 PM PST 24
Peak memory 199568 kb
Host smart-8e2de687-6ca4-4d38-8906-61a443a33f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940633002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.940633002
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.171532944
Short name T639
Test name
Test status
Simulation time 12528147973 ps
CPU time 20.68 seconds
Started Mar 05 01:41:46 PM PST 24
Finished Mar 05 01:42:07 PM PST 24
Peak memory 200328 kb
Host smart-d24e5556-e0b4-48ea-b6f5-63591e19edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171532944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.171532944
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1971782625
Short name T222
Test name
Test status
Simulation time 94653519757 ps
CPU time 157.21 seconds
Started Mar 05 01:41:56 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 200424 kb
Host smart-53c55df4-f073-4724-ab9e-5c7aca052afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971782625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1971782625
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3804255145
Short name T981
Test name
Test status
Simulation time 11540705323 ps
CPU time 18.81 seconds
Started Mar 05 01:41:54 PM PST 24
Finished Mar 05 01:42:13 PM PST 24
Peak memory 199540 kb
Host smart-d49235a6-a0ff-4a69-a65d-b909543d620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804255145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3804255145
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.707832318
Short name T144
Test name
Test status
Simulation time 93779887662 ps
CPU time 85.54 seconds
Started Mar 05 01:41:53 PM PST 24
Finished Mar 05 01:43:19 PM PST 24
Peak memory 200328 kb
Host smart-2a89cf34-05de-4cf4-ba43-368505387a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707832318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.707832318
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2327556837
Short name T531
Test name
Test status
Simulation time 47363280097 ps
CPU time 59.76 seconds
Started Mar 05 01:41:53 PM PST 24
Finished Mar 05 01:42:53 PM PST 24
Peak memory 200352 kb
Host smart-c5d625e5-991f-4489-8ef4-96e7cf86f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327556837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2327556837
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2254084248
Short name T114
Test name
Test status
Simulation time 138895083365 ps
CPU time 241.1 seconds
Started Mar 05 01:41:56 PM PST 24
Finished Mar 05 01:45:57 PM PST 24
Peak memory 200332 kb
Host smart-a08005cf-323c-4bf1-94e7-859a08be2e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254084248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2254084248
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1419968057
Short name T990
Test name
Test status
Simulation time 12191954 ps
CPU time 0.56 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:34:08 PM PST 24
Peak memory 194852 kb
Host smart-0b0d470e-65c2-4328-9316-2aed7652dd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419968057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1419968057
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3774446506
Short name T505
Test name
Test status
Simulation time 21918339939 ps
CPU time 9.99 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:34:15 PM PST 24
Peak memory 200364 kb
Host smart-119cf95c-179f-4ed5-8827-2fadd8c2fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774446506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3774446506
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1762973363
Short name T356
Test name
Test status
Simulation time 36360361963 ps
CPU time 17.2 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:34:25 PM PST 24
Peak memory 200356 kb
Host smart-16c4201b-eaca-47cc-8a1a-8356927e533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762973363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1762973363
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2130935852
Short name T1047
Test name
Test status
Simulation time 29157212567 ps
CPU time 67 seconds
Started Mar 05 01:34:03 PM PST 24
Finished Mar 05 01:35:10 PM PST 24
Peak memory 200316 kb
Host smart-7b21d90d-9388-4958-acd5-c969616cfff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130935852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2130935852
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4013489472
Short name T451
Test name
Test status
Simulation time 1725429620552 ps
CPU time 1362.04 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:56:49 PM PST 24
Peak memory 200308 kb
Host smart-5c021d9f-4e3d-411e-b6d8-5452df9d9338
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013489472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4013489472
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3000431125
Short name T444
Test name
Test status
Simulation time 150724092015 ps
CPU time 587.03 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:43:52 PM PST 24
Peak memory 200312 kb
Host smart-482ddde1-65ec-4fe3-9306-b0839b5d9270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000431125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3000431125
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2787028250
Short name T683
Test name
Test status
Simulation time 11721693297 ps
CPU time 8.85 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:16 PM PST 24
Peak memory 199984 kb
Host smart-752e3c38-94bd-46b5-84fb-af262153a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787028250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2787028250
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4236051990
Short name T398
Test name
Test status
Simulation time 91594418712 ps
CPU time 87.37 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:35:35 PM PST 24
Peak memory 200556 kb
Host smart-21d089bf-4f73-4f1f-8f52-9dd0a29f36f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236051990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4236051990
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2483180768
Short name T534
Test name
Test status
Simulation time 24118911439 ps
CPU time 139.11 seconds
Started Mar 05 01:34:11 PM PST 24
Finished Mar 05 01:36:30 PM PST 24
Peak memory 200316 kb
Host smart-40ac3730-9407-405a-a3cc-2968f45ed37f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483180768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2483180768
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.766333502
Short name T812
Test name
Test status
Simulation time 1511207192 ps
CPU time 7.46 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:12 PM PST 24
Peak memory 198640 kb
Host smart-7bfe9bda-7630-4bd0-bcd6-784a99a7b83b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766333502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.766333502
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2818837224
Short name T1001
Test name
Test status
Simulation time 39201294999 ps
CPU time 26.54 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:34:35 PM PST 24
Peak memory 200236 kb
Host smart-d652830e-40d3-46f1-8e48-b1736b80220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818837224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2818837224
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.446538083
Short name T830
Test name
Test status
Simulation time 2540961345 ps
CPU time 4.26 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:11 PM PST 24
Peak memory 195784 kb
Host smart-ad985b8a-e109-4b3a-a1b4-a27f62f23743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446538083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.446538083
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2325265510
Short name T1090
Test name
Test status
Simulation time 5845976075 ps
CPU time 8.51 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:34:13 PM PST 24
Peak memory 199752 kb
Host smart-7e91dcc2-abbb-4559-a681-cfc3b68796f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325265510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2325265510
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3316789685
Short name T898
Test name
Test status
Simulation time 129425336880 ps
CPU time 188.12 seconds
Started Mar 05 01:34:10 PM PST 24
Finished Mar 05 01:37:18 PM PST 24
Peak memory 216572 kb
Host smart-cb26ba53-6537-4d2d-bfd3-d5c85fa8de81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316789685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3316789685
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3414509090
Short name T430
Test name
Test status
Simulation time 567163022 ps
CPU time 2.35 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:09 PM PST 24
Peak memory 199732 kb
Host smart-7ea3d438-c4c5-4dd6-9968-f2ea4608511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414509090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3414509090
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3509935526
Short name T805
Test name
Test status
Simulation time 61262325028 ps
CPU time 181.26 seconds
Started Mar 05 01:34:02 PM PST 24
Finished Mar 05 01:37:04 PM PST 24
Peak memory 200312 kb
Host smart-91d16c72-fc5f-405f-96e8-df843754170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509935526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3509935526
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2337268418
Short name T739
Test name
Test status
Simulation time 33972200642 ps
CPU time 50.79 seconds
Started Mar 05 01:41:59 PM PST 24
Finished Mar 05 01:42:50 PM PST 24
Peak memory 200376 kb
Host smart-e004e783-d00e-41ef-89d6-75796b05283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337268418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2337268418
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.714692206
Short name T598
Test name
Test status
Simulation time 36969429909 ps
CPU time 17.64 seconds
Started Mar 05 01:41:58 PM PST 24
Finished Mar 05 01:42:15 PM PST 24
Peak memory 200388 kb
Host smart-7bc2c243-b72b-460e-8670-c3b8d63bfca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714692206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.714692206
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2986879511
Short name T315
Test name
Test status
Simulation time 122261536091 ps
CPU time 57.71 seconds
Started Mar 05 01:41:58 PM PST 24
Finished Mar 05 01:42:56 PM PST 24
Peak memory 200328 kb
Host smart-9f46fa75-888f-46f1-a670-c7bb0f98688a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986879511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2986879511
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1161281004
Short name T283
Test name
Test status
Simulation time 55827190433 ps
CPU time 79.02 seconds
Started Mar 05 01:42:00 PM PST 24
Finished Mar 05 01:43:19 PM PST 24
Peak memory 200360 kb
Host smart-ed3e8333-4d27-421d-aa3b-0f9c2d4e09db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161281004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1161281004
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1956104564
Short name T831
Test name
Test status
Simulation time 130369114422 ps
CPU time 53.8 seconds
Started Mar 05 01:41:59 PM PST 24
Finished Mar 05 01:42:52 PM PST 24
Peak memory 199312 kb
Host smart-62d75102-ed13-4a02-99ef-ef3c3fae2926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956104564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1956104564
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2758990620
Short name T702
Test name
Test status
Simulation time 92252828210 ps
CPU time 142.57 seconds
Started Mar 05 01:42:01 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 199772 kb
Host smart-9478a7c3-ee61-40e2-aed7-63a63aff668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758990620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2758990620
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2623097775
Short name T307
Test name
Test status
Simulation time 10973182394 ps
CPU time 32.86 seconds
Started Mar 05 01:41:57 PM PST 24
Finished Mar 05 01:42:30 PM PST 24
Peak memory 200400 kb
Host smart-4357c370-83a2-4a19-8d47-f1338994fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623097775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2623097775
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.875347132
Short name T1074
Test name
Test status
Simulation time 14832199459 ps
CPU time 9.65 seconds
Started Mar 05 01:42:08 PM PST 24
Finished Mar 05 01:42:18 PM PST 24
Peak memory 200272 kb
Host smart-291eec7c-e419-4a9a-8d2f-761ecc7bb47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875347132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.875347132
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.858171111
Short name T789
Test name
Test status
Simulation time 47605025 ps
CPU time 0.56 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:08 PM PST 24
Peak memory 195976 kb
Host smart-836f6eab-0f4f-4d0f-a8a5-7e96430589a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858171111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.858171111
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2505263171
Short name T254
Test name
Test status
Simulation time 37761722606 ps
CPU time 15.79 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:23 PM PST 24
Peak memory 200352 kb
Host smart-8dfebaec-a247-4a37-a64f-54bc941c2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505263171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2505263171
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.126220360
Short name T797
Test name
Test status
Simulation time 16020992966 ps
CPU time 26.48 seconds
Started Mar 05 01:34:06 PM PST 24
Finished Mar 05 01:34:33 PM PST 24
Peak memory 199992 kb
Host smart-9daa7ba1-56bc-430f-9353-e5f643a6bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126220360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.126220360
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2571635393
Short name T731
Test name
Test status
Simulation time 85452413405 ps
CPU time 522.42 seconds
Started Mar 05 01:34:06 PM PST 24
Finished Mar 05 01:42:49 PM PST 24
Peak memory 200408 kb
Host smart-535d44a5-de4b-42dd-94cf-3f4b22eb3b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571635393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2571635393
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.4196526769
Short name T768
Test name
Test status
Simulation time 783063632 ps
CPU time 2.17 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:09 PM PST 24
Peak memory 197292 kb
Host smart-fb68949e-b996-422c-8d12-5c0ae16616b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196526769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4196526769
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3559011501
Short name T563
Test name
Test status
Simulation time 176163480783 ps
CPU time 58.89 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:35:03 PM PST 24
Peak memory 208664 kb
Host smart-21ea097d-85a8-43ba-8e76-68064072df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559011501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3559011501
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.430873044
Short name T660
Test name
Test status
Simulation time 20593760769 ps
CPU time 894.21 seconds
Started Mar 05 01:34:06 PM PST 24
Finished Mar 05 01:49:00 PM PST 24
Peak memory 200352 kb
Host smart-ea494a97-5687-473a-ab9d-2ca08b27c4f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430873044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.430873044
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3527002550
Short name T798
Test name
Test status
Simulation time 1281458925 ps
CPU time 1.83 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:34:10 PM PST 24
Peak memory 196860 kb
Host smart-d53b3a9d-dd36-47b3-82a6-8a30230fa261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527002550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3527002550
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1079470068
Short name T239
Test name
Test status
Simulation time 103957484800 ps
CPU time 75.61 seconds
Started Mar 05 01:34:11 PM PST 24
Finished Mar 05 01:35:27 PM PST 24
Peak memory 198932 kb
Host smart-34411a9e-6653-4497-bee7-8e77606c7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079470068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1079470068
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2666000668
Short name T550
Test name
Test status
Simulation time 41817725323 ps
CPU time 63.13 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:35:11 PM PST 24
Peak memory 195880 kb
Host smart-5f70de0b-99df-4b57-86dd-f7d5164c0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666000668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2666000668
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2714938461
Short name T405
Test name
Test status
Simulation time 11623754710 ps
CPU time 36.06 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:41 PM PST 24
Peak memory 200344 kb
Host smart-78a0f1f6-07d2-4b54-ba98-2875665855ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714938461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2714938461
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.514549983
Short name T557
Test name
Test status
Simulation time 1285123109 ps
CPU time 1.61 seconds
Started Mar 05 01:34:05 PM PST 24
Finished Mar 05 01:34:07 PM PST 24
Peak memory 198892 kb
Host smart-7f5d022c-4e43-4d11-9a9c-fcd03c988178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514549983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.514549983
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3314304657
Short name T198
Test name
Test status
Simulation time 23071872493 ps
CPU time 40.69 seconds
Started Mar 05 01:34:08 PM PST 24
Finished Mar 05 01:34:48 PM PST 24
Peak memory 200240 kb
Host smart-e4516922-9816-44fa-8803-3fbe8fe69a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314304657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3314304657
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.303529901
Short name T169
Test name
Test status
Simulation time 20485012987 ps
CPU time 17.52 seconds
Started Mar 05 01:42:08 PM PST 24
Finished Mar 05 01:42:26 PM PST 24
Peak memory 199044 kb
Host smart-df1693d6-2e7f-4d20-9c20-da41ccb00061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303529901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.303529901
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1486430184
Short name T252
Test name
Test status
Simulation time 22306198083 ps
CPU time 11.48 seconds
Started Mar 05 01:42:05 PM PST 24
Finished Mar 05 01:42:17 PM PST 24
Peak memory 200392 kb
Host smart-e5f425a8-d347-4530-a7c4-ec206e5e570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486430184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1486430184
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2744410810
Short name T720
Test name
Test status
Simulation time 31761960116 ps
CPU time 12.26 seconds
Started Mar 05 01:42:03 PM PST 24
Finished Mar 05 01:42:15 PM PST 24
Peak memory 198068 kb
Host smart-bf41e63b-d238-4b65-98b1-46aa7c4e9546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744410810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2744410810
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3601895731
Short name T238
Test name
Test status
Simulation time 152441040306 ps
CPU time 302.99 seconds
Started Mar 05 01:42:06 PM PST 24
Finished Mar 05 01:47:09 PM PST 24
Peak memory 200272 kb
Host smart-e09e97ff-b990-4efa-9213-5d476169d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601895731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3601895731
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4104323446
Short name T263
Test name
Test status
Simulation time 198892001868 ps
CPU time 84.08 seconds
Started Mar 05 01:42:09 PM PST 24
Finished Mar 05 01:43:33 PM PST 24
Peak memory 200008 kb
Host smart-f0f0a8a0-8e71-40b1-9876-b677e4c11bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104323446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4104323446
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1684269436
Short name T269
Test name
Test status
Simulation time 113834131269 ps
CPU time 177.75 seconds
Started Mar 05 01:42:07 PM PST 24
Finished Mar 05 01:45:05 PM PST 24
Peak memory 199832 kb
Host smart-619543ef-476f-44ab-9ef6-3b88361c9777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684269436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1684269436
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2690045341
Short name T1032
Test name
Test status
Simulation time 152846418096 ps
CPU time 44.62 seconds
Started Mar 05 01:42:09 PM PST 24
Finished Mar 05 01:42:54 PM PST 24
Peak memory 200060 kb
Host smart-d1b9ca70-ee88-4bcb-a058-8fc8c2deccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690045341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2690045341
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.363007538
Short name T131
Test name
Test status
Simulation time 32243880024 ps
CPU time 30.92 seconds
Started Mar 05 01:42:16 PM PST 24
Finished Mar 05 01:42:47 PM PST 24
Peak memory 200280 kb
Host smart-df54e6d3-f074-470b-919e-b5974b912338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363007538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.363007538
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3761568055
Short name T835
Test name
Test status
Simulation time 36673423 ps
CPU time 0.55 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:34:15 PM PST 24
Peak memory 194868 kb
Host smart-120447e8-b2f9-43dd-9d18-acb065a499be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761568055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3761568055
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2496680707
Short name T349
Test name
Test status
Simulation time 179164168732 ps
CPU time 86.8 seconds
Started Mar 05 01:34:12 PM PST 24
Finished Mar 05 01:35:39 PM PST 24
Peak memory 200260 kb
Host smart-84a18be9-b39b-439e-ad67-ff3d0434d7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496680707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2496680707
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_intr.1048813279
Short name T174
Test name
Test status
Simulation time 31458415405 ps
CPU time 53.91 seconds
Started Mar 05 01:34:10 PM PST 24
Finished Mar 05 01:35:04 PM PST 24
Peak memory 200360 kb
Host smart-23a536ce-398e-4ad4-9ab4-7d0ee7d8967e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048813279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1048813279
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2808680765
Short name T415
Test name
Test status
Simulation time 149689885240 ps
CPU time 97.57 seconds
Started Mar 05 01:34:09 PM PST 24
Finished Mar 05 01:35:47 PM PST 24
Peak memory 199800 kb
Host smart-ca4236e3-e8a9-42a6-8b0a-c45e301e2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808680765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2808680765
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1621219418
Short name T659
Test name
Test status
Simulation time 1376260648 ps
CPU time 5.63 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:13 PM PST 24
Peak memory 198088 kb
Host smart-938c3de5-52dc-40a9-adfb-ab3e2e19aefa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621219418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1621219418
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1250007253
Short name T690
Test name
Test status
Simulation time 201911416051 ps
CPU time 22.05 seconds
Started Mar 05 01:34:06 PM PST 24
Finished Mar 05 01:34:29 PM PST 24
Peak memory 200044 kb
Host smart-64019658-82d9-4c62-bb1d-2790e50d625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250007253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1250007253
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3994517533
Short name T676
Test name
Test status
Simulation time 4230303611 ps
CPU time 3.59 seconds
Started Mar 05 01:34:07 PM PST 24
Finished Mar 05 01:34:11 PM PST 24
Peak memory 196192 kb
Host smart-c9d8934b-257b-4e3c-a593-c229f1172825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994517533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3994517533
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3723833785
Short name T44
Test name
Test status
Simulation time 701713112 ps
CPU time 1.65 seconds
Started Mar 05 01:34:04 PM PST 24
Finished Mar 05 01:34:06 PM PST 24
Peak memory 198800 kb
Host smart-0ba1c324-936f-47d2-9052-1998db91d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723833785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3723833785
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.4164065096
Short name T954
Test name
Test status
Simulation time 144946357041 ps
CPU time 59.05 seconds
Started Mar 05 01:34:16 PM PST 24
Finished Mar 05 01:35:16 PM PST 24
Peak memory 200332 kb
Host smart-118561c5-fad5-42c6-96b3-2b888640e148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164065096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4164065096
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1893070307
Short name T118
Test name
Test status
Simulation time 8232628159 ps
CPU time 10.12 seconds
Started Mar 05 01:34:06 PM PST 24
Finished Mar 05 01:34:16 PM PST 24
Peak memory 199796 kb
Host smart-7a345f74-1fdf-4bfa-bd6e-2af0c75bc31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893070307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1893070307
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.709832552
Short name T787
Test name
Test status
Simulation time 85434895091 ps
CPU time 117.57 seconds
Started Mar 05 01:34:12 PM PST 24
Finished Mar 05 01:36:09 PM PST 24
Peak memory 200264 kb
Host smart-dc98da1d-3e78-418b-aa3f-27fc38677d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709832552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.709832552
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1802468095
Short name T736
Test name
Test status
Simulation time 95663902618 ps
CPU time 206.85 seconds
Started Mar 05 01:42:15 PM PST 24
Finished Mar 05 01:45:42 PM PST 24
Peak memory 200340 kb
Host smart-9cc46c26-b860-4408-9524-588e301e9da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802468095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1802468095
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2320862520
Short name T416
Test name
Test status
Simulation time 44582970750 ps
CPU time 4.61 seconds
Started Mar 05 01:42:16 PM PST 24
Finished Mar 05 01:42:21 PM PST 24
Peak memory 200348 kb
Host smart-f37fb96b-9597-47ae-91ae-51533825c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320862520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2320862520
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3750625681
Short name T549
Test name
Test status
Simulation time 79893040774 ps
CPU time 137.03 seconds
Started Mar 05 01:42:12 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 200344 kb
Host smart-f82230ba-40a2-4d39-8bcd-281e152afd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750625681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3750625681
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.707918039
Short name T305
Test name
Test status
Simulation time 12140774583 ps
CPU time 20.52 seconds
Started Mar 05 01:42:14 PM PST 24
Finished Mar 05 01:42:35 PM PST 24
Peak memory 200196 kb
Host smart-b10745d2-adb5-4c19-9947-7952d67f3ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707918039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.707918039
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1174833217
Short name T125
Test name
Test status
Simulation time 109821463151 ps
CPU time 57.54 seconds
Started Mar 05 01:42:19 PM PST 24
Finished Mar 05 01:43:17 PM PST 24
Peak memory 200348 kb
Host smart-201fa42a-fff9-417a-9451-e786dbaf2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174833217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1174833217
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3057556347
Short name T160
Test name
Test status
Simulation time 92912753925 ps
CPU time 40.68 seconds
Started Mar 05 01:42:14 PM PST 24
Finished Mar 05 01:42:54 PM PST 24
Peak memory 199924 kb
Host smart-ddcae030-ebf8-49cf-a1cd-8e7bf94e3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057556347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3057556347
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.622089991
Short name T779
Test name
Test status
Simulation time 24559954555 ps
CPU time 41.02 seconds
Started Mar 05 01:42:21 PM PST 24
Finished Mar 05 01:43:02 PM PST 24
Peak memory 200364 kb
Host smart-efbdeaca-b717-46fa-8d51-682296429a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622089991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.622089991
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3762742369
Short name T197
Test name
Test status
Simulation time 61476232319 ps
CPU time 107.02 seconds
Started Mar 05 01:42:19 PM PST 24
Finished Mar 05 01:44:07 PM PST 24
Peak memory 200340 kb
Host smart-0dd9bdbd-7d03-4af6-9e63-8242d3667865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762742369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3762742369
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1039680488
Short name T127
Test name
Test status
Simulation time 8937859964 ps
CPU time 16.15 seconds
Started Mar 05 01:42:21 PM PST 24
Finished Mar 05 01:42:37 PM PST 24
Peak memory 200392 kb
Host smart-d52fe37e-d2cf-4397-b309-722b9fa28f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039680488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1039680488
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3316893203
Short name T506
Test name
Test status
Simulation time 16421230 ps
CPU time 0.6 seconds
Started Mar 05 01:34:13 PM PST 24
Finished Mar 05 01:34:14 PM PST 24
Peak memory 195980 kb
Host smart-5fced4da-6e40-42f9-b7b8-531037da09f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316893203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3316893203
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3448500018
Short name T628
Test name
Test status
Simulation time 199644717628 ps
CPU time 329.26 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:39:44 PM PST 24
Peak memory 200388 kb
Host smart-75910b20-9388-4530-be4c-43169e795799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448500018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3448500018
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3555161571
Short name T359
Test name
Test status
Simulation time 258914434543 ps
CPU time 42.07 seconds
Started Mar 05 01:34:13 PM PST 24
Finished Mar 05 01:34:55 PM PST 24
Peak memory 199596 kb
Host smart-ac3eaf15-edf7-4ce7-b986-79c74b602661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555161571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3555161571
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.181439612
Short name T406
Test name
Test status
Simulation time 108871420562 ps
CPU time 525.5 seconds
Started Mar 05 01:34:17 PM PST 24
Finished Mar 05 01:43:03 PM PST 24
Peak memory 200340 kb
Host smart-461e9545-28bf-4335-933b-07b596d52b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181439612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.181439612
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1481060773
Short name T623
Test name
Test status
Simulation time 7411206457 ps
CPU time 57.29 seconds
Started Mar 05 01:34:12 PM PST 24
Finished Mar 05 01:35:10 PM PST 24
Peak memory 198412 kb
Host smart-6e7f590d-7f10-466b-b298-eaeca8932139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481060773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1481060773
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1524464233
Short name T656
Test name
Test status
Simulation time 12753247592 ps
CPU time 17.17 seconds
Started Mar 05 01:34:16 PM PST 24
Finished Mar 05 01:34:34 PM PST 24
Peak memory 196248 kb
Host smart-bc6866ae-579b-4f41-b146-b46292fadd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524464233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1524464233
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2666223624
Short name T757
Test name
Test status
Simulation time 10725612416 ps
CPU time 577.05 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:43:52 PM PST 24
Peak memory 200148 kb
Host smart-582fa14d-f8a0-46d0-a319-d2c46355ccca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666223624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2666223624
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4038759552
Short name T657
Test name
Test status
Simulation time 1428438779 ps
CPU time 6.15 seconds
Started Mar 05 01:34:11 PM PST 24
Finished Mar 05 01:34:17 PM PST 24
Peak memory 198328 kb
Host smart-43eaf022-3065-45ae-9a4e-c06aff858a71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038759552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4038759552
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2862638608
Short name T130
Test name
Test status
Simulation time 94161703497 ps
CPU time 42.55 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:34:56 PM PST 24
Peak memory 199828 kb
Host smart-9731d69f-7ab4-434e-aa0e-29cfbb096ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862638608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2862638608
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2561487216
Short name T1052
Test name
Test status
Simulation time 657988924 ps
CPU time 1.81 seconds
Started Mar 05 01:34:17 PM PST 24
Finished Mar 05 01:34:19 PM PST 24
Peak memory 195768 kb
Host smart-b5c74d49-1d7f-46e3-946c-fe77d798c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561487216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2561487216
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2051582258
Short name T778
Test name
Test status
Simulation time 450508497 ps
CPU time 2.24 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:34:16 PM PST 24
Peak memory 198740 kb
Host smart-187f6730-541c-4cdd-9db9-b39dd61849f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051582258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2051582258
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2563045851
Short name T119
Test name
Test status
Simulation time 327842236131 ps
CPU time 216.9 seconds
Started Mar 05 01:34:18 PM PST 24
Finished Mar 05 01:37:55 PM PST 24
Peak memory 200376 kb
Host smart-6af9f963-1646-42ad-985a-ef881be020d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563045851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2563045851
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4148466905
Short name T480
Test name
Test status
Simulation time 2650427828 ps
CPU time 1.4 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:34:15 PM PST 24
Peak memory 198500 kb
Host smart-aafd8c6e-7e74-4c00-b6ce-12b877e114c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148466905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4148466905
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.98010379
Short name T610
Test name
Test status
Simulation time 61004765357 ps
CPU time 46.52 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:35:01 PM PST 24
Peak memory 200348 kb
Host smart-68fea6f7-af02-492a-b302-370c86c1ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98010379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.98010379
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3206024602
Short name T159
Test name
Test status
Simulation time 34155215010 ps
CPU time 55.69 seconds
Started Mar 05 01:42:22 PM PST 24
Finished Mar 05 01:43:18 PM PST 24
Peak memory 200192 kb
Host smart-c688c9f4-a4f5-4dd1-9e40-769fa5e6d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206024602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3206024602
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2014638183
Short name T402
Test name
Test status
Simulation time 110551257668 ps
CPU time 76.65 seconds
Started Mar 05 01:42:22 PM PST 24
Finished Mar 05 01:43:39 PM PST 24
Peak memory 200344 kb
Host smart-10c28284-a822-4d70-b98a-81149c40c758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014638183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2014638183
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4039572304
Short name T154
Test name
Test status
Simulation time 60784642201 ps
CPU time 26.96 seconds
Started Mar 05 01:42:21 PM PST 24
Finished Mar 05 01:42:48 PM PST 24
Peak memory 200372 kb
Host smart-684f064e-1c4f-4115-ba03-3aa44a1ed82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039572304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4039572304
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1890283182
Short name T301
Test name
Test status
Simulation time 35469224966 ps
CPU time 18.24 seconds
Started Mar 05 01:42:22 PM PST 24
Finished Mar 05 01:42:40 PM PST 24
Peak memory 200344 kb
Host smart-d56a918a-f7d9-43b0-b53f-8b0bf48c5940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890283182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1890283182
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3294215920
Short name T235
Test name
Test status
Simulation time 12355364469 ps
CPU time 9.39 seconds
Started Mar 05 01:42:23 PM PST 24
Finished Mar 05 01:42:33 PM PST 24
Peak memory 199028 kb
Host smart-ca5c83b0-5a3e-45a6-b6de-4be52d83fed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294215920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3294215920
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1941072621
Short name T1045
Test name
Test status
Simulation time 72569658622 ps
CPU time 122.24 seconds
Started Mar 05 01:42:30 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 200012 kb
Host smart-4f9debb2-a457-485c-83b8-60960407d381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941072621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1941072621
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1307024880
Short name T589
Test name
Test status
Simulation time 64499107148 ps
CPU time 29.69 seconds
Started Mar 05 01:42:30 PM PST 24
Finished Mar 05 01:43:01 PM PST 24
Peak memory 200352 kb
Host smart-1484ff0a-988d-476b-ad22-1b9e14692250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307024880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1307024880
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3265682625
Short name T524
Test name
Test status
Simulation time 31950129799 ps
CPU time 24.49 seconds
Started Mar 05 01:42:31 PM PST 24
Finished Mar 05 01:42:55 PM PST 24
Peak memory 200324 kb
Host smart-16d192d3-5654-4029-b57c-8a7ee7122577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265682625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3265682625
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2655597742
Short name T941
Test name
Test status
Simulation time 57386794 ps
CPU time 0.53 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:34:23 PM PST 24
Peak memory 194928 kb
Host smart-2b340446-8ddb-45d1-bd2a-c57be2457632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655597742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2655597742
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2446819366
Short name T329
Test name
Test status
Simulation time 110562832848 ps
CPU time 58.52 seconds
Started Mar 05 01:34:17 PM PST 24
Finished Mar 05 01:35:16 PM PST 24
Peak memory 200356 kb
Host smart-d35e8f75-08dd-411b-b45e-a619576e2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446819366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2446819366
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3030036412
Short name T992
Test name
Test status
Simulation time 93122351602 ps
CPU time 60.16 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:35:15 PM PST 24
Peak memory 200408 kb
Host smart-6027d7ec-2067-4d03-b561-c216ffe1f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030036412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3030036412
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3902390865
Short name T321
Test name
Test status
Simulation time 98681610939 ps
CPU time 26.21 seconds
Started Mar 05 01:34:13 PM PST 24
Finished Mar 05 01:34:40 PM PST 24
Peak memory 200412 kb
Host smart-f38995d4-9564-4bbd-be33-6d28f39ddc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902390865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3902390865
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4013547358
Short name T950
Test name
Test status
Simulation time 271787862193 ps
CPU time 233.81 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:38:09 PM PST 24
Peak memory 200344 kb
Host smart-fb62cf0f-0e52-46ff-8d63-793a4c01ef20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013547358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4013547358
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3600337421
Short name T6
Test name
Test status
Simulation time 266104472312 ps
CPU time 481.3 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:42:24 PM PST 24
Peak memory 200400 kb
Host smart-124f7ace-44e9-4672-b31a-3766ca51c176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600337421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3600337421
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2139577981
Short name T631
Test name
Test status
Simulation time 5622424869 ps
CPU time 5.18 seconds
Started Mar 05 01:34:21 PM PST 24
Finished Mar 05 01:34:26 PM PST 24
Peak memory 199584 kb
Host smart-fdc15371-141a-4663-a4c8-9e44be75d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139577981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2139577981
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2891937683
Short name T663
Test name
Test status
Simulation time 10742991985 ps
CPU time 16.11 seconds
Started Mar 05 01:34:16 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 194000 kb
Host smart-a9b661c5-a5cb-47a7-9c27-25855e1f8664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891937683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2891937683
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.810744255
Short name T901
Test name
Test status
Simulation time 16240414773 ps
CPU time 70.68 seconds
Started Mar 05 01:34:25 PM PST 24
Finished Mar 05 01:35:36 PM PST 24
Peak memory 200392 kb
Host smart-00989fe2-3765-4a9d-8bc7-7a6b96cd0a00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810744255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.810744255
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.601743994
Short name T716
Test name
Test status
Simulation time 179312961 ps
CPU time 1.09 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:34:16 PM PST 24
Peak memory 198360 kb
Host smart-cb625bd1-8dbe-49c1-91ad-f5cf9b317256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601743994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.601743994
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.851570412
Short name T323
Test name
Test status
Simulation time 229045649042 ps
CPU time 372.44 seconds
Started Mar 05 01:34:14 PM PST 24
Finished Mar 05 01:40:27 PM PST 24
Peak memory 200316 kb
Host smart-80eaf084-9ba5-4900-bb25-adff10e56a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851570412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.851570412
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3523034477
Short name T421
Test name
Test status
Simulation time 5333891553 ps
CPU time 2.84 seconds
Started Mar 05 01:34:15 PM PST 24
Finished Mar 05 01:34:18 PM PST 24
Peak memory 196272 kb
Host smart-5607d445-d745-4ef6-a06b-82b8f44785f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523034477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3523034477
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.442438319
Short name T795
Test name
Test status
Simulation time 135061918 ps
CPU time 0.91 seconds
Started Mar 05 01:34:13 PM PST 24
Finished Mar 05 01:34:14 PM PST 24
Peak memory 197756 kb
Host smart-a8e53dad-58fc-4448-9d6a-ad35f66e5723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442438319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.442438319
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1231554970
Short name T121
Test name
Test status
Simulation time 353337969755 ps
CPU time 1118.57 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:53:08 PM PST 24
Peak memory 200308 kb
Host smart-ef8e0809-3611-4ffe-9f0c-8136314626cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231554970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1231554970
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3353619698
Short name T897
Test name
Test status
Simulation time 15143039166 ps
CPU time 15.14 seconds
Started Mar 05 01:34:16 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 200300 kb
Host smart-bb6215df-6b7a-48d5-847e-8dbc61df7efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353619698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3353619698
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1231701395
Short name T412
Test name
Test status
Simulation time 86523207603 ps
CPU time 155.74 seconds
Started Mar 05 01:34:17 PM PST 24
Finished Mar 05 01:36:53 PM PST 24
Peak memory 200348 kb
Host smart-79ef1b47-f8cf-4a45-85bb-f44885fc3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231701395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1231701395
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2567695374
Short name T872
Test name
Test status
Simulation time 39588920482 ps
CPU time 53.4 seconds
Started Mar 05 01:42:29 PM PST 24
Finished Mar 05 01:43:23 PM PST 24
Peak memory 200240 kb
Host smart-139cb5b9-d990-4447-b1fe-533c0fa44c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567695374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2567695374
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2647162255
Short name T871
Test name
Test status
Simulation time 34517717491 ps
CPU time 58.69 seconds
Started Mar 05 01:42:29 PM PST 24
Finished Mar 05 01:43:28 PM PST 24
Peak memory 200076 kb
Host smart-9c24c68f-71e5-4ae7-8233-f2775bff76a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647162255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2647162255
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2037386030
Short name T1061
Test name
Test status
Simulation time 290248040906 ps
CPU time 28.52 seconds
Started Mar 05 01:42:37 PM PST 24
Finished Mar 05 01:43:06 PM PST 24
Peak memory 200348 kb
Host smart-4960ef33-1b5e-4f17-b023-2cd50190fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037386030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2037386030
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2730289389
Short name T972
Test name
Test status
Simulation time 41024089993 ps
CPU time 65.85 seconds
Started Mar 05 01:42:33 PM PST 24
Finished Mar 05 01:43:40 PM PST 24
Peak memory 200328 kb
Host smart-926e6f31-c28d-4dac-9e23-899e90c3ebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730289389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2730289389
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.159923654
Short name T199
Test name
Test status
Simulation time 18902121828 ps
CPU time 18.99 seconds
Started Mar 05 01:42:43 PM PST 24
Finished Mar 05 01:43:02 PM PST 24
Peak memory 198912 kb
Host smart-754c8e5e-736f-41a9-b6a4-8f5e7758b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159923654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.159923654
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.710947499
Short name T1040
Test name
Test status
Simulation time 140099876449 ps
CPU time 57.69 seconds
Started Mar 05 01:42:40 PM PST 24
Finished Mar 05 01:43:39 PM PST 24
Peak memory 200376 kb
Host smart-35f1b4cc-635d-4bf4-9da1-dc8ff24be736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710947499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.710947499
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2843403715
Short name T604
Test name
Test status
Simulation time 211184771721 ps
CPU time 91.42 seconds
Started Mar 05 01:42:41 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 199920 kb
Host smart-3ebec8bc-6d5c-498c-9ce8-1db1ce0eb8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843403715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2843403715
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1752075297
Short name T350
Test name
Test status
Simulation time 59800073203 ps
CPU time 34.85 seconds
Started Mar 05 01:42:41 PM PST 24
Finished Mar 05 01:43:17 PM PST 24
Peak memory 200404 kb
Host smart-6720deb5-4458-4621-80d3-a3ad183b35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752075297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1752075297
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1337074225
Short name T540
Test name
Test status
Simulation time 47213808165 ps
CPU time 20.03 seconds
Started Mar 05 01:42:41 PM PST 24
Finished Mar 05 01:43:01 PM PST 24
Peak memory 200232 kb
Host smart-76950533-1358-4387-8059-30c8a9d23fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337074225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1337074225
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.840033392
Short name T58
Test name
Test status
Simulation time 30631916766 ps
CPU time 27.49 seconds
Started Mar 05 01:42:38 PM PST 24
Finished Mar 05 01:43:06 PM PST 24
Peak memory 199988 kb
Host smart-f9a1e16e-bf8c-4926-8939-78737b4f2a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840033392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.840033392
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2708483704
Short name T1042
Test name
Test status
Simulation time 13559624 ps
CPU time 0.58 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:33:09 PM PST 24
Peak memory 194856 kb
Host smart-fdefb1db-2bc0-4198-8ba2-0381762c0c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708483704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2708483704
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.990619206
Short name T770
Test name
Test status
Simulation time 31332440002 ps
CPU time 13.72 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:33:22 PM PST 24
Peak memory 199784 kb
Host smart-89226b83-226f-4f40-8e86-ab94a024e8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990619206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.990619206
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2326138241
Short name T661
Test name
Test status
Simulation time 139610912646 ps
CPU time 58.55 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:34:03 PM PST 24
Peak memory 200232 kb
Host smart-d23dc150-c313-46c9-883c-662f5b8cda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326138241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2326138241
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2919838259
Short name T185
Test name
Test status
Simulation time 17557466707 ps
CPU time 26.37 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:33:32 PM PST 24
Peak memory 200396 kb
Host smart-cd18860f-fc2b-4e4d-988b-9647511b9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919838259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2919838259
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.186235331
Short name T96
Test name
Test status
Simulation time 9100749642 ps
CPU time 4.8 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:33:10 PM PST 24
Peak memory 198648 kb
Host smart-dda622b8-f25f-40bf-a7f7-1050262a5961
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186235331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.186235331
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.113483172
Short name T501
Test name
Test status
Simulation time 101955682532 ps
CPU time 676.41 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:44:22 PM PST 24
Peak memory 200336 kb
Host smart-5a998db5-43a1-42d9-954e-87de7c5e7ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113483172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.113483172
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3419475063
Short name T443
Test name
Test status
Simulation time 12522684538 ps
CPU time 25.21 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:33:30 PM PST 24
Peak memory 198940 kb
Host smart-40f752eb-18e8-4869-87f3-b101114e538d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419475063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3419475063
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1909167994
Short name T475
Test name
Test status
Simulation time 7868985589 ps
CPU time 12.65 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 194180 kb
Host smart-cf9ca18a-5d48-4a42-9ab4-d91c83dcb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909167994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1909167994
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1174636203
Short name T862
Test name
Test status
Simulation time 13095032841 ps
CPU time 756.5 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:45:45 PM PST 24
Peak memory 200404 kb
Host smart-d3499f86-3e5c-47ec-820d-5b832a767511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174636203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1174636203
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1843164684
Short name T682
Test name
Test status
Simulation time 2950126690 ps
CPU time 7.49 seconds
Started Mar 05 01:33:11 PM PST 24
Finished Mar 05 01:33:19 PM PST 24
Peak memory 198972 kb
Host smart-45a1bbf6-0ba7-4668-9d0d-7d86a9747fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843164684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1843164684
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.891044313
Short name T882
Test name
Test status
Simulation time 26532336808 ps
CPU time 42.84 seconds
Started Mar 05 01:33:06 PM PST 24
Finished Mar 05 01:33:49 PM PST 24
Peak memory 200332 kb
Host smart-9d44ea4d-4716-4c84-8c76-4c8632ca537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891044313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.891044313
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1530811035
Short name T396
Test name
Test status
Simulation time 2360337655 ps
CPU time 4.56 seconds
Started Mar 05 01:33:16 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 195924 kb
Host smart-c83b6f63-a6e0-460e-bb52-0ade6a023f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530811035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1530811035
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2314946186
Short name T93
Test name
Test status
Simulation time 268360577 ps
CPU time 0.88 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:33:08 PM PST 24
Peak memory 217864 kb
Host smart-75026f66-dd91-4e63-aefb-e6e0fdd17012
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314946186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2314946186
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2225829037
Short name T908
Test name
Test status
Simulation time 286063193 ps
CPU time 1.23 seconds
Started Mar 05 01:33:04 PM PST 24
Finished Mar 05 01:33:06 PM PST 24
Peak memory 198656 kb
Host smart-c9e4205e-f3e4-450f-8791-08456e733685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225829037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2225829037
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3928212341
Short name T109
Test name
Test status
Simulation time 337036241360 ps
CPU time 558.44 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:42:26 PM PST 24
Peak memory 203228 kb
Host smart-c3e30f50-094c-4d04-a29a-2c2fd56d057f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928212341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3928212341
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2123174765
Short name T539
Test name
Test status
Simulation time 1838159210 ps
CPU time 4.05 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:33:12 PM PST 24
Peak memory 198392 kb
Host smart-a9ef6a1e-7e08-4af5-89fd-89145ace7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123174765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2123174765
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4159973889
Short name T666
Test name
Test status
Simulation time 87026274915 ps
CPU time 178.59 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:36:07 PM PST 24
Peak memory 200344 kb
Host smart-9ee82819-05a8-4f5b-8542-adb0dc02a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159973889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4159973889
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.192017574
Short name T586
Test name
Test status
Simulation time 23041559 ps
CPU time 0.55 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:34:24 PM PST 24
Peak memory 194864 kb
Host smart-de3f91a6-e68a-4ad8-bd1a-2b9de8e0b387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192017574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.192017574
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.235252850
Short name T227
Test name
Test status
Simulation time 185312205028 ps
CPU time 306.12 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:39:35 PM PST 24
Peak memory 200416 kb
Host smart-a81bbcbb-dae4-42a2-b6c9-0db029820945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235252850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.235252850
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2078914851
Short name T675
Test name
Test status
Simulation time 111215169494 ps
CPU time 44.28 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:35:08 PM PST 24
Peak memory 199460 kb
Host smart-59fe83eb-7978-4e5b-a84e-14756fd87f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078914851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2078914851
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1922303575
Short name T1048
Test name
Test status
Simulation time 133770615124 ps
CPU time 240.65 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:38:24 PM PST 24
Peak memory 200344 kb
Host smart-b449b0a5-2f8f-4602-bcce-c9df25501486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922303575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1922303575
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.533073285
Short name T801
Test name
Test status
Simulation time 30374104667 ps
CPU time 44.23 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:35:14 PM PST 24
Peak memory 198688 kb
Host smart-568dbc2b-bd8b-4abd-a4fd-df360a66f928
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533073285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.533073285
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3369293892
Short name T977
Test name
Test status
Simulation time 195308076981 ps
CPU time 451.96 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:42:02 PM PST 24
Peak memory 200336 kb
Host smart-3d208cbd-61d1-41f8-9283-a80200084aa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369293892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3369293892
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4220980261
Short name T583
Test name
Test status
Simulation time 11807787829 ps
CPU time 28.23 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:34:51 PM PST 24
Peak memory 198912 kb
Host smart-73450bb0-7dca-4719-97f0-1e9fab43b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220980261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4220980261
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.20038793
Short name T799
Test name
Test status
Simulation time 5677871236 ps
CPU time 9.09 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 194072 kb
Host smart-38e1054e-236d-41e1-882f-465185b5acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20038793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.20038793
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2766410818
Short name T527
Test name
Test status
Simulation time 15736194668 ps
CPU time 186.6 seconds
Started Mar 05 01:34:26 PM PST 24
Finished Mar 05 01:37:32 PM PST 24
Peak memory 200308 kb
Host smart-632a955e-e0c9-454a-890e-d258ad2324d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766410818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2766410818
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3116949692
Short name T854
Test name
Test status
Simulation time 1487280111 ps
CPU time 9.6 seconds
Started Mar 05 01:34:24 PM PST 24
Finished Mar 05 01:34:34 PM PST 24
Peak memory 198572 kb
Host smart-ba1fe26a-9a5f-413e-a6a1-bc80910c5f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116949692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3116949692
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2200234383
Short name T840
Test name
Test status
Simulation time 53986989229 ps
CPU time 76.31 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:35:40 PM PST 24
Peak memory 199588 kb
Host smart-8522b62b-b41d-4827-bcc9-9d9b5c265ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200234383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2200234383
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.141705938
Short name T434
Test name
Test status
Simulation time 3181628128 ps
CPU time 3.56 seconds
Started Mar 05 01:34:28 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 195880 kb
Host smart-7ba18cc3-89fa-4efd-bb20-f2738a41b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141705938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.141705938
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4289903327
Short name T624
Test name
Test status
Simulation time 459302038 ps
CPU time 2.28 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:34:24 PM PST 24
Peak memory 198876 kb
Host smart-90ed42af-f457-41bb-ba37-8c23aa0fa91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289903327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4289903327
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.743881118
Short name T1063
Test name
Test status
Simulation time 156157683932 ps
CPU time 1133.75 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:53:16 PM PST 24
Peak memory 200336 kb
Host smart-54e1cda5-8024-48fd-825b-198962f4f727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743881118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.743881118
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4172990452
Short name T964
Test name
Test status
Simulation time 1235373875 ps
CPU time 1.95 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 198980 kb
Host smart-f7708496-51f4-4ff8-a514-29688fb5f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172990452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4172990452
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1214467515
Short name T1072
Test name
Test status
Simulation time 28174026063 ps
CPU time 11.88 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:34:35 PM PST 24
Peak memory 197252 kb
Host smart-36403a2f-5675-48ff-a3d1-756f8c74569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214467515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1214467515
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1774279928
Short name T843
Test name
Test status
Simulation time 182003340940 ps
CPU time 58.32 seconds
Started Mar 05 01:42:50 PM PST 24
Finished Mar 05 01:43:49 PM PST 24
Peak memory 200332 kb
Host smart-f89dc72e-d4a0-408a-9d87-a48b8acf9aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774279928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1774279928
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2581798637
Short name T256
Test name
Test status
Simulation time 22866845904 ps
CPU time 33.96 seconds
Started Mar 05 01:42:39 PM PST 24
Finished Mar 05 01:43:14 PM PST 24
Peak memory 199748 kb
Host smart-0a0a1917-27d9-4468-b93b-f60eaf157652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581798637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2581798637
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.4228285889
Short name T1053
Test name
Test status
Simulation time 104522322632 ps
CPU time 173.55 seconds
Started Mar 05 01:42:44 PM PST 24
Finished Mar 05 01:45:38 PM PST 24
Peak memory 200296 kb
Host smart-d51d3471-e261-414d-b2a6-2f6a28928496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228285889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.4228285889
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3806665449
Short name T140
Test name
Test status
Simulation time 12696567350 ps
CPU time 9.64 seconds
Started Mar 05 01:42:43 PM PST 24
Finished Mar 05 01:42:53 PM PST 24
Peak memory 199968 kb
Host smart-09942f54-56a0-431a-a51b-44c382200aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806665449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3806665449
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4054519745
Short name T155
Test name
Test status
Simulation time 62217069518 ps
CPU time 107.56 seconds
Started Mar 05 01:42:48 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 200280 kb
Host smart-e08aa93d-686d-471a-a6f5-22c12f94e41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054519745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4054519745
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2587479584
Short name T602
Test name
Test status
Simulation time 9041914407 ps
CPU time 15.47 seconds
Started Mar 05 01:42:45 PM PST 24
Finished Mar 05 01:43:01 PM PST 24
Peak memory 199316 kb
Host smart-fad40e17-4e34-44f1-b596-45f7896dd4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587479584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2587479584
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2323993290
Short name T311
Test name
Test status
Simulation time 27252036682 ps
CPU time 24.38 seconds
Started Mar 05 01:42:45 PM PST 24
Finished Mar 05 01:43:09 PM PST 24
Peak memory 200340 kb
Host smart-f8e5828f-6ae7-45b2-a35a-a6e77a9adc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323993290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2323993290
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2832266966
Short name T31
Test name
Test status
Simulation time 12845583 ps
CPU time 0.56 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 194916 kb
Host smart-bb24a725-aae8-44b7-80d6-a6bb8ae616e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832266966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2832266966
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4097854104
Short name T994
Test name
Test status
Simulation time 138334877856 ps
CPU time 229.27 seconds
Started Mar 05 01:34:22 PM PST 24
Finished Mar 05 01:38:12 PM PST 24
Peak memory 200376 kb
Host smart-ee9adc97-71dc-41c6-8467-521ed2a9ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097854104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4097854104
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1847513233
Short name T596
Test name
Test status
Simulation time 102183851482 ps
CPU time 10.13 seconds
Started Mar 05 01:34:25 PM PST 24
Finished Mar 05 01:34:36 PM PST 24
Peak memory 198300 kb
Host smart-2b725d5f-6b60-4828-9bef-d97bfae271ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847513233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1847513233
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1848792164
Short name T302
Test name
Test status
Simulation time 16511436866 ps
CPU time 28.76 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:34:52 PM PST 24
Peak memory 200400 kb
Host smart-647939b4-2490-431d-a8b9-e49897321366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848792164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1848792164
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2239933374
Short name T445
Test name
Test status
Simulation time 97758052647 ps
CPU time 29.34 seconds
Started Mar 05 01:34:28 PM PST 24
Finished Mar 05 01:34:58 PM PST 24
Peak memory 200416 kb
Host smart-4c658744-13e8-48b6-abae-395f81ebbc7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239933374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2239933374
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.659575160
Short name T750
Test name
Test status
Simulation time 259342777770 ps
CPU time 163.45 seconds
Started Mar 05 01:34:31 PM PST 24
Finished Mar 05 01:37:15 PM PST 24
Peak memory 200344 kb
Host smart-77a6f079-0720-46c6-8830-3ddac902f163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659575160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.659575160
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2871897630
Short name T741
Test name
Test status
Simulation time 1782344519 ps
CPU time 1.56 seconds
Started Mar 05 01:34:28 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 196816 kb
Host smart-fe0e346c-054a-4059-b091-e67d1b84296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871897630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2871897630
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3426345908
Short name T827
Test name
Test status
Simulation time 95744537057 ps
CPU time 51.82 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:35:21 PM PST 24
Peak memory 199320 kb
Host smart-6ef50e2c-8380-4402-9c06-099aa967b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426345908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3426345908
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1769725918
Short name T723
Test name
Test status
Simulation time 12781287133 ps
CPU time 167.21 seconds
Started Mar 05 01:34:27 PM PST 24
Finished Mar 05 01:37:15 PM PST 24
Peak memory 199812 kb
Host smart-96c81043-e2d7-4949-b419-ff929933b11f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769725918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1769725918
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2203625727
Short name T861
Test name
Test status
Simulation time 707165099 ps
CPU time 8.82 seconds
Started Mar 05 01:34:23 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 198492 kb
Host smart-44204e20-dc45-4504-98ca-02aeb455822d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203625727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2203625727
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3155748910
Short name T483
Test name
Test status
Simulation time 62804669240 ps
CPU time 92.41 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:36:02 PM PST 24
Peak memory 199568 kb
Host smart-a33ee59c-4840-4bd9-8095-d47ea313bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155748910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3155748910
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2856649877
Short name T400
Test name
Test status
Simulation time 5314660039 ps
CPU time 1.67 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:34:32 PM PST 24
Peak memory 196176 kb
Host smart-001f8c8f-9733-45d4-bba1-a00dbf91ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856649877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2856649877
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.4052166860
Short name T464
Test name
Test status
Simulation time 109951176 ps
CPU time 0.93 seconds
Started Mar 05 01:34:24 PM PST 24
Finished Mar 05 01:34:25 PM PST 24
Peak memory 197136 kb
Host smart-71acd4c8-a193-4e09-91a8-57afa09f3323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052166860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4052166860
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1159875912
Short name T946
Test name
Test status
Simulation time 179793776331 ps
CPU time 311.43 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:39:41 PM PST 24
Peak memory 200388 kb
Host smart-3050032b-c752-438f-9cf2-30ab286201f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159875912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1159875912
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1809989230
Short name T3
Test name
Test status
Simulation time 13248627655 ps
CPU time 18.44 seconds
Started Mar 05 01:34:28 PM PST 24
Finished Mar 05 01:34:47 PM PST 24
Peak memory 200264 kb
Host smart-9967fa61-954b-4699-96fa-a6f967021f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809989230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1809989230
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1260561433
Short name T552
Test name
Test status
Simulation time 77543380154 ps
CPU time 34.38 seconds
Started Mar 05 01:34:24 PM PST 24
Finished Mar 05 01:34:59 PM PST 24
Peak memory 200328 kb
Host smart-651e7ca7-08f5-4fdc-9fff-266d55d8f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260561433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1260561433
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1964629091
Short name T247
Test name
Test status
Simulation time 27779619462 ps
CPU time 49.33 seconds
Started Mar 05 01:42:50 PM PST 24
Finished Mar 05 01:43:39 PM PST 24
Peak memory 200352 kb
Host smart-a48d1cd4-c122-457a-a71d-aeca2521bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964629091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1964629091
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2155760524
Short name T143
Test name
Test status
Simulation time 195632496711 ps
CPU time 266.75 seconds
Started Mar 05 01:42:45 PM PST 24
Finished Mar 05 01:47:12 PM PST 24
Peak memory 199524 kb
Host smart-49e0654b-3d55-42fc-af4e-0c4df9f8cbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155760524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2155760524
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.385015613
Short name T176
Test name
Test status
Simulation time 74997417171 ps
CPU time 27.06 seconds
Started Mar 05 01:42:47 PM PST 24
Finished Mar 05 01:43:15 PM PST 24
Peak memory 199324 kb
Host smart-1a57ec39-3a4b-4442-a5b5-6fef2b992e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385015613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.385015613
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2267501434
Short name T867
Test name
Test status
Simulation time 11688934122 ps
CPU time 20.22 seconds
Started Mar 05 01:42:45 PM PST 24
Finished Mar 05 01:43:05 PM PST 24
Peak memory 198476 kb
Host smart-fe90ff73-4a99-4552-9130-bc097496f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267501434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2267501434
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3247542701
Short name T864
Test name
Test status
Simulation time 83906248403 ps
CPU time 38.11 seconds
Started Mar 05 01:42:47 PM PST 24
Finished Mar 05 01:43:26 PM PST 24
Peak memory 200356 kb
Host smart-5d7e78f9-cbb4-4a98-971e-3d40f15293bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247542701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3247542701
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.4060597873
Short name T1083
Test name
Test status
Simulation time 153164053683 ps
CPU time 17.78 seconds
Started Mar 05 01:42:57 PM PST 24
Finished Mar 05 01:43:15 PM PST 24
Peak memory 200028 kb
Host smart-a457b22b-eaf0-4271-9486-1949ef25ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060597873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4060597873
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1549332736
Short name T164
Test name
Test status
Simulation time 125116740732 ps
CPU time 12.36 seconds
Started Mar 05 01:43:03 PM PST 24
Finished Mar 05 01:43:16 PM PST 24
Peak memory 200368 kb
Host smart-828b4d81-620f-4400-b1e8-ba9827afd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549332736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1549332736
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3260027273
Short name T615
Test name
Test status
Simulation time 18385704 ps
CPU time 0.57 seconds
Started Mar 05 01:34:36 PM PST 24
Finished Mar 05 01:34:36 PM PST 24
Peak memory 195932 kb
Host smart-bc2b0ba7-ac2f-4840-81cc-39474228fcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260027273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3260027273
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1597019873
Short name T944
Test name
Test status
Simulation time 69594343544 ps
CPU time 106.85 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:36:17 PM PST 24
Peak memory 200348 kb
Host smart-3b2756f0-5905-4d8c-afed-698b6b5fe3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597019873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1597019873
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2621903450
Short name T765
Test name
Test status
Simulation time 168949353692 ps
CPU time 13.89 seconds
Started Mar 05 01:34:26 PM PST 24
Finished Mar 05 01:34:40 PM PST 24
Peak memory 198256 kb
Host smart-1b4cdfb7-4e86-4b38-b43c-2e9e5290e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621903450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2621903450
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1081648371
Short name T976
Test name
Test status
Simulation time 180984206555 ps
CPU time 49.23 seconds
Started Mar 05 01:34:30 PM PST 24
Finished Mar 05 01:35:19 PM PST 24
Peak memory 200196 kb
Host smart-737b8e0b-5f56-4a0a-9492-7db497edfccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081648371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1081648371
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2072939909
Short name T450
Test name
Test status
Simulation time 259074432556 ps
CPU time 361.82 seconds
Started Mar 05 01:34:27 PM PST 24
Finished Mar 05 01:40:29 PM PST 24
Peak memory 200296 kb
Host smart-57e66f34-0943-4909-bbd9-ae824674de87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072939909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2072939909
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1455764251
Short name T849
Test name
Test status
Simulation time 44661297863 ps
CPU time 158.54 seconds
Started Mar 05 01:34:34 PM PST 24
Finished Mar 05 01:37:13 PM PST 24
Peak memory 200336 kb
Host smart-0ed437d5-dcae-4715-b646-98f23f7bc8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455764251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1455764251
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1799933695
Short name T457
Test name
Test status
Simulation time 10070597778 ps
CPU time 13.65 seconds
Started Mar 05 01:34:40 PM PST 24
Finished Mar 05 01:34:55 PM PST 24
Peak memory 200284 kb
Host smart-4a760d76-4f41-4f54-af10-218669d5862e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799933695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1799933695
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3148770043
Short name T397
Test name
Test status
Simulation time 45060143406 ps
CPU time 77.87 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:35:47 PM PST 24
Peak memory 197656 kb
Host smart-0765e968-9a96-4498-a496-59ad76ae9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148770043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3148770043
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2212855466
Short name T5
Test name
Test status
Simulation time 18134607752 ps
CPU time 478.48 seconds
Started Mar 05 01:34:48 PM PST 24
Finished Mar 05 01:42:47 PM PST 24
Peak memory 200320 kb
Host smart-fbde4108-87aa-452d-bb0a-a331bbcece7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212855466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2212855466
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.710688193
Short name T577
Test name
Test status
Simulation time 3209429875 ps
CPU time 33.07 seconds
Started Mar 05 01:34:27 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 198660 kb
Host smart-ff67d880-704e-4251-b7e5-696b414e1f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710688193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.710688193
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.679539506
Short name T357
Test name
Test status
Simulation time 102666678965 ps
CPU time 183.7 seconds
Started Mar 05 01:34:35 PM PST 24
Finished Mar 05 01:37:39 PM PST 24
Peak memory 200368 kb
Host smart-2d6a1b92-81f6-47b5-a336-debf3c18aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679539506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.679539506
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1887068467
Short name T836
Test name
Test status
Simulation time 2124972869 ps
CPU time 2.19 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 195900 kb
Host smart-7cf490b0-37f9-4f57-a556-81dcfad9e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887068467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1887068467
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.76509311
Short name T846
Test name
Test status
Simulation time 451242273 ps
CPU time 2.58 seconds
Started Mar 05 01:34:28 PM PST 24
Finished Mar 05 01:34:31 PM PST 24
Peak memory 198820 kb
Host smart-796bb0b7-c75f-4435-aad6-c99bdfcf552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76509311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.76509311
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1715470009
Short name T98
Test name
Test status
Simulation time 157289017252 ps
CPU time 1173.38 seconds
Started Mar 05 01:34:36 PM PST 24
Finished Mar 05 01:54:09 PM PST 24
Peak memory 199640 kb
Host smart-d9e8a762-822c-49bb-805c-865818967d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715470009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1715470009
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1501992377
Short name T1025
Test name
Test status
Simulation time 1465487941 ps
CPU time 4.26 seconds
Started Mar 05 01:34:38 PM PST 24
Finished Mar 05 01:34:44 PM PST 24
Peak memory 198396 kb
Host smart-9d6ba966-5f82-4a84-97e2-cabc55499923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501992377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1501992377
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3543698657
Short name T670
Test name
Test status
Simulation time 34138335895 ps
CPU time 65.66 seconds
Started Mar 05 01:34:29 PM PST 24
Finished Mar 05 01:35:35 PM PST 24
Peak memory 200440 kb
Host smart-81cd679b-ba4c-4f68-80e9-74c5dbeaa704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543698657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3543698657
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1987554666
Short name T187
Test name
Test status
Simulation time 23262415481 ps
CPU time 17.57 seconds
Started Mar 05 01:43:02 PM PST 24
Finished Mar 05 01:43:20 PM PST 24
Peak memory 200296 kb
Host smart-fe91cd62-1f03-46eb-8258-f27a3056df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987554666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1987554666
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2084941857
Short name T646
Test name
Test status
Simulation time 52803946003 ps
CPU time 24.32 seconds
Started Mar 05 01:43:11 PM PST 24
Finished Mar 05 01:43:35 PM PST 24
Peak memory 200332 kb
Host smart-b1351826-5e68-4789-8c82-5d392f41762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084941857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2084941857
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1689097661
Short name T279
Test name
Test status
Simulation time 47334535028 ps
CPU time 15.06 seconds
Started Mar 05 01:43:08 PM PST 24
Finished Mar 05 01:43:23 PM PST 24
Peak memory 200360 kb
Host smart-8d483e1b-3cc1-43b6-ac18-a307b2a21e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689097661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1689097661
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1576903409
Short name T817
Test name
Test status
Simulation time 83229234693 ps
CPU time 76.26 seconds
Started Mar 05 01:43:06 PM PST 24
Finished Mar 05 01:44:22 PM PST 24
Peak memory 200244 kb
Host smart-d3b4ac51-ecf4-41b3-b00f-cad806f7b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576903409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1576903409
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1289395545
Short name T618
Test name
Test status
Simulation time 55840328351 ps
CPU time 24.2 seconds
Started Mar 05 01:43:08 PM PST 24
Finished Mar 05 01:43:33 PM PST 24
Peak memory 200292 kb
Host smart-82c48da3-1659-4894-8372-1c6d694bc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289395545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1289395545
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1144936769
Short name T189
Test name
Test status
Simulation time 41860475319 ps
CPU time 34.65 seconds
Started Mar 05 01:43:08 PM PST 24
Finished Mar 05 01:43:43 PM PST 24
Peak memory 200360 kb
Host smart-339cbe8d-30e0-4383-b7ea-40f293a904e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144936769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1144936769
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1958784145
Short name T1027
Test name
Test status
Simulation time 13945273635 ps
CPU time 14.13 seconds
Started Mar 05 01:43:13 PM PST 24
Finished Mar 05 01:43:28 PM PST 24
Peak memory 200336 kb
Host smart-fad33f56-ca7f-4119-a8e1-5160d2f29442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958784145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1958784145
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.683094903
Short name T726
Test name
Test status
Simulation time 45188347415 ps
CPU time 19.27 seconds
Started Mar 05 01:43:23 PM PST 24
Finished Mar 05 01:43:42 PM PST 24
Peak memory 200192 kb
Host smart-6a18aa8e-ab33-4c68-915f-71f76f020f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683094903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.683094903
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1371810501
Short name T32
Test name
Test status
Simulation time 110933064 ps
CPU time 0.58 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:34:46 PM PST 24
Peak memory 195932 kb
Host smart-8c722bea-7140-4a69-af86-9f96441fb046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371810501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1371810501
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1824709093
Short name T351
Test name
Test status
Simulation time 221451725806 ps
CPU time 28.57 seconds
Started Mar 05 01:34:35 PM PST 24
Finished Mar 05 01:35:04 PM PST 24
Peak memory 200424 kb
Host smart-d0e4de3c-ab76-4141-986c-7d34eaf15bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824709093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1824709093
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2212815439
Short name T236
Test name
Test status
Simulation time 212986551879 ps
CPU time 181.02 seconds
Started Mar 05 01:34:39 PM PST 24
Finished Mar 05 01:37:41 PM PST 24
Peak memory 199440 kb
Host smart-6210ca65-1980-4616-85a3-583810820c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212815439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2212815439
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1811907982
Short name T318
Test name
Test status
Simulation time 253831266826 ps
CPU time 69.8 seconds
Started Mar 05 01:34:35 PM PST 24
Finished Mar 05 01:35:45 PM PST 24
Peak memory 200272 kb
Host smart-25356192-73bc-4dc9-857c-95b6b6627090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811907982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1811907982
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_loopback.387754102
Short name T669
Test name
Test status
Simulation time 1261585662 ps
CPU time 2.66 seconds
Started Mar 05 01:34:48 PM PST 24
Finished Mar 05 01:34:52 PM PST 24
Peak memory 195840 kb
Host smart-548dbd9c-e220-47e1-9941-565324fa531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387754102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.387754102
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4065912454
Short name T401
Test name
Test status
Simulation time 146854475575 ps
CPU time 369.81 seconds
Started Mar 05 01:34:35 PM PST 24
Finished Mar 05 01:40:45 PM PST 24
Peak memory 208732 kb
Host smart-b1387c1f-7ff5-4d50-9f1f-cbd1d02349a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065912454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4065912454
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1178507453
Short name T764
Test name
Test status
Simulation time 4836568272 ps
CPU time 21.05 seconds
Started Mar 05 01:34:42 PM PST 24
Finished Mar 05 01:35:03 PM PST 24
Peak memory 199164 kb
Host smart-d32fd6ea-b60a-4900-a532-d22dc3af93fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178507453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1178507453
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1653062399
Short name T575
Test name
Test status
Simulation time 18106664727 ps
CPU time 9.09 seconds
Started Mar 05 01:34:37 PM PST 24
Finished Mar 05 01:34:47 PM PST 24
Peak memory 199560 kb
Host smart-923f82c5-02c5-4609-8ee0-aa9ef5962a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653062399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1653062399
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2460535547
Short name T469
Test name
Test status
Simulation time 46151534439 ps
CPU time 20.06 seconds
Started Mar 05 01:34:37 PM PST 24
Finished Mar 05 01:34:57 PM PST 24
Peak memory 195896 kb
Host smart-0bec0ab7-22dc-4a7f-aee1-647308e537cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460535547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2460535547
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2897200231
Short name T417
Test name
Test status
Simulation time 481793487 ps
CPU time 4.37 seconds
Started Mar 05 01:34:39 PM PST 24
Finished Mar 05 01:34:44 PM PST 24
Peak memory 198736 kb
Host smart-31d943ba-c997-4c38-a029-3f7f91bf0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897200231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2897200231
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3334094880
Short name T558
Test name
Test status
Simulation time 1143915468 ps
CPU time 3.16 seconds
Started Mar 05 01:34:40 PM PST 24
Finished Mar 05 01:34:45 PM PST 24
Peak memory 198652 kb
Host smart-e58ec475-e741-4114-8ebf-d83b7295b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334094880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3334094880
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3255680255
Short name T851
Test name
Test status
Simulation time 155740743999 ps
CPU time 100.4 seconds
Started Mar 05 01:34:39 PM PST 24
Finished Mar 05 01:36:20 PM PST 24
Peak memory 200300 kb
Host smart-b5d5e601-8431-4de9-b77d-dfc5ad045874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255680255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3255680255
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2036164971
Short name T1030
Test name
Test status
Simulation time 94892669236 ps
CPU time 46.44 seconds
Started Mar 05 01:43:16 PM PST 24
Finished Mar 05 01:44:03 PM PST 24
Peak memory 200356 kb
Host smart-ffce2b95-c077-40cd-96cf-c693a3581f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036164971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2036164971
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3183001410
Short name T715
Test name
Test status
Simulation time 27711489890 ps
CPU time 13.11 seconds
Started Mar 05 01:43:18 PM PST 24
Finished Mar 05 01:43:32 PM PST 24
Peak memory 200296 kb
Host smart-863ff784-4671-4d0a-9ef2-963fb7911b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183001410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3183001410
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1310609469
Short name T518
Test name
Test status
Simulation time 7011247785 ps
CPU time 6.01 seconds
Started Mar 05 01:43:15 PM PST 24
Finished Mar 05 01:43:21 PM PST 24
Peak memory 197980 kb
Host smart-8df0ccff-a966-4a2f-b49d-6d39eefe6c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310609469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1310609469
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1409809251
Short name T1034
Test name
Test status
Simulation time 93860859491 ps
CPU time 137.75 seconds
Started Mar 05 01:43:17 PM PST 24
Finished Mar 05 01:45:35 PM PST 24
Peak memory 200348 kb
Host smart-3a2da397-ea20-443b-90ae-2e6bc12bf8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409809251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1409809251
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.319536663
Short name T244
Test name
Test status
Simulation time 30523965081 ps
CPU time 45.13 seconds
Started Mar 05 01:43:16 PM PST 24
Finished Mar 05 01:44:01 PM PST 24
Peak memory 200408 kb
Host smart-3222c16f-aa28-42e7-8f3d-edb38d7e5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319536663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.319536663
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2319370964
Short name T627
Test name
Test status
Simulation time 203786846581 ps
CPU time 28.75 seconds
Started Mar 05 01:43:16 PM PST 24
Finished Mar 05 01:43:45 PM PST 24
Peak memory 200372 kb
Host smart-bc142152-be77-43f4-8638-70dd5185df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319370964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2319370964
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2753373639
Short name T216
Test name
Test status
Simulation time 12421669554 ps
CPU time 23.42 seconds
Started Mar 05 01:43:23 PM PST 24
Finished Mar 05 01:43:47 PM PST 24
Peak memory 200164 kb
Host smart-6169251a-d97a-4600-a8bd-f5704d40fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753373639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2753373639
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3247979702
Short name T245
Test name
Test status
Simulation time 245578258049 ps
CPU time 60.23 seconds
Started Mar 05 01:43:25 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 199688 kb
Host smart-460d6cf5-24af-42e1-a708-70642542809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247979702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3247979702
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.940891396
Short name T206
Test name
Test status
Simulation time 16933641303 ps
CPU time 31.88 seconds
Started Mar 05 01:43:23 PM PST 24
Finished Mar 05 01:43:56 PM PST 24
Peak memory 200284 kb
Host smart-35e172bf-40a9-4d60-adfe-821db5a94f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940891396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.940891396
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2777237683
Short name T924
Test name
Test status
Simulation time 229249113003 ps
CPU time 118.21 seconds
Started Mar 05 01:43:24 PM PST 24
Finished Mar 05 01:45:23 PM PST 24
Peak memory 200420 kb
Host smart-9861c6b9-bb48-4869-8268-7c729618c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777237683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2777237683
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.463211825
Short name T744
Test name
Test status
Simulation time 27554757 ps
CPU time 0.54 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:34:45 PM PST 24
Peak memory 194856 kb
Host smart-b6b439e6-221c-4414-a7b3-b5d5b0d7df45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463211825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.463211825
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3354045295
Short name T414
Test name
Test status
Simulation time 230889099027 ps
CPU time 40.37 seconds
Started Mar 05 01:34:42 PM PST 24
Finished Mar 05 01:35:23 PM PST 24
Peak memory 199920 kb
Host smart-551bb161-da63-4374-8bdd-5f297fd74975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354045295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3354045295
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3635312351
Short name T603
Test name
Test status
Simulation time 82233989599 ps
CPU time 33.79 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:35:27 PM PST 24
Peak memory 200304 kb
Host smart-9fa9ecf9-ded6-474c-bd37-f2adb7bac7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635312351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3635312351
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1009482717
Short name T1017
Test name
Test status
Simulation time 27776351343 ps
CPU time 13.72 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:34:59 PM PST 24
Peak memory 200372 kb
Host smart-83fa2e34-cb89-420c-b9af-88c0530f4cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009482717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1009482717
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2540797155
Short name T803
Test name
Test status
Simulation time 152749724256 ps
CPU time 335.77 seconds
Started Mar 05 01:34:47 PM PST 24
Finished Mar 05 01:40:23 PM PST 24
Peak memory 200424 kb
Host smart-3558e73e-fc63-4575-a111-fdf918eec2c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540797155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2540797155
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3104558065
Short name T605
Test name
Test status
Simulation time 78875897725 ps
CPU time 84.84 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:36:10 PM PST 24
Peak memory 200384 kb
Host smart-fd64de43-df2d-4307-86bb-b945960f5a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104558065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3104558065
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2710617221
Short name T546
Test name
Test status
Simulation time 127740714 ps
CPU time 0.7 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:34:46 PM PST 24
Peak memory 197032 kb
Host smart-81f21953-bc48-40e0-95bd-3e98b11da317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710617221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2710617221
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1464159153
Short name T979
Test name
Test status
Simulation time 37282676166 ps
CPU time 64.6 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:35:56 PM PST 24
Peak memory 198440 kb
Host smart-ad4abeed-519a-4a4c-96b9-fa3d818374d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464159153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1464159153
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1040226271
Short name T599
Test name
Test status
Simulation time 32704206793 ps
CPU time 440.03 seconds
Started Mar 05 01:34:46 PM PST 24
Finished Mar 05 01:42:06 PM PST 24
Peak memory 200372 kb
Host smart-e4f9393b-d216-48b4-99ea-70bbbd809998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040226271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1040226271
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2174961292
Short name T13
Test name
Test status
Simulation time 4865115280 ps
CPU time 10.57 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:34:56 PM PST 24
Peak memory 198688 kb
Host smart-8ddfdcb5-eabb-4649-9a61-5b889112b0f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174961292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2174961292
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3949262173
Short name T257
Test name
Test status
Simulation time 83555668048 ps
CPU time 140.69 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:37:06 PM PST 24
Peak memory 199936 kb
Host smart-43809ea8-404a-4333-847b-7d716636601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949262173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3949262173
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2616770346
Short name T553
Test name
Test status
Simulation time 40190255951 ps
CPU time 15.7 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 195860 kb
Host smart-93bdeb4d-1aa3-47c5-b924-02065289b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616770346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2616770346
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1882028913
Short name T609
Test name
Test status
Simulation time 523630263 ps
CPU time 1.2 seconds
Started Mar 05 01:34:47 PM PST 24
Finished Mar 05 01:34:49 PM PST 24
Peak memory 198252 kb
Host smart-8bbd5acc-b2c6-4c67-b962-0f412fde1d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882028913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1882028913
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.187849287
Short name T220
Test name
Test status
Simulation time 195532718872 ps
CPU time 356.26 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:40:49 PM PST 24
Peak memory 200316 kb
Host smart-4d2bc93b-834f-4e63-befd-08fdb32e48b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187849287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.187849287
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3424488789
Short name T761
Test name
Test status
Simulation time 840868949 ps
CPU time 3.32 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:34:49 PM PST 24
Peak memory 198908 kb
Host smart-2482d96d-e2bb-4dc6-b7da-9563453e5abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424488789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3424488789
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1411328884
Short name T526
Test name
Test status
Simulation time 10740290890 ps
CPU time 18 seconds
Started Mar 05 01:34:47 PM PST 24
Finished Mar 05 01:35:05 PM PST 24
Peak memory 199956 kb
Host smart-dc91121f-d63c-4d28-940f-a301b187cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411328884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1411328884
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3332482151
Short name T354
Test name
Test status
Simulation time 24760401213 ps
CPU time 44.21 seconds
Started Mar 05 01:43:25 PM PST 24
Finished Mar 05 01:44:09 PM PST 24
Peak memory 200312 kb
Host smart-6c2dca81-2264-4d13-b078-949b084704a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332482151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3332482151
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.488902715
Short name T264
Test name
Test status
Simulation time 42208562862 ps
CPU time 71.43 seconds
Started Mar 05 01:43:25 PM PST 24
Finished Mar 05 01:44:37 PM PST 24
Peak memory 200348 kb
Host smart-9cec8c7b-c70e-49cb-9280-ebe071d65f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488902715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.488902715
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.401598157
Short name T54
Test name
Test status
Simulation time 119153542119 ps
CPU time 44.47 seconds
Started Mar 05 01:43:22 PM PST 24
Finished Mar 05 01:44:07 PM PST 24
Peak memory 199976 kb
Host smart-53a70b4c-dae0-44a0-a2ae-4b8b9003f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401598157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.401598157
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.983649443
Short name T617
Test name
Test status
Simulation time 69567983905 ps
CPU time 137.01 seconds
Started Mar 05 01:43:25 PM PST 24
Finished Mar 05 01:45:43 PM PST 24
Peak memory 200300 kb
Host smart-18193a15-b8f0-4fa0-b855-29e691c4e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983649443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.983649443
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2216824958
Short name T695
Test name
Test status
Simulation time 325163446104 ps
CPU time 175.3 seconds
Started Mar 05 01:43:26 PM PST 24
Finished Mar 05 01:46:22 PM PST 24
Peak memory 200412 kb
Host smart-24b5b34b-2531-4ee1-98af-b72731340498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216824958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2216824958
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3476656126
Short name T204
Test name
Test status
Simulation time 150430522469 ps
CPU time 232.32 seconds
Started Mar 05 01:43:30 PM PST 24
Finished Mar 05 01:47:22 PM PST 24
Peak memory 200248 kb
Host smart-47d797c8-c098-4965-9339-351ab2715cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476656126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3476656126
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.161928243
Short name T754
Test name
Test status
Simulation time 86050913022 ps
CPU time 144.42 seconds
Started Mar 05 01:43:35 PM PST 24
Finished Mar 05 01:46:00 PM PST 24
Peak memory 200344 kb
Host smart-503c91de-19a5-475e-8937-59535841f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161928243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.161928243
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3547467057
Short name T781
Test name
Test status
Simulation time 66271562070 ps
CPU time 118.27 seconds
Started Mar 05 01:43:33 PM PST 24
Finished Mar 05 01:45:31 PM PST 24
Peak memory 200344 kb
Host smart-01e7c945-206f-4fd4-bdad-4665e7ed89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547467057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3547467057
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1193176547
Short name T99
Test name
Test status
Simulation time 24603653740 ps
CPU time 8.03 seconds
Started Mar 05 01:43:34 PM PST 24
Finished Mar 05 01:43:42 PM PST 24
Peak memory 200312 kb
Host smart-1aa7af9f-7dc3-481c-a31b-da3f9a5f69ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193176547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1193176547
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.229019998
Short name T295
Test name
Test status
Simulation time 101233501202 ps
CPU time 157.52 seconds
Started Mar 05 01:43:31 PM PST 24
Finished Mar 05 01:46:09 PM PST 24
Peak memory 200312 kb
Host smart-7006392a-4e7f-4d83-b0e6-fe14b54e4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229019998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.229019998
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3145920391
Short name T704
Test name
Test status
Simulation time 13024659 ps
CPU time 0.6 seconds
Started Mar 05 01:34:51 PM PST 24
Finished Mar 05 01:34:52 PM PST 24
Peak memory 194920 kb
Host smart-c589759e-9a04-4d06-88fb-a277760d3f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145920391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3145920391
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3330712397
Short name T973
Test name
Test status
Simulation time 60233232500 ps
CPU time 22.96 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:35:08 PM PST 24
Peak memory 200280 kb
Host smart-a0766f3e-6d5c-4182-a4c0-46307bd241df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330712397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3330712397
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2337496207
Short name T1029
Test name
Test status
Simulation time 48312487512 ps
CPU time 23.44 seconds
Started Mar 05 01:34:45 PM PST 24
Finished Mar 05 01:35:09 PM PST 24
Peak memory 199820 kb
Host smart-d44a4c48-7d9d-470b-a29b-19e61a0e0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337496207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2337496207
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.556307902
Short name T214
Test name
Test status
Simulation time 123530378224 ps
CPU time 37.88 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:35:22 PM PST 24
Peak memory 200132 kb
Host smart-5e9cb313-ebc3-427d-85ad-b39552526834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556307902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.556307902
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4151568382
Short name T23
Test name
Test status
Simulation time 324288582367 ps
CPU time 450.05 seconds
Started Mar 05 01:34:46 PM PST 24
Finished Mar 05 01:42:16 PM PST 24
Peak memory 199032 kb
Host smart-7931a645-b3b6-4605-9d74-c71c85f57409
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151568382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4151568382
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.797805334
Short name T999
Test name
Test status
Simulation time 129207576022 ps
CPU time 1380.15 seconds
Started Mar 05 01:34:56 PM PST 24
Finished Mar 05 01:57:58 PM PST 24
Peak memory 200268 kb
Host smart-5d4b4925-0327-4352-9d7f-04b33b447463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797805334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.797805334
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.4032513343
Short name T26
Test name
Test status
Simulation time 9058567391 ps
CPU time 4.96 seconds
Started Mar 05 01:34:49 PM PST 24
Finished Mar 05 01:34:55 PM PST 24
Peak memory 199504 kb
Host smart-5bf34f61-b68f-4a57-b9ac-ab4aa44e470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032513343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4032513343
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2390045575
Short name T922
Test name
Test status
Simulation time 79764982614 ps
CPU time 66.75 seconds
Started Mar 05 01:34:47 PM PST 24
Finished Mar 05 01:35:54 PM PST 24
Peak memory 200252 kb
Host smart-d97523e1-874e-4ea7-87cb-3429a23e9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390045575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2390045575
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.616229659
Short name T986
Test name
Test status
Simulation time 12647330270 ps
CPU time 679.14 seconds
Started Mar 05 01:34:53 PM PST 24
Finished Mar 05 01:46:14 PM PST 24
Peak memory 200448 kb
Host smart-b5c83134-2647-460f-9cba-f03a3ee09d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616229659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.616229659
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.428488206
Short name T467
Test name
Test status
Simulation time 4594612694 ps
CPU time 17.74 seconds
Started Mar 05 01:34:44 PM PST 24
Finished Mar 05 01:35:02 PM PST 24
Peak memory 199204 kb
Host smart-8de2b6e0-2cc5-4ec5-99b7-83c68bd69d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428488206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.428488206
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3535189011
Short name T1085
Test name
Test status
Simulation time 91138040650 ps
CPU time 27.39 seconds
Started Mar 05 01:34:49 PM PST 24
Finished Mar 05 01:35:17 PM PST 24
Peak memory 199128 kb
Host smart-7527db7d-433d-40d6-a034-09afef572653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535189011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3535189011
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1181986370
Short name T423
Test name
Test status
Simulation time 4200051754 ps
CPU time 2.1 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:34:53 PM PST 24
Peak memory 196196 kb
Host smart-0de7b57c-d5b7-472b-aa88-4d8daedbe285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181986370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1181986370
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.598696525
Short name T806
Test name
Test status
Simulation time 533446655 ps
CPU time 1.11 seconds
Started Mar 05 01:34:43 PM PST 24
Finished Mar 05 01:34:45 PM PST 24
Peak memory 198168 kb
Host smart-ba3f844c-45cb-44c4-a8ff-986a318c2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598696525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.598696525
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.855548951
Short name T153
Test name
Test status
Simulation time 240770370971 ps
CPU time 203.07 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:38:16 PM PST 24
Peak memory 200392 kb
Host smart-5f42cf9e-a633-4504-8be4-3dc4032a6aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855548951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.855548951
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3743429648
Short name T1077
Test name
Test status
Simulation time 883188843 ps
CPU time 1.47 seconds
Started Mar 05 01:34:49 PM PST 24
Finished Mar 05 01:34:51 PM PST 24
Peak memory 198556 kb
Host smart-4d368ebb-b3a8-4f09-b05a-8c7f4be020d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743429648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3743429648
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4142171991
Short name T912
Test name
Test status
Simulation time 103294728449 ps
CPU time 90.27 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:36:23 PM PST 24
Peak memory 200304 kb
Host smart-7e8295f5-8752-40e0-855b-fbd5c6f6500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142171991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4142171991
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3263751453
Short name T135
Test name
Test status
Simulation time 5229419747 ps
CPU time 10.07 seconds
Started Mar 05 01:43:30 PM PST 24
Finished Mar 05 01:43:41 PM PST 24
Peak memory 200344 kb
Host smart-ae87fba7-4005-4106-9241-f1bb29032ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263751453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3263751453
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1139462356
Short name T776
Test name
Test status
Simulation time 26352045085 ps
CPU time 42.54 seconds
Started Mar 05 01:43:35 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 200292 kb
Host smart-a5fbbcec-5b3b-45a3-ade0-78e03890d4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139462356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1139462356
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3888288293
Short name T336
Test name
Test status
Simulation time 13580422088 ps
CPU time 11.19 seconds
Started Mar 05 01:43:33 PM PST 24
Finished Mar 05 01:43:44 PM PST 24
Peak memory 200392 kb
Host smart-f82c70f9-1393-4646-b618-5286d0ba400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888288293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3888288293
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3147944162
Short name T1091
Test name
Test status
Simulation time 93659017765 ps
CPU time 31.96 seconds
Started Mar 05 01:43:38 PM PST 24
Finished Mar 05 01:44:10 PM PST 24
Peak memory 200404 kb
Host smart-3fc347e3-da9e-4db5-8493-942f215ee83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147944162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3147944162
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3177435153
Short name T759
Test name
Test status
Simulation time 174066504544 ps
CPU time 74.78 seconds
Started Mar 05 01:43:39 PM PST 24
Finished Mar 05 01:44:54 PM PST 24
Peak memory 200332 kb
Host smart-2d7dde44-08c5-4ee1-8e5d-6c56399dd031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177435153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3177435153
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1750798446
Short name T1044
Test name
Test status
Simulation time 51647497000 ps
CPU time 84.8 seconds
Started Mar 05 01:43:41 PM PST 24
Finished Mar 05 01:45:06 PM PST 24
Peak memory 199672 kb
Host smart-4270895d-2b79-4915-aec7-2124e9718330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750798446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1750798446
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1812906445
Short name T322
Test name
Test status
Simulation time 79717322250 ps
CPU time 88.13 seconds
Started Mar 05 01:43:42 PM PST 24
Finished Mar 05 01:45:10 PM PST 24
Peak memory 200336 kb
Host smart-716316da-3cc5-45aa-aa4f-54520fe716b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812906445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1812906445
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1764363498
Short name T652
Test name
Test status
Simulation time 9038255840 ps
CPU time 18.09 seconds
Started Mar 05 01:43:40 PM PST 24
Finished Mar 05 01:43:58 PM PST 24
Peak memory 200380 kb
Host smart-40c2da47-3f5f-4507-bd58-e20b057830f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764363498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1764363498
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1150281537
Short name T844
Test name
Test status
Simulation time 34176450 ps
CPU time 0.57 seconds
Started Mar 05 01:34:49 PM PST 24
Finished Mar 05 01:34:50 PM PST 24
Peak memory 195020 kb
Host smart-9b8c07d9-a20c-4147-9b08-77a276a17a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150281537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1150281537
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1234828545
Short name T1059
Test name
Test status
Simulation time 58819757221 ps
CPU time 19.32 seconds
Started Mar 05 01:34:51 PM PST 24
Finished Mar 05 01:35:11 PM PST 24
Peak memory 200360 kb
Host smart-1c58bc0c-b664-44c2-9c3c-8608f6e0ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234828545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1234828545
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2264380131
Short name T1039
Test name
Test status
Simulation time 132994809123 ps
CPU time 191.48 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:38:05 PM PST 24
Peak memory 200252 kb
Host smart-8bab95a3-f627-44ee-ba60-4654253072fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264380131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2264380131
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3244831570
Short name T147
Test name
Test status
Simulation time 59267910983 ps
CPU time 22.78 seconds
Started Mar 05 01:34:52 PM PST 24
Finished Mar 05 01:35:15 PM PST 24
Peak memory 200296 kb
Host smart-7e74b61a-0f43-4513-a819-dfbe4cef68e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244831570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3244831570
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4173430608
Short name T18
Test name
Test status
Simulation time 239013214313 ps
CPU time 117.41 seconds
Started Mar 05 01:34:53 PM PST 24
Finished Mar 05 01:36:52 PM PST 24
Peak memory 200380 kb
Host smart-a58f821f-e3e3-4645-a725-a63d1f285337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173430608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4173430608
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.646614888
Short name T458
Test name
Test status
Simulation time 500088860 ps
CPU time 1.45 seconds
Started Mar 05 01:34:48 PM PST 24
Finished Mar 05 01:34:51 PM PST 24
Peak memory 195848 kb
Host smart-f0115530-52f6-4d27-8260-ca33777cb9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646614888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.646614888
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2948583908
Short name T566
Test name
Test status
Simulation time 107303052173 ps
CPU time 90.45 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:36:21 PM PST 24
Peak memory 200540 kb
Host smart-2cf95d45-a899-4567-b3f1-7261b35e3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948583908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2948583908
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2841028255
Short name T478
Test name
Test status
Simulation time 8891362731 ps
CPU time 250.14 seconds
Started Mar 05 01:34:51 PM PST 24
Finished Mar 05 01:39:02 PM PST 24
Peak memory 200396 kb
Host smart-ab6d56d1-0808-4135-9b7d-68a0f5b1885c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841028255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2841028255
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2092711595
Short name T793
Test name
Test status
Simulation time 2587979535 ps
CPU time 4.82 seconds
Started Mar 05 01:34:53 PM PST 24
Finished Mar 05 01:34:58 PM PST 24
Peak memory 198696 kb
Host smart-6cf35fa1-d1d9-4511-a92e-c70f5577cc16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092711595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2092711595
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1819785592
Short name T880
Test name
Test status
Simulation time 112139490037 ps
CPU time 158.22 seconds
Started Mar 05 01:34:51 PM PST 24
Finished Mar 05 01:37:29 PM PST 24
Peak memory 200356 kb
Host smart-82fb71a3-eb5d-440d-9366-9f49e521f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819785592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1819785592
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.623499062
Short name T960
Test name
Test status
Simulation time 2754860041 ps
CPU time 1.44 seconds
Started Mar 05 01:34:49 PM PST 24
Finished Mar 05 01:34:51 PM PST 24
Peak memory 195936 kb
Host smart-f4099557-65bf-49b5-9cf0-bf1e71ac860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623499062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.623499062
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1504837383
Short name T856
Test name
Test status
Simulation time 624910538 ps
CPU time 3.05 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:34:54 PM PST 24
Peak memory 199636 kb
Host smart-6689b6e0-ec6e-4755-8cac-adeda2145b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504837383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1504837383
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1471209953
Short name T890
Test name
Test status
Simulation time 7260691850 ps
CPU time 8.85 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:34:59 PM PST 24
Peak memory 199788 kb
Host smart-9364e92e-d5b4-467d-955c-4aca09e90885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471209953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1471209953
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2400000030
Short name T848
Test name
Test status
Simulation time 9777790599 ps
CPU time 5.06 seconds
Started Mar 05 01:34:50 PM PST 24
Finished Mar 05 01:34:56 PM PST 24
Peak memory 197192 kb
Host smart-53b8d756-2ff0-4262-8f41-faf7676f103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400000030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2400000030
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.4235884633
Short name T95
Test name
Test status
Simulation time 49377410338 ps
CPU time 66.84 seconds
Started Mar 05 01:43:38 PM PST 24
Finished Mar 05 01:44:44 PM PST 24
Peak memory 200384 kb
Host smart-994b4d42-8b1d-454a-b112-53c24f061ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235884633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4235884633
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1701643122
Short name T326
Test name
Test status
Simulation time 21440473049 ps
CPU time 20.06 seconds
Started Mar 05 01:43:44 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 200336 kb
Host smart-83e977b5-0baf-4d07-b161-1f204914cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701643122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1701643122
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1318230349
Short name T195
Test name
Test status
Simulation time 41634167614 ps
CPU time 36.51 seconds
Started Mar 05 01:43:44 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 200372 kb
Host smart-e255bc6b-a4b6-4424-a6d6-74c35ec012c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318230349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1318230349
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1362292259
Short name T230
Test name
Test status
Simulation time 26517693572 ps
CPU time 42.97 seconds
Started Mar 05 01:43:45 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 199744 kb
Host smart-80f79a3d-09ce-4d48-ba3a-540d9a5cd934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362292259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1362292259
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.656445381
Short name T510
Test name
Test status
Simulation time 64658421987 ps
CPU time 24.61 seconds
Started Mar 05 01:43:45 PM PST 24
Finished Mar 05 01:44:10 PM PST 24
Peak memory 199316 kb
Host smart-268638d1-52b1-403c-9c69-68d485217613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656445381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.656445381
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1660833836
Short name T498
Test name
Test status
Simulation time 27323876272 ps
CPU time 20.86 seconds
Started Mar 05 01:43:47 PM PST 24
Finished Mar 05 01:44:08 PM PST 24
Peak memory 200020 kb
Host smart-6cc2376f-ddec-46a0-942d-9b39f6045ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660833836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1660833836
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.500319074
Short name T373
Test name
Test status
Simulation time 115002374896 ps
CPU time 215.23 seconds
Started Mar 05 01:43:48 PM PST 24
Finished Mar 05 01:47:23 PM PST 24
Peak memory 200256 kb
Host smart-ff6af870-db14-4001-97fc-a552fa51cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500319074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.500319074
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.126351135
Short name T42
Test name
Test status
Simulation time 21970430421 ps
CPU time 39.05 seconds
Started Mar 05 01:43:46 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 200352 kb
Host smart-89180f5d-754d-419b-bda2-60724fe0eda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126351135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.126351135
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.234661629
Short name T640
Test name
Test status
Simulation time 56722097 ps
CPU time 0.55 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 195928 kb
Host smart-9fd5f70e-5cf8-49ff-97a0-5804393b5665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234661629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.234661629
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2653732502
Short name T816
Test name
Test status
Simulation time 92054883473 ps
CPU time 141.28 seconds
Started Mar 05 01:35:01 PM PST 24
Finished Mar 05 01:37:23 PM PST 24
Peak memory 200396 kb
Host smart-7d272e1a-8e4c-456f-a76f-ee3d43939d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653732502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2653732502
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1401433319
Short name T365
Test name
Test status
Simulation time 217854507232 ps
CPU time 184.23 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:38:03 PM PST 24
Peak memory 200296 kb
Host smart-31c3eee0-a145-40af-8b68-d31a62d2b419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401433319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1401433319
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3503876679
Short name T286
Test name
Test status
Simulation time 57400219358 ps
CPU time 45.2 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:35:44 PM PST 24
Peak memory 200340 kb
Host smart-5e16f674-8980-4c86-a6c7-89466af964a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503876679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3503876679
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.661242111
Short name T975
Test name
Test status
Simulation time 421860061709 ps
CPU time 931.76 seconds
Started Mar 05 01:34:57 PM PST 24
Finished Mar 05 01:50:30 PM PST 24
Peak memory 200360 kb
Host smart-657c604c-3747-49a2-ab12-5bb12c65723d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661242111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.661242111
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1240605228
Short name T1006
Test name
Test status
Simulation time 135510363664 ps
CPU time 227.73 seconds
Started Mar 05 01:34:57 PM PST 24
Finished Mar 05 01:38:46 PM PST 24
Peak memory 200392 kb
Host smart-fc56b44c-a253-41e6-9486-bed75158447c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240605228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1240605228
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1505748102
Short name T807
Test name
Test status
Simulation time 6096750306 ps
CPU time 11.56 seconds
Started Mar 05 01:34:58 PM PST 24
Finished Mar 05 01:35:10 PM PST 24
Peak memory 199400 kb
Host smart-d17493f6-651d-406c-a0d0-8bcb0d8c63ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505748102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1505748102
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3896692916
Short name T993
Test name
Test status
Simulation time 209318071454 ps
CPU time 38.2 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:35:37 PM PST 24
Peak memory 200576 kb
Host smart-e01d5f09-99de-479a-8367-d9e14c737e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896692916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3896692916
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3828168592
Short name T1087
Test name
Test status
Simulation time 6532151763 ps
CPU time 356.22 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:40:55 PM PST 24
Peak memory 200440 kb
Host smart-dad9c998-08fb-4045-bd82-09384e7e4eda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828168592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3828168592
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2614214735
Short name T948
Test name
Test status
Simulation time 174972383 ps
CPU time 1.06 seconds
Started Mar 05 01:34:57 PM PST 24
Finished Mar 05 01:34:59 PM PST 24
Peak memory 198416 kb
Host smart-f6ce2728-2cc0-417f-9cc8-8495a91c9c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614214735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2614214735
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3267062437
Short name T725
Test name
Test status
Simulation time 150684197252 ps
CPU time 183.01 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:38:02 PM PST 24
Peak memory 200400 kb
Host smart-63133a39-40c8-4c86-9ee9-08627ee8bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267062437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3267062437
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4102513604
Short name T436
Test name
Test status
Simulation time 1474217306 ps
CPU time 1.77 seconds
Started Mar 05 01:35:00 PM PST 24
Finished Mar 05 01:35:02 PM PST 24
Peak memory 195748 kb
Host smart-0bb05d44-a493-4752-9813-9da8898ca097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102513604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4102513604
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3338504124
Short name T705
Test name
Test status
Simulation time 5424729867 ps
CPU time 13.1 seconds
Started Mar 05 01:34:53 PM PST 24
Finished Mar 05 01:35:08 PM PST 24
Peak memory 199704 kb
Host smart-1b43bd1d-62e4-46ef-a4cd-1225baf1f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338504124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3338504124
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.848031180
Short name T947
Test name
Test status
Simulation time 504433681 ps
CPU time 1.36 seconds
Started Mar 05 01:34:58 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 198136 kb
Host smart-e1311121-bca9-4784-993c-12b6019e7a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848031180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.848031180
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.392730948
Short name T671
Test name
Test status
Simulation time 28054663949 ps
CPU time 9.56 seconds
Started Mar 05 01:34:51 PM PST 24
Finished Mar 05 01:35:01 PM PST 24
Peak memory 198664 kb
Host smart-c4ae676d-fe22-4e24-b8c6-3c91d6bba38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392730948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.392730948
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.4039733934
Short name T616
Test name
Test status
Simulation time 123518098792 ps
CPU time 47.34 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:43 PM PST 24
Peak memory 200344 kb
Host smart-7c54d924-d924-4ad7-886e-d835802c20c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039733934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4039733934
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4132562293
Short name T638
Test name
Test status
Simulation time 9047810720 ps
CPU time 4.34 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:01 PM PST 24
Peak memory 200268 kb
Host smart-05694d70-b91a-4eed-b5aa-84c22748359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132562293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4132562293
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2272929252
Short name T968
Test name
Test status
Simulation time 133878437249 ps
CPU time 181.08 seconds
Started Mar 05 01:43:55 PM PST 24
Finished Mar 05 01:46:57 PM PST 24
Peak memory 200372 kb
Host smart-a01765e7-2697-40ec-8794-14764704ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272929252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2272929252
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2877518390
Short name T499
Test name
Test status
Simulation time 23382032224 ps
CPU time 36.27 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 200168 kb
Host smart-bf0c6184-cca3-4eeb-9b2c-6770e287858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877518390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2877518390
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3945701015
Short name T241
Test name
Test status
Simulation time 57225738837 ps
CPU time 161.53 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:46:38 PM PST 24
Peak memory 200080 kb
Host smart-5fc36d3c-fd5b-4d93-b7fa-b1ee7517451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945701015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3945701015
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.132256897
Short name T304
Test name
Test status
Simulation time 81979145540 ps
CPU time 34.58 seconds
Started Mar 05 01:43:54 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 200284 kb
Host smart-f433bd11-4053-4f8e-955b-52a14c6842b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132256897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.132256897
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3038973705
Short name T502
Test name
Test status
Simulation time 38218023 ps
CPU time 0.58 seconds
Started Mar 05 01:35:04 PM PST 24
Finished Mar 05 01:35:05 PM PST 24
Peak memory 194940 kb
Host smart-9734c22b-a0d4-4403-a6fd-1c52357d5ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038973705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3038973705
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3449889182
Short name T991
Test name
Test status
Simulation time 274014305957 ps
CPU time 119.69 seconds
Started Mar 05 01:35:00 PM PST 24
Finished Mar 05 01:37:00 PM PST 24
Peak memory 200432 kb
Host smart-c5368185-6ccf-4d47-80f8-0c6d0c82a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449889182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3449889182
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2095375895
Short name T266
Test name
Test status
Simulation time 74630727122 ps
CPU time 32.86 seconds
Started Mar 05 01:34:59 PM PST 24
Finished Mar 05 01:35:31 PM PST 24
Peak memory 200288 kb
Host smart-f8cb1bd0-b30b-4026-86f9-608116c05daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095375895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2095375895
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.874053076
Short name T303
Test name
Test status
Simulation time 19817940156 ps
CPU time 30.54 seconds
Started Mar 05 01:35:00 PM PST 24
Finished Mar 05 01:35:31 PM PST 24
Peak memory 200184 kb
Host smart-95be593c-f9f4-47e3-99b2-d671ca10e0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874053076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.874053076
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3549475983
Short name T1088
Test name
Test status
Simulation time 2143633347996 ps
CPU time 3343.92 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 02:30:54 PM PST 24
Peak memory 199292 kb
Host smart-0951aab7-1f7c-4018-8cd4-e0759aa4a5d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549475983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3549475983
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2353305906
Short name T547
Test name
Test status
Simulation time 112645230101 ps
CPU time 331.57 seconds
Started Mar 05 01:35:18 PM PST 24
Finished Mar 05 01:40:50 PM PST 24
Peak memory 200292 kb
Host smart-14e372dd-0184-489a-b105-7bea2f99eec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353305906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2353305906
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3501747023
Short name T688
Test name
Test status
Simulation time 78889981140 ps
CPU time 32.13 seconds
Started Mar 05 01:35:07 PM PST 24
Finished Mar 05 01:35:42 PM PST 24
Peak memory 199244 kb
Host smart-3c4e38b4-e5e2-4032-8738-4d4a026d8f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501747023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3501747023
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3484165004
Short name T282
Test name
Test status
Simulation time 16984045523 ps
CPU time 233.11 seconds
Started Mar 05 01:35:05 PM PST 24
Finished Mar 05 01:39:03 PM PST 24
Peak memory 200332 kb
Host smart-e98a7671-c0fb-4c12-8c62-112f9fa46d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484165004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3484165004
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1308520695
Short name T278
Test name
Test status
Simulation time 56477132269 ps
CPU time 25.77 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:35:53 PM PST 24
Peak memory 200296 kb
Host smart-271c43d5-ed07-45e4-8aa0-0f4d10b0a21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308520695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1308520695
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3537429500
Short name T658
Test name
Test status
Simulation time 593092515 ps
CPU time 1.58 seconds
Started Mar 05 01:35:05 PM PST 24
Finished Mar 05 01:35:12 PM PST 24
Peak memory 195888 kb
Host smart-5ca7b0d1-7fab-4700-ae2e-45094c4f4b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537429500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3537429500
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2159994263
Short name T465
Test name
Test status
Simulation time 5886492333 ps
CPU time 17.28 seconds
Started Mar 05 01:35:00 PM PST 24
Finished Mar 05 01:35:18 PM PST 24
Peak memory 199820 kb
Host smart-2afc15c5-0d56-4fe5-9c10-ca2fd766e17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159994263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2159994263
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3920183103
Short name T38
Test name
Test status
Simulation time 68962662996 ps
CPU time 577.52 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:45:04 PM PST 24
Peak memory 216948 kb
Host smart-f92a8a3f-7496-4549-8ae3-a4eee1b83dea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920183103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3920183103
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1372644586
Short name T637
Test name
Test status
Simulation time 1162434088 ps
CPU time 3.73 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 01:35:14 PM PST 24
Peak memory 200308 kb
Host smart-683977e3-3fe3-4b7f-9a2c-84f34b81deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372644586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1372644586
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.612631309
Short name T951
Test name
Test status
Simulation time 148330674095 ps
CPU time 71.3 seconds
Started Mar 05 01:34:58 PM PST 24
Finished Mar 05 01:36:09 PM PST 24
Peak memory 200328 kb
Host smart-06f204a9-653d-445f-ba2e-061b8f333a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612631309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.612631309
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.852353274
Short name T209
Test name
Test status
Simulation time 12655446230 ps
CPU time 19.25 seconds
Started Mar 05 01:43:56 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 200376 kb
Host smart-bb494286-da02-41ca-8101-480fd0d8e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852353274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.852353274
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2571696557
Short name T234
Test name
Test status
Simulation time 98786714817 ps
CPU time 220.26 seconds
Started Mar 05 01:43:58 PM PST 24
Finished Mar 05 01:47:38 PM PST 24
Peak memory 200300 kb
Host smart-48043bca-d992-4ee9-a59d-1926a3b76ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571696557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2571696557
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2039821567
Short name T512
Test name
Test status
Simulation time 13573222764 ps
CPU time 23.06 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 197628 kb
Host smart-7197c4ad-1a20-46d1-b001-58d020a49159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039821567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2039821567
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.244560406
Short name T1065
Test name
Test status
Simulation time 12580194766 ps
CPU time 20.65 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 199832 kb
Host smart-15dc5c90-08c5-489a-b6e6-66d82d1309da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244560406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.244560406
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1742191648
Short name T548
Test name
Test status
Simulation time 104094976315 ps
CPU time 174.77 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:46:54 PM PST 24
Peak memory 200328 kb
Host smart-56f95a2f-e8b8-4825-903f-bc8396bd67de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742191648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1742191648
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.530829092
Short name T310
Test name
Test status
Simulation time 38761692708 ps
CPU time 80.01 seconds
Started Mar 05 01:43:58 PM PST 24
Finished Mar 05 01:45:18 PM PST 24
Peak memory 200340 kb
Host smart-f5962f1a-f33d-4d2c-8082-08f4f1621a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530829092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.530829092
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3439582170
Short name T811
Test name
Test status
Simulation time 157391086406 ps
CPU time 44.57 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:44:45 PM PST 24
Peak memory 200272 kb
Host smart-5816b7bb-9677-4621-809e-cace073c433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439582170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3439582170
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3913328390
Short name T368
Test name
Test status
Simulation time 51649896764 ps
CPU time 17.07 seconds
Started Mar 05 01:43:57 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 199628 kb
Host smart-86eff7e3-45d1-4774-8111-98875f4be6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913328390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3913328390
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1318687691
Short name T927
Test name
Test status
Simulation time 12453806 ps
CPU time 0.54 seconds
Started Mar 05 01:35:17 PM PST 24
Finished Mar 05 01:35:18 PM PST 24
Peak memory 195900 kb
Host smart-3d5ef46f-d5a1-42cc-a17a-110a3c97ee37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318687691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1318687691
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1772802104
Short name T333
Test name
Test status
Simulation time 70366881586 ps
CPU time 60.04 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 01:36:10 PM PST 24
Peak memory 200360 kb
Host smart-552dc086-e3ec-47a3-98cd-b3c95ec2fffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772802104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1772802104
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2625339808
Short name T433
Test name
Test status
Simulation time 187351984242 ps
CPU time 72.2 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 01:36:22 PM PST 24
Peak memory 200308 kb
Host smart-584d78b0-f649-48df-8320-ad6ce0e7d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625339808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2625339808
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2253431250
Short name T183
Test name
Test status
Simulation time 43626856994 ps
CPU time 34.37 seconds
Started Mar 05 01:35:04 PM PST 24
Finished Mar 05 01:35:40 PM PST 24
Peak memory 200000 kb
Host smart-5cea052b-351b-447a-9cbc-73b2332cb9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253431250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2253431250
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2160421983
Short name T619
Test name
Test status
Simulation time 168622151061 ps
CPU time 730.96 seconds
Started Mar 05 01:35:03 PM PST 24
Finished Mar 05 01:47:14 PM PST 24
Peak memory 200368 kb
Host smart-26ed8d28-6759-4e5d-8dd8-5ab81ab3e889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160421983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2160421983
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3639156193
Short name T459
Test name
Test status
Simulation time 8048627720 ps
CPU time 19.75 seconds
Started Mar 05 01:35:05 PM PST 24
Finished Mar 05 01:35:30 PM PST 24
Peak memory 198416 kb
Host smart-320d63c5-c144-4fe0-9c83-98a1b7d5ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639156193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3639156193
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.640584770
Short name T1051
Test name
Test status
Simulation time 81268528618 ps
CPU time 71.67 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:36:39 PM PST 24
Peak memory 208596 kb
Host smart-48bf2ec7-2627-4527-b856-a0df305d35c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640584770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.640584770
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3866382352
Short name T718
Test name
Test status
Simulation time 15934895167 ps
CPU time 883.39 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 200360 kb
Host smart-c82b3c07-ed5c-4b1a-a18d-b7aab4ebcf03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866382352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3866382352
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2105686052
Short name T494
Test name
Test status
Simulation time 1448751277 ps
CPU time 4.45 seconds
Started Mar 05 01:35:05 PM PST 24
Finished Mar 05 01:35:14 PM PST 24
Peak memory 198436 kb
Host smart-3b981313-6f2a-41cc-9ec5-45370b262a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105686052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2105686052
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.782120022
Short name T983
Test name
Test status
Simulation time 9771783510 ps
CPU time 17.07 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:35:44 PM PST 24
Peak memory 197996 kb
Host smart-fd043a6f-ffaa-455b-8803-af25f8f61879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782120022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.782120022
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3094319787
Short name T825
Test name
Test status
Simulation time 4712011611 ps
CPU time 3 seconds
Started Mar 05 01:35:04 PM PST 24
Finished Mar 05 01:35:07 PM PST 24
Peak memory 196104 kb
Host smart-e6d06e03-79ec-4bb4-b97f-42855245994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094319787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3094319787
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3906505547
Short name T632
Test name
Test status
Simulation time 5662878457 ps
CPU time 22.06 seconds
Started Mar 05 01:35:05 PM PST 24
Finished Mar 05 01:35:32 PM PST 24
Peak memory 199208 kb
Host smart-800189e4-eb6f-4d29-8d4e-403e2921d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906505547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3906505547
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2662591093
Short name T834
Test name
Test status
Simulation time 155037382489 ps
CPU time 92.85 seconds
Started Mar 05 01:35:03 PM PST 24
Finished Mar 05 01:36:36 PM PST 24
Peak memory 200388 kb
Host smart-de0ff629-bd0f-4201-8b80-eafffea6f1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662591093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2662591093
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1652439244
Short name T751
Test name
Test status
Simulation time 735350565 ps
CPU time 2.68 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 01:35:13 PM PST 24
Peak memory 198460 kb
Host smart-0e8fcd17-1039-479e-ae52-a1bc584e7fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652439244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1652439244
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3057319988
Short name T749
Test name
Test status
Simulation time 26059426658 ps
CPU time 19.65 seconds
Started Mar 05 01:35:06 PM PST 24
Finished Mar 05 01:35:30 PM PST 24
Peak memory 200424 kb
Host smart-b06fc2fa-25d5-4379-9b0d-1fce1e1143b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057319988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3057319988
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3357644918
Short name T221
Test name
Test status
Simulation time 49244893877 ps
CPU time 33.59 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 200308 kb
Host smart-7faaa90a-7f4a-4678-82ae-a6e8da5b05fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357644918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3357644918
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4205657676
Short name T894
Test name
Test status
Simulation time 96806844697 ps
CPU time 49.24 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:52 PM PST 24
Peak memory 200248 kb
Host smart-276b5707-aee5-40b0-91a5-6081bec30277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205657676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4205657676
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3040214370
Short name T306
Test name
Test status
Simulation time 13649356338 ps
CPU time 6.67 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:09 PM PST 24
Peak memory 199016 kb
Host smart-07718966-a9ab-4ca1-bc36-759e53ff1a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040214370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3040214370
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.847434009
Short name T819
Test name
Test status
Simulation time 40309590875 ps
CPU time 44.11 seconds
Started Mar 05 01:43:58 PM PST 24
Finished Mar 05 01:44:43 PM PST 24
Peak memory 200484 kb
Host smart-5968ada4-a040-4aa6-b9b3-b0472062b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847434009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.847434009
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3911413048
Short name T1018
Test name
Test status
Simulation time 21920403112 ps
CPU time 48.42 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:47 PM PST 24
Peak memory 200368 kb
Host smart-6f39702a-21d1-43fd-82ec-0a4c11c2df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911413048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3911413048
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2862779272
Short name T714
Test name
Test status
Simulation time 78096346630 ps
CPU time 69.75 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:45:10 PM PST 24
Peak memory 200340 kb
Host smart-3aa13ec5-5dc1-47fe-ba59-33d69824d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862779272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2862779272
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3797885434
Short name T1004
Test name
Test status
Simulation time 65224585960 ps
CPU time 28.42 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:31 PM PST 24
Peak memory 200312 kb
Host smart-27780db1-b1ec-4a10-824d-e46c6b54c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797885434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3797885434
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1016824930
Short name T267
Test name
Test status
Simulation time 52705185607 ps
CPU time 17.23 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:44:17 PM PST 24
Peak memory 200352 kb
Host smart-c3d22af8-b7f8-417c-aaa2-ec171c9f7eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016824930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1016824930
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3178432236
Short name T879
Test name
Test status
Simulation time 58249692150 ps
CPU time 45.01 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:47 PM PST 24
Peak memory 200308 kb
Host smart-b9fa7f4a-a5b3-4f0f-8856-b91a8667c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178432236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3178432236
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3906880227
Short name T746
Test name
Test status
Simulation time 19656194 ps
CPU time 0.61 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:14 PM PST 24
Peak memory 195940 kb
Host smart-93617b4b-d586-4017-bdfb-60bd67afa82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906880227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3906880227
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.293291718
Short name T625
Test name
Test status
Simulation time 51741312002 ps
CPU time 88.48 seconds
Started Mar 05 01:33:05 PM PST 24
Finished Mar 05 01:34:35 PM PST 24
Peak memory 200444 kb
Host smart-4516da72-91d7-49f8-8a8b-fcdca1f35b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293291718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.293291718
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2498813557
Short name T328
Test name
Test status
Simulation time 117880327860 ps
CPU time 80.11 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:34:34 PM PST 24
Peak memory 200324 kb
Host smart-eb1b5e0d-54c2-4aae-976e-cf9558c5c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498813557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2498813557
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.372104366
Short name T1031
Test name
Test status
Simulation time 105933889012 ps
CPU time 44.58 seconds
Started Mar 05 01:33:12 PM PST 24
Finished Mar 05 01:33:58 PM PST 24
Peak memory 200408 kb
Host smart-56d3ae3a-4e47-4cc2-9269-d5dacd56bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372104366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.372104366
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1730010828
Short name T21
Test name
Test status
Simulation time 769499008004 ps
CPU time 104.06 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:35:00 PM PST 24
Peak memory 198804 kb
Host smart-522c8aa4-8d51-452d-ac8c-be4cb395884a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730010828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1730010828
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.980390609
Short name T698
Test name
Test status
Simulation time 154436099186 ps
CPU time 796.66 seconds
Started Mar 05 01:33:14 PM PST 24
Finished Mar 05 01:46:31 PM PST 24
Peak memory 200396 kb
Host smart-9fe32442-8b76-4657-b614-7d8119333c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980390609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.980390609
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3314029306
Short name T521
Test name
Test status
Simulation time 11639364066 ps
CPU time 4.87 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:33:20 PM PST 24
Peak memory 198292 kb
Host smart-079bb54f-0878-4080-a3ec-13bd245e8461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314029306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3314029306
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1700119151
Short name T409
Test name
Test status
Simulation time 68210564329 ps
CPU time 58.96 seconds
Started Mar 05 01:33:14 PM PST 24
Finished Mar 05 01:34:13 PM PST 24
Peak memory 199072 kb
Host smart-26b07e21-8504-406f-a547-c3e04fc2ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700119151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1700119151
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.273259124
Short name T711
Test name
Test status
Simulation time 1236166674 ps
CPU time 35.26 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:49 PM PST 24
Peak memory 200168 kb
Host smart-91a91e7a-390c-416f-a0ec-aed5f7d9160c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273259124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.273259124
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.94723453
Short name T721
Test name
Test status
Simulation time 2719205654 ps
CPU time 16.55 seconds
Started Mar 05 01:33:16 PM PST 24
Finished Mar 05 01:33:34 PM PST 24
Peak memory 198876 kb
Host smart-d65f6032-8b18-4bcb-ac70-7301b6ca3a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94723453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.94723453
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.276390157
Short name T133
Test name
Test status
Simulation time 112803852330 ps
CPU time 22.2 seconds
Started Mar 05 01:33:14 PM PST 24
Finished Mar 05 01:33:37 PM PST 24
Peak memory 200324 kb
Host smart-1bc5195a-3c74-4199-9d3d-9b19cc984c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276390157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.276390157
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2188342106
Short name T998
Test name
Test status
Simulation time 6298427474 ps
CPU time 3.71 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:17 PM PST 24
Peak memory 196224 kb
Host smart-a44515a1-02d7-4003-9a0b-06e76cce712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188342106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2188342106
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1943060588
Short name T34
Test name
Test status
Simulation time 73224571 ps
CPU time 0.81 seconds
Started Mar 05 01:33:14 PM PST 24
Finished Mar 05 01:33:15 PM PST 24
Peak memory 217840 kb
Host smart-848cdef7-338c-4518-804e-afe401e04cde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943060588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1943060588
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1163478358
Short name T889
Test name
Test status
Simulation time 6207461013 ps
CPU time 27.06 seconds
Started Mar 05 01:33:07 PM PST 24
Finished Mar 05 01:33:35 PM PST 24
Peak memory 200292 kb
Host smart-c1c180a7-9224-43b3-8cf5-e4676f83496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163478358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1163478358
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2050759720
Short name T523
Test name
Test status
Simulation time 224072610047 ps
CPU time 88.4 seconds
Started Mar 05 01:33:14 PM PST 24
Finished Mar 05 01:34:43 PM PST 24
Peak memory 208780 kb
Host smart-d901a85e-28a3-4657-8d13-3ee6e5f99948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050759720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2050759720
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.79400356
Short name T12
Test name
Test status
Simulation time 292295347545 ps
CPU time 345.84 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:39:00 PM PST 24
Peak memory 216984 kb
Host smart-9bcd53d7-aa34-40ef-82b4-8352ed412cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79400356 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.79400356
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3806610008
Short name T394
Test name
Test status
Simulation time 1222379260 ps
CPU time 2.28 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:16 PM PST 24
Peak memory 198704 kb
Host smart-e09498ba-3f0d-4230-afc5-06491ca8b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806610008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3806610008
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2584338980
Short name T597
Test name
Test status
Simulation time 13493386990 ps
CPU time 5.54 seconds
Started Mar 05 01:33:08 PM PST 24
Finished Mar 05 01:33:14 PM PST 24
Peak memory 197576 kb
Host smart-e71fb3ef-69c1-49a3-a83c-4d918b6e533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584338980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2584338980
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.89769312
Short name T762
Test name
Test status
Simulation time 14908931 ps
CPU time 0.55 seconds
Started Mar 05 01:35:12 PM PST 24
Finished Mar 05 01:35:13 PM PST 24
Peak memory 194912 kb
Host smart-3b6d519e-0643-4db8-9bcd-2876b59559cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89769312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.89769312
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.764000847
Short name T828
Test name
Test status
Simulation time 67140535649 ps
CPU time 68.3 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:36:23 PM PST 24
Peak memory 200364 kb
Host smart-286f0fbd-9ade-41dc-873b-be484e8f7136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764000847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.764000847
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3687602605
Short name T708
Test name
Test status
Simulation time 56317420293 ps
CPU time 27.02 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:40 PM PST 24
Peak memory 200348 kb
Host smart-c70f421a-7d49-47d2-bd56-ad2819dc58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687602605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3687602605
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1977948221
Short name T51
Test name
Test status
Simulation time 9159490705 ps
CPU time 2.64 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:15 PM PST 24
Peak memory 198568 kb
Host smart-15313702-a9c4-473d-98ce-2a2dd4a7627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977948221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1977948221
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1782576305
Short name T474
Test name
Test status
Simulation time 22940269770 ps
CPU time 7.95 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:35:22 PM PST 24
Peak memory 198020 kb
Host smart-8ddb835c-9771-4747-8acd-4f937b307353
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782576305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1782576305
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.844881068
Short name T857
Test name
Test status
Simulation time 153804497403 ps
CPU time 1031.33 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:52:25 PM PST 24
Peak memory 200392 kb
Host smart-1f373d80-66c2-4be8-86bf-f895469efea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844881068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.844881068
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1847350227
Short name T771
Test name
Test status
Simulation time 4625544838 ps
CPU time 3.73 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:35:18 PM PST 24
Peak memory 198644 kb
Host smart-d37e9d31-2d8d-4e87-b628-d4751a7e838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847350227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1847350227
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1792833843
Short name T581
Test name
Test status
Simulation time 21546171638 ps
CPU time 38.03 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:35:52 PM PST 24
Peak memory 197848 kb
Host smart-30971568-8391-42f8-a7ec-b3767392dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792833843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1792833843
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2638755930
Short name T103
Test name
Test status
Simulation time 12990066422 ps
CPU time 761.94 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:47:57 PM PST 24
Peak memory 200436 kb
Host smart-3d0d6d63-e2ff-4faf-ada6-40adacaf23d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638755930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2638755930
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1902164299
Short name T514
Test name
Test status
Simulation time 5203192273 ps
CPU time 11.76 seconds
Started Mar 05 01:35:17 PM PST 24
Finished Mar 05 01:35:29 PM PST 24
Peak memory 199192 kb
Host smart-e891d99f-e687-4a59-b854-ef5d529aa1c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902164299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1902164299
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3954558190
Short name T361
Test name
Test status
Simulation time 151316203443 ps
CPU time 14.62 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:35:43 PM PST 24
Peak memory 199996 kb
Host smart-6bdaef3b-9e58-4007-902a-da115fddf7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954558190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3954558190
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.164396992
Short name T678
Test name
Test status
Simulation time 35803715020 ps
CPU time 30.68 seconds
Started Mar 05 01:35:14 PM PST 24
Finished Mar 05 01:35:45 PM PST 24
Peak memory 195876 kb
Host smart-4117b2e0-a7cb-4e17-a9d9-4f8721dd88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164396992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.164396992
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4086338384
Short name T485
Test name
Test status
Simulation time 450011087 ps
CPU time 1.97 seconds
Started Mar 05 01:35:11 PM PST 24
Finished Mar 05 01:35:13 PM PST 24
Peak memory 198076 kb
Host smart-f8a0bb07-4d88-4e65-bd1b-20ca86b912b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086338384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4086338384
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1065482201
Short name T225
Test name
Test status
Simulation time 346170368436 ps
CPU time 1247.95 seconds
Started Mar 05 01:35:11 PM PST 24
Finished Mar 05 01:55:59 PM PST 24
Peak memory 200412 kb
Host smart-c2d3c90a-828e-426d-a7fd-306dd2b72ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065482201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1065482201
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2377432662
Short name T574
Test name
Test status
Simulation time 6794686707 ps
CPU time 13.37 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:27 PM PST 24
Peak memory 199592 kb
Host smart-2f67a507-ddac-488e-a4af-779709ea859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377432662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2377432662
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1293551408
Short name T1021
Test name
Test status
Simulation time 69897771457 ps
CPU time 77.87 seconds
Started Mar 05 01:35:12 PM PST 24
Finished Mar 05 01:36:30 PM PST 24
Peak memory 200360 kb
Host smart-2e32827c-fc0d-4e0b-ab6b-85e72f061b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293551408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1293551408
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2455278576
Short name T567
Test name
Test status
Simulation time 31352960 ps
CPU time 0.56 seconds
Started Mar 05 01:35:20 PM PST 24
Finished Mar 05 01:35:21 PM PST 24
Peak memory 195940 kb
Host smart-0f5fed4c-ff60-46ea-9f2e-68232fd4203c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455278576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2455278576
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.138312727
Short name T342
Test name
Test status
Simulation time 83077101209 ps
CPU time 38.7 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:52 PM PST 24
Peak memory 200404 kb
Host smart-819139ac-da56-4e65-af46-26a10a0feef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138312727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.138312727
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3787424198
Short name T504
Test name
Test status
Simulation time 84078535044 ps
CPU time 134.43 seconds
Started Mar 05 01:35:11 PM PST 24
Finished Mar 05 01:37:26 PM PST 24
Peak memory 200312 kb
Host smart-ffff70d5-7ddb-4a41-ac3f-6d7d2f5d3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787424198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3787424198
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1670182371
Short name T152
Test name
Test status
Simulation time 119737314042 ps
CPU time 78.38 seconds
Started Mar 05 01:35:11 PM PST 24
Finished Mar 05 01:36:30 PM PST 24
Peak memory 199612 kb
Host smart-bb1c97ee-065b-49e4-ac8f-dfc571676e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670182371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1670182371
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1971626625
Short name T852
Test name
Test status
Simulation time 490188940646 ps
CPU time 767.2 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:48:01 PM PST 24
Peak memory 200404 kb
Host smart-96273ac0-68ae-490d-a407-f6a93f556415
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971626625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1971626625
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1808302151
Short name T516
Test name
Test status
Simulation time 90615451846 ps
CPU time 233.46 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:39:06 PM PST 24
Peak memory 200352 kb
Host smart-dbdb146b-849a-4ade-80ad-840abe106867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808302151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1808302151
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.226656602
Short name T454
Test name
Test status
Simulation time 3579680395 ps
CPU time 2.67 seconds
Started Mar 05 01:35:20 PM PST 24
Finished Mar 05 01:35:22 PM PST 24
Peak memory 199632 kb
Host smart-83165b37-232a-4e3c-9141-9eb335469d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226656602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.226656602
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.285979312
Short name T630
Test name
Test status
Simulation time 7191599499 ps
CPU time 7.32 seconds
Started Mar 05 01:35:19 PM PST 24
Finished Mar 05 01:35:27 PM PST 24
Peak memory 194128 kb
Host smart-30d44843-668e-4817-a574-aabd4f14a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285979312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.285979312
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.778468249
Short name T953
Test name
Test status
Simulation time 25361958870 ps
CPU time 1484.69 seconds
Started Mar 05 01:35:15 PM PST 24
Finished Mar 05 02:00:00 PM PST 24
Peak memory 200420 kb
Host smart-919bd4ff-e6ea-45e2-bb95-cbbaddb042e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778468249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.778468249
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1490327743
Short name T463
Test name
Test status
Simulation time 2121804758 ps
CPU time 1.06 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:14 PM PST 24
Peak memory 198104 kb
Host smart-ea60502e-79c7-462c-b3c6-5bb45526049e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490327743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1490327743
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.4107385817
Short name T886
Test name
Test status
Simulation time 189141339568 ps
CPU time 128.71 seconds
Started Mar 05 01:35:12 PM PST 24
Finished Mar 05 01:37:21 PM PST 24
Peak memory 200372 kb
Host smart-52614c0e-ee4f-466c-bda2-65829930c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107385817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4107385817
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1230849424
Short name T460
Test name
Test status
Simulation time 1825998249 ps
CPU time 3.19 seconds
Started Mar 05 01:35:12 PM PST 24
Finished Mar 05 01:35:15 PM PST 24
Peak memory 195888 kb
Host smart-0b31ed4e-552e-4ce7-84fd-d359387597da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230849424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1230849424
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3114539250
Short name T672
Test name
Test status
Simulation time 518038524 ps
CPU time 1.7 seconds
Started Mar 05 01:35:12 PM PST 24
Finished Mar 05 01:35:14 PM PST 24
Peak memory 198176 kb
Host smart-95c7f6de-c155-4447-a31a-76fd29e7508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114539250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3114539250
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.863363827
Short name T453
Test name
Test status
Simulation time 907269011083 ps
CPU time 296.45 seconds
Started Mar 05 01:35:19 PM PST 24
Finished Mar 05 01:40:16 PM PST 24
Peak memory 200536 kb
Host smart-c686f47d-5af8-464b-8c63-cc1dcd2f06cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863363827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.863363827
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1172101561
Short name T706
Test name
Test status
Simulation time 1200303462 ps
CPU time 4.96 seconds
Started Mar 05 01:35:13 PM PST 24
Finished Mar 05 01:35:19 PM PST 24
Peak memory 198964 kb
Host smart-f101bcfe-0e86-4fd2-b41b-ba1663bdc3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172101561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1172101561
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.920544907
Short name T473
Test name
Test status
Simulation time 35565288215 ps
CPU time 14.17 seconds
Started Mar 05 01:35:36 PM PST 24
Finished Mar 05 01:35:50 PM PST 24
Peak memory 197692 kb
Host smart-b2004a62-91b0-4b07-9e10-fd929ee73856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920544907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.920544907
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1269177686
Short name T594
Test name
Test status
Simulation time 17640886 ps
CPU time 0.55 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:35:29 PM PST 24
Peak memory 195884 kb
Host smart-776be9d7-9c8f-4bb6-b327-6b8f0505042f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269177686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1269177686
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.201959812
Short name T556
Test name
Test status
Simulation time 115876628652 ps
CPU time 162.83 seconds
Started Mar 05 01:35:21 PM PST 24
Finished Mar 05 01:38:04 PM PST 24
Peak memory 200468 kb
Host smart-eefbd04c-661e-4ca3-832b-0c367af06f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201959812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.201959812
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.722417487
Short name T595
Test name
Test status
Simulation time 126245466198 ps
CPU time 61.17 seconds
Started Mar 05 01:35:22 PM PST 24
Finished Mar 05 01:36:24 PM PST 24
Peak memory 200328 kb
Host smart-b7fc2737-14e1-49e5-aebe-57fa1bb040ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722417487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.722417487
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.666610671
Short name T47
Test name
Test status
Simulation time 65515330715 ps
CPU time 42.52 seconds
Started Mar 05 01:35:20 PM PST 24
Finished Mar 05 01:36:03 PM PST 24
Peak memory 200416 kb
Host smart-0c78c507-2f98-45e4-bf73-21fdf74e2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666610671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.666610671
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4064358687
Short name T490
Test name
Test status
Simulation time 327112439075 ps
CPU time 146.29 seconds
Started Mar 05 01:35:19 PM PST 24
Finished Mar 05 01:37:45 PM PST 24
Peak memory 200328 kb
Host smart-68258802-b186-4ffb-90fd-c0566b28d233
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064358687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4064358687
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3366103736
Short name T391
Test name
Test status
Simulation time 158352415300 ps
CPU time 168.23 seconds
Started Mar 05 01:35:30 PM PST 24
Finished Mar 05 01:38:18 PM PST 24
Peak memory 200352 kb
Host smart-31e011c8-efe2-446b-af71-5dd96d13cd91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366103736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3366103736
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1468025925
Short name T503
Test name
Test status
Simulation time 55910020667 ps
CPU time 104.03 seconds
Started Mar 05 01:35:30 PM PST 24
Finished Mar 05 01:37:14 PM PST 24
Peak memory 200548 kb
Host smart-bd0be023-1a3d-40c2-bee0-ef5477521407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468025925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1468025925
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3769002428
Short name T978
Test name
Test status
Simulation time 13499804338 ps
CPU time 261.8 seconds
Started Mar 05 01:35:30 PM PST 24
Finished Mar 05 01:39:52 PM PST 24
Peak memory 200428 kb
Host smart-55c524ba-f717-433b-a2f4-6184a67e9d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769002428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3769002428
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.435806452
Short name T384
Test name
Test status
Simulation time 202970273544 ps
CPU time 37.76 seconds
Started Mar 05 01:35:22 PM PST 24
Finished Mar 05 01:35:59 PM PST 24
Peak memory 199960 kb
Host smart-8377090d-e291-4f85-915f-2fdec7365f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435806452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.435806452
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1196803092
Short name T568
Test name
Test status
Simulation time 33447196184 ps
CPU time 27.08 seconds
Started Mar 05 01:35:20 PM PST 24
Finished Mar 05 01:35:47 PM PST 24
Peak memory 196196 kb
Host smart-22c63a4b-8f68-494c-8b7f-257fc1068a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196803092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1196803092
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.338508066
Short name T1055
Test name
Test status
Simulation time 675937759 ps
CPU time 2.11 seconds
Started Mar 05 01:35:22 PM PST 24
Finished Mar 05 01:35:24 PM PST 24
Peak memory 198908 kb
Host smart-bf124ddd-17af-4255-b4df-7474402766ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338508066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.338508066
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1639447172
Short name T918
Test name
Test status
Simulation time 7682028387 ps
CPU time 11.68 seconds
Started Mar 05 01:35:20 PM PST 24
Finished Mar 05 01:35:32 PM PST 24
Peak memory 200440 kb
Host smart-d1399d20-9c93-44d9-9eec-13c8cf7fd11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639447172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1639447172
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3440825115
Short name T915
Test name
Test status
Simulation time 125498398707 ps
CPU time 62.87 seconds
Started Mar 05 01:35:19 PM PST 24
Finished Mar 05 01:36:22 PM PST 24
Peak memory 200328 kb
Host smart-30205a8b-db81-44de-9a03-f82c97381c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440825115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3440825115
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3208655579
Short name T481
Test name
Test status
Simulation time 11786476 ps
CPU time 0.55 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:35:27 PM PST 24
Peak memory 195944 kb
Host smart-4f739bd5-5f18-47ce-8142-3b7853f59e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208655579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3208655579
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.568571582
Short name T1024
Test name
Test status
Simulation time 111290217017 ps
CPU time 39.55 seconds
Started Mar 05 01:35:31 PM PST 24
Finished Mar 05 01:36:10 PM PST 24
Peak memory 200364 kb
Host smart-795c70a3-c7a7-4789-a56c-b4f57e9c057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568571582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.568571582
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3563831104
Short name T925
Test name
Test status
Simulation time 52795731209 ps
CPU time 58.7 seconds
Started Mar 05 01:35:30 PM PST 24
Finished Mar 05 01:36:29 PM PST 24
Peak memory 200308 kb
Host smart-729a864e-db4c-40db-ad9b-a44f3e777c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563831104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3563831104
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1713673702
Short name T432
Test name
Test status
Simulation time 23908688779 ps
CPU time 42.25 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:36:09 PM PST 24
Peak memory 200444 kb
Host smart-4eefc078-5fd5-434e-abf4-f30c95ec7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713673702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1713673702
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2647569591
Short name T431
Test name
Test status
Simulation time 100358648124 ps
CPU time 173.49 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:38:20 PM PST 24
Peak memory 200304 kb
Host smart-4e9ada91-398c-4903-8ca1-ea107b8c05a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647569591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2647569591
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1381942827
Short name T1016
Test name
Test status
Simulation time 217929741129 ps
CPU time 259.56 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:39:47 PM PST 24
Peak memory 200376 kb
Host smart-9a282c49-c022-45d7-b571-e6d825f4372f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381942827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1381942827
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2684985011
Short name T1014
Test name
Test status
Simulation time 3404611648 ps
CPU time 2.62 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:35:29 PM PST 24
Peak memory 200028 kb
Host smart-94d165f5-9742-437e-b880-4b7c54ff7057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684985011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2684985011
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1969475781
Short name T665
Test name
Test status
Simulation time 572325434778 ps
CPU time 90.94 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:36:58 PM PST 24
Peak memory 199528 kb
Host smart-f10c2ea5-cb68-4467-8728-4dbe93a16a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969475781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1969475781
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.833158684
Short name T810
Test name
Test status
Simulation time 14580145221 ps
CPU time 413.64 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:42:21 PM PST 24
Peak memory 200276 kb
Host smart-d745e6fd-57c2-46dc-ade4-54283abdf3d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833158684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.833158684
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1362542737
Short name T878
Test name
Test status
Simulation time 3662908153 ps
CPU time 29.7 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:35:56 PM PST 24
Peak memory 198744 kb
Host smart-28e2d8d1-b4e7-4fba-a884-c580e3ea7c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362542737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1362542737
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1710659377
Short name T353
Test name
Test status
Simulation time 36967883007 ps
CPU time 17.82 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:35:46 PM PST 24
Peak memory 200360 kb
Host smart-f609a789-df80-4ff2-a91f-fdfd2bbdfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710659377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1710659377
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2893364114
Short name T435
Test name
Test status
Simulation time 35803690460 ps
CPU time 15.38 seconds
Started Mar 05 01:35:30 PM PST 24
Finished Mar 05 01:35:45 PM PST 24
Peak memory 195968 kb
Host smart-200184bf-48bb-419b-bca3-b76fc0d6d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893364114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2893364114
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3146103779
Short name T753
Test name
Test status
Simulation time 5982719725 ps
CPU time 19.97 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:35:48 PM PST 24
Peak memory 199672 kb
Host smart-4faf4fad-79ba-42a4-97cb-e881608a0df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146103779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3146103779
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.157454160
Short name T452
Test name
Test status
Simulation time 477116044712 ps
CPU time 332.34 seconds
Started Mar 05 01:35:26 PM PST 24
Finished Mar 05 01:40:59 PM PST 24
Peak memory 208772 kb
Host smart-1ca7e77a-933b-4540-af0a-14656db194ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157454160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.157454160
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3034936762
Short name T17
Test name
Test status
Simulation time 1314808238 ps
CPU time 1.53 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:35:29 PM PST 24
Peak memory 198348 kb
Host smart-393bd69c-ff80-4cf0-bacf-fe37d4b81eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034936762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3034936762
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1336715332
Short name T399
Test name
Test status
Simulation time 144037043166 ps
CPU time 233.81 seconds
Started Mar 05 01:35:27 PM PST 24
Finished Mar 05 01:39:21 PM PST 24
Peak memory 200232 kb
Host smart-c21cd456-a7ce-41fb-b9f6-3ed16a5c5a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336715332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1336715332
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.360337777
Short name T648
Test name
Test status
Simulation time 39610013 ps
CPU time 0.57 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:36 PM PST 24
Peak memory 195840 kb
Host smart-00386f47-38cc-4c52-92b7-1938b39eb070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360337777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.360337777
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1609828957
Short name T43
Test name
Test status
Simulation time 3875107377 ps
CPU time 7.41 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:42 PM PST 24
Peak memory 197396 kb
Host smart-ab1dda77-5ade-43d6-8a32-6a132d382952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609828957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1609828957
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1708856343
Short name T217
Test name
Test status
Simulation time 18767323859 ps
CPU time 35.11 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:36:09 PM PST 24
Peak memory 200308 kb
Host smart-2aeb52e2-643e-49e9-a0d5-bd5b3226631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708856343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1708856343
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3013185090
Short name T579
Test name
Test status
Simulation time 433466759033 ps
CPU time 92.45 seconds
Started Mar 05 01:35:36 PM PST 24
Finished Mar 05 01:37:09 PM PST 24
Peak memory 200380 kb
Host smart-ea0b680a-f87b-4934-8050-018df54739b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013185090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3013185090
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.835258848
Short name T1082
Test name
Test status
Simulation time 114381375408 ps
CPU time 793.43 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:48:48 PM PST 24
Peak memory 200344 kb
Host smart-f9eb4a68-5309-4fd1-b2b6-495da2979e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835258848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.835258848
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2379406321
Short name T933
Test name
Test status
Simulation time 1373435690 ps
CPU time 2.83 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:38 PM PST 24
Peak memory 195736 kb
Host smart-43430aca-720a-4490-89d2-59276e17dd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379406321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2379406321
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.799218803
Short name T703
Test name
Test status
Simulation time 50867330169 ps
CPU time 20.7 seconds
Started Mar 05 01:35:36 PM PST 24
Finished Mar 05 01:35:57 PM PST 24
Peak memory 197768 kb
Host smart-a5e911a1-2d8e-40d9-bf36-ea7e4cabd8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799218803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.799218803
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1390211992
Short name T710
Test name
Test status
Simulation time 1934055231 ps
CPU time 51.42 seconds
Started Mar 05 01:35:36 PM PST 24
Finished Mar 05 01:36:28 PM PST 24
Peak memory 200304 kb
Host smart-2391ff43-8161-432c-8d1c-17c12f714f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390211992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1390211992
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2815580825
Short name T1022
Test name
Test status
Simulation time 3999575850 ps
CPU time 16.4 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:51 PM PST 24
Peak memory 198868 kb
Host smart-c0dbddbf-0fda-4b6c-bf0e-f165aa86566a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815580825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2815580825
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.792051379
Short name T923
Test name
Test status
Simulation time 24279275693 ps
CPU time 45.45 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:36:20 PM PST 24
Peak memory 200348 kb
Host smart-6f358fae-b39e-4b53-ac9c-eb5a5bb6f2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792051379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.792051379
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1868401426
Short name T917
Test name
Test status
Simulation time 4879566933 ps
CPU time 8 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:43 PM PST 24
Peak memory 196152 kb
Host smart-67011946-317b-45f0-8ea3-47001cec54a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868401426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1868401426
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3610556285
Short name T530
Test name
Test status
Simulation time 5290264950 ps
CPU time 16.09 seconds
Started Mar 05 01:35:28 PM PST 24
Finished Mar 05 01:35:44 PM PST 24
Peak memory 199716 kb
Host smart-8c4e86d4-a4ce-46e2-bc71-50e19e93b09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610556285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3610556285
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3345090217
Short name T273
Test name
Test status
Simulation time 1008697149768 ps
CPU time 1225.73 seconds
Started Mar 05 01:35:33 PM PST 24
Finished Mar 05 01:55:59 PM PST 24
Peak memory 200652 kb
Host smart-6b4af5f2-d7a5-4209-99ec-57e4ec357e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345090217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3345090217
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2355990004
Short name T1012
Test name
Test status
Simulation time 1864262448 ps
CPU time 2.01 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:35:36 PM PST 24
Peak memory 198348 kb
Host smart-80b973b0-17fc-49dc-88be-ee3e116bbfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355990004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2355990004
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1262908650
Short name T1084
Test name
Test status
Simulation time 36601686614 ps
CPU time 41.89 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:36:16 PM PST 24
Peak memory 200336 kb
Host smart-c5df62c4-fcfb-4655-ba9e-147547f54509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262908650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1262908650
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3365721827
Short name T887
Test name
Test status
Simulation time 11638406 ps
CPU time 0.57 seconds
Started Mar 05 01:35:49 PM PST 24
Finished Mar 05 01:35:49 PM PST 24
Peak memory 195948 kb
Host smart-321845aa-9b2e-42e9-8527-eecb75ad9732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365721827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3365721827
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1652488948
Short name T281
Test name
Test status
Simulation time 260113758002 ps
CPU time 193.12 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:38:48 PM PST 24
Peak memory 200360 kb
Host smart-d67e5e84-5ea0-4bf2-adc8-b848df8cab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652488948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1652488948
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3989074846
Short name T246
Test name
Test status
Simulation time 35188375933 ps
CPU time 61.91 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:36:36 PM PST 24
Peak memory 200384 kb
Host smart-b5658aa9-8fd6-460a-8a8d-61d2002f9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989074846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3989074846
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3565383224
Short name T1080
Test name
Test status
Simulation time 27374950679 ps
CPU time 70.19 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:36:45 PM PST 24
Peak memory 200332 kb
Host smart-d0c2b95a-d0fa-4639-9e68-4272eac1605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565383224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3565383224
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.786997018
Short name T446
Test name
Test status
Simulation time 44889759112 ps
CPU time 28.09 seconds
Started Mar 05 01:35:37 PM PST 24
Finished Mar 05 01:36:05 PM PST 24
Peak memory 199656 kb
Host smart-27f31504-ab85-405d-ac9f-2ca398165f83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786997018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.786997018
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.469089154
Short name T641
Test name
Test status
Simulation time 42792892886 ps
CPU time 244.59 seconds
Started Mar 05 01:35:40 PM PST 24
Finished Mar 05 01:39:45 PM PST 24
Peak memory 200332 kb
Host smart-9dac93d6-5a70-4a55-a683-f3651b0b86eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469089154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.469089154
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.58479239
Short name T790
Test name
Test status
Simulation time 3997370120 ps
CPU time 5.58 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:41 PM PST 24
Peak memory 199640 kb
Host smart-145af6c1-bd0e-4cb3-8b4d-2c99c74f448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58479239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.58479239
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3765550943
Short name T813
Test name
Test status
Simulation time 65227394980 ps
CPU time 114.39 seconds
Started Mar 05 01:35:33 PM PST 24
Finished Mar 05 01:37:27 PM PST 24
Peak memory 200540 kb
Host smart-4ebe9bba-db85-4c44-975e-6aa5a05ca0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765550943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3765550943
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2407565591
Short name T808
Test name
Test status
Simulation time 21371988370 ps
CPU time 475.79 seconds
Started Mar 05 01:35:41 PM PST 24
Finished Mar 05 01:43:37 PM PST 24
Peak memory 200372 kb
Host smart-fd72372b-e3ef-4430-8296-3de420220627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407565591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2407565591
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4094325855
Short name T724
Test name
Test status
Simulation time 173551290 ps
CPU time 0.6 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:35 PM PST 24
Peak memory 195784 kb
Host smart-74fcd739-d894-418d-97ce-38790c649b1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094325855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4094325855
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3667435874
Short name T362
Test name
Test status
Simulation time 18347418902 ps
CPU time 16.17 seconds
Started Mar 05 01:35:35 PM PST 24
Finished Mar 05 01:35:52 PM PST 24
Peak memory 199724 kb
Host smart-b88158d6-9108-4949-957f-bc4d62186c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667435874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3667435874
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3983876512
Short name T956
Test name
Test status
Simulation time 4374736798 ps
CPU time 8.43 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:35:43 PM PST 24
Peak memory 196292 kb
Host smart-7baf736c-1800-4592-9489-c487cc217d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983876512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3983876512
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.72732749
Short name T959
Test name
Test status
Simulation time 848797793 ps
CPU time 1.97 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:35:36 PM PST 24
Peak memory 198152 kb
Host smart-89f87df2-b183-4c4c-8d56-df952534fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72732749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.72732749
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3205951236
Short name T348
Test name
Test status
Simulation time 116618198482 ps
CPU time 211.74 seconds
Started Mar 05 01:35:42 PM PST 24
Finished Mar 05 01:39:14 PM PST 24
Peak memory 208828 kb
Host smart-a24a84c3-a57b-48aa-9cc6-9d73fa42ab48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205951236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3205951236
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2295682212
Short name T441
Test name
Test status
Simulation time 155687081069 ps
CPU time 907.33 seconds
Started Mar 05 01:35:43 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 225896 kb
Host smart-36bdf84c-3d55-4258-b769-bf604e8e5123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295682212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2295682212
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2822785152
Short name T587
Test name
Test status
Simulation time 1559946154 ps
CPU time 2.89 seconds
Started Mar 05 01:35:38 PM PST 24
Finished Mar 05 01:35:41 PM PST 24
Peak memory 198748 kb
Host smart-f2b51d76-717f-47a8-8fa3-3f5d7ab9f633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822785152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2822785152
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2458470026
Short name T823
Test name
Test status
Simulation time 204131380505 ps
CPU time 116.18 seconds
Started Mar 05 01:35:34 PM PST 24
Finished Mar 05 01:37:30 PM PST 24
Peak memory 200408 kb
Host smart-086eafbb-4ef2-4cd6-b062-90d734d36015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458470026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2458470026
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1354000458
Short name T1081
Test name
Test status
Simulation time 42176778 ps
CPU time 0.57 seconds
Started Mar 05 01:35:48 PM PST 24
Finished Mar 05 01:35:49 PM PST 24
Peak memory 195024 kb
Host smart-4a656dd9-8c9b-4ffe-a8f2-4f5a68f3f29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354000458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1354000458
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1591604971
Short name T378
Test name
Test status
Simulation time 249534855344 ps
CPU time 434.94 seconds
Started Mar 05 01:35:44 PM PST 24
Finished Mar 05 01:43:00 PM PST 24
Peak memory 200328 kb
Host smart-ed10b3b4-6b1f-429a-b84a-4eae2df3b41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591604971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1591604971
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.943487821
Short name T330
Test name
Test status
Simulation time 70392624291 ps
CPU time 110.54 seconds
Started Mar 05 01:35:43 PM PST 24
Finished Mar 05 01:37:33 PM PST 24
Peak memory 200076 kb
Host smart-dd4b8963-f408-4718-ad35-15260ad4aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943487821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.943487821
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.272941694
Short name T582
Test name
Test status
Simulation time 101644192548 ps
CPU time 39.95 seconds
Started Mar 05 01:35:44 PM PST 24
Finished Mar 05 01:36:24 PM PST 24
Peak memory 198684 kb
Host smart-de1605d5-2397-4e70-b777-51cc9b5df543
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272941694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.272941694
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1855458018
Short name T1005
Test name
Test status
Simulation time 113485286942 ps
CPU time 507.62 seconds
Started Mar 05 01:35:51 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 200324 kb
Host smart-3aba7d61-f5e5-4c53-99ea-8fa82cc11f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855458018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1855458018
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3614468396
Short name T707
Test name
Test status
Simulation time 3248947258 ps
CPU time 3.81 seconds
Started Mar 05 01:35:49 PM PST 24
Finished Mar 05 01:35:53 PM PST 24
Peak memory 198800 kb
Host smart-3bbf29f0-7f42-42d5-b4da-59be71fb345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614468396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3614468396
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1203398066
Short name T1073
Test name
Test status
Simulation time 174539739015 ps
CPU time 149 seconds
Started Mar 05 01:35:40 PM PST 24
Finished Mar 05 01:38:09 PM PST 24
Peak memory 208664 kb
Host smart-7e17f2ce-cc54-4e96-b172-7cc0af5709f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203398066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1203398066
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2637444023
Short name T202
Test name
Test status
Simulation time 19771749869 ps
CPU time 213 seconds
Started Mar 05 01:35:51 PM PST 24
Finished Mar 05 01:39:25 PM PST 24
Peak memory 200360 kb
Host smart-1b95533b-49a1-481d-a20b-c2ebac969902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637444023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2637444023
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.244318745
Short name T25
Test name
Test status
Simulation time 2606325542 ps
CPU time 22.22 seconds
Started Mar 05 01:35:42 PM PST 24
Finished Mar 05 01:36:04 PM PST 24
Peak memory 198844 kb
Host smart-a380476c-8367-4cfa-a2a5-821945dafdc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244318745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.244318745
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1566662620
Short name T606
Test name
Test status
Simulation time 274873447976 ps
CPU time 35.14 seconds
Started Mar 05 01:35:42 PM PST 24
Finished Mar 05 01:36:17 PM PST 24
Peak memory 200284 kb
Host smart-b496dce7-b997-482f-afde-bf3344b506bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566662620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1566662620
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3982469900
Short name T697
Test name
Test status
Simulation time 6383647588 ps
CPU time 3.14 seconds
Started Mar 05 01:35:42 PM PST 24
Finished Mar 05 01:35:45 PM PST 24
Peak memory 196100 kb
Host smart-82fb4c9a-15ed-4f03-a9c4-e9149de0294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982469900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3982469900
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1021334662
Short name T407
Test name
Test status
Simulation time 943843225 ps
CPU time 3.37 seconds
Started Mar 05 01:35:41 PM PST 24
Finished Mar 05 01:35:44 PM PST 24
Peak memory 199648 kb
Host smart-980a56ff-ef6c-4d82-9526-cbd67e667351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021334662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1021334662
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.753617532
Short name T60
Test name
Test status
Simulation time 100446185862 ps
CPU time 314.08 seconds
Started Mar 05 01:35:52 PM PST 24
Finished Mar 05 01:41:07 PM PST 24
Peak memory 215676 kb
Host smart-afb70ca6-14b2-486d-9738-0afd8e097754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753617532 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.753617532
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3640950949
Short name T727
Test name
Test status
Simulation time 7065776418 ps
CPU time 17.64 seconds
Started Mar 05 01:35:50 PM PST 24
Finished Mar 05 01:36:08 PM PST 24
Peak memory 200432 kb
Host smart-39cd1a09-0618-411c-a2d1-72163316386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640950949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3640950949
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1979395011
Short name T1007
Test name
Test status
Simulation time 11489192414 ps
CPU time 17.25 seconds
Started Mar 05 01:35:43 PM PST 24
Finished Mar 05 01:36:00 PM PST 24
Peak memory 200340 kb
Host smart-a870c043-180e-41f7-b015-8ff6fefb0364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979395011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1979395011
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3289996326
Short name T52
Test name
Test status
Simulation time 33733154 ps
CPU time 0.56 seconds
Started Mar 05 01:36:13 PM PST 24
Finished Mar 05 01:36:13 PM PST 24
Peak memory 195964 kb
Host smart-bbc3ddf8-a9e5-4f7f-bbc6-a7222a8f9899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289996326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3289996326
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2519577701
Short name T974
Test name
Test status
Simulation time 271595269412 ps
CPU time 39.64 seconds
Started Mar 05 01:36:01 PM PST 24
Finished Mar 05 01:36:41 PM PST 24
Peak memory 200460 kb
Host smart-1710459d-abdf-467c-857b-017b1e39c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519577701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2519577701
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2703474047
Short name T1064
Test name
Test status
Simulation time 32377335861 ps
CPU time 56.5 seconds
Started Mar 05 01:35:59 PM PST 24
Finished Mar 05 01:36:57 PM PST 24
Peak memory 199620 kb
Host smart-0dc9163a-56ae-4a88-907c-1b8b13798d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703474047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2703474047
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.1539581340
Short name T15
Test name
Test status
Simulation time 91065565523 ps
CPU time 127.17 seconds
Started Mar 05 01:36:11 PM PST 24
Finished Mar 05 01:38:18 PM PST 24
Peak memory 200268 kb
Host smart-cf8e542a-9a34-4fba-b1fd-58f50d64a459
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539581340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1539581340
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3342640502
Short name T685
Test name
Test status
Simulation time 26825122872 ps
CPU time 157.59 seconds
Started Mar 05 01:36:15 PM PST 24
Finished Mar 05 01:38:53 PM PST 24
Peak memory 200288 kb
Host smart-65c026f2-9fca-4f70-9221-81fba591eacc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342640502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3342640502
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_noise_filter.380433784
Short name T1075
Test name
Test status
Simulation time 67778822351 ps
CPU time 127.2 seconds
Started Mar 05 01:36:10 PM PST 24
Finished Mar 05 01:38:17 PM PST 24
Peak memory 199972 kb
Host smart-023b0abf-96bc-4e16-8be0-677abe1ecf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380433784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.380433784
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1281865806
Short name T101
Test name
Test status
Simulation time 23525158111 ps
CPU time 262.37 seconds
Started Mar 05 01:36:08 PM PST 24
Finished Mar 05 01:40:31 PM PST 24
Peak memory 200356 kb
Host smart-290e012e-b84e-48b4-ac9c-80c41a430a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281865806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1281865806
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.4216099405
Short name T1041
Test name
Test status
Simulation time 2670782263 ps
CPU time 9.05 seconds
Started Mar 05 01:36:00 PM PST 24
Finished Mar 05 01:36:10 PM PST 24
Peak memory 198772 kb
Host smart-83e51d9f-514f-4d4c-9b06-c8d6225fc645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216099405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4216099405
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3168686009
Short name T899
Test name
Test status
Simulation time 174805789641 ps
CPU time 50.77 seconds
Started Mar 05 01:36:11 PM PST 24
Finished Mar 05 01:37:02 PM PST 24
Peak memory 200388 kb
Host smart-c20f2b24-079b-4659-8c6d-f6e462a73c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168686009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3168686009
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1011430291
Short name T786
Test name
Test status
Simulation time 5037225880 ps
CPU time 2.27 seconds
Started Mar 05 01:36:08 PM PST 24
Finished Mar 05 01:36:11 PM PST 24
Peak memory 196192 kb
Host smart-d1d225fa-d3d3-42a3-ae4d-d25e13f19456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011430291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1011430291
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.375200450
Short name T1069
Test name
Test status
Simulation time 647131442 ps
CPU time 2.56 seconds
Started Mar 05 01:35:50 PM PST 24
Finished Mar 05 01:35:53 PM PST 24
Peak memory 198656 kb
Host smart-ebbe5117-d526-466f-9e53-ee4f6439e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375200450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.375200450
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3842049642
Short name T826
Test name
Test status
Simulation time 44871201112 ps
CPU time 74.09 seconds
Started Mar 05 01:36:17 PM PST 24
Finished Mar 05 01:37:32 PM PST 24
Peak memory 200460 kb
Host smart-13b33850-0848-4059-bc0d-5c4d95ef47fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842049642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3842049642
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1249821288
Short name T942
Test name
Test status
Simulation time 720537980 ps
CPU time 2.35 seconds
Started Mar 05 01:36:10 PM PST 24
Finished Mar 05 01:36:13 PM PST 24
Peak memory 198892 kb
Host smart-b9704630-5441-4664-8f96-d705960b9b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249821288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1249821288
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.916671777
Short name T738
Test name
Test status
Simulation time 142107562116 ps
CPU time 54.37 seconds
Started Mar 05 01:35:58 PM PST 24
Finished Mar 05 01:36:52 PM PST 24
Peak memory 200324 kb
Host smart-9871845e-0b51-43db-a6f6-58ef4772669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916671777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.916671777
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.612346934
Short name T519
Test name
Test status
Simulation time 74336249 ps
CPU time 0.55 seconds
Started Mar 05 01:36:40 PM PST 24
Finished Mar 05 01:36:41 PM PST 24
Peak memory 195796 kb
Host smart-5873bd80-a3f2-43ef-83ea-662070bf8b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612346934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.612346934
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1213573342
Short name T982
Test name
Test status
Simulation time 75578213362 ps
CPU time 60.61 seconds
Started Mar 05 01:36:21 PM PST 24
Finished Mar 05 01:37:22 PM PST 24
Peak memory 200384 kb
Host smart-ec1e0b12-569b-4b17-933e-8c77bc893003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213573342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1213573342
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2579201160
Short name T200
Test name
Test status
Simulation time 112953539955 ps
CPU time 159.86 seconds
Started Mar 05 01:36:20 PM PST 24
Finished Mar 05 01:39:01 PM PST 24
Peak memory 200336 kb
Host smart-774e319d-74fa-4980-95a7-320b0765bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579201160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2579201160
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3319217446
Short name T626
Test name
Test status
Simulation time 49994025687 ps
CPU time 23.57 seconds
Started Mar 05 01:36:22 PM PST 24
Finished Mar 05 01:36:45 PM PST 24
Peak memory 198672 kb
Host smart-e24e35d0-3141-4fa0-99d6-bc187b00cef0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319217446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3319217446
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.412307883
Short name T829
Test name
Test status
Simulation time 141907755785 ps
CPU time 690.61 seconds
Started Mar 05 01:36:38 PM PST 24
Finished Mar 05 01:48:09 PM PST 24
Peak memory 200392 kb
Host smart-7e7c5a20-37c5-42d1-aefd-862e8686ea29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412307883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.412307883
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.352349198
Short name T525
Test name
Test status
Simulation time 5684027243 ps
CPU time 8.19 seconds
Started Mar 05 01:36:29 PM PST 24
Finished Mar 05 01:36:38 PM PST 24
Peak memory 200336 kb
Host smart-03dd9ef4-0c4b-4fdc-8f4c-1feb1ffcec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352349198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.352349198
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.749072581
Short name T565
Test name
Test status
Simulation time 4489354485 ps
CPU time 8.16 seconds
Started Mar 05 01:36:23 PM PST 24
Finished Mar 05 01:36:32 PM PST 24
Peak memory 194836 kb
Host smart-27a27b95-c52c-458f-87ac-96faecf1d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749072581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.749072581
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4177747491
Short name T822
Test name
Test status
Simulation time 4595151919 ps
CPU time 131.39 seconds
Started Mar 05 01:36:33 PM PST 24
Finished Mar 05 01:38:45 PM PST 24
Peak memory 200264 kb
Host smart-547e19b1-2632-4e78-bbf1-b29e17f9ff73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177747491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4177747491
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1694619201
Short name T1056
Test name
Test status
Simulation time 1690003760 ps
CPU time 2.69 seconds
Started Mar 05 01:36:23 PM PST 24
Finished Mar 05 01:36:26 PM PST 24
Peak memory 198080 kb
Host smart-9fd7f710-3954-4ffb-a50f-1bdbaff2e317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694619201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1694619201
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3174769402
Short name T938
Test name
Test status
Simulation time 13919829804 ps
CPU time 11.66 seconds
Started Mar 05 01:36:30 PM PST 24
Finished Mar 05 01:36:42 PM PST 24
Peak memory 198136 kb
Host smart-fb21fd3c-cc64-4a91-abd6-be0dd34cd03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174769402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3174769402
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.491936406
Short name T573
Test name
Test status
Simulation time 49421581276 ps
CPU time 20.28 seconds
Started Mar 05 01:36:30 PM PST 24
Finished Mar 05 01:36:51 PM PST 24
Peak memory 195844 kb
Host smart-c76cbeda-6f1a-4dee-9e2f-3d2cc0db85ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491936406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.491936406
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4146556972
Short name T477
Test name
Test status
Simulation time 270220512 ps
CPU time 1.06 seconds
Started Mar 05 01:36:17 PM PST 24
Finished Mar 05 01:36:19 PM PST 24
Peak memory 198516 kb
Host smart-a1030fdd-ea5b-47ba-90e3-4e85464446cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146556972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4146556972
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2671869744
Short name T788
Test name
Test status
Simulation time 211226332840 ps
CPU time 1448.94 seconds
Started Mar 05 01:36:40 PM PST 24
Finished Mar 05 02:00:49 PM PST 24
Peak memory 200420 kb
Host smart-10ee241d-8a27-4aa1-9162-9f3c1ac83e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671869744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2671869744
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3378368887
Short name T796
Test name
Test status
Simulation time 1085815763 ps
CPU time 1.33 seconds
Started Mar 05 01:36:34 PM PST 24
Finished Mar 05 01:36:35 PM PST 24
Peak memory 198152 kb
Host smart-3c84d4bc-6939-4dc6-a46d-bae791142f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378368887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3378368887
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3778711988
Short name T425
Test name
Test status
Simulation time 38695285135 ps
CPU time 64.71 seconds
Started Mar 05 01:36:21 PM PST 24
Finished Mar 05 01:37:26 PM PST 24
Peak memory 200416 kb
Host smart-cd8575f4-7e03-44b4-b60a-ff246c883195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778711988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3778711988
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1559194710
Short name T570
Test name
Test status
Simulation time 12174373 ps
CPU time 0.56 seconds
Started Mar 05 01:37:00 PM PST 24
Finished Mar 05 01:37:01 PM PST 24
Peak memory 194916 kb
Host smart-67457e3a-4fc7-4a56-986d-9e1c569cafd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559194710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1559194710
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2286914808
Short name T190
Test name
Test status
Simulation time 44858498581 ps
CPU time 14.68 seconds
Started Mar 05 01:36:43 PM PST 24
Finished Mar 05 01:36:59 PM PST 24
Peak memory 200384 kb
Host smart-a9585f7d-8aee-4671-a503-ee39592d570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286914808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2286914808
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3477321639
Short name T102
Test name
Test status
Simulation time 30592983914 ps
CPU time 50.77 seconds
Started Mar 05 01:36:43 PM PST 24
Finished Mar 05 01:37:35 PM PST 24
Peak memory 200356 kb
Host smart-0beb9de5-904c-45b9-a5e3-cdd14700163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477321639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3477321639
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3422840827
Short name T971
Test name
Test status
Simulation time 53881650378 ps
CPU time 46.19 seconds
Started Mar 05 01:36:47 PM PST 24
Finished Mar 05 01:37:33 PM PST 24
Peak memory 200368 kb
Host smart-ff361e93-1cad-449f-a5d5-ed41e1d07520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422840827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3422840827
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3574272452
Short name T756
Test name
Test status
Simulation time 2149061995077 ps
CPU time 693.89 seconds
Started Mar 05 01:36:53 PM PST 24
Finished Mar 05 01:48:29 PM PST 24
Peak memory 200404 kb
Host smart-8abb29b5-3002-414b-a81b-3d8cfa3e4380
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574272452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3574272452
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3203963312
Short name T113
Test name
Test status
Simulation time 70580040701 ps
CPU time 259.34 seconds
Started Mar 05 01:37:06 PM PST 24
Finished Mar 05 01:41:26 PM PST 24
Peak memory 200360 kb
Host smart-885f6eca-83e5-4da0-a8e0-0141f30be338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203963312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3203963312
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2436942671
Short name T907
Test name
Test status
Simulation time 601314561 ps
CPU time 1.64 seconds
Started Mar 05 01:36:55 PM PST 24
Finished Mar 05 01:36:57 PM PST 24
Peak memory 198632 kb
Host smart-62a25686-c4a5-441a-aa8c-d7bcefb08ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436942671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2436942671
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3591253310
Short name T919
Test name
Test status
Simulation time 48920733392 ps
CPU time 23.07 seconds
Started Mar 05 01:36:56 PM PST 24
Finished Mar 05 01:37:19 PM PST 24
Peak memory 199536 kb
Host smart-f70f2a61-8598-49a2-8d22-49852582a7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591253310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3591253310
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2747042367
Short name T1038
Test name
Test status
Simulation time 4364205580 ps
CPU time 57.83 seconds
Started Mar 05 01:36:53 PM PST 24
Finished Mar 05 01:37:53 PM PST 24
Peak memory 200352 kb
Host smart-ee4fb391-d6bb-4b8d-a591-9556fcc8ad17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747042367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2747042367
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1568314540
Short name T920
Test name
Test status
Simulation time 186002550484 ps
CPU time 20.69 seconds
Started Mar 05 01:36:57 PM PST 24
Finished Mar 05 01:37:17 PM PST 24
Peak memory 200308 kb
Host smart-0388abfd-c954-4085-ad17-bcf70d3796ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568314540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1568314540
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.4022253881
Short name T554
Test name
Test status
Simulation time 4141050745 ps
CPU time 7.55 seconds
Started Mar 05 01:36:54 PM PST 24
Finished Mar 05 01:37:03 PM PST 24
Peak memory 196176 kb
Host smart-f0fefa3e-0cff-4791-ab7c-35a199f4bb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022253881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4022253881
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1089532381
Short name T995
Test name
Test status
Simulation time 902825019 ps
CPU time 2.13 seconds
Started Mar 05 01:36:40 PM PST 24
Finished Mar 05 01:36:42 PM PST 24
Peak memory 198212 kb
Host smart-3641eaa4-e3f0-464f-aa67-ad9c0f1fcf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089532381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1089532381
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.80420320
Short name T366
Test name
Test status
Simulation time 174935336336 ps
CPU time 161.89 seconds
Started Mar 05 01:37:00 PM PST 24
Finished Mar 05 01:39:42 PM PST 24
Peak memory 200312 kb
Host smart-800f13a6-ad93-430a-83b3-fa4af8328799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80420320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.80420320
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.453149460
Short name T536
Test name
Test status
Simulation time 7952413796 ps
CPU time 4.7 seconds
Started Mar 05 01:36:55 PM PST 24
Finished Mar 05 01:37:00 PM PST 24
Peak memory 200056 kb
Host smart-b61c6870-e98f-4185-97b0-e8dd01248a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453149460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.453149460
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2701144578
Short name T532
Test name
Test status
Simulation time 48273853941 ps
CPU time 42.2 seconds
Started Mar 05 01:36:39 PM PST 24
Finished Mar 05 01:37:22 PM PST 24
Peak memory 200412 kb
Host smart-4faa1046-fc7f-450d-be05-ad3066069997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701144578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2701144578
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4031356765
Short name T900
Test name
Test status
Simulation time 72822034 ps
CPU time 0.59 seconds
Started Mar 05 01:33:24 PM PST 24
Finished Mar 05 01:33:25 PM PST 24
Peak memory 195932 kb
Host smart-505ec1d5-8a52-4270-adbc-4da3d7825c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031356765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4031356765
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.464310431
Short name T600
Test name
Test status
Simulation time 96299923518 ps
CPU time 176.37 seconds
Started Mar 05 01:33:11 PM PST 24
Finished Mar 05 01:36:08 PM PST 24
Peak memory 200344 kb
Host smart-bf8a8510-b59b-4017-8725-2b6ed46fe038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464310431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.464310431
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2488958664
Short name T1093
Test name
Test status
Simulation time 171305426412 ps
CPU time 759.47 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:45:56 PM PST 24
Peak memory 200380 kb
Host smart-55b903eb-8f21-480f-8e57-060f6a47feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488958664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2488958664
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3831868418
Short name T537
Test name
Test status
Simulation time 82974005843 ps
CPU time 47.56 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:34:01 PM PST 24
Peak memory 200428 kb
Host smart-4af0b47c-ffac-48a0-80aa-dc67959a9438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831868418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3831868418
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1833260838
Short name T868
Test name
Test status
Simulation time 13074254511 ps
CPU time 3.23 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:33:19 PM PST 24
Peak memory 196008 kb
Host smart-a9d9c39b-1437-4afc-a858-dc9cfa9015a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833260838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1833260838
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_loopback.3331047126
Short name T896
Test name
Test status
Simulation time 1678365871 ps
CPU time 5.94 seconds
Started Mar 05 01:33:12 PM PST 24
Finished Mar 05 01:33:18 PM PST 24
Peak memory 198268 kb
Host smart-f538c3a1-02c9-42e1-af74-b4b4fd722c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331047126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3331047126
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.875552103
Short name T913
Test name
Test status
Simulation time 103610868793 ps
CPU time 182.36 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:36:16 PM PST 24
Peak memory 197464 kb
Host smart-abda1f75-3f21-49b2-8b57-0c3c869f34b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875552103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.875552103
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1072402032
Short name T22
Test name
Test status
Simulation time 31170458045 ps
CPU time 461.63 seconds
Started Mar 05 01:33:21 PM PST 24
Finished Mar 05 01:41:03 PM PST 24
Peak memory 200408 kb
Host smart-8ac7c407-e7de-469e-b879-45a9880de11e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072402032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1072402032
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3638442171
Short name T613
Test name
Test status
Simulation time 1484162530 ps
CPU time 1.9 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:33:17 PM PST 24
Peak memory 198508 kb
Host smart-5511aac0-fe3f-4632-89af-f1653d1ec145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638442171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3638442171
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2410184190
Short name T636
Test name
Test status
Simulation time 53092595781 ps
CPU time 20.63 seconds
Started Mar 05 01:33:15 PM PST 24
Finished Mar 05 01:33:36 PM PST 24
Peak memory 200200 kb
Host smart-ba0c1c9f-250d-4508-bb00-9b08394da458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410184190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2410184190
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1797384559
Short name T555
Test name
Test status
Simulation time 1734052824 ps
CPU time 3.62 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:17 PM PST 24
Peak memory 195768 kb
Host smart-397f5853-0976-4a5f-a57e-a9c551b6a1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797384559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1797384559
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2835394961
Short name T35
Test name
Test status
Simulation time 70918804 ps
CPU time 0.88 seconds
Started Mar 05 01:33:27 PM PST 24
Finished Mar 05 01:33:28 PM PST 24
Peak memory 217956 kb
Host smart-c7b2a295-b73a-4474-bdba-2653176b9076
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835394961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2835394961
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2731544621
Short name T902
Test name
Test status
Simulation time 859315731 ps
CPU time 2.15 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:16 PM PST 24
Peak memory 198772 kb
Host smart-2c85e934-06e9-4fbf-baf3-f21f651b541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731544621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2731544621
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2100806515
Short name T654
Test name
Test status
Simulation time 80639935041 ps
CPU time 129.81 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:35:32 PM PST 24
Peak memory 200372 kb
Host smart-7f80834b-0c73-417f-a76d-2cdfc290d35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100806515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2100806515
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1556577404
Short name T870
Test name
Test status
Simulation time 6917850851 ps
CPU time 19.95 seconds
Started Mar 05 01:33:13 PM PST 24
Finished Mar 05 01:33:34 PM PST 24
Peak memory 200104 kb
Host smart-9428cf58-c5dd-410b-a08f-469c2978b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556577404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1556577404
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3482034217
Short name T967
Test name
Test status
Simulation time 14946286945 ps
CPU time 7.3 seconds
Started Mar 05 01:33:12 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 200260 kb
Host smart-6d0fa019-6616-4e2b-b396-97b49d2962e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482034217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3482034217
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3646361245
Short name T92
Test name
Test status
Simulation time 38818986 ps
CPU time 0.57 seconds
Started Mar 05 01:37:27 PM PST 24
Finished Mar 05 01:37:28 PM PST 24
Peak memory 195924 kb
Host smart-7f62d06d-2c50-4dca-8480-e0c9a210d8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646361245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3646361245
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.4175706937
Short name T1086
Test name
Test status
Simulation time 127183020302 ps
CPU time 58.72 seconds
Started Mar 05 01:37:02 PM PST 24
Finished Mar 05 01:38:01 PM PST 24
Peak memory 200348 kb
Host smart-cceda81b-c414-4288-90ad-11110adfa560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175706937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4175706937
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3944303567
Short name T588
Test name
Test status
Simulation time 47138548991 ps
CPU time 42.85 seconds
Started Mar 05 01:37:11 PM PST 24
Finished Mar 05 01:37:54 PM PST 24
Peak memory 200352 kb
Host smart-8ae7a9af-2991-4a37-a9ca-9d2687a62093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944303567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3944303567
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3923148250
Short name T298
Test name
Test status
Simulation time 113298972331 ps
CPU time 526.49 seconds
Started Mar 05 01:37:17 PM PST 24
Finished Mar 05 01:46:04 PM PST 24
Peak memory 200336 kb
Host smart-f043d695-d3ef-4ac9-88be-18184d4ea1f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923148250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3923148250
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.358755519
Short name T590
Test name
Test status
Simulation time 9075838161 ps
CPU time 5.33 seconds
Started Mar 05 01:37:18 PM PST 24
Finished Mar 05 01:37:24 PM PST 24
Peak memory 199424 kb
Host smart-b8aa1790-18d4-44be-b901-676fd134c056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358755519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.358755519
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1016723489
Short name T178
Test name
Test status
Simulation time 62015245522 ps
CPU time 125.13 seconds
Started Mar 05 01:37:13 PM PST 24
Finished Mar 05 01:39:19 PM PST 24
Peak memory 208740 kb
Host smart-afdca656-5035-465a-85ec-e56a8df14ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016723489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1016723489
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.515786806
Short name T97
Test name
Test status
Simulation time 17342499451 ps
CPU time 57.17 seconds
Started Mar 05 01:37:16 PM PST 24
Finished Mar 05 01:38:14 PM PST 24
Peak memory 200356 kb
Host smart-9ab21964-37b0-41e0-bbdf-3f557829313c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515786806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.515786806
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1774603978
Short name T755
Test name
Test status
Simulation time 118760881 ps
CPU time 0.97 seconds
Started Mar 05 01:37:10 PM PST 24
Finished Mar 05 01:37:11 PM PST 24
Peak memory 198028 kb
Host smart-2dbebcf8-e5f8-47b7-9108-9595566ede98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774603978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1774603978
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.373980546
Short name T377
Test name
Test status
Simulation time 177064132030 ps
CPU time 65.25 seconds
Started Mar 05 01:37:11 PM PST 24
Finished Mar 05 01:38:16 PM PST 24
Peak memory 200320 kb
Host smart-174c1294-58c0-49a4-840e-429cd0bdc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373980546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.373980546
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3057227361
Short name T1060
Test name
Test status
Simulation time 2881399136 ps
CPU time 1.9 seconds
Started Mar 05 01:37:16 PM PST 24
Finished Mar 05 01:37:18 PM PST 24
Peak memory 195872 kb
Host smart-4d3ce1ba-6757-4254-a577-eac0113a9278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057227361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3057227361
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3476575123
Short name T881
Test name
Test status
Simulation time 5539838985 ps
CPU time 11.45 seconds
Started Mar 05 01:37:03 PM PST 24
Finished Mar 05 01:37:14 PM PST 24
Peak memory 199888 kb
Host smart-fee22978-c440-42bf-991b-91b6ab7c7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476575123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3476575123
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3402823408
Short name T543
Test name
Test status
Simulation time 7329236403 ps
CPU time 9.2 seconds
Started Mar 05 01:37:18 PM PST 24
Finished Mar 05 01:37:27 PM PST 24
Peak memory 199916 kb
Host smart-67ea0ff3-e55a-45ea-af75-3841dcffe4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402823408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3402823408
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2563704993
Short name T117
Test name
Test status
Simulation time 117370280840 ps
CPU time 91.56 seconds
Started Mar 05 01:37:02 PM PST 24
Finished Mar 05 01:38:34 PM PST 24
Peak memory 200356 kb
Host smart-a63c192a-f704-49ba-b8d4-263efae20a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563704993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2563704993
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1097699843
Short name T717
Test name
Test status
Simulation time 81692658 ps
CPU time 0.57 seconds
Started Mar 05 01:37:39 PM PST 24
Finished Mar 05 01:37:40 PM PST 24
Peak memory 195964 kb
Host smart-80d7b98f-12c4-4f12-aca7-59be97b4d1d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097699843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1097699843
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2423620751
Short name T875
Test name
Test status
Simulation time 64585904412 ps
CPU time 19.82 seconds
Started Mar 05 01:37:25 PM PST 24
Finished Mar 05 01:37:45 PM PST 24
Peak memory 199976 kb
Host smart-473ead77-e97c-4860-9c92-8d2d63e13d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423620751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2423620751
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.386418128
Short name T1013
Test name
Test status
Simulation time 22647592267 ps
CPU time 37.22 seconds
Started Mar 05 01:37:25 PM PST 24
Finished Mar 05 01:38:03 PM PST 24
Peak memory 200356 kb
Host smart-bbee5db8-51a8-4dca-8353-3e8b2e784406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386418128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.386418128
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3884163313
Short name T1026
Test name
Test status
Simulation time 119707673617 ps
CPU time 342.48 seconds
Started Mar 05 01:37:37 PM PST 24
Finished Mar 05 01:43:20 PM PST 24
Peak memory 200316 kb
Host smart-118638b7-9097-4730-b1cf-e43aa5f19609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884163313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3884163313
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.426702116
Short name T1094
Test name
Test status
Simulation time 8465128547 ps
CPU time 10.75 seconds
Started Mar 05 01:37:36 PM PST 24
Finished Mar 05 01:37:47 PM PST 24
Peak memory 199060 kb
Host smart-77be04fd-798f-477c-a664-9bbe2bd31a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426702116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.426702116
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.492665034
Short name T1062
Test name
Test status
Simulation time 236197448348 ps
CPU time 102.71 seconds
Started Mar 05 01:37:29 PM PST 24
Finished Mar 05 01:39:12 PM PST 24
Peak memory 208772 kb
Host smart-196082b0-6f81-4170-9258-39c0ecb29704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492665034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.492665034
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1697245317
Short name T767
Test name
Test status
Simulation time 12784942882 ps
CPU time 758.29 seconds
Started Mar 05 01:37:35 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 200420 kb
Host smart-7a115888-4790-4866-bd85-c0a973286bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697245317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1697245317
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1023577885
Short name T931
Test name
Test status
Simulation time 3302462279 ps
CPU time 25.57 seconds
Started Mar 05 01:37:28 PM PST 24
Finished Mar 05 01:37:54 PM PST 24
Peak memory 198968 kb
Host smart-a662e263-b08b-49ba-85c9-e6e0998281f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023577885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1023577885
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3243572337
Short name T955
Test name
Test status
Simulation time 42126241164 ps
CPU time 18.86 seconds
Started Mar 05 01:37:30 PM PST 24
Finished Mar 05 01:37:51 PM PST 24
Peak memory 195988 kb
Host smart-a16ad526-cd63-4673-b382-7fd3229377b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243572337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3243572337
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3769167584
Short name T542
Test name
Test status
Simulation time 572576879 ps
CPU time 1.86 seconds
Started Mar 05 01:37:24 PM PST 24
Finished Mar 05 01:37:27 PM PST 24
Peak memory 198848 kb
Host smart-653dfea1-15ad-4f30-965c-65eeb9c1f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769167584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3769167584
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1540455599
Short name T748
Test name
Test status
Simulation time 159513717953 ps
CPU time 292.24 seconds
Started Mar 05 01:37:36 PM PST 24
Finished Mar 05 01:42:29 PM PST 24
Peak memory 200376 kb
Host smart-9cf80f20-0678-4732-accb-0f91bb3ecc85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540455599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1540455599
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1654017377
Short name T997
Test name
Test status
Simulation time 6873136402 ps
CPU time 10.72 seconds
Started Mar 05 01:37:36 PM PST 24
Finished Mar 05 01:37:47 PM PST 24
Peak memory 199916 kb
Host smart-2127b9e7-9f74-44a7-b63f-2c00ef75ef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654017377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1654017377
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.222054356
Short name T934
Test name
Test status
Simulation time 121711045710 ps
CPU time 19.82 seconds
Started Mar 05 01:37:27 PM PST 24
Finished Mar 05 01:37:47 PM PST 24
Peak memory 200400 kb
Host smart-34cd649c-bea8-4fdd-842d-f8f8a9cce4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222054356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.222054356
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2638381056
Short name T935
Test name
Test status
Simulation time 142772289 ps
CPU time 0.53 seconds
Started Mar 05 01:37:51 PM PST 24
Finished Mar 05 01:37:52 PM PST 24
Peak memory 194984 kb
Host smart-05b2b81f-deec-4304-bf46-3d136ea243d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638381056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2638381056
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.87143509
Short name T162
Test name
Test status
Simulation time 139781835720 ps
CPU time 124.22 seconds
Started Mar 05 01:37:45 PM PST 24
Finished Mar 05 01:39:51 PM PST 24
Peak memory 200404 kb
Host smart-4bc45b0c-58a1-4358-8f10-97bf32b9660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87143509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.87143509
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1389233759
Short name T987
Test name
Test status
Simulation time 141760842193 ps
CPU time 82.03 seconds
Started Mar 05 01:37:43 PM PST 24
Finished Mar 05 01:39:06 PM PST 24
Peak memory 200344 kb
Host smart-308cef18-208f-4db1-9f4b-d8b2048b44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389233759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1389233759
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.809416499
Short name T784
Test name
Test status
Simulation time 79961204054 ps
CPU time 32.22 seconds
Started Mar 05 01:37:42 PM PST 24
Finished Mar 05 01:38:15 PM PST 24
Peak memory 200344 kb
Host smart-dfe2dd58-84eb-4154-9f53-cc1cde6407aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809416499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.809416499
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1761780411
Short name T916
Test name
Test status
Simulation time 227418833260 ps
CPU time 100.84 seconds
Started Mar 05 01:37:44 PM PST 24
Finished Mar 05 01:39:27 PM PST 24
Peak memory 200408 kb
Host smart-9bee9a7f-a288-48e8-8efe-1a3c3b0a8fb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761780411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1761780411
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1178463225
Short name T578
Test name
Test status
Simulation time 37335135028 ps
CPU time 69.27 seconds
Started Mar 05 01:37:52 PM PST 24
Finished Mar 05 01:39:02 PM PST 24
Peak memory 200360 kb
Host smart-d5bb1350-5b7f-4a9a-b32c-07e625036a00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178463225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1178463225
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.287628782
Short name T456
Test name
Test status
Simulation time 7122099200 ps
CPU time 19.4 seconds
Started Mar 05 01:37:50 PM PST 24
Finished Mar 05 01:38:10 PM PST 24
Peak memory 198984 kb
Host smart-5c6779b2-bd93-49f4-b6ac-465898aeb177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287628782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.287628782
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2318788959
Short name T633
Test name
Test status
Simulation time 21253831520 ps
CPU time 19.26 seconds
Started Mar 05 01:37:51 PM PST 24
Finished Mar 05 01:38:12 PM PST 24
Peak memory 198784 kb
Host smart-a56c5eeb-7280-472a-b30b-7945db889ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318788959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2318788959
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1138224992
Short name T488
Test name
Test status
Simulation time 2934251322 ps
CPU time 33.64 seconds
Started Mar 05 01:37:45 PM PST 24
Finished Mar 05 01:38:20 PM PST 24
Peak memory 198908 kb
Host smart-e00cf125-426e-487e-b03f-43749eb81a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138224992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1138224992
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1488604941
Short name T773
Test name
Test status
Simulation time 186156501977 ps
CPU time 22.66 seconds
Started Mar 05 01:37:43 PM PST 24
Finished Mar 05 01:38:07 PM PST 24
Peak memory 199592 kb
Host smart-4f44757d-04db-44f3-9800-67cd66c2c5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488604941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1488604941
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3583390848
Short name T712
Test name
Test status
Simulation time 5805592542 ps
CPU time 9.57 seconds
Started Mar 05 01:37:51 PM PST 24
Finished Mar 05 01:38:01 PM PST 24
Peak memory 196144 kb
Host smart-00f34bee-11fe-4156-843b-093ad733fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583390848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3583390848
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.427884785
Short name T629
Test name
Test status
Simulation time 5477402126 ps
CPU time 12.6 seconds
Started Mar 05 01:37:38 PM PST 24
Finished Mar 05 01:37:51 PM PST 24
Peak memory 199712 kb
Host smart-89478f7c-8209-40ff-b093-dcb18bf37570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427884785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.427884785
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3259555624
Short name T591
Test name
Test status
Simulation time 778100285 ps
CPU time 2.38 seconds
Started Mar 05 01:37:49 PM PST 24
Finished Mar 05 01:37:52 PM PST 24
Peak memory 199608 kb
Host smart-39b00f20-6a77-4dbf-be9a-1bd7d4d206f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259555624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3259555624
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.46317995
Short name T564
Test name
Test status
Simulation time 43841134778 ps
CPU time 25.29 seconds
Started Mar 05 01:37:43 PM PST 24
Finished Mar 05 01:38:09 PM PST 24
Peak memory 200328 kb
Host smart-e95c04c1-ef75-4ccf-9e8a-9862bb6bad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46317995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.46317995
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3640608577
Short name T914
Test name
Test status
Simulation time 13543352 ps
CPU time 0.6 seconds
Started Mar 05 01:38:03 PM PST 24
Finished Mar 05 01:38:04 PM PST 24
Peak memory 195940 kb
Host smart-db1de5fb-5300-4bc2-8443-632964f4963c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640608577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3640608577
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3620252916
Short name T497
Test name
Test status
Simulation time 22686529524 ps
CPU time 21.4 seconds
Started Mar 05 01:37:57 PM PST 24
Finished Mar 05 01:38:18 PM PST 24
Peak memory 200400 kb
Host smart-3114ee75-c655-41ee-8f39-32ab2c97ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620252916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3620252916
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3081085632
Short name T250
Test name
Test status
Simulation time 83150396719 ps
CPU time 32.19 seconds
Started Mar 05 01:38:02 PM PST 24
Finished Mar 05 01:38:35 PM PST 24
Peak memory 200424 kb
Host smart-2c6547f0-73ee-403d-a573-9aaa3b48ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081085632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3081085632
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2902072846
Short name T493
Test name
Test status
Simulation time 129492661967 ps
CPU time 23.13 seconds
Started Mar 05 01:37:56 PM PST 24
Finished Mar 05 01:38:20 PM PST 24
Peak memory 200300 kb
Host smart-2a529e18-c08d-4183-8539-8749f85c0f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902072846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2902072846
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2184978152
Short name T592
Test name
Test status
Simulation time 108908875327 ps
CPU time 14.97 seconds
Started Mar 05 01:37:58 PM PST 24
Finished Mar 05 01:38:13 PM PST 24
Peak memory 200136 kb
Host smart-8dfa9c5d-c1cc-4cc0-a5f2-68541b7b2e1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184978152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2184978152
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.649906167
Short name T572
Test name
Test status
Simulation time 101333292517 ps
CPU time 813.06 seconds
Started Mar 05 01:38:05 PM PST 24
Finished Mar 05 01:51:39 PM PST 24
Peak memory 200336 kb
Host smart-a129be9d-8cc6-4b66-805a-b6351e10b40a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649906167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.649906167
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.396915884
Short name T455
Test name
Test status
Simulation time 8160048605 ps
CPU time 16.21 seconds
Started Mar 05 01:38:04 PM PST 24
Finished Mar 05 01:38:22 PM PST 24
Peak memory 198096 kb
Host smart-5a54d332-34c7-4027-9c63-875530cf7ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396915884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.396915884
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2631678753
Short name T709
Test name
Test status
Simulation time 239890073250 ps
CPU time 75.86 seconds
Started Mar 05 01:37:59 PM PST 24
Finished Mar 05 01:39:15 PM PST 24
Peak memory 200500 kb
Host smart-28f35356-6b38-468f-88e3-e3e28783c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631678753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2631678753
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.4080699168
Short name T804
Test name
Test status
Simulation time 19718008749 ps
CPU time 283.91 seconds
Started Mar 05 01:38:08 PM PST 24
Finished Mar 05 01:42:54 PM PST 24
Peak memory 200316 kb
Host smart-f82aafdc-a142-4c22-96b2-56c4e34ed1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080699168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4080699168
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1540514696
Short name T650
Test name
Test status
Simulation time 1738265782 ps
CPU time 4.79 seconds
Started Mar 05 01:37:56 PM PST 24
Finished Mar 05 01:38:01 PM PST 24
Peak memory 198392 kb
Host smart-a6a1654d-3f7c-47fc-b875-e3c19b1e9590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540514696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1540514696
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1611127670
Short name T559
Test name
Test status
Simulation time 193585146101 ps
CPU time 86.21 seconds
Started Mar 05 01:38:03 PM PST 24
Finished Mar 05 01:39:30 PM PST 24
Peak memory 200260 kb
Host smart-58ee6bd3-eb50-4e4c-9619-8c5089f31b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611127670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1611127670
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.513864594
Short name T869
Test name
Test status
Simulation time 6056954531 ps
CPU time 5.71 seconds
Started Mar 05 01:37:59 PM PST 24
Finished Mar 05 01:38:05 PM PST 24
Peak memory 196136 kb
Host smart-fc482b3c-c37c-4981-b683-f2d02b80b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513864594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.513864594
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2790864685
Short name T845
Test name
Test status
Simulation time 873734963 ps
CPU time 1.33 seconds
Started Mar 05 01:37:59 PM PST 24
Finished Mar 05 01:38:00 PM PST 24
Peak memory 198768 kb
Host smart-4aceb9af-a67f-4d32-a9b2-59596aebe7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790864685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2790864685
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2821078728
Short name T1076
Test name
Test status
Simulation time 1013340206 ps
CPU time 3.53 seconds
Started Mar 05 01:38:01 PM PST 24
Finished Mar 05 01:38:05 PM PST 24
Peak memory 198420 kb
Host smart-6bf93057-4b30-44ca-ba37-eb814bf445ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821078728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2821078728
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4222159177
Short name T1019
Test name
Test status
Simulation time 94410047385 ps
CPU time 51.58 seconds
Started Mar 05 01:38:00 PM PST 24
Finished Mar 05 01:38:51 PM PST 24
Peak memory 200384 kb
Host smart-e0b29715-ad08-4ef6-aeba-be7a2c62ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222159177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4222159177
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2114657
Short name T958
Test name
Test status
Simulation time 20916894 ps
CPU time 0.57 seconds
Started Mar 05 01:38:25 PM PST 24
Finished Mar 05 01:38:26 PM PST 24
Peak memory 194984 kb
Host smart-1210a0f0-7ab4-4674-8b3f-fbb7eac39671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2114657
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1061264501
Short name T664
Test name
Test status
Simulation time 133775940907 ps
CPU time 27.15 seconds
Started Mar 05 01:38:11 PM PST 24
Finished Mar 05 01:38:38 PM PST 24
Peak memory 200344 kb
Host smart-a24d9e2a-abd9-47fe-83a7-41cb7ee24474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061264501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1061264501
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1740368836
Short name T522
Test name
Test status
Simulation time 22044266500 ps
CPU time 37.99 seconds
Started Mar 05 01:38:10 PM PST 24
Finished Mar 05 01:38:48 PM PST 24
Peak memory 200336 kb
Host smart-9fe9ae9d-6025-4171-83e6-51ccb5e62080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740368836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1740368836
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1174145111
Short name T395
Test name
Test status
Simulation time 279758647593 ps
CPU time 103.85 seconds
Started Mar 05 01:38:14 PM PST 24
Finished Mar 05 01:39:58 PM PST 24
Peak memory 199784 kb
Host smart-ec214fb2-0e1b-4fca-8783-e2275bb1869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174145111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1174145111
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1538546155
Short name T1043
Test name
Test status
Simulation time 20452236275 ps
CPU time 9.46 seconds
Started Mar 05 01:38:13 PM PST 24
Finished Mar 05 01:38:23 PM PST 24
Peak memory 199848 kb
Host smart-645b5cba-e718-490b-87b8-c7ff96dbadf6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538546155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1538546155
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.974419979
Short name T386
Test name
Test status
Simulation time 68030138249 ps
CPU time 115.82 seconds
Started Mar 05 01:38:25 PM PST 24
Finished Mar 05 01:40:21 PM PST 24
Peak memory 200432 kb
Host smart-a34fcff3-4414-494a-b560-b2b6edce49b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974419979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.974419979
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2664296147
Short name T461
Test name
Test status
Simulation time 4934648321 ps
CPU time 10.43 seconds
Started Mar 05 01:38:20 PM PST 24
Finished Mar 05 01:38:30 PM PST 24
Peak memory 198764 kb
Host smart-fd8af691-88e0-41e5-9d44-a95865173acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664296147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2664296147
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2512039789
Short name T988
Test name
Test status
Simulation time 438594868900 ps
CPU time 113.8 seconds
Started Mar 05 01:38:19 PM PST 24
Finished Mar 05 01:40:13 PM PST 24
Peak memory 208560 kb
Host smart-f6b406cf-e4fd-4f90-a9cb-75b856c58c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512039789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2512039789
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.938662913
Short name T249
Test name
Test status
Simulation time 21425763430 ps
CPU time 318.77 seconds
Started Mar 05 01:38:20 PM PST 24
Finished Mar 05 01:43:39 PM PST 24
Peak memory 200384 kb
Host smart-9ba03f53-4173-45a7-9142-c3f01d1331d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938662913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.938662913
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3028030493
Short name T466
Test name
Test status
Simulation time 783909901 ps
CPU time 2.1 seconds
Started Mar 05 01:38:18 PM PST 24
Finished Mar 05 01:38:21 PM PST 24
Peak memory 198500 kb
Host smart-392651d1-b251-4fc1-bdca-1b211bf9f662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028030493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3028030493
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.997069601
Short name T369
Test name
Test status
Simulation time 64058790416 ps
CPU time 37.16 seconds
Started Mar 05 01:38:18 PM PST 24
Finished Mar 05 01:38:55 PM PST 24
Peak memory 200272 kb
Host smart-ee5ed89a-e44b-4f54-aa88-cb27d7c390f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997069601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.997069601
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1170932660
Short name T949
Test name
Test status
Simulation time 38841633342 ps
CPU time 17.61 seconds
Started Mar 05 01:38:18 PM PST 24
Finished Mar 05 01:38:36 PM PST 24
Peak memory 195792 kb
Host smart-55e70308-88c2-4304-bf47-3656040d6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170932660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1170932660
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.390042384
Short name T858
Test name
Test status
Simulation time 6230235390 ps
CPU time 19.18 seconds
Started Mar 05 01:38:03 PM PST 24
Finished Mar 05 01:38:23 PM PST 24
Peak memory 199668 kb
Host smart-61ba3c2b-79f0-43a8-a6db-c53534aaef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390042384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.390042384
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1995692982
Short name T888
Test name
Test status
Simulation time 341119400656 ps
CPU time 1558.09 seconds
Started Mar 05 01:38:24 PM PST 24
Finished Mar 05 02:04:23 PM PST 24
Peak memory 200580 kb
Host smart-14ec1135-4013-4146-8bb7-087ac7c3c1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995692982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1995692982
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2094583526
Short name T1050
Test name
Test status
Simulation time 1643599058 ps
CPU time 1.51 seconds
Started Mar 05 01:38:17 PM PST 24
Finished Mar 05 01:38:19 PM PST 24
Peak memory 198632 kb
Host smart-85bf2491-b912-4d67-8169-3df025bd97e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094583526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2094583526
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.908341421
Short name T943
Test name
Test status
Simulation time 16921603810 ps
CPU time 32.45 seconds
Started Mar 05 01:38:04 PM PST 24
Finished Mar 05 01:38:38 PM PST 24
Peak memory 200332 kb
Host smart-753053c1-ec69-4d38-aabb-ce5a99665665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908341421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.908341421
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1086515034
Short name T1028
Test name
Test status
Simulation time 88874810 ps
CPU time 0.56 seconds
Started Mar 05 01:38:49 PM PST 24
Finished Mar 05 01:38:49 PM PST 24
Peak memory 195024 kb
Host smart-fa35875f-151e-4eba-9d02-1b314d987bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086515034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1086515034
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.779207412
Short name T874
Test name
Test status
Simulation time 143651719514 ps
CPU time 34.04 seconds
Started Mar 05 01:38:34 PM PST 24
Finished Mar 05 01:39:09 PM PST 24
Peak memory 200352 kb
Host smart-caa7a185-1a68-4ae4-bd24-e082fded3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779207412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.779207412
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1991855420
Short name T893
Test name
Test status
Simulation time 54640598198 ps
CPU time 104.15 seconds
Started Mar 05 01:38:33 PM PST 24
Finished Mar 05 01:40:17 PM PST 24
Peak memory 200272 kb
Host smart-62d98188-f57d-4d9f-9ef8-0e14ba8f8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991855420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1991855420
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.575216309
Short name T921
Test name
Test status
Simulation time 34072690641 ps
CPU time 17.22 seconds
Started Mar 05 01:38:32 PM PST 24
Finished Mar 05 01:38:50 PM PST 24
Peak memory 200236 kb
Host smart-58ffe0b6-1c19-46fb-b3f2-fc974e73a11e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575216309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.575216309
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.765045612
Short name T517
Test name
Test status
Simulation time 77974604110 ps
CPU time 239.11 seconds
Started Mar 05 01:38:45 PM PST 24
Finished Mar 05 01:42:45 PM PST 24
Peak memory 200324 kb
Host smart-f1dd255e-640b-4aff-af51-a992496a8e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765045612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.765045612
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.334391015
Short name T1010
Test name
Test status
Simulation time 9527688165 ps
CPU time 12 seconds
Started Mar 05 01:38:52 PM PST 24
Finished Mar 05 01:39:04 PM PST 24
Peak memory 198892 kb
Host smart-3090b2b5-123d-4157-8490-6fabfa0832ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334391015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.334391015
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2458168918
Short name T743
Test name
Test status
Simulation time 242463849941 ps
CPU time 52.2 seconds
Started Mar 05 01:38:51 PM PST 24
Finished Mar 05 01:39:44 PM PST 24
Peak memory 200484 kb
Host smart-0a8b7bde-cce8-4995-9cd0-5bb7bab134a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458168918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2458168918
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2166266377
Short name T895
Test name
Test status
Simulation time 22586088479 ps
CPU time 145.88 seconds
Started Mar 05 01:38:46 PM PST 24
Finished Mar 05 01:41:12 PM PST 24
Peak memory 200324 kb
Host smart-6bf7d866-6b6d-4c7c-bd3e-7f7b24ad6a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166266377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2166266377
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1850928775
Short name T1036
Test name
Test status
Simulation time 136371123622 ps
CPU time 210.24 seconds
Started Mar 05 01:38:42 PM PST 24
Finished Mar 05 01:42:12 PM PST 24
Peak memory 200392 kb
Host smart-bb14a62d-41b0-4d1b-9634-f75193d9cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850928775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1850928775
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3607526496
Short name T728
Test name
Test status
Simulation time 46304971678 ps
CPU time 62.69 seconds
Started Mar 05 01:38:41 PM PST 24
Finished Mar 05 01:39:44 PM PST 24
Peak memory 195728 kb
Host smart-c54e3ec7-e97f-4423-abd9-472bb1775b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607526496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3607526496
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3076395442
Short name T487
Test name
Test status
Simulation time 5546603847 ps
CPU time 26.1 seconds
Started Mar 05 01:38:25 PM PST 24
Finished Mar 05 01:38:51 PM PST 24
Peak memory 199752 kb
Host smart-91506e15-0aa9-4b08-8fe3-745bf508106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076395442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3076395442
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2303259655
Short name T792
Test name
Test status
Simulation time 3300495273163 ps
CPU time 1356.52 seconds
Started Mar 05 01:38:51 PM PST 24
Finished Mar 05 02:01:28 PM PST 24
Peak memory 208828 kb
Host smart-22205f26-dc4d-45e8-87a7-58cb2eaf9c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303259655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2303259655
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2094554273
Short name T105
Test name
Test status
Simulation time 67429381600 ps
CPU time 190.15 seconds
Started Mar 05 01:38:50 PM PST 24
Finished Mar 05 01:42:00 PM PST 24
Peak memory 217160 kb
Host smart-563660a7-1090-4100-8703-edd97d3c22ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094554273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2094554273
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3619213797
Short name T429
Test name
Test status
Simulation time 821091077 ps
CPU time 2.67 seconds
Started Mar 05 01:38:40 PM PST 24
Finished Mar 05 01:38:43 PM PST 24
Peak memory 198288 kb
Host smart-d26f8f94-7dbd-407a-b20e-a4257695fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619213797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3619213797
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1318780798
Short name T824
Test name
Test status
Simulation time 36549101954 ps
CPU time 68.4 seconds
Started Mar 05 01:38:24 PM PST 24
Finished Mar 05 01:39:32 PM PST 24
Peak memory 200344 kb
Host smart-9d6cf9f5-b78d-45c2-b9ca-5ec1e903c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318780798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1318780798
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3073411468
Short name T620
Test name
Test status
Simulation time 54020163 ps
CPU time 0.57 seconds
Started Mar 05 01:38:55 PM PST 24
Finished Mar 05 01:38:57 PM PST 24
Peak memory 195972 kb
Host smart-87b60b13-afad-4500-86c7-fb6dc6530e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073411468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3073411468
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4230625389
Short name T308
Test name
Test status
Simulation time 73393950294 ps
CPU time 113.01 seconds
Started Mar 05 01:38:46 PM PST 24
Finished Mar 05 01:40:39 PM PST 24
Peak memory 200200 kb
Host smart-a696ec9d-8487-43b2-8db2-fc9b77559c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230625389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4230625389
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1597650157
Short name T331
Test name
Test status
Simulation time 189591419516 ps
CPU time 343.07 seconds
Started Mar 05 01:38:50 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 200328 kb
Host smart-b906fad4-556f-48af-8bf6-c1882b5bda33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597650157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1597650157
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.631412708
Short name T936
Test name
Test status
Simulation time 39608550460 ps
CPU time 7.77 seconds
Started Mar 05 01:38:50 PM PST 24
Finished Mar 05 01:38:58 PM PST 24
Peak memory 200396 kb
Host smart-37f4dfdd-6ec8-41d6-9640-0d62e211930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631412708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.631412708
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.372955699
Short name T1067
Test name
Test status
Simulation time 369030387928 ps
CPU time 508.36 seconds
Started Mar 05 01:38:51 PM PST 24
Finished Mar 05 01:47:19 PM PST 24
Peak memory 200296 kb
Host smart-bdd69788-02f5-408e-a5c4-535cf705031e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372955699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.372955699
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3574936080
Short name T496
Test name
Test status
Simulation time 305761339379 ps
CPU time 100.41 seconds
Started Mar 05 01:39:04 PM PST 24
Finished Mar 05 01:40:44 PM PST 24
Peak memory 200404 kb
Host smart-360810fc-104d-4dd0-b115-be941d09e242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574936080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3574936080
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3702240704
Short name T642
Test name
Test status
Simulation time 10818237058 ps
CPU time 22.87 seconds
Started Mar 05 01:38:58 PM PST 24
Finished Mar 05 01:39:21 PM PST 24
Peak memory 199656 kb
Host smart-a432a270-79c0-4134-96f0-239a5f3c3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702240704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3702240704
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1376165037
Short name T422
Test name
Test status
Simulation time 177554628970 ps
CPU time 87.64 seconds
Started Mar 05 01:38:49 PM PST 24
Finished Mar 05 01:40:17 PM PST 24
Peak memory 199492 kb
Host smart-28068c4f-2b99-4f77-8b4f-5fe415f086e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376165037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1376165037
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.992981283
Short name T611
Test name
Test status
Simulation time 23291155610 ps
CPU time 560.23 seconds
Started Mar 05 01:38:56 PM PST 24
Finished Mar 05 01:48:17 PM PST 24
Peak memory 200328 kb
Host smart-986f186c-8218-45d7-a9e2-642248ed4043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992981283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.992981283
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2608827370
Short name T313
Test name
Test status
Simulation time 47272067255 ps
CPU time 66.46 seconds
Started Mar 05 01:38:55 PM PST 24
Finished Mar 05 01:40:03 PM PST 24
Peak memory 199680 kb
Host smart-7ac94922-140e-41ec-b076-f4627a2316dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608827370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2608827370
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1874731243
Short name T392
Test name
Test status
Simulation time 46316703712 ps
CPU time 19.64 seconds
Started Mar 05 01:38:52 PM PST 24
Finished Mar 05 01:39:13 PM PST 24
Peak memory 196120 kb
Host smart-457679ff-4f78-469e-a8b0-4aae9a6fafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874731243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1874731243
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.97194633
Short name T1008
Test name
Test status
Simulation time 97736428 ps
CPU time 0.76 seconds
Started Mar 05 01:38:48 PM PST 24
Finished Mar 05 01:38:49 PM PST 24
Peak memory 196868 kb
Host smart-2402bbd1-7bbd-437a-9d71-b7753275dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97194633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.97194633
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.4030306552
Short name T911
Test name
Test status
Simulation time 400706299696 ps
CPU time 578.51 seconds
Started Mar 05 01:38:54 PM PST 24
Finished Mar 05 01:48:35 PM PST 24
Peak memory 216524 kb
Host smart-feeaf501-a278-44fb-90f7-812c40716f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030306552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4030306552
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.971001742
Short name T62
Test name
Test status
Simulation time 276119671128 ps
CPU time 495.15 seconds
Started Mar 05 01:38:57 PM PST 24
Finished Mar 05 01:47:12 PM PST 24
Peak memory 217132 kb
Host smart-90ea3951-cf1b-4f34-9336-895a69e82ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971001742 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.971001742
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.190831462
Short name T945
Test name
Test status
Simulation time 6898100241 ps
CPU time 12.13 seconds
Started Mar 05 01:38:54 PM PST 24
Finished Mar 05 01:39:08 PM PST 24
Peak memory 199932 kb
Host smart-eb334578-c883-4141-9075-e5605b094fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190831462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.190831462
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.4232971100
Short name T1092
Test name
Test status
Simulation time 24907810107 ps
CPU time 57.52 seconds
Started Mar 05 01:38:50 PM PST 24
Finished Mar 05 01:39:47 PM PST 24
Peak memory 200388 kb
Host smart-28e7043b-f243-4128-b111-7e2e7d4e531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232971100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.4232971100
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1578833461
Short name T1070
Test name
Test status
Simulation time 397699755241 ps
CPU time 42.99 seconds
Started Mar 05 01:39:03 PM PST 24
Finished Mar 05 01:39:46 PM PST 24
Peak memory 200388 kb
Host smart-b9f077cb-11a8-4d29-8433-da3f89406aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578833461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1578833461
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2549848864
Short name T410
Test name
Test status
Simulation time 144161317653 ps
CPU time 23.5 seconds
Started Mar 05 01:39:04 PM PST 24
Finished Mar 05 01:39:28 PM PST 24
Peak memory 200412 kb
Host smart-822b6709-c97d-44e5-892a-77b760c82b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549848864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2549848864
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2668729906
Short name T962
Test name
Test status
Simulation time 171170242431 ps
CPU time 193.24 seconds
Started Mar 05 01:39:11 PM PST 24
Finished Mar 05 01:42:25 PM PST 24
Peak memory 200348 kb
Host smart-df1c5f12-5ac8-40d9-8f52-bcbed48da87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668729906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2668729906
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.470248996
Short name T479
Test name
Test status
Simulation time 382754208 ps
CPU time 1.2 seconds
Started Mar 05 01:39:19 PM PST 24
Finished Mar 05 01:39:23 PM PST 24
Peak memory 197500 kb
Host smart-318b5122-4723-4478-95ee-79cf846b5a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470248996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.470248996
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.195652480
Short name T733
Test name
Test status
Simulation time 240672940018 ps
CPU time 84.28 seconds
Started Mar 05 01:39:03 PM PST 24
Finished Mar 05 01:40:28 PM PST 24
Peak memory 200816 kb
Host smart-5afcaa26-8e9e-4881-8312-95c254709693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195652480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.195652480
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1544294330
Short name T248
Test name
Test status
Simulation time 7630605938 ps
CPU time 369.9 seconds
Started Mar 05 01:39:08 PM PST 24
Finished Mar 05 01:45:19 PM PST 24
Peak memory 200440 kb
Host smart-dcaabf7a-05a8-4a1a-8794-640a0644bfa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544294330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1544294330
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4243229254
Short name T14
Test name
Test status
Simulation time 3377923063 ps
CPU time 17.93 seconds
Started Mar 05 01:39:04 PM PST 24
Finished Mar 05 01:39:22 PM PST 24
Peak memory 198724 kb
Host smart-6d32c046-bdda-473b-8a5e-75fa002aad44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243229254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4243229254
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3105691732
Short name T45
Test name
Test status
Simulation time 21760400359 ps
CPU time 29.51 seconds
Started Mar 05 01:39:09 PM PST 24
Finished Mar 05 01:39:38 PM PST 24
Peak memory 198148 kb
Host smart-073ce6a1-96ac-4045-8a94-fe6d7f99b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105691732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3105691732
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1621244760
Short name T838
Test name
Test status
Simulation time 4007717492 ps
CPU time 5.14 seconds
Started Mar 05 01:39:05 PM PST 24
Finished Mar 05 01:39:13 PM PST 24
Peak memory 196244 kb
Host smart-90028253-fb29-4470-afe5-a58ae2c1c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621244760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1621244760
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3998338678
Short name T439
Test name
Test status
Simulation time 671639763 ps
CPU time 3.1 seconds
Started Mar 05 01:38:56 PM PST 24
Finished Mar 05 01:39:00 PM PST 24
Peak memory 198796 kb
Host smart-2e83ba6c-d894-4b90-bb2a-dcbe04451557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998338678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3998338678
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1254167140
Short name T177
Test name
Test status
Simulation time 147681493558 ps
CPU time 334.46 seconds
Started Mar 05 01:39:09 PM PST 24
Finished Mar 05 01:44:44 PM PST 24
Peak memory 200376 kb
Host smart-ddbe9ca9-dc82-4e55-af6d-39962a0969cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254167140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1254167140
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.4152249276
Short name T440
Test name
Test status
Simulation time 47610646300 ps
CPU time 138.5 seconds
Started Mar 05 01:39:11 PM PST 24
Finished Mar 05 01:41:30 PM PST 24
Peak memory 216096 kb
Host smart-94310255-4f60-4aea-9f9b-7382f397278c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152249276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4152249276
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3857070882
Short name T910
Test name
Test status
Simulation time 2830015072 ps
CPU time 1.91 seconds
Started Mar 05 01:39:06 PM PST 24
Finished Mar 05 01:39:10 PM PST 24
Peak memory 198448 kb
Host smart-ea8d11de-a3a3-496d-974a-879f20bd0371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857070882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3857070882
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4180395457
Short name T691
Test name
Test status
Simulation time 112974062803 ps
CPU time 47.54 seconds
Started Mar 05 01:38:59 PM PST 24
Finished Mar 05 01:39:47 PM PST 24
Peak memory 200300 kb
Host smart-bcd9b18c-1624-4d42-a86e-bed902597396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180395457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4180395457
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3133935619
Short name T841
Test name
Test status
Simulation time 37608904 ps
CPU time 0.6 seconds
Started Mar 05 01:39:32 PM PST 24
Finished Mar 05 01:39:34 PM PST 24
Peak memory 195840 kb
Host smart-a65260fc-98a2-4d15-82be-23c14be3d024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133935619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3133935619
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2393342078
Short name T766
Test name
Test status
Simulation time 33668788245 ps
CPU time 55.25 seconds
Started Mar 05 01:39:20 PM PST 24
Finished Mar 05 01:40:17 PM PST 24
Peak memory 200380 kb
Host smart-bb1e0c9f-bdac-4018-95a9-3be3f73b5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393342078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2393342078
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2935518869
Short name T367
Test name
Test status
Simulation time 58258011452 ps
CPU time 13.66 seconds
Started Mar 05 01:39:18 PM PST 24
Finished Mar 05 01:39:35 PM PST 24
Peak memory 200336 kb
Host smart-545006a8-3c32-43ae-bd2d-6ee2b20db510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935518869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2935518869
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3109012950
Short name T734
Test name
Test status
Simulation time 44870084761 ps
CPU time 17.9 seconds
Started Mar 05 01:39:19 PM PST 24
Finished Mar 05 01:39:40 PM PST 24
Peak memory 199212 kb
Host smart-a34192a4-c421-4c3a-a867-ee508df0e8b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109012950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3109012950
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_loopback.1181530805
Short name T674
Test name
Test status
Simulation time 7806680565 ps
CPU time 11.48 seconds
Started Mar 05 01:39:33 PM PST 24
Finished Mar 05 01:39:45 PM PST 24
Peak memory 199476 kb
Host smart-df6aa11b-a574-4996-bea5-ddee487dc290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181530805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1181530805
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1001286807
Short name T680
Test name
Test status
Simulation time 49106591127 ps
CPU time 23.14 seconds
Started Mar 05 01:39:20 PM PST 24
Finished Mar 05 01:39:45 PM PST 24
Peak memory 198088 kb
Host smart-cb72566f-31f2-42fa-87df-88b887dc468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001286807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1001286807
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3009472565
Short name T408
Test name
Test status
Simulation time 15349494469 ps
CPU time 856.86 seconds
Started Mar 05 01:39:25 PM PST 24
Finished Mar 05 01:53:44 PM PST 24
Peak memory 200416 kb
Host smart-b19b6d22-b9a6-4f07-9857-f549ce4c8ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009472565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3009472565
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1401198204
Short name T700
Test name
Test status
Simulation time 714417002 ps
CPU time 5.49 seconds
Started Mar 05 01:39:18 PM PST 24
Finished Mar 05 01:39:26 PM PST 24
Peak memory 198464 kb
Host smart-b848b403-7582-46b1-949a-37931d06fe93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401198204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1401198204
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2028448440
Short name T128
Test name
Test status
Simulation time 266573892496 ps
CPU time 203.84 seconds
Started Mar 05 01:39:27 PM PST 24
Finished Mar 05 01:42:51 PM PST 24
Peak memory 200048 kb
Host smart-5c581399-d6bc-4264-a3c9-5b9e56d6d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028448440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2028448440
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1847424509
Short name T760
Test name
Test status
Simulation time 42995862312 ps
CPU time 16.02 seconds
Started Mar 05 01:39:25 PM PST 24
Finished Mar 05 01:39:43 PM PST 24
Peak memory 195952 kb
Host smart-51dea671-300c-43dd-9706-a9366e770234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847424509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1847424509
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2575154388
Short name T758
Test name
Test status
Simulation time 527396897 ps
CPU time 1.29 seconds
Started Mar 05 01:39:16 PM PST 24
Finished Mar 05 01:39:20 PM PST 24
Peak memory 199328 kb
Host smart-78a7eead-fdc0-4e83-adc8-7f4c98980840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575154388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2575154388
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2090844635
Short name T149
Test name
Test status
Simulation time 680704659711 ps
CPU time 513.92 seconds
Started Mar 05 01:39:24 PM PST 24
Finished Mar 05 01:48:00 PM PST 24
Peak memory 208740 kb
Host smart-463e60b0-3dcc-4e9a-a6d1-402953e915f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090844635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2090844635
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.609191449
Short name T111
Test name
Test status
Simulation time 6389656999 ps
CPU time 13.82 seconds
Started Mar 05 01:39:24 PM PST 24
Finished Mar 05 01:39:40 PM PST 24
Peak memory 199920 kb
Host smart-462168d2-7ee4-4d9a-93e7-7de25d54e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609191449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.609191449
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2901767122
Short name T747
Test name
Test status
Simulation time 127086697358 ps
CPU time 57.81 seconds
Started Mar 05 01:39:16 PM PST 24
Finished Mar 05 01:40:15 PM PST 24
Peak memory 200412 kb
Host smart-598d1573-4609-4f06-96dd-935e1dec6f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901767122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2901767122
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.737795456
Short name T1037
Test name
Test status
Simulation time 14644916 ps
CPU time 0.57 seconds
Started Mar 05 01:39:40 PM PST 24
Finished Mar 05 01:39:41 PM PST 24
Peak memory 195884 kb
Host smart-51f42cd0-ae3e-4784-825a-da8792a244a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737795456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.737795456
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4242249994
Short name T352
Test name
Test status
Simulation time 139034496270 ps
CPU time 62.1 seconds
Started Mar 05 01:39:29 PM PST 24
Finished Mar 05 01:40:31 PM PST 24
Peak memory 200400 kb
Host smart-b00d34ef-3688-4ba4-8163-f5871a574583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242249994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4242249994
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1281082047
Short name T272
Test name
Test status
Simulation time 161389606739 ps
CPU time 251.52 seconds
Started Mar 05 01:39:33 PM PST 24
Finished Mar 05 01:43:45 PM PST 24
Peak memory 200368 kb
Host smart-b189fb01-e58a-4acb-9af2-cacdf0c70da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281082047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1281082047
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2829715882
Short name T116
Test name
Test status
Simulation time 30070632618 ps
CPU time 47.44 seconds
Started Mar 05 01:39:31 PM PST 24
Finished Mar 05 01:40:21 PM PST 24
Peak memory 199988 kb
Host smart-ca7d7ad9-1579-4d33-84de-2eece3d90da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829715882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2829715882
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2801417185
Short name T653
Test name
Test status
Simulation time 14034032812 ps
CPU time 22.81 seconds
Started Mar 05 01:39:30 PM PST 24
Finished Mar 05 01:39:53 PM PST 24
Peak memory 199852 kb
Host smart-6c5020f9-a555-46c4-bc2f-28ef178dd541
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801417185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2801417185
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3278892053
Short name T802
Test name
Test status
Simulation time 69767845638 ps
CPU time 346.84 seconds
Started Mar 05 01:39:39 PM PST 24
Finished Mar 05 01:45:27 PM PST 24
Peak memory 200332 kb
Host smart-8d99e375-0242-4225-ae41-2cc76ff0a382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278892053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3278892053
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.948103101
Short name T509
Test name
Test status
Simulation time 5010815872 ps
CPU time 3.71 seconds
Started Mar 05 01:39:39 PM PST 24
Finished Mar 05 01:39:42 PM PST 24
Peak memory 198612 kb
Host smart-77b6f45a-cf53-4787-9684-6f35c94f4b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948103101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.948103101
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2733501557
Short name T134
Test name
Test status
Simulation time 174991633139 ps
CPU time 77.59 seconds
Started Mar 05 01:39:37 PM PST 24
Finished Mar 05 01:40:54 PM PST 24
Peak memory 200200 kb
Host smart-6e464b82-2bed-4d03-baa6-96062ca1496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733501557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2733501557
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.217654244
Short name T385
Test name
Test status
Simulation time 15521278045 ps
CPU time 145.24 seconds
Started Mar 05 01:39:41 PM PST 24
Finished Mar 05 01:42:07 PM PST 24
Peak memory 200440 kb
Host smart-0f013135-d378-4a87-ac21-fbcaf3dcbfc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217654244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.217654244
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.217398663
Short name T1071
Test name
Test status
Simulation time 159245075 ps
CPU time 0.69 seconds
Started Mar 05 01:39:33 PM PST 24
Finished Mar 05 01:39:34 PM PST 24
Peak memory 195836 kb
Host smart-ffa373f9-aa59-4661-b8bf-5cbaea1a601c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217398663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.217398663
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2550982934
Short name T347
Test name
Test status
Simulation time 38464121506 ps
CPU time 18.52 seconds
Started Mar 05 01:39:42 PM PST 24
Finished Mar 05 01:40:01 PM PST 24
Peak memory 200204 kb
Host smart-b185c1c6-4385-4f3a-918e-5b1e37860726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550982934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2550982934
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.153118226
Short name T1057
Test name
Test status
Simulation time 4256625990 ps
CPU time 6.59 seconds
Started Mar 05 01:39:32 PM PST 24
Finished Mar 05 01:39:40 PM PST 24
Peak memory 196192 kb
Host smart-211af433-02d0-4495-8768-a1f876a13942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153118226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.153118226
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1017016759
Short name T740
Test name
Test status
Simulation time 5893350784 ps
CPU time 24.87 seconds
Started Mar 05 01:39:32 PM PST 24
Finished Mar 05 01:39:58 PM PST 24
Peak memory 199460 kb
Host smart-9bb9d04c-ba9e-499b-80f7-b3c4cc5f32fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017016759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1017016759
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2382351715
Short name T562
Test name
Test status
Simulation time 36891698964 ps
CPU time 85.67 seconds
Started Mar 05 01:39:42 PM PST 24
Finished Mar 05 01:41:08 PM PST 24
Peak memory 200328 kb
Host smart-33a86307-4994-4a3d-bd52-fd32e37bdcf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382351715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2382351715
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2363892828
Short name T544
Test name
Test status
Simulation time 1111304967 ps
CPU time 4.21 seconds
Started Mar 05 01:39:43 PM PST 24
Finished Mar 05 01:39:48 PM PST 24
Peak memory 198920 kb
Host smart-b9b40607-c1d3-4315-ad87-08b327ce8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363892828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2363892828
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1300296948
Short name T146
Test name
Test status
Simulation time 83077477263 ps
CPU time 83.88 seconds
Started Mar 05 01:39:32 PM PST 24
Finished Mar 05 01:40:57 PM PST 24
Peak memory 200320 kb
Host smart-78697621-d509-4ab4-ad8c-ddfa867be8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300296948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1300296948
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.997036419
Short name T649
Test name
Test status
Simulation time 42181129 ps
CPU time 0.58 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 195932 kb
Host smart-03d5604c-ead3-4972-9b29-b34ae00bbe1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997036419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.997036419
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1352286856
Short name T865
Test name
Test status
Simulation time 145822826136 ps
CPU time 246.71 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:37:28 PM PST 24
Peak memory 200348 kb
Host smart-ba7c8bb8-bfee-4c3c-a2f8-4df37f1c56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352286856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1352286856
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.2449088222
Short name T719
Test name
Test status
Simulation time 1113900015691 ps
CPU time 527.68 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:42:09 PM PST 24
Peak memory 200272 kb
Host smart-d7c7ca7c-2683-4783-af89-262ee3780826
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449088222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2449088222
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1068028789
Short name T1054
Test name
Test status
Simulation time 145413491009 ps
CPU time 385.82 seconds
Started Mar 05 01:33:23 PM PST 24
Finished Mar 05 01:39:49 PM PST 24
Peak memory 200344 kb
Host smart-705333a6-1a0a-4b1e-8b84-a00d66bc8204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068028789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1068028789
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2736671356
Short name T1
Test name
Test status
Simulation time 65456447 ps
CPU time 0.64 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:33:21 PM PST 24
Peak memory 195712 kb
Host smart-1212b853-1e14-443d-9738-1551c2bd5ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736671356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2736671356
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.547708423
Short name T126
Test name
Test status
Simulation time 127648599929 ps
CPU time 140.95 seconds
Started Mar 05 01:33:19 PM PST 24
Finished Mar 05 01:35:41 PM PST 24
Peak memory 208772 kb
Host smart-4a04cd50-db3c-4507-9f23-8d4c4742008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547708423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.547708423
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3972362324
Short name T842
Test name
Test status
Simulation time 3876496226 ps
CPU time 225.21 seconds
Started Mar 05 01:33:23 PM PST 24
Finished Mar 05 01:37:08 PM PST 24
Peak memory 200356 kb
Host smart-8ace089d-ddc4-4725-a95e-fe6178ecedb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972362324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3972362324
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.4168186244
Short name T1000
Test name
Test status
Simulation time 3403214665 ps
CPU time 35 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:33:55 PM PST 24
Peak memory 199260 kb
Host smart-3ea8e860-68a7-4114-9e82-bd7d419d1c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168186244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4168186244
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.93294270
Short name T884
Test name
Test status
Simulation time 37608524018 ps
CPU time 55.02 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:34:17 PM PST 24
Peak memory 200396 kb
Host smart-1f24a638-3529-4ed3-9a49-0a04b4dd1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93294270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.93294270
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2003102423
Short name T462
Test name
Test status
Simulation time 29625362438 ps
CPU time 13.31 seconds
Started Mar 05 01:33:23 PM PST 24
Finished Mar 05 01:33:36 PM PST 24
Peak memory 196136 kb
Host smart-4e882f9c-4832-47e3-887f-0f8ac83937fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003102423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2003102423
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3206539452
Short name T1035
Test name
Test status
Simulation time 667687505 ps
CPU time 2.52 seconds
Started Mar 05 01:33:24 PM PST 24
Finished Mar 05 01:33:27 PM PST 24
Peak memory 199248 kb
Host smart-4965ec09-a57c-42c4-98ee-7f68b3daf30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206539452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3206539452
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3293728864
Short name T722
Test name
Test status
Simulation time 67067438477 ps
CPU time 28.76 seconds
Started Mar 05 01:33:19 PM PST 24
Finished Mar 05 01:33:49 PM PST 24
Peak memory 200588 kb
Host smart-447c18fb-16cc-4ef6-8bd0-830704f478f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293728864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3293728864
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2880066343
Short name T418
Test name
Test status
Simulation time 993311569 ps
CPU time 2.41 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:33:25 PM PST 24
Peak memory 198436 kb
Host smart-e80c83de-84ea-47f1-9690-a583742048b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880066343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2880066343
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2994886888
Short name T775
Test name
Test status
Simulation time 171230069794 ps
CPU time 149.54 seconds
Started Mar 05 01:33:23 PM PST 24
Finished Mar 05 01:35:53 PM PST 24
Peak memory 200412 kb
Host smart-602c510e-b726-4ef8-8d1e-ec18182c5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994886888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2994886888
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3102516216
Short name T276
Test name
Test status
Simulation time 18910624744 ps
CPU time 16.61 seconds
Started Mar 05 01:39:41 PM PST 24
Finished Mar 05 01:39:58 PM PST 24
Peak memory 200192 kb
Host smart-bddf40e3-57c5-4feb-9859-f1e6c6219928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102516216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3102516216
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3599460372
Short name T1033
Test name
Test status
Simulation time 148106588502 ps
CPU time 825.94 seconds
Started Mar 05 01:39:46 PM PST 24
Finished Mar 05 01:53:32 PM PST 24
Peak memory 217120 kb
Host smart-26cfa720-f923-4e71-899a-a3944d4f4068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599460372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3599460372
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3774131209
Short name T403
Test name
Test status
Simulation time 53766519572 ps
CPU time 19.48 seconds
Started Mar 05 01:39:58 PM PST 24
Finished Mar 05 01:40:23 PM PST 24
Peak memory 200076 kb
Host smart-667c1955-2b8a-4277-9d92-e784e168ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774131209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3774131209
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3899094522
Short name T883
Test name
Test status
Simulation time 79657872148 ps
CPU time 83.77 seconds
Started Mar 05 01:39:57 PM PST 24
Finished Mar 05 01:41:26 PM PST 24
Peak memory 200288 kb
Host smart-df6fbdf3-eb3b-40d2-b750-31a1861b6e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899094522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3899094522
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2601702706
Short name T260
Test name
Test status
Simulation time 8088458450 ps
CPU time 13.76 seconds
Started Mar 05 01:39:55 PM PST 24
Finished Mar 05 01:40:13 PM PST 24
Peak memory 200332 kb
Host smart-29755f29-5381-4577-a6e7-8b716e152126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601702706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2601702706
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.415716437
Short name T420
Test name
Test status
Simulation time 27499642157 ps
CPU time 46.29 seconds
Started Mar 05 01:39:56 PM PST 24
Finished Mar 05 01:40:46 PM PST 24
Peak memory 200364 kb
Host smart-11290385-3026-4fb5-bf5c-c9ac1232d343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415716437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.415716437
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1929589592
Short name T360
Test name
Test status
Simulation time 49768459946 ps
CPU time 76.93 seconds
Started Mar 05 01:39:58 PM PST 24
Finished Mar 05 01:41:20 PM PST 24
Peak memory 200360 kb
Host smart-8034952b-3d21-4a1f-9f1f-34ac9d3227e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929589592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1929589592
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3406380698
Short name T258
Test name
Test status
Simulation time 18324170740 ps
CPU time 14.61 seconds
Started Mar 05 01:39:54 PM PST 24
Finished Mar 05 01:40:11 PM PST 24
Peak memory 199828 kb
Host smart-7593659e-397d-4f63-86cd-07ee20bcdbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406380698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3406380698
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.753519465
Short name T1079
Test name
Test status
Simulation time 7619290315 ps
CPU time 14.25 seconds
Started Mar 05 01:40:02 PM PST 24
Finished Mar 05 01:40:19 PM PST 24
Peak memory 200128 kb
Host smart-d0e4bf46-60cc-4767-aedd-d4600baea639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753519465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.753519465
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1891959137
Short name T571
Test name
Test status
Simulation time 46347025768 ps
CPU time 517.68 seconds
Started Mar 05 01:39:59 PM PST 24
Finished Mar 05 01:48:41 PM PST 24
Peak memory 215768 kb
Host smart-a7f13192-849c-4f59-aa17-a67605363757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891959137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1891959137
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1022217113
Short name T196
Test name
Test status
Simulation time 187617246746 ps
CPU time 323.55 seconds
Started Mar 05 01:40:00 PM PST 24
Finished Mar 05 01:45:27 PM PST 24
Peak memory 200132 kb
Host smart-df70317b-f18d-44d2-a731-0024814a4562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022217113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1022217113
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3766646097
Short name T110
Test name
Test status
Simulation time 143452423298 ps
CPU time 317.74 seconds
Started Mar 05 01:39:57 PM PST 24
Finished Mar 05 01:45:20 PM PST 24
Peak memory 209840 kb
Host smart-7140395a-d905-4661-b7b6-3f9707d75fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766646097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3766646097
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2863500842
Short name T186
Test name
Test status
Simulation time 7812437493 ps
CPU time 14.93 seconds
Started Mar 05 01:40:02 PM PST 24
Finished Mar 05 01:40:19 PM PST 24
Peak memory 199940 kb
Host smart-770ebf62-d171-4bbf-be1f-c533891e1e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863500842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2863500842
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3570010445
Short name T219
Test name
Test status
Simulation time 196007906669 ps
CPU time 790.6 seconds
Started Mar 05 01:40:15 PM PST 24
Finished Mar 05 01:53:25 PM PST 24
Peak memory 216960 kb
Host smart-64783298-b4e0-4f06-a22f-3a1530c9d5a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570010445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3570010445
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3544302166
Short name T601
Test name
Test status
Simulation time 40360869 ps
CPU time 0.56 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:33:29 PM PST 24
Peak memory 194920 kb
Host smart-f2286f32-d9b5-4449-86a8-8e63508d224c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544302166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3544302166
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2744981519
Short name T1046
Test name
Test status
Simulation time 28473269581 ps
CPU time 36.54 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:33:59 PM PST 24
Peak memory 200416 kb
Host smart-9c7fe3aa-f6e0-4e68-ab6b-ecc8b1886bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744981519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2744981519
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_intr.1084147817
Short name T507
Test name
Test status
Simulation time 22624897105 ps
CPU time 9.87 seconds
Started Mar 05 01:33:20 PM PST 24
Finished Mar 05 01:33:30 PM PST 24
Peak memory 196836 kb
Host smart-23ad7d3e-c060-44ab-9c17-ac8609c77fda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084147817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1084147817
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3832285262
Short name T769
Test name
Test status
Simulation time 146194719893 ps
CPU time 117.23 seconds
Started Mar 05 01:33:28 PM PST 24
Finished Mar 05 01:35:25 PM PST 24
Peak memory 200304 kb
Host smart-f65b4382-e791-49d2-8a64-6600f137ff72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832285262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3832285262
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3890516755
Short name T513
Test name
Test status
Simulation time 6148523998 ps
CPU time 10.16 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:33:39 PM PST 24
Peak memory 198516 kb
Host smart-abcd227a-e4fe-48d1-b63a-f96fb31fad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890516755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3890516755
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3126466447
Short name T673
Test name
Test status
Simulation time 92330319655 ps
CPU time 98.47 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:35:01 PM PST 24
Peak memory 200152 kb
Host smart-9806af90-de86-441a-b40f-1bd741e87bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126466447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3126466447
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.903043512
Short name T853
Test name
Test status
Simulation time 12478149628 ps
CPU time 634.66 seconds
Started Mar 05 01:33:28 PM PST 24
Finished Mar 05 01:44:03 PM PST 24
Peak memory 200324 kb
Host smart-68d3bf7b-ee22-4803-b53d-b23146f16e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903043512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.903043512
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1985793038
Short name T847
Test name
Test status
Simulation time 149046242138 ps
CPU time 232.83 seconds
Started Mar 05 01:33:21 PM PST 24
Finished Mar 05 01:37:14 PM PST 24
Peak memory 200356 kb
Host smart-5257bee9-3c48-4bf0-8bef-3a3e3eaa15a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985793038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1985793038
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.69534703
Short name T4
Test name
Test status
Simulation time 4111872875 ps
CPU time 1.83 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:33:24 PM PST 24
Peak memory 196196 kb
Host smart-ec7c91ab-260f-4e6c-8e77-486b8e0de7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69534703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.69534703
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1318631997
Short name T729
Test name
Test status
Simulation time 449210713 ps
CPU time 1.51 seconds
Started Mar 05 01:33:22 PM PST 24
Finished Mar 05 01:33:24 PM PST 24
Peak memory 198228 kb
Host smart-3f015065-4af4-4ae5-ae91-1eef55362fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318631997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1318631997
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2341672346
Short name T251
Test name
Test status
Simulation time 350087480283 ps
CPU time 280.23 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:38:10 PM PST 24
Peak memory 200372 kb
Host smart-2036de65-765b-4c27-8fc3-da14907396c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341672346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2341672346
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.400815087
Short name T560
Test name
Test status
Simulation time 4188839664 ps
CPU time 2.26 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:33:32 PM PST 24
Peak memory 198752 kb
Host smart-01896041-5478-4649-88a7-fb4aa2f6afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400815087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.400815087
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4190452659
Short name T387
Test name
Test status
Simulation time 327513694602 ps
CPU time 108.11 seconds
Started Mar 05 01:33:21 PM PST 24
Finished Mar 05 01:35:10 PM PST 24
Peak memory 200268 kb
Host smart-71c3760e-435d-4a3a-b9ac-e981e1045db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190452659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4190452659
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2635058736
Short name T1015
Test name
Test status
Simulation time 139720426128 ps
CPU time 23.15 seconds
Started Mar 05 01:40:08 PM PST 24
Finished Mar 05 01:40:31 PM PST 24
Peak memory 200356 kb
Host smart-dbc8c917-cb38-46a7-aaa4-f1ad05bf455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635058736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2635058736
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2312432495
Short name T104
Test name
Test status
Simulation time 22974204143 ps
CPU time 165.07 seconds
Started Mar 05 01:40:07 PM PST 24
Finished Mar 05 01:42:52 PM PST 24
Peak memory 208800 kb
Host smart-8b4d0a2d-f179-4866-bcb4-216597bd5267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312432495 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2312432495
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1972909773
Short name T141
Test name
Test status
Simulation time 29502725171 ps
CPU time 52.24 seconds
Started Mar 05 01:40:04 PM PST 24
Finished Mar 05 01:40:58 PM PST 24
Peak memory 200464 kb
Host smart-89cd33af-6809-4392-a68e-6e1a32223688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972909773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1972909773
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1637171099
Short name T61
Test name
Test status
Simulation time 143972058800 ps
CPU time 1130.51 seconds
Started Mar 05 01:40:05 PM PST 24
Finished Mar 05 01:58:57 PM PST 24
Peak memory 216648 kb
Host smart-8831b2c0-7a93-4b86-9e63-a3ae81f785b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637171099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1637171099
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2407487375
Short name T701
Test name
Test status
Simulation time 10536568733 ps
CPU time 18.62 seconds
Started Mar 05 01:40:04 PM PST 24
Finished Mar 05 01:40:24 PM PST 24
Peak memory 200368 kb
Host smart-245dc813-b33a-401f-b219-49b24aecad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407487375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2407487375
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3102272303
Short name T107
Test name
Test status
Simulation time 65611849228 ps
CPU time 507.49 seconds
Started Mar 05 01:40:08 PM PST 24
Finished Mar 05 01:48:36 PM PST 24
Peak memory 215132 kb
Host smart-54a8c0f1-c78d-4d6e-ad0e-cd7f27d607d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102272303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3102272303
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2489935547
Short name T207
Test name
Test status
Simulation time 38796646890 ps
CPU time 20.66 seconds
Started Mar 05 01:40:11 PM PST 24
Finished Mar 05 01:40:31 PM PST 24
Peak memory 200344 kb
Host smart-e259f2b8-44c2-48aa-a797-72abf4f21f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489935547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2489935547
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2892707049
Short name T137
Test name
Test status
Simulation time 111471266155 ps
CPU time 189.94 seconds
Started Mar 05 01:40:11 PM PST 24
Finished Mar 05 01:43:21 PM PST 24
Peak memory 200352 kb
Host smart-713d83e2-6acb-4ba8-8a33-73a5d2862204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892707049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2892707049
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1425079131
Short name T158
Test name
Test status
Simulation time 8516584400 ps
CPU time 12.82 seconds
Started Mar 05 01:40:10 PM PST 24
Finished Mar 05 01:40:24 PM PST 24
Peak memory 200336 kb
Host smart-c235528d-edce-4d49-ade0-4537e07658eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425079131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1425079131
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1781673249
Short name T63
Test name
Test status
Simulation time 18444879579 ps
CPU time 153.4 seconds
Started Mar 05 01:40:14 PM PST 24
Finished Mar 05 01:42:48 PM PST 24
Peak memory 209076 kb
Host smart-8256f355-571e-4dcf-949a-2f1a7a0a4a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781673249 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1781673249
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2166682717
Short name T774
Test name
Test status
Simulation time 5966997315 ps
CPU time 10.74 seconds
Started Mar 05 01:40:17 PM PST 24
Finished Mar 05 01:40:28 PM PST 24
Peak memory 197900 kb
Host smart-05fcac22-1b34-4b3d-b36d-f451c495aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166682717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2166682717
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2330485255
Short name T1009
Test name
Test status
Simulation time 15079912 ps
CPU time 0.57 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:33:36 PM PST 24
Peak memory 195960 kb
Host smart-fcf51d96-b6a3-4385-9813-a8cdf65beee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330485255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2330485255
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.168346153
Short name T783
Test name
Test status
Simulation time 18721417466 ps
CPU time 29.82 seconds
Started Mar 05 01:33:30 PM PST 24
Finished Mar 05 01:34:00 PM PST 24
Peak memory 200328 kb
Host smart-a2968558-9168-471f-b116-ee6dd1076305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168346153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.168346153
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1055144329
Short name T667
Test name
Test status
Simulation time 33354423476 ps
CPU time 60.52 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:34:30 PM PST 24
Peak memory 200320 kb
Host smart-00f6bef0-b82c-4d75-a6f7-502680b3fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055144329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1055144329
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4189596074
Short name T355
Test name
Test status
Simulation time 137544321900 ps
CPU time 14.79 seconds
Started Mar 05 01:33:30 PM PST 24
Finished Mar 05 01:33:45 PM PST 24
Peak memory 200048 kb
Host smart-80b62387-a06f-4683-b6ea-afa9ebf9a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189596074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4189596074
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2944753256
Short name T644
Test name
Test status
Simulation time 245222937591 ps
CPU time 205.87 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:37:02 PM PST 24
Peak memory 200344 kb
Host smart-ff9b6aa5-8368-4841-a825-a9b0200028cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944753256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2944753256
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1673328463
Short name T53
Test name
Test status
Simulation time 4698743658 ps
CPU time 9.17 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:33:38 PM PST 24
Peak memory 197784 kb
Host smart-bffb3ba7-c246-49d3-a1e8-54199cdee278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673328463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1673328463
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.1747312290
Short name T645
Test name
Test status
Simulation time 19345098603 ps
CPU time 1045.99 seconds
Started Mar 05 01:33:29 PM PST 24
Finished Mar 05 01:50:55 PM PST 24
Peak memory 200412 kb
Host smart-d2ddd860-213f-4223-85c9-e7088fedcd6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747312290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1747312290
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3286521986
Short name T580
Test name
Test status
Simulation time 4610831370 ps
CPU time 10.38 seconds
Started Mar 05 01:33:27 PM PST 24
Finished Mar 05 01:33:38 PM PST 24
Peak memory 198728 kb
Host smart-d1ec82b4-0cb4-422b-9695-1d31bfe47cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286521986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3286521986
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3102853842
Short name T383
Test name
Test status
Simulation time 198881855509 ps
CPU time 412.75 seconds
Started Mar 05 01:33:30 PM PST 24
Finished Mar 05 01:40:23 PM PST 24
Peak memory 200360 kb
Host smart-579eac4a-6c48-41ed-972a-20c7e7aeb04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102853842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3102853842
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.911551318
Short name T528
Test name
Test status
Simulation time 34439085464 ps
CPU time 42.08 seconds
Started Mar 05 01:33:30 PM PST 24
Finished Mar 05 01:34:12 PM PST 24
Peak memory 196176 kb
Host smart-22598a44-0d5e-4801-ab40-2f5597dd4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911551318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.911551318
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2448629033
Short name T584
Test name
Test status
Simulation time 444656040 ps
CPU time 1.83 seconds
Started Mar 05 01:33:28 PM PST 24
Finished Mar 05 01:33:30 PM PST 24
Peak memory 198204 kb
Host smart-6d458c13-5e5e-4d1f-8a16-f10881c2e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448629033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2448629033
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1576420238
Short name T980
Test name
Test status
Simulation time 774318662 ps
CPU time 1.65 seconds
Started Mar 05 01:33:31 PM PST 24
Finished Mar 05 01:33:33 PM PST 24
Peak memory 198728 kb
Host smart-2fae8225-d13d-4e99-ad3b-07b8ba0cf4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576420238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1576420238
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2140890734
Short name T538
Test name
Test status
Simulation time 98670679489 ps
CPU time 49.27 seconds
Started Mar 05 01:33:30 PM PST 24
Finished Mar 05 01:34:19 PM PST 24
Peak memory 200356 kb
Host smart-ebc61c0a-d861-4f8e-9350-19bfde4c6b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140890734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2140890734
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.550846147
Short name T223
Test name
Test status
Simulation time 28334113226 ps
CPU time 59.39 seconds
Started Mar 05 01:40:18 PM PST 24
Finished Mar 05 01:41:17 PM PST 24
Peak memory 200360 kb
Host smart-b326f4c7-cd0c-43a8-8b04-706487a5f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550846147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.550846147
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1407205679
Short name T108
Test name
Test status
Simulation time 173585365190 ps
CPU time 824.11 seconds
Started Mar 05 01:40:18 PM PST 24
Finished Mar 05 01:54:02 PM PST 24
Peak memory 216592 kb
Host smart-e602b670-a141-4961-8c78-08a3bd5e7c65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407205679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1407205679
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1463086919
Short name T732
Test name
Test status
Simulation time 140595031012 ps
CPU time 248.13 seconds
Started Mar 05 01:40:30 PM PST 24
Finished Mar 05 01:44:38 PM PST 24
Peak memory 200368 kb
Host smart-7924f4a2-5761-4eae-98f1-f500ab087add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463086919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1463086919
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3832480013
Short name T139
Test name
Test status
Simulation time 31921120251 ps
CPU time 12.45 seconds
Started Mar 05 01:40:33 PM PST 24
Finished Mar 05 01:40:46 PM PST 24
Peak memory 200340 kb
Host smart-00d5c65b-ce7e-43cc-b168-23235fd2361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832480013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3832480013
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.656850123
Short name T193
Test name
Test status
Simulation time 99733915207 ps
CPU time 37.17 seconds
Started Mar 05 01:40:34 PM PST 24
Finished Mar 05 01:41:11 PM PST 24
Peak memory 200332 kb
Host smart-1f50b3b9-9d23-4ee4-ac58-1c539e8d928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656850123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.656850123
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3315790395
Short name T59
Test name
Test status
Simulation time 26207737029 ps
CPU time 51.3 seconds
Started Mar 05 01:40:38 PM PST 24
Finished Mar 05 01:41:29 PM PST 24
Peak memory 200144 kb
Host smart-d66539ac-ac11-4451-8135-1df534703ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315790395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3315790395
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2424452298
Short name T940
Test name
Test status
Simulation time 78440582626 ps
CPU time 165.27 seconds
Started Mar 05 01:40:32 PM PST 24
Finished Mar 05 01:43:18 PM PST 24
Peak memory 208728 kb
Host smart-b3786818-9091-4056-8eb9-b77852b6071b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424452298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2424452298
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.342636542
Short name T213
Test name
Test status
Simulation time 75892182137 ps
CPU time 114.86 seconds
Started Mar 05 01:40:37 PM PST 24
Finished Mar 05 01:42:32 PM PST 24
Peak memory 200364 kb
Host smart-443e9734-627c-40d3-99a0-0c2cc245116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342636542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.342636542
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.930947979
Short name T447
Test name
Test status
Simulation time 14763597645 ps
CPU time 27.47 seconds
Started Mar 05 01:40:50 PM PST 24
Finished Mar 05 01:41:18 PM PST 24
Peak memory 200388 kb
Host smart-d0486496-b1ac-412b-ac1e-9ab992d7e225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930947979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.930947979
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2724152675
Short name T122
Test name
Test status
Simulation time 13694903590 ps
CPU time 8.25 seconds
Started Mar 05 01:40:48 PM PST 24
Finished Mar 05 01:40:57 PM PST 24
Peak memory 199932 kb
Host smart-1368d9db-c1cc-43b5-8950-853bb180eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724152675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2724152675
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.659790725
Short name T335
Test name
Test status
Simulation time 18791829084 ps
CPU time 15.8 seconds
Started Mar 05 01:40:51 PM PST 24
Finished Mar 05 01:41:07 PM PST 24
Peak memory 200336 kb
Host smart-a2b84656-15d5-46c5-8961-e5f893b4445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659790725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.659790725
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1770834726
Short name T194
Test name
Test status
Simulation time 114715945177 ps
CPU time 26.34 seconds
Started Mar 05 01:40:52 PM PST 24
Finished Mar 05 01:41:19 PM PST 24
Peak memory 200324 kb
Host smart-96c4e6a1-0834-4e73-ba3b-b0b883c6520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770834726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1770834726
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3549171626
Short name T484
Test name
Test status
Simulation time 12788727 ps
CPU time 0.57 seconds
Started Mar 05 01:33:37 PM PST 24
Finished Mar 05 01:33:37 PM PST 24
Peak memory 195892 kb
Host smart-741da31a-994f-4853-b721-61bd238a7cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549171626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3549171626
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3647186505
Short name T772
Test name
Test status
Simulation time 111862688215 ps
CPU time 186.77 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:36:43 PM PST 24
Peak memory 200360 kb
Host smart-a09090db-5d3c-42ed-ab41-2dabc97fa36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647186505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3647186505
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1794952348
Short name T928
Test name
Test status
Simulation time 32105539106 ps
CPU time 25.11 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:04 PM PST 24
Peak memory 200344 kb
Host smart-c1bdf979-98b5-4875-beeb-9727bc992764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794952348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1794952348
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_intr.1331211723
Short name T932
Test name
Test status
Simulation time 30279624304 ps
CPU time 5.23 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:33:43 PM PST 24
Peak memory 197504 kb
Host smart-dd3f994a-19cd-4895-b314-68e5bbc14e25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331211723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1331211723
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.1620160807
Short name T500
Test name
Test status
Simulation time 1744917263 ps
CPU time 3.95 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:33:39 PM PST 24
Peak memory 198216 kb
Host smart-adcd3551-c24d-4edd-be4d-2380cc8bcb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620160807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1620160807
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2208273362
Short name T909
Test name
Test status
Simulation time 43404232457 ps
CPU time 79.27 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:34:55 PM PST 24
Peak memory 199188 kb
Host smart-68bfb768-7373-4ea2-bb9f-e231ecd16984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208273362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2208273362
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3488600242
Short name T634
Test name
Test status
Simulation time 10463718291 ps
CPU time 277.69 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:38:14 PM PST 24
Peak memory 200384 kb
Host smart-27b12f58-481e-4178-9751-2c456dc3ed36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488600242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3488600242
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.345751021
Short name T482
Test name
Test status
Simulation time 4022654298 ps
CPU time 7.72 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:33:43 PM PST 24
Peak memory 198752 kb
Host smart-e2b7bee6-e947-458e-8894-d415c20a416f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345751021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.345751021
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2401049252
Short name T780
Test name
Test status
Simulation time 52684585490 ps
CPU time 21.94 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:34:00 PM PST 24
Peak memory 198096 kb
Host smart-902a7afb-6b27-4910-846c-482eedaa47ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401049252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2401049252
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.583084438
Short name T585
Test name
Test status
Simulation time 42364287074 ps
CPU time 35.48 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:34:13 PM PST 24
Peak memory 195832 kb
Host smart-025f3fb7-24b4-448b-b0c0-09ee0343bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583084438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.583084438
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1079097967
Short name T535
Test name
Test status
Simulation time 11627627057 ps
CPU time 16.64 seconds
Started Mar 05 01:33:34 PM PST 24
Finished Mar 05 01:33:51 PM PST 24
Peak memory 200084 kb
Host smart-9671528c-af41-4395-9d73-99d2a1da80b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079097967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1079097967
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1524315447
Short name T569
Test name
Test status
Simulation time 2477676647 ps
CPU time 2.75 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:33:38 PM PST 24
Peak memory 199152 kb
Host smart-94ef93c4-6a42-41cd-893c-af702e47ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524315447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1524315447
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3858765351
Short name T713
Test name
Test status
Simulation time 21533945369 ps
CPU time 44.53 seconds
Started Mar 05 01:33:35 PM PST 24
Finished Mar 05 01:34:20 PM PST 24
Peak memory 200328 kb
Host smart-03f1afab-3cba-4cbc-b78b-f6eeb5cef26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858765351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3858765351
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.805864074
Short name T325
Test name
Test status
Simulation time 37653072566 ps
CPU time 35.41 seconds
Started Mar 05 01:40:50 PM PST 24
Finished Mar 05 01:41:26 PM PST 24
Peak memory 200392 kb
Host smart-3cba0ab5-358a-4cfa-941c-71d5d6d14053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805864074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.805864074
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1007393670
Short name T215
Test name
Test status
Simulation time 167626695829 ps
CPU time 68.06 seconds
Started Mar 05 01:40:49 PM PST 24
Finished Mar 05 01:41:57 PM PST 24
Peak memory 200432 kb
Host smart-7f2081f9-4618-484a-8a63-b355b095611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007393670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1007393670
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2089238833
Short name T929
Test name
Test status
Simulation time 161818155118 ps
CPU time 86.97 seconds
Started Mar 05 01:40:51 PM PST 24
Finished Mar 05 01:42:18 PM PST 24
Peak memory 200328 kb
Host smart-2def2713-e5ac-4b84-ba8e-0fc5dd380dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089238833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2089238833
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2628667222
Short name T231
Test name
Test status
Simulation time 58388453572 ps
CPU time 53.4 seconds
Started Mar 05 01:41:01 PM PST 24
Finished Mar 05 01:41:54 PM PST 24
Peak memory 199560 kb
Host smart-70321f31-9373-4627-998e-e8eb9ba6e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628667222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2628667222
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2233347603
Short name T316
Test name
Test status
Simulation time 24226462999 ps
CPU time 32.17 seconds
Started Mar 05 01:40:55 PM PST 24
Finished Mar 05 01:41:27 PM PST 24
Peak memory 200232 kb
Host smart-915b0752-5066-46a1-80a5-1f29ffa6a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233347603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2233347603
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3301383722
Short name T904
Test name
Test status
Simulation time 89540279302 ps
CPU time 26.04 seconds
Started Mar 05 01:40:59 PM PST 24
Finished Mar 05 01:41:25 PM PST 24
Peak memory 199668 kb
Host smart-999e6eef-f28f-48f3-a831-215dbfb53b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301383722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3301383722
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1913444428
Short name T985
Test name
Test status
Simulation time 101483929763 ps
CPU time 23.01 seconds
Started Mar 05 01:40:55 PM PST 24
Finished Mar 05 01:41:18 PM PST 24
Peak memory 200240 kb
Host smart-2fef80e3-509a-4e88-aca3-84d3586fcc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913444428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1913444428
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2286888095
Short name T963
Test name
Test status
Simulation time 134079631 ps
CPU time 0.58 seconds
Started Mar 05 01:33:40 PM PST 24
Finished Mar 05 01:33:41 PM PST 24
Peak memory 194772 kb
Host smart-e30fff36-808d-4ec0-94e3-ad2453352adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286888095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2286888095
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3487076823
Short name T832
Test name
Test status
Simulation time 53950431389 ps
CPU time 47.2 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:26 PM PST 24
Peak memory 200332 kb
Host smart-f9ef22f2-7bf4-47a1-8e6f-5177af9ec4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487076823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3487076823
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3988794166
Short name T873
Test name
Test status
Simulation time 85327525234 ps
CPU time 55.57 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:34:33 PM PST 24
Peak memory 200332 kb
Host smart-db695e44-1048-486c-b48f-8f2f8f0d2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988794166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3988794166
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.4272714927
Short name T794
Test name
Test status
Simulation time 324799727728 ps
CPU time 303.06 seconds
Started Mar 05 01:33:36 PM PST 24
Finished Mar 05 01:38:39 PM PST 24
Peak memory 200348 kb
Host smart-40c4cbac-619b-4d69-9896-eb71738ca036
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272714927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4272714927
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2602881545
Short name T424
Test name
Test status
Simulation time 74845223651 ps
CPU time 425.07 seconds
Started Mar 05 01:33:40 PM PST 24
Finished Mar 05 01:40:45 PM PST 24
Peak memory 200192 kb
Host smart-a9201d99-3ac3-47b2-a48c-8fb58fc39a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602881545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2602881545
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1099387617
Short name T686
Test name
Test status
Simulation time 8015711355 ps
CPU time 6.35 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:33:46 PM PST 24
Peak memory 199180 kb
Host smart-e410f0e3-4f1b-4f82-ae6d-a85873c7ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099387617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1099387617
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2852761012
Short name T166
Test name
Test status
Simulation time 56951178374 ps
CPU time 25.84 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:05 PM PST 24
Peak memory 199004 kb
Host smart-22f6ed5a-2e52-4d5c-b271-28565275ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852761012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2852761012
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3611555789
Short name T684
Test name
Test status
Simulation time 16157181476 ps
CPU time 431.42 seconds
Started Mar 05 01:33:47 PM PST 24
Finished Mar 05 01:40:58 PM PST 24
Peak memory 200420 kb
Host smart-c17b33f7-1d7b-4455-8e99-4a36aee6657b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611555789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3611555789
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3247921733
Short name T1002
Test name
Test status
Simulation time 3676217313 ps
CPU time 28.62 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:34:08 PM PST 24
Peak memory 198788 kb
Host smart-c0be7c68-b371-4281-8560-b7079eb50626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247921733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3247921733
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.355054696
Short name T411
Test name
Test status
Simulation time 77882322221 ps
CPU time 105.55 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:35:25 PM PST 24
Peak memory 199020 kb
Host smart-2cd02305-fa59-4898-a613-b4a228110619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355054696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.355054696
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2219982381
Short name T860
Test name
Test status
Simulation time 3603591678 ps
CPU time 5.19 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:33:45 PM PST 24
Peak memory 196148 kb
Host smart-5b21f03e-c454-4184-ab50-9d74590755a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219982381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2219982381
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3297294601
Short name T681
Test name
Test status
Simulation time 6010061933 ps
CPU time 16.2 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:33:55 PM PST 24
Peak memory 199712 kb
Host smart-553dc948-1baa-472a-8fb2-835707e8c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297294601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3297294601
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.350987990
Short name T151
Test name
Test status
Simulation time 267656192656 ps
CPU time 437.86 seconds
Started Mar 05 01:33:39 PM PST 24
Finished Mar 05 01:40:57 PM PST 24
Peak memory 200312 kb
Host smart-6df60f76-ff35-43f4-ba62-3fe5c40bd873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350987990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.350987990
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3011075498
Short name T468
Test name
Test status
Simulation time 10722169535 ps
CPU time 6.51 seconds
Started Mar 05 01:33:41 PM PST 24
Finished Mar 05 01:33:48 PM PST 24
Peak memory 199852 kb
Host smart-d528645a-1ef9-4a0f-88ca-904c7c47055c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011075498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3011075498
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3826548243
Short name T1095
Test name
Test status
Simulation time 51050763674 ps
CPU time 17.83 seconds
Started Mar 05 01:33:38 PM PST 24
Finished Mar 05 01:33:56 PM PST 24
Peak memory 200336 kb
Host smart-79a918ca-9428-41f1-bbec-2dacd31cd8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826548243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3826548243
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2832977426
Short name T226
Test name
Test status
Simulation time 53514220671 ps
CPU time 110.84 seconds
Started Mar 05 01:40:53 PM PST 24
Finished Mar 05 01:42:44 PM PST 24
Peak memory 200360 kb
Host smart-ed322d0a-8cae-448d-bcea-f0d1c0bd8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832977426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2832977426
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2900725187
Short name T124
Test name
Test status
Simulation time 61940171744 ps
CPU time 34.01 seconds
Started Mar 05 01:40:54 PM PST 24
Finished Mar 05 01:41:28 PM PST 24
Peak memory 200272 kb
Host smart-6efe6c66-9d6e-4ddd-af85-8cacc1c72f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900725187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2900725187
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3193902457
Short name T608
Test name
Test status
Simulation time 81429799851 ps
CPU time 176.93 seconds
Started Mar 05 01:41:01 PM PST 24
Finished Mar 05 01:43:58 PM PST 24
Peak memory 200368 kb
Host smart-29ad10a5-b5de-4cd5-8c98-0cec9f55d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193902457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3193902457
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.772270908
Short name T271
Test name
Test status
Simulation time 55110947013 ps
CPU time 25.51 seconds
Started Mar 05 01:41:01 PM PST 24
Finished Mar 05 01:41:27 PM PST 24
Peak memory 200264 kb
Host smart-1f06a59a-57e5-4469-9458-2c6901441b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772270908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.772270908
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3040558087
Short name T237
Test name
Test status
Simulation time 16613593846 ps
CPU time 14.21 seconds
Started Mar 05 01:41:08 PM PST 24
Finished Mar 05 01:41:23 PM PST 24
Peak memory 200416 kb
Host smart-10457d77-afb7-4317-ae62-ebbeb4592727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040558087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3040558087
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2659123446
Short name T696
Test name
Test status
Simulation time 31828971154 ps
CPU time 21.52 seconds
Started Mar 05 01:41:08 PM PST 24
Finished Mar 05 01:41:30 PM PST 24
Peak memory 200368 kb
Host smart-d5a59bf7-dc7f-4d4f-9d1f-e947e70528e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659123446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2659123446
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1954644932
Short name T782
Test name
Test status
Simulation time 37815023470 ps
CPU time 14.79 seconds
Started Mar 05 01:41:08 PM PST 24
Finished Mar 05 01:41:23 PM PST 24
Peak memory 199640 kb
Host smart-3327e6e1-8ad5-4a5a-bd27-669925d4ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954644932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1954644932
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2966216574
Short name T179
Test name
Test status
Simulation time 130228609517 ps
CPU time 758.9 seconds
Started Mar 05 01:41:10 PM PST 24
Finished Mar 05 01:53:49 PM PST 24
Peak memory 217080 kb
Host smart-eea0dcca-66e4-427d-a68e-bbd36292b285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966216574 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2966216574
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3681246683
Short name T338
Test name
Test status
Simulation time 56798128511 ps
CPU time 12.44 seconds
Started Mar 05 01:41:10 PM PST 24
Finished Mar 05 01:41:22 PM PST 24
Peak memory 200336 kb
Host smart-6fa3be9c-a24d-4c8a-a487-fd118156ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681246683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3681246683
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3681572740
Short name T905
Test name
Test status
Simulation time 17934172085 ps
CPU time 32.27 seconds
Started Mar 05 01:41:09 PM PST 24
Finished Mar 05 01:41:42 PM PST 24
Peak memory 199968 kb
Host smart-b186592b-6d18-4678-89e0-11b606e9dcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681572740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3681572740
Directory /workspace/99.uart_fifo_reset/latest
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