Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97450	1			T1	242		T2	119		T3	1204
all_values[1]	97450	1			T1	242		T2	119		T3	1204
all_values[2]	97450	1			T1	242		T2	119		T3	1204
all_values[3]	97450	1			T1	242		T2	119		T3	1204
all_values[4]	97450	1			T1	242		T2	119		T3	1204
all_values[5]	97450	1			T1	242		T2	119		T3	1204
all_values[6]	97450	1			T1	242		T2	119		T3	1204
all_values[7]	97450	1			T1	242		T2	119		T3	1204

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390217

1

T1

1109

T2

609

T3

3092

auto[1]

389383

1

T1

827

T2

343

T3

6540

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718964

1

T1

1679

T2

907

T3

9222

auto[1]

60636

1

T1

257

T2

45

T3

410

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23742	1			T1	25		T2	45		T3	520
all_values[0]	auto[0]	auto[1]	23096	1			T1	113		T2	23		T3	81
all_values[0]	auto[1]	auto[0]	25650	1			T1	10		T2	37		T3	282
all_values[0]	auto[1]	auto[1]	24962	1			T1	94		T2	14		T3	321
all_values[1]	auto[0]	auto[0]	45024	1			T1	141		T2	113		T3	623
all_values[1]	auto[0]	auto[1]	3314	1			T1	26		T2	1		T5	2
all_values[1]	auto[1]	auto[0]	45872	1			T1	74		T2	5		T3	581
all_values[1]	auto[1]	auto[1]	3240	1			T1	1		T9	4		T38	1
all_values[2]	auto[0]	auto[0]	48483	1			T1	72		T2	107		T3	146
all_values[2]	auto[0]	auto[1]	2229	1			T1	5		T2	7		T3	4
all_values[2]	auto[1]	auto[0]	44777	1			T1	163		T2	5		T3	1050
all_values[2]	auto[1]	auto[1]	1961	1			T1	2		T3	4		T4	2
all_values[3]	auto[0]	auto[0]	47988	1			T1	89		T2	114		T3	164
all_values[3]	auto[0]	auto[1]	164	1			T9	4		T11	3		T75	4
all_values[3]	auto[1]	auto[0]	49147	1			T1	149		T2	5		T3	1040
all_values[3]	auto[1]	auto[1]	151	1			T1	4		T9	8		T11	2
all_values[4]	auto[0]	auto[0]	47722	1			T1	199		T2	51		T3	757
all_values[4]	auto[0]	auto[1]	289	1			T1	6		T9	4		T11	9
all_values[4]	auto[1]	auto[0]	49169	1			T1	36		T2	68		T3	447
all_values[4]	auto[1]	auto[1]	270	1			T1	1		T9	6		T11	11
all_values[5]	auto[0]	auto[0]	49127	1			T1	168		T2	46		T3	126
all_values[5]	auto[0]	auto[1]	121	1			T9	4		T76	2		T109	4
all_values[5]	auto[1]	auto[0]	48066	1			T1	74		T2	73		T3	1078
all_values[5]	auto[1]	auto[1]	136	1			T9	8		T75	4		T76	2
all_values[6]	auto[0]	auto[0]	48886	1			T1	116		T2	51		T3	85
all_values[6]	auto[0]	auto[1]	121	1			T1	1		T9	3		T75	2
all_values[6]	auto[1]	auto[0]	48302	1			T1	124		T2	68		T3	1119
all_values[6]	auto[1]	auto[1]	141	1			T1	1		T9	6		T75	4
all_values[7]	auto[0]	auto[0]	49704	1			T1	145		T2	51		T3	586
all_values[7]	auto[0]	auto[1]	207	1			T1	3		T9	5		T335	1
all_values[7]	auto[1]	auto[0]	47305	1			T1	94		T2	68		T3	618
all_values[7]	auto[1]	auto[1]	234	1			T9	4		T335	2		T75	2