Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2025

1

T1

5

T2

1

T3

1

auto[UartRx]

2025

1

T1

5

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3865	1			T1	10		T2	2		T3	2
values[1]	21	1			T23	1		T32	1		T99	1
values[2]	14	1			T23	2		T33	1		T37	1
values[3]	19	1			T33	1		T36	2		T102	1
values[4]	15	1			T23	2		T31	1		T280	2
values[5]	18	1			T23	1		T32	2		T36	1
values[6]	18	1			T9	1		T23	1		T33	1
values[7]	12	1			T9	1		T23	1		T31	1
values[8]	18	1			T9	2		T32	1		T33	1
values[9]	22	1			T23	1		T34	1		T37	4
values[10]	20	1			T9	1		T23	1		T24	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1968	1			T1	5		T2	1		T3	1
auto[UartTx]	values[1]	10	1			T23	1		T32	1		T100	1
auto[UartTx]	values[2]	6	1			T33	1		T37	1		T102	1
auto[UartTx]	values[3]	3	1			T36	1		T200	1		T373	1
auto[UartTx]	values[4]	6	1			T23	2		T280	2		T103	1
auto[UartTx]	values[5]	3	1			T37	1		T374	1		T445	1
auto[UartTx]	values[6]	4	1			T9	1		T51	1		T446	1
auto[UartTx]	values[7]	6	1			T23	1		T37	1		T53	1
auto[UartTx]	values[8]	4	1			T9	1		T280	1		T53	1
auto[UartTx]	values[9]	7	1			T37	1		T101	2		T447	1
auto[UartTx]	values[10]	6	1			T31	1		T37	1		T101	1
auto[UartRx]	values[0]	1897	1			T1	5		T2	1		T3	1
auto[UartRx]	values[1]	11	1			T99	1		T101	1		T102	2
auto[UartRx]	values[2]	8	1			T23	2		T99	1		T100	1
auto[UartRx]	values[3]	16	1			T33	1		T36	1		T102	1
auto[UartRx]	values[4]	9	1			T31	1		T448	1		T288	1
auto[UartRx]	values[5]	15	1			T23	1		T32	2		T36	1
auto[UartRx]	values[6]	14	1			T23	1		T33	1		T36	1
auto[UartRx]	values[7]	6	1			T9	1		T31	1		T100	1
auto[UartRx]	values[8]	14	1			T9	1		T32	1		T33	1
auto[UartRx]	values[9]	15	1			T23	1		T34	1		T37	3
auto[UartRx]	values[10]	14	1			T9	1		T23	1		T24	1