Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1916	1			T1	4		T2	2		T5	4
auto[BaudRate115200]	1436	1			T1	3		T3	2		T4	1
auto[BaudRate230400]	1503	1			T1	3		T2	1		T3	1
auto[BaudRate128Kbps]	1399	1			T1	2		T5	2		T6	2
auto[BaudRate256Kbps]	1627	1			T3	1		T4	2		T6	3
auto[BaudRate1Mbps]	1433	1			T2	3		T3	4		T4	1
auto[BaudRate1p5Mbps]	1032	1			T1	2		T3	1		T9	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1333	1			T39	7		T152	5		T13	10
freqs[25]	924	1			T20	24		T335	9		T75	14
freqs[48]	516	1			T1	14		T21	33		T42	10
freqs[50]	392	1			T2	6		T6	6		T10	5
freqs[100]	892	1			T3	9		T141	6		T449	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	228	1			T39	2		T13	10		T450	6
auto[BaudRate9600]	freqs[25]	152	1			T20	3		T335	1		T75	1
auto[BaudRate9600]	freqs[48]	65	1			T1	4		T21	3		T11	2
auto[BaudRate9600]	freqs[50]	75	1			T2	2		T440	1		T285	1
auto[BaudRate9600]	freqs[100]	182	1			T141	1		T449	9		T451	6
auto[BaudRate115200]	freqs[24]	185	1			T39	1		T152	2		T450	6
auto[BaudRate115200]	freqs[25]	132	1			T335	2		T75	4		T110	1
auto[BaudRate115200]	freqs[48]	106	1			T1	3		T21	9		T42	2
auto[BaudRate115200]	freqs[50]	42	1			T10	2		T452	6		T146	3
auto[BaudRate115200]	freqs[100]	119	1			T3	2		T141	2		T149	1
auto[BaudRate230400]	freqs[24]	248	1			T39	1		T152	1		T450	3
auto[BaudRate230400]	freqs[25]	130	1			T75	2		T308	1		T111	2
auto[BaudRate230400]	freqs[48]	61	1			T1	3		T42	2		T11	2
auto[BaudRate230400]	freqs[50]	59	1			T2	1		T6	1		T270	2
auto[BaudRate230400]	freqs[100]	115	1			T3	1		T141	1		T149	2
auto[BaudRate128Kbps]	freqs[24]	171	1			T39	2		T152	1		T450	12
auto[BaudRate128Kbps]	freqs[25]	113	1			T20	6		T335	1		T402	1
auto[BaudRate128Kbps]	freqs[48]	61	1			T1	2		T21	6		T42	2
auto[BaudRate128Kbps]	freqs[50]	47	1			T6	2		T10	1		T285	2
auto[BaudRate128Kbps]	freqs[100]	103	1			T141	1		T149	6		T451	3
auto[BaudRate256Kbps]	freqs[24]	201	1			T450	9		T265	1		T193	1
auto[BaudRate256Kbps]	freqs[25]	150	1			T20	3		T335	3		T75	3
auto[BaudRate256Kbps]	freqs[48]	76	1			T42	1		T162	1		T292	2
auto[BaudRate256Kbps]	freqs[50]	47	1			T6	3		T285	2		T324	1
auto[BaudRate256Kbps]	freqs[100]	127	1			T3	1		T149	3		T297	3
auto[BaudRate1Mbps]	freqs[24]	186	1			T39	1		T152	1		T450	3
auto[BaudRate1Mbps]	freqs[25]	168	1			T20	9		T335	1		T75	4
auto[BaudRate1Mbps]	freqs[48]	83	1			T21	6		T42	2		T162	1
auto[BaudRate1Mbps]	freqs[50]	67	1			T2	3		T285	1		T324	1
auto[BaudRate1Mbps]	freqs[100]	110	1			T3	4		T141	1		T149	4
auto[BaudRate1p5Mbps]	freqs[25]	79	1			T20	3		T335	1		T402	1
auto[BaudRate1p5Mbps]	freqs[48]	64	1			T1	2		T21	9		T42	1
auto[BaudRate1p5Mbps]	freqs[50]	55	1			T10	2		T440	1		T270	2
auto[BaudRate1p5Mbps]	freqs[100]	136	1			T3	1		T149	4		T297	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded