Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2618 1 T1 2 T5 2 T9 5
all_levels[1] 930 1 T2 1 T17 7 T322 6
all_levels[2] 939 1 T11 4 T18 4 T140 10
all_levels[3] 741 1 T1 25 T11 178 T16 6
all_levels[4] 329 1 T38 1 T168 4 T186 5
all_levels[5] 945 1 T18 12 T453 368 T454 130
all_levels[6] 11 1 T418 4 T455 4 T200 3
all_levels[7] 32 1 T418 4 T96 6 T391 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%