Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97450	1			T1	242		T2	119		T3	1204
all_pins[1]	97450	1			T1	242		T2	119		T3	1204
all_pins[2]	97450	1			T1	242		T2	119		T3	1204
all_pins[3]	97450	1			T1	242		T2	119		T3	1204
all_pins[4]	97450	1			T1	242		T2	119		T3	1204
all_pins[5]	97450	1			T1	242		T2	119		T3	1204
all_pins[6]	97450	1			T1	242		T2	119		T3	1204
all_pins[7]	97450	1			T1	242		T2	119		T3	1204

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	747923	1			T1	1829		T2	938		T3	9306
values[0x1]	31677	1			T1	107		T2	14		T3	326
transitions[0x0=>0x1]	30932	1			T1	106		T2	14		T3	326
transitions[0x1=>0x0]	30499	1			T1	106		T2	14		T3	325

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	72450	1			T1	145		T2	105		T3	882
all_pins[0]	values[0x1]	25000	1			T1	97		T2	14		T3	322
all_pins[0]	transitions[0x0=>0x1]	24620	1			T1	96		T2	14		T3	322
all_pins[0]	transitions[0x1=>0x0]	2856	1			T9	1		T152	1		T235	1
all_pins[1]	values[0x0]	94214	1			T1	241		T2	119		T3	1204
all_pins[1]	values[0x1]	3236	1			T1	1		T9	4		T38	1
all_pins[1]	transitions[0x0=>0x1]	3166	1			T1	1		T9	3		T38	1
all_pins[1]	transitions[0x1=>0x0]	1915	1			T1	2		T3	4		T4	2
all_pins[2]	values[0x0]	95465	1			T1	240		T2	119		T3	1200
all_pins[2]	values[0x1]	1985	1			T1	2		T3	4		T4	2
all_pins[2]	transitions[0x0=>0x1]	1958	1			T1	2		T3	4		T4	2
all_pins[2]	transitions[0x1=>0x0]	124	1			T1	4		T9	3		T11	2
all_pins[3]	values[0x0]	97299	1			T1	238		T2	119		T3	1204
all_pins[3]	values[0x1]	151	1			T1	4		T9	8		T11	2
all_pins[3]	transitions[0x0=>0x1]	124	1			T1	4		T9	5		T11	2
all_pins[3]	transitions[0x1=>0x0]	243	1			T1	1		T9	3		T11	11
all_pins[4]	values[0x0]	97180	1			T1	241		T2	119		T3	1204
all_pins[4]	values[0x1]	270	1			T1	1		T9	6		T11	11
all_pins[4]	transitions[0x0=>0x1]	212	1			T1	1		T9	1		T11	11
all_pins[4]	transitions[0x1=>0x0]	106	1			T1	1		T9	3		T75	1
all_pins[5]	values[0x0]	97286	1			T1	241		T2	119		T3	1204
all_pins[5]	values[0x1]	164	1			T1	1		T9	8		T75	4
all_pins[5]	transitions[0x0=>0x1]	120	1			T1	1		T9	6		T75	1
all_pins[5]	transitions[0x1=>0x0]	593	1			T1	1		T5	5		T9	4
all_pins[6]	values[0x0]	96813	1			T1	241		T2	119		T3	1204
all_pins[6]	values[0x1]	637	1			T1	1		T5	5		T9	6
all_pins[6]	transitions[0x0=>0x1]	593	1			T1	1		T5	5		T9	5
all_pins[6]	transitions[0x1=>0x0]	190	1			T9	3		T335	2		T75	1
all_pins[7]	values[0x0]	97216	1			T1	242		T2	119		T3	1204
all_pins[7]	values[0x1]	234	1			T9	4		T335	2		T75	2
all_pins[7]	transitions[0x0=>0x1]	139	1			T9	3		T335	2		T318	1
all_pins[7]	transitions[0x1=>0x0]	24472	1			T1	97		T2	14		T3	321